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/* THIS IS OPEN SOURCE CODE */
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#ifndef __POWER7_EVENTS_H__
#define __POWER7_EVENTS_H__
/*
* File: power7_events.h
* CVS:
* Author: Corey Ashford
* cjashfor@us.ibm.com
* Mods: <your name here>
* <your email address>
*
* (C) Copyright IBM Corporation, 2009. All Rights Reserved.
* Contributed by Corey Ashford <cjashfor.ibm.com>
*
* Note: This code was automatically generated and should not be modified by
* hand.
*
*/
#define POWER7_PME_PM_NEST_4 0
#define POWER7_PME_PM_IC_DEMAND_L2_BR_ALL 1
#define POWER7_PME_PM_PMC2_SAVED 2
#define POWER7_PME_PM_CMPLU_STALL_DFU 3
#define POWER7_PME_PM_VSU0_16FLOP 4
#define POWER7_PME_PM_NEST_3 5
#define POWER7_PME_PM_MRK_LSU_DERAT_MISS 6
#define POWER7_PME_PM_MRK_ST_CMPL 7
#define POWER7_PME_PM_L2_ST_DISP 8
#define POWER7_PME_PM_L2_CASTOUT_MOD 9
#define POWER7_PME_PM_ISEG 10
#define POWER7_PME_PM_MRK_INST_TIMEO 11
#define POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR 12
#define POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM 13
#define POWER7_PME_PM_IERAT_WR_64K 14
#define POWER7_PME_PM_MRK_DTLB_MISS_16M 15
#define POWER7_PME_PM_IERAT_MISS 16
#define POWER7_PME_PM_MRK_PTEG_FROM_LMEM 17
#define POWER7_PME_PM_FLOP 18
#define POWER7_PME_PM_THRD_PRIO_4_5_CYC 19
#define POWER7_PME_PM_BR_PRED_TA 20
#define POWER7_PME_PM_CMPLU_STALL_FXU 21
#define POWER7_PME_PM_EXT_INT 22
#define POWER7_PME_PM_VSU_FSQRT_FDIV 23
#define POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC 24
#define POWER7_PME_PM_LSU1_LDF 25
#define POWER7_PME_PM_IC_WRITE_ALL 26
#define POWER7_PME_PM_LSU0_SRQ_STFWD 27
#define POWER7_PME_PM_PTEG_FROM_RL2L3_MOD 28
#define POWER7_PME_PM_MRK_DATA_FROM_L31_SHR 29
#define POWER7_PME_PM_DATA_FROM_L21_MOD 30
#define POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED 31
#define POWER7_PME_PM_VSU0_8FLOP 32
#define POWER7_PME_PM_POWER_EVENT1 33
#define POWER7_PME_PM_DISP_CLB_HELD_BAL 34
#define POWER7_PME_PM_VSU1_2FLOP 35
#define POWER7_PME_PM_LWSYNC_HELD 36
#define POWER7_PME_PM_INST_FROM_L21_MOD 37
#define POWER7_PME_PM_IC_REQ_ALL 38
#define POWER7_PME_PM_DSLB_MISS 39
#define POWER7_PME_PM_L3_MISS 40
#define POWER7_PME_PM_LSU0_L1_PREF 41
#define POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED 42
#define POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE 43
#define POWER7_PME_PM_L2_INST 44
#define POWER7_PME_PM_VSU0_FRSP 45
#define POWER7_PME_PM_FLUSH_DISP 46
#define POWER7_PME_PM_PTEG_FROM_L2MISS 47
#define POWER7_PME_PM_VSU1_DQ_ISSUED 48
#define POWER7_PME_PM_CMPLU_STALL_LSU 49
#define POWER7_PME_PM_MRK_DATA_FROM_DMEM 50
#define POWER7_PME_PM_LSU_FLUSH_ULD 51
#define POWER7_PME_PM_PTEG_FROM_LMEM 52
#define POWER7_PME_PM_MRK_DERAT_MISS_16M 53
#define POWER7_PME_PM_THRD_ALL_RUN_CYC 54
#define POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT 55
#define POWER7_PME_PM_DATA_FROM_DL2L3_MOD 56
#define POWER7_PME_PM_VSU_FRSP 57
#define POWER7_PME_PM_MRK_DATA_FROM_L21_MOD 58
#define POWER7_PME_PM_PMC1_OVERFLOW 59
#define POWER7_PME_PM_VSU0_SINGLE 60
#define POWER7_PME_PM_MRK_PTEG_FROM_L3MISS 61
#define POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR 62
#define POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED 63
#define POWER7_PME_PM_VSU1_FEST 64
#define POWER7_PME_PM_MRK_INST_DISP 65
#define POWER7_PME_PM_VSU0_COMPLEX_ISSUED 66
#define POWER7_PME_PM_LSU1_FLUSH_UST 67
#define POWER7_PME_PM_INST_CMPL 68
#define POWER7_PME_PM_FXU_IDLE 69
#define POWER7_PME_PM_LSU0_FLUSH_ULD 70
#define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD 71
#define POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC 72
#define POWER7_PME_PM_LSU1_REJECT_LMQ_FULL 73
#define POWER7_PME_PM_INST_PTEG_FROM_L21_MOD 74
#define POWER7_PME_PM_GCT_UTIL_3TO6_SLOT 75
#define POWER7_PME_PM_INST_FROM_RL2L3_MOD 76
#define POWER7_PME_PM_SHL_CREATED 77
#define POWER7_PME_PM_L2_ST_HIT 78
#define POWER7_PME_PM_DATA_FROM_DMEM 79
#define POWER7_PME_PM_L3_LD_MISS 80
#define POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE 81
#define POWER7_PME_PM_DISP_CLB_HELD_RES 82
#define POWER7_PME_PM_L2_SN_SX_I_DONE 83
#define POWER7_PME_PM_GRP_CMPL 84
#define POWER7_PME_PM_BCPLUS8_CONV 85
#define POWER7_PME_PM_STCX_CMPL 86
#define POWER7_PME_PM_VSU0_2FLOP 87
#define POWER7_PME_PM_L3_PREF_MISS 88
#define POWER7_PME_PM_LSU_SRQ_SYNC_CYC 89
#define POWER7_PME_PM_LSU_REJECT_ERAT_MISS 90
#define POWER7_PME_PM_L1_ICACHE_MISS 91
#define POWER7_PME_PM_LSU1_FLUSH_SRQ 92
#define POWER7_PME_PM_LD_REF_L1_LSU0 93
#define POWER7_PME_PM_VSU0_FEST 94
#define POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED 95
#define POWER7_PME_PM_FREQ_UP 96
#define POWER7_PME_PM_DATA_FROM_LMEM 97
#define POWER7_PME_PM_LSU1_LDX 98
#define POWER7_PME_PM_PMC3_OVERFLOW 99
#define POWER7_PME_PM_MRK_BR_MPRED 100
#define POWER7_PME_PM_SHL_MATCH 101
#define POWER7_PME_PM_MRK_BR_TAKEN 102
#define POWER7_PME_PM_ISLB_MISS 103
#define POWER7_PME_PM_CYC 104
#define POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC 105
#define POWER7_PME_PM_DISP_HELD_THERMAL 106
#define POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR 107
#define POWER7_PME_PM_LSU1_SRQ_STFWD 108
#define POWER7_PME_PM_GCT_NOSLOT_BR_MPRED 109
#define POWER7_PME_PM_1PLUS_PPC_CMPL 110
#define POWER7_PME_PM_PTEG_FROM_DMEM 111
#define POWER7_PME_PM_VSU_2FLOP 112
#define POWER7_PME_PM_GCT_FULL_CYC 113
#define POWER7_PME_PM_MRK_DATA_FROM_L3_CYC 114
#define POWER7_PME_PM_LSU_SRQ_S0_ALLOC 115
#define POWER7_PME_PM_MRK_DERAT_MISS_4K 116
#define POWER7_PME_PM_BR_MPRED_TA 117
#define POWER7_PME_PM_INST_PTEG_FROM_L2MISS 118
#define POWER7_PME_PM_DPU_HELD_POWER 119
#define POWER7_PME_PM_RUN_INST_CMPL 120
#define POWER7_PME_PM_MRK_VSU_FIN 121
#define POWER7_PME_PM_LSU_SRQ_S0_VALID 122
#define POWER7_PME_PM_GCT_EMPTY_CYC 123
#define POWER7_PME_PM_IOPS_DISP 124
#define POWER7_PME_PM_RUN_SPURR 125
#define POWER7_PME_PM_PTEG_FROM_L21_MOD 126
#define POWER7_PME_PM_VSU0_1FLOP 127
#define POWER7_PME_PM_SNOOP_TLBIE 128
#define POWER7_PME_PM_DATA_FROM_L3MISS 129
#define POWER7_PME_PM_VSU_SINGLE 130
#define POWER7_PME_PM_DTLB_MISS_16G 131
#define POWER7_PME_PM_CMPLU_STALL_VECTOR 132
#define POWER7_PME_PM_FLUSH 133
#define POWER7_PME_PM_L2_LD_HIT 134
#define POWER7_PME_PM_NEST_2 135
#define POWER7_PME_PM_VSU1_1FLOP 136
#define POWER7_PME_PM_IC_PREF_REQ 137
#define POWER7_PME_PM_L3_LD_HIT 138
#define POWER7_PME_PM_GCT_NOSLOT_IC_MISS 139
#define POWER7_PME_PM_DISP_HELD 140
#define POWER7_PME_PM_L2_LD 141
#define POWER7_PME_PM_LSU_FLUSH_SRQ 142
#define POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC 143
#define POWER7_PME_PM_L2_RCST_BUSY_RC_FULL 144
#define POWER7_PME_PM_TB_BIT_TRANS 145
#define POWER7_PME_PM_THERMAL_MAX 146
#define POWER7_PME_PM_LSU1_FLUSH_ULD 147
#define POWER7_PME_PM_LSU1_REJECT_LHS 148
#define POWER7_PME_PM_LSU_LRQ_S0_ALLOC 149
#define POWER7_PME_PM_POWER_EVENT4 150
#define POWER7_PME_PM_DATA_FROM_L31_SHR 151
#define POWER7_PME_PM_BR_UNCOND 152
#define POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC 153
#define POWER7_PME_PM_PMC4_REWIND 154
#define POWER7_PME_PM_L2_RCLD_DISP 155
#define POWER7_PME_PM_THRD_PRIO_2_3_CYC 156
#define POWER7_PME_PM_MRK_PTEG_FROM_L2MISS 157
#define POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 158
#define POWER7_PME_PM_LSU_DERAT_MISS 159
#define POWER7_PME_PM_IC_PREF_CANCEL_L2 160
#define POWER7_PME_PM_GCT_UTIL_7TO10_SLOT 161
#define POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT 162
#define POWER7_PME_PM_BR_PRED_CCACHE 163
#define POWER7_PME_PM_MRK_ST_CMPL_INT 164
#define POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC 165
#define POWER7_PME_PM_MRK_DATA_FROM_L3MISS 166
#define POWER7_PME_PM_GCT_NOSLOT_CYC 167
#define POWER7_PME_PM_LSU_SET_MPRED 168
#define POWER7_PME_PM_FLUSH_DISP_TLBIE 169
#define POWER7_PME_PM_VSU1_FCONV 170
#define POWER7_PME_PM_NEST_1 171
#define POWER7_PME_PM_DERAT_MISS_16G 172
#define POWER7_PME_PM_INST_FROM_LMEM 173
#define POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT 174
#define POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG 175
#define POWER7_PME_PM_INST_PTEG_FROM_L2 176
#define POWER7_PME_PM_PTEG_FROM_L2 177
#define POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC 178
#define POWER7_PME_PM_MRK_DTLB_MISS_4K 179
#define POWER7_PME_PM_VSU0_FPSCR 180
#define POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED 181
#define POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD 182
#define POWER7_PME_PM_L2_LD_MISS 183
#define POWER7_PME_PM_VMX_RESULT_SAT_1 184
#define POWER7_PME_PM_L1_PREF 185
#define POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC 186
#define POWER7_PME_PM_GRP_IC_MISS_NONSPEC 187
#define POWER7_PME_PM_SHL_MERGED 188
#define POWER7_PME_PM_DATA_FROM_L3 189
#define POWER7_PME_PM_LSU_FLUSH 190
#define POWER7_PME_PM_LSU_SRQ_SYNC_COUNT 191
#define POWER7_PME_PM_PMC2_OVERFLOW 192
#define POWER7_PME_PM_LSU_LDF 193
#define POWER7_PME_PM_POWER_EVENT3 194
#define POWER7_PME_PM_DISP_WT 195
#define POWER7_PME_PM_CMPLU_STALL_REJECT 196
#define POWER7_PME_PM_IC_BANK_CONFLICT 197
#define POWER7_PME_PM_BR_MPRED_CR_TA 198
#define POWER7_PME_PM_L2_INST_MISS 199
#define POWER7_PME_PM_CMPLU_STALL_ERAT_MISS 200
#define POWER7_PME_PM_MRK_LSU_FLUSH 201
#define POWER7_PME_PM_L2_LDST 202
#define POWER7_PME_PM_INST_FROM_L31_SHR 203
#define POWER7_PME_PM_VSU0_FIN 204
#define POWER7_PME_PM_LARX_LSU 205
#define POWER7_PME_PM_INST_FROM_RMEM 206
#define POWER7_PME_PM_DISP_CLB_HELD_TLBIE 207
#define POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC 208
#define POWER7_PME_PM_BR_PRED_CR 209
#define POWER7_PME_PM_LSU_REJECT 210
#define POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT 211
#define POWER7_PME_PM_LSU0_REJECT_LMQ_FULL 212
#define POWER7_PME_PM_VSU_FEST 213
#define POWER7_PME_PM_PTEG_FROM_L3 214
#define POWER7_PME_PM_POWER_EVENT2 215
#define POWER7_PME_PM_IC_PREF_CANCEL_PAGE 216
#define POWER7_PME_PM_VSU0_FSQRT_FDIV 217
#define POWER7_PME_PM_MRK_GRP_CMPL 218
#define POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED 219
#define POWER7_PME_PM_GRP_DISP 220
#define POWER7_PME_PM_LSU0_LDX 221
#define POWER7_PME_PM_DATA_FROM_L2 222
#define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD 223
#define POWER7_PME_PM_LD_REF_L1 224
#define POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED 225
#define POWER7_PME_PM_VSU1_2FLOP_DOUBLE 226
#define POWER7_PME_PM_THRD_PRIO_6_7_CYC 227
#define POWER7_PME_PM_BR_MPRED_CR 228
#define POWER7_PME_PM_LD_MISS_L1 229
#define POWER7_PME_PM_DATA_FROM_RL2L3_MOD 230
#define POWER7_PME_PM_LSU_SRQ_FULL_CYC 231
#define POWER7_PME_PM_TABLEWALK_CYC 232
#define POWER7_PME_PM_MRK_PTEG_FROM_RMEM 233
#define POWER7_PME_PM_LSU_SRQ_STFWD 234
#define POWER7_PME_PM_INST_PTEG_FROM_RMEM 235
#define POWER7_PME_PM_FXU0_FIN 236
#define POWER7_PME_PM_PTEG_FROM_L31_MOD 237
#define POWER7_PME_PM_PMC5_OVERFLOW 238
#define POWER7_PME_PM_LD_REF_L1_LSU1 239
#define POWER7_PME_PM_INST_PTEG_FROM_L21_SHR 240
#define POWER7_PME_PM_CMPLU_STALL_THRD 241
#define POWER7_PME_PM_DATA_FROM_RMEM 242
#define POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED 243
#define POWER7_PME_PM_BR_MPRED_LSTACK 244
#define POWER7_PME_PM_NEST_8 245
#define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC 246
#define POWER7_PME_PM_LSU0_FLUSH_UST 247
#define POWER7_PME_PM_LSU_NCST 248
#define POWER7_PME_PM_BR_TAKEN 249
#define POWER7_PME_PM_INST_PTEG_FROM_LMEM 250
#define POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS 251
#define POWER7_PME_PM_DTLB_MISS_4K 252
#define POWER7_PME_PM_PMC4_SAVED 253
#define POWER7_PME_PM_VSU1_PERMUTE_ISSUED 254
#define POWER7_PME_PM_SLB_MISS 255
#define POWER7_PME_PM_LSU1_FLUSH_LRQ 256
#define POWER7_PME_PM_DTLB_MISS 257
#define POWER7_PME_PM_VSU1_FRSP 258
#define POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED 259
#define POWER7_PME_PM_L2_CASTOUT_SHR 260
#define POWER7_PME_PM_NEST_7 261
#define POWER7_PME_PM_DATA_FROM_DL2L3_SHR 262
#define POWER7_PME_PM_VSU1_STF 263
#define POWER7_PME_PM_ST_FIN 264
#define POWER7_PME_PM_PTEG_FROM_L21_SHR 265
#define POWER7_PME_PM_L2_LOC_GUESS_WRONG 266
#define POWER7_PME_PM_MRK_STCX_FAIL 267
#define POWER7_PME_PM_LSU0_REJECT_LHS 268
#define POWER7_PME_PM_IC_PREF_CANCEL_HIT 269
#define POWER7_PME_PM_L3_PREF_BUSY 270
#define POWER7_PME_PM_MRK_BRU_FIN 271
#define POWER7_PME_PM_LSU1_NCLD 272
#define POWER7_PME_PM_INST_PTEG_FROM_L31_MOD 273
#define POWER7_PME_PM_LSU_NCLD 274
#define POWER7_PME_PM_LSU_LDX 275
#define POWER7_PME_PM_L2_LOC_GUESS_CORRECT 276
#define POWER7_PME_PM_THRESH_TIMEO 277
#define POWER7_PME_PM_L3_PREF_ST 278
#define POWER7_PME_PM_DISP_CLB_HELD_SYNC 279
#define POWER7_PME_PM_VSU_SIMPLE_ISSUED 280
#define POWER7_PME_PM_VSU1_SINGLE 281
#define POWER7_PME_PM_DATA_TABLEWALK_CYC 282
#define POWER7_PME_PM_L2_RC_ST_DONE 283
#define POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD 284
#define POWER7_PME_PM_LARX_LSU1 285
#define POWER7_PME_PM_MRK_DATA_FROM_RMEM 286
#define POWER7_PME_PM_DISP_CLB_HELD 287
#define POWER7_PME_PM_DERAT_MISS_4K 288
#define POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR 289
#define POWER7_PME_PM_SEG_EXCEPTION 290
#define POWER7_PME_PM_FLUSH_DISP_SB 291
#define POWER7_PME_PM_L2_DC_INV 292
#define POWER7_PME_PM_PTEG_FROM_DL2L3_MOD 293
#define POWER7_PME_PM_DSEG 294
#define POWER7_PME_PM_BR_PRED_LSTACK 295
#define POWER7_PME_PM_VSU0_STF 296
#define POWER7_PME_PM_LSU_FX_FIN 297
#define POWER7_PME_PM_DERAT_MISS_16M 298
#define POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD 299
#define POWER7_PME_PM_INST_FROM_L3 300
#define POWER7_PME_PM_MRK_IFU_FIN 301
#define POWER7_PME_PM_ITLB_MISS 302
#define POWER7_PME_PM_VSU_STF 303
#define POWER7_PME_PM_LSU_FLUSH_UST 304
#define POWER7_PME_PM_L2_LDST_MISS 305
#define POWER7_PME_PM_FXU1_FIN 306
#define POWER7_PME_PM_SHL_DEALLOCATED 307
#define POWER7_PME_PM_L2_SN_M_WR_DONE 308
#define POWER7_PME_PM_LSU_REJECT_SET_MPRED 309
#define POWER7_PME_PM_L3_PREF_LD 310
#define POWER7_PME_PM_L2_SN_M_RD_DONE 311
#define POWER7_PME_PM_MRK_DERAT_MISS_16G 312
#define POWER7_PME_PM_VSU_FCONV 313
#define POWER7_PME_PM_ANY_THRD_RUN_CYC 314
#define POWER7_PME_PM_LSU_LMQ_FULL_CYC 315
#define POWER7_PME_PM_MRK_LSU_REJECT_LHS 316
#define POWER7_PME_PM_MRK_LD_MISS_L1_CYC 317
#define POWER7_PME_PM_MRK_DATA_FROM_L2_CYC 318
#define POWER7_PME_PM_INST_IMC_MATCH_DISP 319
#define POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC 320
#define POWER7_PME_PM_VSU0_SIMPLE_ISSUED 321
#define POWER7_PME_PM_CMPLU_STALL_DIV 322
#define POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR 323
#define POWER7_PME_PM_VSU_FMA_DOUBLE 324
#define POWER7_PME_PM_VSU_4FLOP 325
#define POWER7_PME_PM_VSU1_FIN 326
#define POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD 327
#define POWER7_PME_PM_RUN_CYC 328
#define POWER7_PME_PM_PTEG_FROM_RMEM 329
#define POWER7_PME_PM_LSU_LRQ_S0_VALID 330
#define POWER7_PME_PM_LSU0_LDF 331
#define POWER7_PME_PM_FLUSH_COMPLETION 332
#define POWER7_PME_PM_ST_MISS_L1 333
#define POWER7_PME_PM_L2_NODE_PUMP 334
#define POWER7_PME_PM_INST_FROM_DL2L3_SHR 335
#define POWER7_PME_PM_MRK_STALL_CMPLU_CYC 336
#define POWER7_PME_PM_VSU1_DENORM 337
#define POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC 338
#define POWER7_PME_PM_GCT_USAGE_1TO2_SLOT 339
#define POWER7_PME_PM_NEST_6 340
#define POWER7_PME_PM_INST_FROM_L3MISS 341
#define POWER7_PME_PM_EE_OFF_EXT_INT 342
#define POWER7_PME_PM_INST_PTEG_FROM_DMEM 343
#define POWER7_PME_PM_INST_FROM_DL2L3_MOD 344
#define POWER7_PME_PM_PMC6_OVERFLOW 345
#define POWER7_PME_PM_VSU_2FLOP_DOUBLE 346
#define POWER7_PME_PM_TLB_MISS 347
#define POWER7_PME_PM_FXU_BUSY 348
#define POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER 349
#define POWER7_PME_PM_LSU_REJECT_LMQ_FULL 350
#define POWER7_PME_PM_IC_RELOAD_SHR 351
#define POWER7_PME_PM_GRP_MRK 352
#define POWER7_PME_PM_MRK_ST_NEST 353
#define POWER7_PME_PM_VSU1_FSQRT_FDIV 354
#define POWER7_PME_PM_LSU0_FLUSH_LRQ 355
#define POWER7_PME_PM_LARX_LSU0 356
#define POWER7_PME_PM_IBUF_FULL_CYC 357
#define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC 358
#define POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC 359
#define POWER7_PME_PM_GRP_MRK_CYC 360
#define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC 361
#define POWER7_PME_PM_L2_GLOB_GUESS_CORRECT 362
#define POWER7_PME_PM_LSU_REJECT_LHS 363
#define POWER7_PME_PM_MRK_DATA_FROM_LMEM 364
#define POWER7_PME_PM_INST_PTEG_FROM_L3 365
#define POWER7_PME_PM_FREQ_DOWN 366
#define POWER7_PME_PM_INST_FROM_RL2L3_SHR 367
#define POWER7_PME_PM_MRK_INST_ISSUED 368
#define POWER7_PME_PM_PTEG_FROM_L3MISS 369
#define POWER7_PME_PM_RUN_PURR 370
#define POWER7_PME_PM_MRK_DATA_FROM_L3 371
#define POWER7_PME_PM_MRK_GRP_IC_MISS 372
#define POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS 373
#define POWER7_PME_PM_PTEG_FROM_RL2L3_SHR 374
#define POWER7_PME_PM_LSU_FLUSH_LRQ 375
#define POWER7_PME_PM_MRK_DERAT_MISS_64K 376
#define POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD 377
#define POWER7_PME_PM_L2_ST_MISS 378
#define POWER7_PME_PM_LWSYNC 379
#define POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE 380
#define POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR 381
#define POWER7_PME_PM_MRK_LSU_FLUSH_LRQ 382
#define POWER7_PME_PM_INST_IMC_MATCH_CMPL 383
#define POWER7_PME_PM_MRK_INST_FIN 384
#define POWER7_PME_PM_INST_FROM_L31_MOD 385
#define POWER7_PME_PM_MRK_DTLB_MISS_64K 386
#define POWER7_PME_PM_LSU_FIN 387
#define POWER7_PME_PM_MRK_LSU_REJECT 388
#define POWER7_PME_PM_L2_CO_FAIL_BUSY 389
#define POWER7_PME_PM_DATA_FROM_L31_MOD 390
#define POWER7_PME_PM_THERMAL_WARN 391
#define POWER7_PME_PM_VSU0_4FLOP 392
#define POWER7_PME_PM_BR_MPRED_CCACHE 393
#define POWER7_PME_PM_L1_DEMAND_WRITE 394
#define POWER7_PME_PM_FLUSH_BR_MPRED 395
#define POWER7_PME_PM_MRK_DTLB_MISS_16G 396
#define POWER7_PME_PM_MRK_PTEG_FROM_DMEM 397
#define POWER7_PME_PM_L2_RCST_DISP 398
#define POWER7_PME_PM_CMPLU_STALL 399
#define POWER7_PME_PM_LSU_PARTIAL_CDF 400
#define POWER7_PME_PM_DISP_CLB_HELD_SB 401
#define POWER7_PME_PM_VSU0_FMA_DOUBLE 402
#define POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE 403
#define POWER7_PME_PM_IC_DEMAND_CYC 404
#define POWER7_PME_PM_MRK_DATA_FROM_L21_SHR 405
#define POWER7_PME_PM_MRK_LSU_FLUSH_UST 406
#define POWER7_PME_PM_INST_PTEG_FROM_L3MISS 407
#define POWER7_PME_PM_VSU_DENORM 408
#define POWER7_PME_PM_MRK_LSU_PARTIAL_CDF 409
#define POWER7_PME_PM_INST_FROM_L21_SHR 410
#define POWER7_PME_PM_IC_PREF_WRITE 411
#define POWER7_PME_PM_BR_PRED 412
#define POWER7_PME_PM_INST_FROM_DMEM 413
#define POWER7_PME_PM_IC_PREF_CANCEL_ALL 414
#define POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM 415
#define POWER7_PME_PM_MRK_LSU_FLUSH_SRQ 416
#define POWER7_PME_PM_MRK_FIN_STALL_CYC 417
#define POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT 418
#define POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER 419
#define POWER7_PME_PM_VSU1_DD_ISSUED 420
#define POWER7_PME_PM_PTEG_FROM_L31_SHR 421
#define POWER7_PME_PM_DATA_FROM_L21_SHR 422
#define POWER7_PME_PM_LSU0_NCLD 423
#define POWER7_PME_PM_VSU1_4FLOP 424
#define POWER7_PME_PM_VSU1_8FLOP 425
#define POWER7_PME_PM_VSU_8FLOP 426
#define POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 427
#define POWER7_PME_PM_DTLB_MISS_64K 428
#define POWER7_PME_PM_THRD_CONC_RUN_INST 429
#define POWER7_PME_PM_MRK_PTEG_FROM_L2 430
#define POWER7_PME_PM_VSU_FIN 431
#define POWER7_PME_PM_MRK_DATA_FROM_L31_MOD 432
#define POWER7_PME_PM_THRD_PRIO_0_1_CYC 433
#define POWER7_PME_PM_DERAT_MISS_64K 434
#define POWER7_PME_PM_PMC2_REWIND 435
#define POWER7_PME_PM_INST_FROM_L2 436
#define POWER7_PME_PM_GRP_BR_MPRED_NONSPEC 437
#define POWER7_PME_PM_INST_DISP 438
#define POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM 439
#define POWER7_PME_PM_L1_DCACHE_RELOAD_VALID 440
#define POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED 441
#define POWER7_PME_PM_L3_PREF_HIT 442
#define POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD 443
#define POWER7_PME_PM_MRK_FXU_FIN 444
#define POWER7_PME_PM_PMC4_OVERFLOW 445
#define POWER7_PME_PM_MRK_PTEG_FROM_L3 446
#define POWER7_PME_PM_LSU0_LMQ_LHR_MERGE 447
#define POWER7_PME_PM_BTAC_HIT 448
#define POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS 449
#define POWER7_PME_PM_L3_RD_BUSY 450
#define POWER7_PME_PM_INST_FROM_L2MISS 451
#define POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC 452
#define POWER7_PME_PM_L2_ST 453
#define POWER7_PME_PM_VSU0_DENORM 454
#define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR 455
#define POWER7_PME_PM_BR_PRED_CR_TA 456
#define POWER7_PME_PM_VSU0_FCONV 457
#define POWER7_PME_PM_MRK_LSU_FLUSH_ULD 458
#define POWER7_PME_PM_BTAC_MISS 459
#define POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT 460
#define POWER7_PME_PM_MRK_DATA_FROM_L2 461
#define POWER7_PME_PM_VSU_FMA 462
#define POWER7_PME_PM_LSU0_FLUSH_SRQ 463
#define POWER7_PME_PM_LSU1_L1_PREF 464
#define POWER7_PME_PM_IOPS_CMPL 465
#define POWER7_PME_PM_L2_SYS_PUMP 466
#define POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL 467
#define POWER7_PME_PM_BCPLUS8_RSLV_TAKEN 468
#define POWER7_PME_PM_NEST_5 469
#define POWER7_PME_PM_LSU_LMQ_S0_ALLOC 470
#define POWER7_PME_PM_FLUSH_DISP_SYNC 471
#define POWER7_PME_PM_L2_IC_INV 472
#define POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC 473
#define POWER7_PME_PM_L3_PREF_LDST 474
#define POWER7_PME_PM_LSU_SRQ_EMPTY_CYC 475
#define POWER7_PME_PM_LSU_LMQ_S0_VALID 476
#define POWER7_PME_PM_FLUSH_PARTIAL 477
#define POWER7_PME_PM_VSU1_FMA_DOUBLE 478
#define POWER7_PME_PM_1PLUS_PPC_DISP 479
#define POWER7_PME_PM_DATA_FROM_L2MISS 480
#define POWER7_PME_PM_SUSPENDED 481
#define POWER7_PME_PM_VSU0_FMA 482
#define POWER7_PME_PM_CMPLU_STALL_SCALAR 483
#define POWER7_PME_PM_STCX_FAIL 484
#define POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE 485
#define POWER7_PME_PM_DC_PREF_DST 486
#define POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED 487
#define POWER7_PME_PM_L3_HIT 488
#define POWER7_PME_PM_L2_GLOB_GUESS_WRONG 489
#define POWER7_PME_PM_MRK_DFU_FIN 490
#define POWER7_PME_PM_INST_FROM_L1 491
#define POWER7_PME_PM_BRU_FIN 492
#define POWER7_PME_PM_IC_DEMAND_REQ 493
#define POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE 494
#define POWER7_PME_PM_VSU1_FMA 495
#define POWER7_PME_PM_MRK_LD_MISS_L1 496
#define POWER7_PME_PM_VSU0_2FLOP_DOUBLE 497
#define POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM 498
#define POWER7_PME_PM_INST_PTEG_FROM_L31_SHR 499
#define POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS 500
#define POWER7_PME_PM_MRK_DATA_FROM_L2MISS 501
#define POWER7_PME_PM_DATA_FROM_RL2L3_SHR 502
#define POWER7_PME_PM_INST_FROM_PREF 503
#define POWER7_PME_PM_VSU1_SQ 504
#define POWER7_PME_PM_L2_LD_DISP 505
#define POWER7_PME_PM_L2_DISP_ALL 506
#define POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC 507
#define POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE 508
#define POWER7_PME_PM_BR_MPRED 509
#define POWER7_PME_PM_VSU_1FLOP 510
#define POWER7_PME_PM_HV_CYC 511
#define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR 512
#define POWER7_PME_PM_DTLB_MISS_16M 513
#define POWER7_PME_PM_MRK_LSU_FIN 514
#define POWER7_PME_PM_LSU1_LMQ_LHR_MERGE 515
#define POWER7_PME_PM_IFU_FIN 516
static const int power7_event_ids[][POWER7_NUM_EVENT_COUNTERS] = {
[ POWER7_PME_PM_NEST_4 ] = { 213, 213, 208, 203, -1, -1 },
[ POWER7_PME_PM_IC_DEMAND_L2_BR_ALL ] = { 65, 62, 60, 60, -1, -1 },
[ POWER7_PME_PM_PMC2_SAVED ] = { 218, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_DFU ] = { -1, 18, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_16FLOP ] = { 269, 267, 261, 255, -1, -1 },
[ POWER7_PME_PM_NEST_3 ] = { 212, 212, 207, 202, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_DERAT_MISS ] = { -1, -1, 188, -1, -1, -1 },
[ POWER7_PME_PM_MRK_ST_CMPL ] = { 208, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_ST_DISP ] = { -1, -1, -1, 95, -1, -1 },
[ POWER7_PME_PM_L2_CASTOUT_MOD ] = { 99, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_ISEG ] = { 95, 89, 88, 85, -1, -1 },
[ POWER7_PME_PM_MRK_INST_TIMEO ] = { -1, -1, -1, 184, -1, -1 },
[ POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = { -1, -1, 100, -1, -1, -1 },
[ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM ] = { 167, 161, 161, 154, -1, -1 },
[ POWER7_PME_PM_IERAT_WR_64K ] = { 78, 74, 72, 72, -1, -1 },
[ POWER7_PME_PM_MRK_DTLB_MISS_16M ] = { -1, -1, -1, 181, -1, -1 },
[ POWER7_PME_PM_IERAT_MISS ] = { 77, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_LMEM ] = { -1, -1, -1, 198, -1, -1 },
[ POWER7_PME_PM_FLOP ] = { 42, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_THRD_PRIO_4_5_CYC ] = { 244, 242, 237, 231, -1, -1 },
[ POWER7_PME_PM_BR_PRED_TA ] = { 14, 12, 13, 14, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_FXU ] = { -1, 19, -1, -1, -1, -1 },
[ POWER7_PME_PM_EXT_INT ] = { -1, 43, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU_FSQRT_FDIV ] = { 260, 258, 252, 246, -1, -1 },
[ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = { 196, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU1_LDF ] = { 174, 168, 168, 161, -1, -1 },
[ POWER7_PME_PM_IC_WRITE_ALL ] = { 76, 73, 71, 71, -1, -1 },
[ POWER7_PME_PM_LSU0_SRQ_STFWD ] = { 165, 159, 159, 152, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_RL2L3_MOD ] = { 225, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR ] = { 188, 184, -1, -1, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_L21_MOD ] = { -1, -1, 20, -1, -1, -1 },
[ POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED ] = { 310, 308, 302, 296, -1, -1 },
[ POWER7_PME_PM_VSU0_8FLOP ] = { 274, 272, 266, 260, -1, -1 },
[ POWER7_PME_PM_POWER_EVENT1 ] = { 222, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_DISP_CLB_HELD_BAL ] = { 32, 33, 29, 31, -1, -1 },
[ POWER7_PME_PM_VSU1_2FLOP ] = { 294, 292, 286, 280, -1, -1 },
[ POWER7_PME_PM_LWSYNC_HELD ] = { 182, 176, 176, 169, -1, -1 },
[ POWER7_PME_PM_INST_FROM_L21_MOD ] = { -1, -1, 79, -1, -1, -1 },
[ POWER7_PME_PM_IC_REQ_ALL ] = { 75, 72, 70, 70, -1, -1 },
[ POWER7_PME_PM_DSLB_MISS ] = { 39, 40, 37, 37, -1, -1 },
[ POWER7_PME_PM_L3_MISS ] = { 110, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU0_L1_PREF ] = { 158, 152, 152, 145, -1, -1 },
[ POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED ] = { 263, 261, 255, 249, -1, -1 },
[ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE ] = { 168, 162, 162, 155, -1, -1 },
[ POWER7_PME_PM_L2_INST ] = { -1, -1, 93, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_FRSP ] = { 283, 281, 275, 269, -1, -1 },
[ POWER7_PME_PM_FLUSH_DISP ] = { 44, 45, 43, 42, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_L2MISS ] = { -1, -1, -1, 212, -1, -1 },
[ POWER7_PME_PM_VSU1_DQ_ISSUED ] = { 300, 298, 292, 286, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_LSU ] = { -1, 20, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_DMEM ] = { 184, 179, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_FLUSH_ULD ] = { 126, 121, 122, 115, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_LMEM ] = { -1, -1, -1, 213, -1, -1 },
[ POWER7_PME_PM_MRK_DERAT_MISS_16M ] = { -1, -1, 184, -1, -1, -1 },
[ POWER7_PME_PM_THRD_ALL_RUN_CYC ] = { -1, 239, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT ] = { -1, -1, 202, -1, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_DL2L3_MOD ] = { -1, -1, 18, 24, -1, -1 },
[ POWER7_PME_PM_VSU_FRSP ] = { 259, 257, 251, 245, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD ] = { -1, -1, 180, -1, -1, -1 },
[ POWER7_PME_PM_PMC1_OVERFLOW ] = { -1, 218, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_SINGLE ] = { 289, 287, 281, 275, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_L3MISS ] = { -1, 206, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR ] = { -1, 205, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED ] = { 292, 290, 284, 278, -1, -1 },
[ POWER7_PME_PM_VSU1_FEST ] = { 302, 300, 294, 288, -1, -1 },
[ POWER7_PME_PM_MRK_INST_DISP ] = { -1, 194, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_COMPLEX_ISSUED ] = { 275, 273, 267, 261, -1, -1 },
[ POWER7_PME_PM_LSU1_FLUSH_UST ] = { 172, 166, 166, 159, -1, -1 },
[ POWER7_PME_PM_INST_CMPL ] = { 80, 76, 74, 75, -1, -1 },
[ POWER7_PME_PM_FXU_IDLE ] = { 49, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU0_FLUSH_ULD ] = { 156, 150, 150, 143, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { -1, -1, 178, 170, -1, -1 },
[ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC ] = { -1, -1, 129, -1, -1, -1 },
[ POWER7_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 179, 173, 173, 166, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_L21_MOD ] = { -1, -1, 84, -1, -1, -1 },
[ POWER7_PME_PM_GCT_UTIL_3TO6_SLOT ] = { 55, 56, 53, 55, -1, -1 },
[ POWER7_PME_PM_INST_FROM_RL2L3_MOD ] = { 88, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_SHL_CREATED ] = { 228, 227, 222, 217, -1, -1 },
[ POWER7_PME_PM_L2_ST_HIT ] = { -1, -1, -1, 96, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_DMEM ] = { 22, 24, -1, -1, -1, -1 },
[ POWER7_PME_PM_L3_LD_MISS ] = { -1, 104, -1, -1, -1, -1 },
[ POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 48, -1, -1 },
[ POWER7_PME_PM_DISP_CLB_HELD_RES ] = { 33, 34, 30, 32, -1, -1 },
[ POWER7_PME_PM_L2_SN_SX_I_DONE ] = { -1, -1, 101, -1, -1, -1 },
[ POWER7_PME_PM_GRP_CMPL ] = { -1, -1, 55, -1, -1, -1 },
[ POWER7_PME_PM_BCPLUS8_CONV ] = { 2, 0, 1, 1, -1, -1 },
[ POWER7_PME_PM_STCX_CMPL ] = { 234, 234, 229, 223, -1, -1 },
[ POWER7_PME_PM_VSU0_2FLOP ] = { 271, 269, 263, 257, -1, -1 },
[ POWER7_PME_PM_L3_PREF_MISS ] = { -1, -1, 106, -1, -1, -1 },
[ POWER7_PME_PM_LSU_SRQ_SYNC_CYC ] = { 149, 143, 143, 136, -1, -1 },
[ POWER7_PME_PM_LSU_REJECT_ERAT_MISS ] = { -1, 134, -1, -1, -1, -1 },
[ POWER7_PME_PM_L1_ICACHE_MISS ] = { -1, 92, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU1_FLUSH_SRQ ] = { 170, 164, 164, 157, -1, -1 },
[ POWER7_PME_PM_LD_REF_L1_LSU0 ] = { 118, 112, 112, 107, -1, -1 },
[ POWER7_PME_PM_VSU0_FEST ] = { 278, 276, 270, 264, -1, -1 },
[ POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED ] = { 268, 266, 260, 254, -1, -1 },
[ POWER7_PME_PM_FREQ_UP ] = { -1, -1, -1, 47, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_LMEM ] = { -1, -1, 23, 27, -1, -1 },
[ POWER7_PME_PM_LSU1_LDX ] = { 175, 169, 169, 162, -1, -1 },
[ POWER7_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 208, -1, -1 },
[ POWER7_PME_PM_MRK_BR_MPRED ] = { -1, -1, 177, -1, -1, -1 },
[ POWER7_PME_PM_SHL_MATCH ] = { 230, 229, 224, 219, -1, -1 },
[ POWER7_PME_PM_MRK_BR_TAKEN ] = { 183, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_ISLB_MISS ] = { 96, 90, 89, 86, -1, -1 },
[ POWER7_PME_PM_CYC ] = { 21, 23, 17, 23, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC ] = { -1, -1, -1, 171, -1, -1 },
[ POWER7_PME_PM_DISP_HELD_THERMAL ] = { -1, -1, 34, -1, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR ] = { -1, 88, 85, -1, -1, -1 },
[ POWER7_PME_PM_LSU1_SRQ_STFWD ] = { 180, 174, 174, 167, -1, -1 },
[ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED ] = { -1, -1, -1, 51, -1, -1 },
[ POWER7_PME_PM_1PLUS_PPC_CMPL ] = { 0, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_DMEM ] = { -1, 220, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU_2FLOP ] = { 249, 247, 241, 235, -1, -1 },
[ POWER7_PME_PM_GCT_FULL_CYC ] = { 51, 52, 50, 50, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L3_CYC ] = { -1, -1, -1, 175, -1, -1 },
[ POWER7_PME_PM_LSU_SRQ_S0_ALLOC ] = { 145, 139, 139, 132, -1, -1 },
[ POWER7_PME_PM_MRK_DERAT_MISS_4K ] = { 191, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_BR_MPRED_TA ] = { 8, 6, 7, 8, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_L2MISS ] = { -1, -1, -1, 83, -1, -1 },
[ POWER7_PME_PM_DPU_HELD_POWER ] = { -1, 38, -1, -1, -1, -1 },
[ POWER7_PME_PM_RUN_INST_CMPL ] = { -1, -1, -1, 214, 0, -1 },
[ POWER7_PME_PM_MRK_VSU_FIN ] = { -1, -1, 204, -1, -1, -1 },
[ POWER7_PME_PM_LSU_SRQ_S0_VALID ] = { 146, 140, 140, 133, -1, -1 },
[ POWER7_PME_PM_GCT_EMPTY_CYC ] = { -1, 51, -1, -1, -1, -1 },
[ POWER7_PME_PM_IOPS_DISP ] = { -1, -1, 87, -1, -1, -1 },
[ POWER7_PME_PM_RUN_SPURR ] = { 226, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_L21_MOD ] = { -1, -1, 218, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_1FLOP ] = { 270, 268, 262, 256, -1, -1 },
[ POWER7_PME_PM_SNOOP_TLBIE ] = { 233, 232, 227, 222, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_L3MISS ] = { -1, 28, 22, -1, -1, -1 },
[ POWER7_PME_PM_VSU_SINGLE ] = { 265, 263, 257, 251, -1, -1 },
[ POWER7_PME_PM_DTLB_MISS_16G ] = { 40, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_VECTOR ] = { -1, 22, -1, -1, -1, -1 },
[ POWER7_PME_PM_FLUSH ] = { -1, -1, -1, 40, -1, -1 },
[ POWER7_PME_PM_L2_LD_HIT ] = { -1, -1, 96, -1, -1, -1 },
[ POWER7_PME_PM_NEST_2 ] = { 211, 211, 206, 201, -1, -1 },
[ POWER7_PME_PM_VSU1_1FLOP ] = { 293, 291, 285, 279, -1, -1 },
[ POWER7_PME_PM_IC_PREF_REQ ] = { 72, 69, 67, 67, -1, -1 },
[ POWER7_PME_PM_L3_LD_HIT ] = { -1, 103, -1, -1, -1, -1 },
[ POWER7_PME_PM_GCT_NOSLOT_IC_MISS ] = { -1, 53, -1, -1, -1, -1 },
[ POWER7_PME_PM_DISP_HELD ] = { 37, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_LD ] = { 103, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_FLUSH_SRQ ] = { 125, 120, 121, 114, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = { -1, -1, -1, 176, -1, -1 },
[ POWER7_PME_PM_L2_RCST_BUSY_RC_FULL ] = { -1, 101, -1, -1, -1, -1 },
[ POWER7_PME_PM_TB_BIT_TRANS ] = { -1, -1, 232, -1, -1, -1 },
[ POWER7_PME_PM_THERMAL_MAX ] = { -1, -1, -1, 226, -1, -1 },
[ POWER7_PME_PM_LSU1_FLUSH_ULD ] = { 171, 165, 165, 158, -1, -1 },
[ POWER7_PME_PM_LSU1_REJECT_LHS ] = { 178, 172, 172, 165, -1, -1 },
[ POWER7_PME_PM_LSU_LRQ_S0_ALLOC ] = { 134, 129, 130, 122, -1, -1 },
[ POWER7_PME_PM_POWER_EVENT4 ] = { -1, -1, -1, 209, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_L31_SHR ] = { 26, 27, -1, -1, -1, -1 },
[ POWER7_PME_PM_BR_UNCOND ] = { 15, 14, 14, 15, -1, -1 },
[ POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC ] = { 166, 160, 160, 153, -1, -1 },
[ POWER7_PME_PM_PMC4_REWIND ] = { 220, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_RCLD_DISP ] = { 106, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_THRD_PRIO_2_3_CYC ] = { 243, 241, 236, 230, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_L2MISS ] = { -1, -1, -1, 197, -1, -1 },
[ POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { 64, 61, 59, 59, -1, -1 },
[ POWER7_PME_PM_LSU_DERAT_MISS ] = { -1, 117, 117, -1, -1, -1 },
[ POWER7_PME_PM_IC_PREF_CANCEL_L2 ] = { 70, 67, 65, 65, -1, -1 },
[ POWER7_PME_PM_GCT_UTIL_7TO10_SLOT ] = { 56, 57, 54, 56, -1, -1 },
[ POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT ] = { 194, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_BR_PRED_CCACHE ] = { 10, 8, 9, 10, -1, -1 },
[ POWER7_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 200, -1, -1, -1 },
[ POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC ] = { 150, 144, 144, 137, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L3MISS ] = { -1, 186, -1, -1, -1, -1 },
[ POWER7_PME_PM_GCT_NOSLOT_CYC ] = { 52, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_SET_MPRED ] = { 143, 138, 138, 130, -1, -1 },
[ POWER7_PME_PM_FLUSH_DISP_TLBIE ] = { 47, 48, 46, 45, -1, -1 },
[ POWER7_PME_PM_VSU1_FCONV ] = { 301, 299, 293, 287, -1, -1 },
[ POWER7_PME_PM_NEST_1 ] = { 210, 210, 205, 200, -1, -1 },
[ POWER7_PME_PM_DERAT_MISS_16G ] = { -1, -1, -1, 29, -1, -1 },
[ POWER7_PME_PM_INST_FROM_LMEM ] = { -1, -1, 81, 80, -1, -1 },
[ POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { 66, 63, 61, 61, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG ] = { -1, 21, -1, -1, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_L2 ] = { 91, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_L2 ] = { 223, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = { -1, 182, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DTLB_MISS_4K ] = { -1, 192, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_FPSCR ] = { 282, 280, 274, 268, -1, -1 },
[ POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED ] = { 315, 313, 307, 301, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = { 207, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_LD_MISS ] = { -1, 97, -1, -1, -1, -1 },
[ POWER7_PME_PM_VMX_RESULT_SAT_1 ] = { 247, 245, 239, 233, -1, -1 },
[ POWER7_PME_PM_L1_PREF ] = { 98, 93, 92, 89, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { -1, 187, -1, -1, -1, -1 },
[ POWER7_PME_PM_GRP_IC_MISS_NONSPEC ] = { 58, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_SHL_MERGED ] = { 231, 230, 225, 220, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_L3 ] = { 24, 26, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_FLUSH ] = { 123, 118, 119, 112, -1, -1 },
[ POWER7_PME_PM_LSU_SRQ_SYNC_COUNT ] = { 148, 142, 142, 135, -1, -1 },
[ POWER7_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 213, -1, -1, -1 },
[ POWER7_PME_PM_LSU_LDF ] = { 129, 123, 124, 117, -1, -1 },
[ POWER7_PME_PM_POWER_EVENT3 ] = { -1, -1, 217, -1, -1, -1 },
[ POWER7_PME_PM_DISP_WT ] = { -1, -1, 35, -1, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_REJECT ] = { -1, -1, -1, 21, -1, -1 },
[ POWER7_PME_PM_IC_BANK_CONFLICT ] = { 62, 60, 58, 58, -1, -1 },
[ POWER7_PME_PM_BR_MPRED_CR_TA ] = { 6, 4, 5, 6, -1, -1 },
[ POWER7_PME_PM_L2_INST_MISS ] = { -1, -1, 94, -1, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_ERAT_MISS ] = { -1, -1, -1, 20, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_FLUSH ] = { 198, 196, 189, 187, -1, -1 },
[ POWER7_PME_PM_L2_LDST ] = { 104, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_INST_FROM_L31_SHR ] = { 86, 81, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_FIN ] = { 279, 277, 271, 265, -1, -1 },
[ POWER7_PME_PM_LARX_LSU ] = { 114, 108, 108, 102, -1, -1 },
[ POWER7_PME_PM_INST_FROM_RMEM ] = { -1, -1, 82, -1, -1, -1 },
[ POWER7_PME_PM_DISP_CLB_HELD_TLBIE ] = { 36, 37, 33, 35, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = { -1, 180, -1, -1, -1, -1 },
[ POWER7_PME_PM_BR_PRED_CR ] = { 11, 9, 10, 11, -1, -1 },
[ POWER7_PME_PM_LSU_REJECT ] = { 139, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT ] = { 19, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 164, 158, 158, 151, -1, -1 },
[ POWER7_PME_PM_VSU_FEST ] = { 255, 253, 247, 241, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_L3 ] = { -1, 221, -1, -1, -1, -1 },
[ POWER7_PME_PM_POWER_EVENT2 ] = { -1, 219, -1, -1, -1, -1 },
[ POWER7_PME_PM_IC_PREF_CANCEL_PAGE ] = { 71, 68, 66, 66, -1, -1 },
[ POWER7_PME_PM_VSU0_FSQRT_FDIV ] = { 284, 282, 276, 270, -1, -1 },
[ POWER7_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 182, -1, -1 },
[ POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED ] = { 286, 284, 278, 272, -1, -1 },
[ POWER7_PME_PM_GRP_DISP ] = { -1, -1, 56, -1, -1, -1 },
[ POWER7_PME_PM_LSU0_LDX ] = { 160, 154, 154, 147, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_L2 ] = { 23, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { 189, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LD_REF_L1 ] = { 117, 111, 111, 106, -1, -1 },
[ POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED ] = { 291, 289, 283, 277, -1, -1 },
[ POWER7_PME_PM_VSU1_2FLOP_DOUBLE ] = { 295, 293, 287, 281, -1, -1 },
[ POWER7_PME_PM_THRD_PRIO_6_7_CYC ] = { 245, 243, 238, 232, -1, -1 },
[ POWER7_PME_PM_BR_MPRED_CR ] = { 5, 3, 4, 5, -1, -1 },
[ POWER7_PME_PM_LD_MISS_L1 ] = { -1, -1, -1, 105, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_RL2L3_MOD ] = { 27, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_SRQ_FULL_CYC ] = { 144, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_TABLEWALK_CYC ] = { 237, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_RMEM ] = { -1, -1, 199, -1, -1, -1 },
[ POWER7_PME_PM_LSU_SRQ_STFWD ] = { 147, 141, 141, 134, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_RMEM ] = { -1, -1, 86, -1, -1, -1 },
[ POWER7_PME_PM_FXU0_FIN ] = { 50, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_L31_MOD ] = { 224, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_PMC5_OVERFLOW ] = { 221, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LD_REF_L1_LSU1 ] = { 119, 113, 113, 108, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_L21_SHR ] = { -1, -1, -1, 82, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_THRD ] = { 20, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_RMEM ] = { -1, -1, 24, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED ] = { 287, 285, 279, 273, -1, -1 },
[ POWER7_PME_PM_BR_MPRED_LSTACK ] = { 7, 5, 6, 7, -1, -1 },
[ POWER7_PME_PM_NEST_8 ] = { 217, 217, 212, 207, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = { -1, -1, -1, 178, -1, -1 },
[ POWER7_PME_PM_LSU0_FLUSH_UST ] = { 157, 151, 151, 144, -1, -1 },
[ POWER7_PME_PM_LSU_NCST ] = { 137, 132, 133, 125, -1, -1 },
[ POWER7_PME_PM_BR_TAKEN ] = { -1, 13, -1, -1, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_LMEM ] = { -1, -1, -1, 84, -1, -1 },
[ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS ] = { -1, -1, -1, 52, -1, -1 },
[ POWER7_PME_PM_DTLB_MISS_4K ] = { -1, 41, -1, -1, -1, -1 },
[ POWER7_PME_PM_PMC4_SAVED ] = { -1, -1, 215, -1, -1, -1 },
[ POWER7_PME_PM_VSU1_PERMUTE_ISSUED ] = { 309, 307, 301, 295, -1, -1 },
[ POWER7_PME_PM_SLB_MISS ] = { 232, 231, 226, 221, -1, -1 },
[ POWER7_PME_PM_LSU1_FLUSH_LRQ ] = { 169, 163, 163, 156, -1, -1 },
[ POWER7_PME_PM_DTLB_MISS ] = { -1, -1, 38, -1, -1, -1 },
[ POWER7_PME_PM_VSU1_FRSP ] = { 306, 304, 298, 292, -1, -1 },
[ POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED ] = { 267, 265, 259, 253, -1, -1 },
[ POWER7_PME_PM_L2_CASTOUT_SHR ] = { 100, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_NEST_7 ] = { 216, 216, 211, 206, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_DL2L3_SHR ] = { -1, -1, 19, -1, -1, -1 },
[ POWER7_PME_PM_VSU1_STF ] = { 314, 312, 306, 300, -1, -1 },
[ POWER7_PME_PM_ST_FIN ] = { -1, 233, -1, -1, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_L21_SHR ] = { -1, -1, -1, 211, -1, -1 },
[ POWER7_PME_PM_L2_LOC_GUESS_WRONG ] = { -1, 99, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_STCX_FAIL ] = { 209, 209, 203, 199, -1, -1 },
[ POWER7_PME_PM_LSU0_REJECT_LHS ] = { 163, 157, 157, 150, -1, -1 },
[ POWER7_PME_PM_IC_PREF_CANCEL_HIT ] = { 69, 66, 64, 64, -1, -1 },
[ POWER7_PME_PM_L3_PREF_BUSY ] = { -1, -1, -1, 97, -1, -1 },
[ POWER7_PME_PM_MRK_BRU_FIN ] = { -1, 177, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU1_NCLD ] = { 177, 171, 171, 164, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_L31_MOD ] = { 92, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_NCLD ] = { 136, 131, 132, 124, -1, -1 },
[ POWER7_PME_PM_LSU_LDX ] = { 130, 124, 125, 118, -1, -1 },
[ POWER7_PME_PM_L2_LOC_GUESS_CORRECT ] = { 105, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_THRESH_TIMEO ] = { 246, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_L3_PREF_ST ] = { 113, 107, 107, 100, -1, -1 },
[ POWER7_PME_PM_DISP_CLB_HELD_SYNC ] = { 35, 36, 32, 34, -1, -1 },
[ POWER7_PME_PM_VSU_SIMPLE_ISSUED ] = { 264, 262, 256, 250, -1, -1 },
[ POWER7_PME_PM_VSU1_SINGLE ] = { 312, 310, 304, 298, -1, -1 },
[ POWER7_PME_PM_DATA_TABLEWALK_CYC ] = { -1, -1, 25, -1, -1, -1 },
[ POWER7_PME_PM_L2_RC_ST_DONE ] = { -1, -1, 98, -1, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD ] = { -1, -1, 197, -1, -1, -1 },
[ POWER7_PME_PM_LARX_LSU1 ] = { 116, 110, 110, 104, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_RMEM ] = { -1, -1, 183, -1, -1, -1 },
[ POWER7_PME_PM_DISP_CLB_HELD ] = { 31, 32, 28, 30, -1, -1 },
[ POWER7_PME_PM_DERAT_MISS_4K ] = { 30, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = { 107, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_SEG_EXCEPTION ] = { 227, 226, 221, 216, -1, -1 },
[ POWER7_PME_PM_FLUSH_DISP_SB ] = { 45, 46, 44, 43, -1, -1 },
[ POWER7_PME_PM_L2_DC_INV ] = { -1, 94, -1, -1, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 210, -1, -1 },
[ POWER7_PME_PM_DSEG ] = { 38, 39, 36, 36, -1, -1 },
[ POWER7_PME_PM_BR_PRED_LSTACK ] = { 13, 11, 12, 13, -1, -1 },
[ POWER7_PME_PM_VSU0_STF ] = { 290, 288, 282, 276, -1, -1 },
[ POWER7_PME_PM_LSU_FX_FIN ] = { 128, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_DERAT_MISS_16M ] = { -1, -1, 27, -1, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 195, -1, -1 },
[ POWER7_PME_PM_INST_FROM_L3 ] = { 84, 80, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_IFU_FIN ] = { -1, -1, 186, -1, -1, -1 },
[ POWER7_PME_PM_ITLB_MISS ] = { -1, -1, -1, 87, -1, -1 },
[ POWER7_PME_PM_VSU_STF ] = { 266, 264, 258, 252, -1, -1 },
[ POWER7_PME_PM_LSU_FLUSH_UST ] = { 127, 122, 123, 116, -1, -1 },
[ POWER7_PME_PM_L2_LDST_MISS ] = { -1, 98, -1, -1, -1, -1 },
[ POWER7_PME_PM_FXU1_FIN ] = { -1, -1, -1, 49, -1, -1 },
[ POWER7_PME_PM_SHL_DEALLOCATED ] = { 229, 228, 223, 218, -1, -1 },
[ POWER7_PME_PM_L2_SN_M_WR_DONE ] = { -1, -1, -1, 94, -1, -1 },
[ POWER7_PME_PM_LSU_REJECT_SET_MPRED ] = { 142, 137, 137, 129, -1, -1 },
[ POWER7_PME_PM_L3_PREF_LD ] = { 111, 105, 104, 98, -1, -1 },
[ POWER7_PME_PM_L2_SN_M_RD_DONE ] = { -1, -1, -1, 93, -1, -1 },
[ POWER7_PME_PM_MRK_DERAT_MISS_16G ] = { -1, -1, -1, 180, -1, -1 },
[ POWER7_PME_PM_VSU_FCONV ] = { 254, 252, 246, 240, -1, -1 },
[ POWER7_PME_PM_ANY_THRD_RUN_CYC ] = { 1, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_LMQ_FULL_CYC ] = { 131, 125, 126, 119, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_REJECT_LHS ] = { 204, 202, 196, 194, -1, -1 },
[ POWER7_PME_PM_MRK_LD_MISS_L1_CYC ] = { -1, -1, -1, 185, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L2_CYC ] = { -1, 181, -1, -1, -1, -1 },
[ POWER7_PME_PM_INST_IMC_MATCH_DISP ] = { -1, -1, 83, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { -1, -1, -1, 179, -1, -1 },
[ POWER7_PME_PM_VSU0_SIMPLE_ISSUED ] = { 288, 286, 280, 274, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_DIV ] = { -1, -1, -1, 19, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = { -1, 207, 198, -1, -1, -1 },
[ POWER7_PME_PM_VSU_FMA_DOUBLE ] = { 258, 256, 250, 244, -1, -1 },
[ POWER7_PME_PM_VSU_4FLOP ] = { 251, 249, 243, 237, -1, -1 },
[ POWER7_PME_PM_VSU1_FIN ] = { 303, 301, 295, 289, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD ] = { 93, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_RUN_CYC ] = { -1, 225, -1, -1, -1, 0 },
[ POWER7_PME_PM_PTEG_FROM_RMEM ] = { -1, -1, 220, -1, -1, -1 },
[ POWER7_PME_PM_LSU_LRQ_S0_VALID ] = { 135, 130, 131, 123, -1, -1 },
[ POWER7_PME_PM_LSU0_LDF ] = { 159, 153, 153, 146, -1, -1 },
[ POWER7_PME_PM_FLUSH_COMPLETION ] = { -1, -1, 42, -1, -1, -1 },
[ POWER7_PME_PM_ST_MISS_L1 ] = { -1, -1, 228, -1, -1, -1 },
[ POWER7_PME_PM_L2_NODE_PUMP ] = { -1, -1, 97, -1, -1, -1 },
[ POWER7_PME_PM_INST_FROM_DL2L3_SHR ] = { -1, -1, 77, -1, -1, -1 },
[ POWER7_PME_PM_MRK_STALL_CMPLU_CYC ] = { -1, -1, 201, -1, -1, -1 },
[ POWER7_PME_PM_VSU1_DENORM ] = { 299, 297, 291, 285, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = { -1, 185, -1, -1, -1, -1 },
[ POWER7_PME_PM_GCT_USAGE_1TO2_SLOT ] = { 53, 54, 51, 53, -1, -1 },
[ POWER7_PME_PM_NEST_6 ] = { 215, 215, 210, 205, -1, -1 },
[ POWER7_PME_PM_INST_FROM_L3MISS ] = { -1, 82, -1, -1, -1, -1 },
[ POWER7_PME_PM_EE_OFF_EXT_INT ] = { 41, 42, 40, 39, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_DMEM ] = { -1, 84, -1, -1, -1, -1 },
[ POWER7_PME_PM_INST_FROM_DL2L3_MOD ] = { -1, -1, 76, 76, -1, -1 },
[ POWER7_PME_PM_PMC6_OVERFLOW ] = { -1, -1, 216, -1, -1, -1 },
[ POWER7_PME_PM_VSU_2FLOP_DOUBLE ] = { 250, 248, 242, 236, -1, -1 },
[ POWER7_PME_PM_TLB_MISS ] = { -1, 244, -1, -1, -1, -1 },
[ POWER7_PME_PM_FXU_BUSY ] = { -1, 50, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = { -1, 100, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_REJECT_LMQ_FULL ] = { 141, 136, 136, 128, -1, -1 },
[ POWER7_PME_PM_IC_RELOAD_SHR ] = { 74, 71, 69, 69, -1, -1 },
[ POWER7_PME_PM_GRP_MRK ] = { 59, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_ST_NEST ] = { -1, 208, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU1_FSQRT_FDIV ] = { 307, 305, 299, 293, -1, -1 },
[ POWER7_PME_PM_LSU0_FLUSH_LRQ ] = { 154, 148, 148, 141, -1, -1 },
[ POWER7_PME_PM_LARX_LSU0 ] = { 115, 109, 109, 103, -1, -1 },
[ POWER7_PME_PM_IBUF_FULL_CYC ] = { 61, 59, 57, 57, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = { -1, 178, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC ] = { 120, 114, 114, 109, -1, -1 },
[ POWER7_PME_PM_GRP_MRK_CYC ] = { 60, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = { -1, 189, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_GLOB_GUESS_CORRECT ] = { 102, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU_REJECT_LHS ] = { 140, 135, 135, 127, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_LMEM ] = { -1, -1, 182, 177, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_L3 ] = { -1, 85, -1, -1, -1, -1 },
[ POWER7_PME_PM_FREQ_DOWN ] = { -1, -1, 48, -1, -1, -1 },
[ POWER7_PME_PM_INST_FROM_RL2L3_SHR ] = { 89, 83, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_INST_ISSUED ] = { 195, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_L3MISS ] = { -1, 223, -1, -1, -1, -1 },
[ POWER7_PME_PM_RUN_PURR ] = { -1, -1, -1, 215, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L3 ] = { 186, 183, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_GRP_IC_MISS ] = { -1, -1, -1, 183, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { -1, 17, -1, -1, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_RL2L3_SHR ] = { -1, 224, 219, -1, -1, -1 },
[ POWER7_PME_PM_LSU_FLUSH_LRQ ] = { 124, 119, 120, 113, -1, -1 },
[ POWER7_PME_PM_MRK_DERAT_MISS_64K ] = { -1, 190, -1, -1, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 81, -1, -1 },
[ POWER7_PME_PM_L2_ST_MISS ] = { -1, 102, -1, -1, -1, -1 },
[ POWER7_PME_PM_LWSYNC ] = { 181, 175, 175, 168, -1, -1 },
[ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE ] = { 153, 147, 147, 140, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR ] = { -1, -1, -1, 196, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_FLUSH_LRQ ] = { 199, 197, 190, 188, -1, -1 },
[ POWER7_PME_PM_INST_IMC_MATCH_CMPL ] = { 90, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_INST_FIN ] = { -1, -1, 187, -1, -1, -1 },
[ POWER7_PME_PM_INST_FROM_L31_MOD ] = { 85, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DTLB_MISS_64K ] = { -1, -1, 185, -1, -1, -1 },
[ POWER7_PME_PM_LSU_FIN ] = { -1, -1, 118, -1, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_REJECT ] = { -1, -1, -1, 193, -1, -1 },
[ POWER7_PME_PM_L2_CO_FAIL_BUSY ] = { 101, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_L31_MOD ] = { 25, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_THERMAL_WARN ] = { 238, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_4FLOP ] = { 273, 271, 265, 259, -1, -1 },
[ POWER7_PME_PM_BR_MPRED_CCACHE ] = { 4, 2, 3, 4, -1, -1 },
[ POWER7_PME_PM_L1_DEMAND_WRITE ] = { 97, 91, 91, 88, -1, -1 },
[ POWER7_PME_PM_FLUSH_BR_MPRED ] = { 43, 44, 41, 41, -1, -1 },
[ POWER7_PME_PM_MRK_DTLB_MISS_16G ] = { 192, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_DMEM ] = { -1, 203, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_RCST_DISP ] = { -1, -1, 99, -1, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL ] = { -1, -1, -1, 18, -1, -1 },
[ POWER7_PME_PM_LSU_PARTIAL_CDF ] = { 138, 133, 134, 126, -1, -1 },
[ POWER7_PME_PM_DISP_CLB_HELD_SB ] = { 34, 35, 31, 33, -1, -1 },
[ POWER7_PME_PM_VSU0_FMA_DOUBLE ] = { 281, 279, 273, 267, -1, -1 },
[ POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, 49, -1, -1, -1 },
[ POWER7_PME_PM_IC_DEMAND_CYC ] = { 63, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR ] = { -1, -1, 181, 173, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_FLUSH_UST ] = { 202, 200, 193, 191, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_L3MISS ] = { -1, 87, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU_DENORM ] = { 253, 251, 245, 239, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_PARTIAL_CDF ] = { 203, 201, 194, 192, -1, -1 },
[ POWER7_PME_PM_INST_FROM_L21_SHR ] = { -1, -1, 80, 78, -1, -1 },
[ POWER7_PME_PM_IC_PREF_WRITE ] = { 73, 70, 68, 68, -1, -1 },
[ POWER7_PME_PM_BR_PRED ] = { 9, 7, 8, 9, -1, -1 },
[ POWER7_PME_PM_INST_FROM_DMEM ] = { 81, 78, -1, -1, -1, -1 },
[ POWER7_PME_PM_IC_PREF_CANCEL_ALL ] = { 68, 65, 63, 63, -1, -1 },
[ POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM ] = { 121, 115, 115, 110, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_FLUSH_SRQ ] = { 200, 198, 191, 189, -1, -1 },
[ POWER7_PME_PM_MRK_FIN_STALL_CYC ] = { 193, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT ] = { 54, 55, 52, 54, -1, -1 },
[ POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = { -1, -1, -1, 92, -1, -1 },
[ POWER7_PME_PM_VSU1_DD_ISSUED ] = { 298, 296, 290, 284, -1, -1 },
[ POWER7_PME_PM_PTEG_FROM_L31_SHR ] = { -1, 222, -1, -1, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_L21_SHR ] = { -1, -1, 21, 25, -1, -1 },
[ POWER7_PME_PM_LSU0_NCLD ] = { 162, 156, 156, 149, -1, -1 },
[ POWER7_PME_PM_VSU1_4FLOP ] = { 296, 294, 288, 282, -1, -1 },
[ POWER7_PME_PM_VSU1_8FLOP ] = { 297, 295, 289, 283, -1, -1 },
[ POWER7_PME_PM_VSU_8FLOP ] = { 252, 250, 244, 238, -1, -1 },
[ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 128, -1, -1, -1, -1 },
[ POWER7_PME_PM_DTLB_MISS_64K ] = { -1, -1, 39, -1, -1, -1 },
[ POWER7_PME_PM_THRD_CONC_RUN_INST ] = { -1, -1, 234, -1, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_L2 ] = { 205, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU_FIN ] = { 256, 254, 248, 242, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD ] = { 187, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_THRD_PRIO_0_1_CYC ] = { 242, 240, 235, 229, -1, -1 },
[ POWER7_PME_PM_DERAT_MISS_64K ] = { -1, 31, -1, -1, -1, -1 },
[ POWER7_PME_PM_PMC2_REWIND ] = { -1, -1, 214, -1, -1, -1 },
[ POWER7_PME_PM_INST_FROM_L2 ] = { 83, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_GRP_BR_MPRED_NONSPEC ] = { 57, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_INST_DISP ] = { -1, 77, 75, -1, -1, -1 },
[ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM ] = { 152, 146, 146, 139, -1, -1 },
[ POWER7_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 90, -1, -1, -1 },
[ POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED ] = { 262, 260, 254, 248, -1, -1 },
[ POWER7_PME_PM_L3_PREF_HIT ] = { -1, -1, 103, -1, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD ] = { 206, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_FXU_FIN ] = { -1, 193, -1, -1, -1, -1 },
[ POWER7_PME_PM_PMC4_OVERFLOW ] = { 219, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_PTEG_FROM_L3 ] = { -1, 204, -1, -1, -1, -1 },
[ POWER7_PME_PM_LSU0_LMQ_LHR_MERGE ] = { 161, 155, 155, 148, -1, -1 },
[ POWER7_PME_PM_BTAC_HIT ] = { 17, 15, 15, 16, -1, -1 },
[ POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS ] = { 79, 75, 73, 73, -1, -1 },
[ POWER7_PME_PM_L3_RD_BUSY ] = { -1, -1, -1, 101, -1, -1 },
[ POWER7_PME_PM_INST_FROM_L2MISS ] = { -1, -1, -1, 79, -1, -1 },
[ POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC ] = { 151, 145, 145, 138, -1, -1 },
[ POWER7_PME_PM_L2_ST ] = { 108, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_DENORM ] = { 276, 274, 268, 262, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { -1, -1, 179, -1, -1, -1 },
[ POWER7_PME_PM_BR_PRED_CR_TA ] = { 12, 10, 11, 12, -1, -1 },
[ POWER7_PME_PM_VSU0_FCONV ] = { 277, 275, 269, 263, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_FLUSH_ULD ] = { 201, 199, 192, 190, -1, -1 },
[ POWER7_PME_PM_BTAC_MISS ] = { 18, 16, 16, 17, -1, -1 },
[ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT ] = { 197, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L2 ] = { 185, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU_FMA ] = { 257, 255, 249, 243, -1, -1 },
[ POWER7_PME_PM_LSU0_FLUSH_SRQ ] = { 155, 149, 149, 142, -1, -1 },
[ POWER7_PME_PM_LSU1_L1_PREF ] = { 173, 167, 167, 160, -1, -1 },
[ POWER7_PME_PM_IOPS_CMPL ] = { 94, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_SYS_PUMP ] = { -1, -1, 102, -1, -1, -1 },
[ POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL ] = { -1, -1, -1, 91, -1, -1 },
[ POWER7_PME_PM_BCPLUS8_RSLV_TAKEN ] = { 3, 1, 2, 2, -1, -1 },
[ POWER7_PME_PM_NEST_5 ] = { 214, 214, 209, 204, -1, -1 },
[ POWER7_PME_PM_LSU_LMQ_S0_ALLOC ] = { 132, 126, 127, 120, -1, -1 },
[ POWER7_PME_PM_FLUSH_DISP_SYNC ] = { 46, 47, 45, 44, -1, -1 },
[ POWER7_PME_PM_L2_IC_INV ] = { -1, 96, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = { -1, -1, -1, 172, -1, -1 },
[ POWER7_PME_PM_L3_PREF_LDST ] = { 112, 106, 105, 99, -1, -1 },
[ POWER7_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 131, -1, -1 },
[ POWER7_PME_PM_LSU_LMQ_S0_VALID ] = { 133, 127, 128, 121, -1, -1 },
[ POWER7_PME_PM_FLUSH_PARTIAL ] = { 48, 49, 47, 46, -1, -1 },
[ POWER7_PME_PM_VSU1_FMA_DOUBLE ] = { 305, 303, 297, 291, -1, -1 },
[ POWER7_PME_PM_1PLUS_PPC_DISP ] = { -1, -1, -1, 0, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_L2MISS ] = { -1, 25, -1, 26, -1, -1 },
[ POWER7_PME_PM_SUSPENDED ] = { 236, 236, 231, 225, -1, -1 },
[ POWER7_PME_PM_VSU0_FMA ] = { 280, 278, 272, 266, -1, -1 },
[ POWER7_PME_PM_CMPLU_STALL_SCALAR ] = { -1, -1, -1, 22, -1, -1 },
[ POWER7_PME_PM_STCX_FAIL ] = { 235, 235, 230, 224, -1, -1 },
[ POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE ] = { 285, 283, 277, 271, -1, -1 },
[ POWER7_PME_PM_DC_PREF_DST ] = { 29, 30, 26, 28, -1, -1 },
[ POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED ] = { 311, 309, 303, 297, -1, -1 },
[ POWER7_PME_PM_L3_HIT ] = { 109, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_L2_GLOB_GUESS_WRONG ] = { -1, 95, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DFU_FIN ] = { -1, 191, -1, -1, -1, -1 },
[ POWER7_PME_PM_INST_FROM_L1 ] = { 82, 79, 78, 77, -1, -1 },
[ POWER7_PME_PM_BRU_FIN ] = { 16, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_IC_DEMAND_REQ ] = { 67, 64, 62, 62, -1, -1 },
[ POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE ] = { 308, 306, 300, 294, -1, -1 },
[ POWER7_PME_PM_VSU1_FMA ] = { 304, 302, 296, 290, -1, -1 },
[ POWER7_PME_PM_MRK_LD_MISS_L1 ] = { -1, 195, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU0_2FLOP_DOUBLE ] = { 272, 270, 264, 258, -1, -1 },
[ POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM ] = { 122, 116, 116, 111, -1, -1 },
[ POWER7_PME_PM_INST_PTEG_FROM_L31_SHR ] = { -1, 86, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = { -1, -1, 195, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_L2MISS ] = { -1, -1, -1, 174, -1, -1 },
[ POWER7_PME_PM_DATA_FROM_RL2L3_SHR ] = { 28, 29, -1, -1, -1, -1 },
[ POWER7_PME_PM_INST_FROM_PREF ] = { 87, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU1_SQ ] = { 313, 311, 305, 299, -1, -1 },
[ POWER7_PME_PM_L2_LD_DISP ] = { -1, -1, 95, -1, -1, -1 },
[ POWER7_PME_PM_L2_DISP_ALL ] = { -1, -1, -1, 90, -1, -1 },
[ POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { 241, -1, -1, -1, -1, -1 },
[ POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE ] = { 261, 259, 253, 247, -1, -1 },
[ POWER7_PME_PM_BR_MPRED ] = { -1, -1, -1, 3, -1, -1 },
[ POWER7_PME_PM_VSU_1FLOP ] = { 248, 246, 240, 234, -1, -1 },
[ POWER7_PME_PM_HV_CYC ] = { -1, 58, -1, -1, -1, -1 },
[ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { 190, 188, -1, -1, -1, -1 },
[ POWER7_PME_PM_DTLB_MISS_16M ] = { -1, -1, -1, 38, -1, -1 },
[ POWER7_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, 186, -1, -1 },
[ POWER7_PME_PM_LSU1_LMQ_LHR_MERGE ] = { 176, 170, 170, 163, -1, -1 },
[ POWER7_PME_PM_IFU_FIN ] = { -1, -1, -1, 74, -1, -1 }
};
static const unsigned long long power7_group_vecs[][POWER7_NUM_GROUP_VEC] = {
[ POWER7_PME_PM_NEST_4 ] = {
0x2000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_IC_DEMAND_L2_BR_ALL ] = {
0x0000000000000000ULL,
0x0000000000040000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_PMC2_SAVED ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000001000ULL
},
[ POWER7_PME_PM_CMPLU_STALL_DFU ] = {
0x0000000000000000ULL,
0x0000000004000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU0_16FLOP ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000008ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_NEST_3 ] = {
0x2000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_LSU_DERAT_MISS ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000800000000000ULL
},
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[ POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0008000000000000ULL
},
[ POWER7_PME_PM_MRK_FXU_FIN ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0040000000000000ULL
},
[ POWER7_PME_PM_PMC4_OVERFLOW ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000200ULL
},
[ POWER7_PME_PM_MRK_PTEG_FROM_L3 ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0008000000000000ULL
},
[ POWER7_PME_PM_LSU0_LMQ_LHR_MERGE ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000400000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_BTAC_HIT ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x1000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000020ULL
},
[ POWER7_PME_PM_L3_RD_BUSY ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0004000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_INST_FROM_L2MISS ] = {
0x0000000000000000ULL,
0x0005880000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0040000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_L2_ST ] = {
0x0200000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU0_DENORM ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000001ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000008000000ULL
},
[ POWER7_PME_PM_BR_PRED_CR_TA ] = {
0x0000000000000020ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU0_FCONV ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000001000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_LSU_FLUSH_ULD ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000004000000000ULL
},
[ POWER7_PME_PM_BTAC_MISS ] = {
0x0000000000000800ULL,
0x0000000000000000ULL,
0x1000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000002000000000ULL
},
[ POWER7_PME_PM_MRK_DATA_FROM_L2 ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000090000000ULL
},
[ POWER7_PME_PM_VSU_FMA ] = {
0x0000000000000000ULL,
0x2000000000000000ULL,
0x0000000000030000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_LSU0_FLUSH_SRQ ] = {
0x0000040000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_LSU1_L1_PREF ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000008000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_IOPS_CMPL ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000200000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_L2_SYS_PUMP ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000002ULL
},
[ POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL ] = {
0x0040000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_BCPLUS8_RSLV_TAKEN ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x2000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_NEST_5 ] = {
0x4000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_LSU_LMQ_S0_ALLOC ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000004000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_FLUSH_DISP_SYNC ] = {
0x0000000800000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_L2_IC_INV ] = {
0x0000000000000000ULL,
0x0000000000000800ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000002000000000ULL
},
[ POWER7_PME_PM_L3_PREF_LDST ] = {
0x0000000000000000ULL,
0x0100000000000000ULL,
0x0004000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
0x0000000000000000ULL,
0x0000000000000010ULL,
0x0000000000100000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_LSU_LMQ_S0_VALID ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000002400000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_FLUSH_PARTIAL ] = {
0x0000001000000000ULL,
0x0000000000000000ULL,
0x0000004000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU1_FMA_DOUBLE ] = {
0x0000000000000000ULL,
0x4000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_1PLUS_PPC_DISP ] = {
0x0000000000000000ULL,
0x0000000000031001ULL,
0x0000000100000000ULL,
0x0000000000040000ULL
},
[ POWER7_PME_PM_DATA_FROM_L2MISS ] = {
0x0000000000008000ULL,
0x0000005260000000ULL,
0x0000000000000000ULL,
0x0000000000100000ULL
},
[ POWER7_PME_PM_SUSPENDED ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000100000000000ULL,
0x0000000000400000ULL
},
[ POWER7_PME_PM_VSU0_FMA ] = {
0x0000000000000000ULL,
0x2000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_CMPLU_STALL_SCALAR ] = {
0x0000000000000000ULL,
0x0000000001000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_STCX_FAIL ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x1800000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000020ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_DC_PREF_DST ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0040000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000080ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_L3_HIT ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0001000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_L2_GLOB_GUESS_WRONG ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000020000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_DFU_FIN ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0200000000000000ULL
},
[ POWER7_PME_PM_INST_FROM_L1 ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000040000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_BRU_FIN ] = {
0x0000000000000008ULL,
0x0000000000000000ULL,
0x0000000000008000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_IC_DEMAND_REQ ] = {
0x8000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000020ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU1_FMA ] = {
0x0000000000000000ULL,
0x2000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_LD_MISS_L1 ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000004000000ULL
},
[ POWER7_PME_PM_VSU0_2FLOP_DOUBLE ] = {
0x0000000000000000ULL,
0x1000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM ] = {
0x0000000000000000ULL,
0x0200000000000000ULL,
0x0020000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_INST_PTEG_FROM_L31_SHR ] = {
0x0000000004000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0800000000000000ULL
},
[ POWER7_PME_PM_MRK_DATA_FROM_L2MISS ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000010000000ULL
},
[ POWER7_PME_PM_DATA_FROM_RL2L3_SHR ] = {
0x0000000000000000ULL,
0x0000002680000004ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_INST_FROM_PREF ] = {
0x0000000000000000ULL,
0x0009000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU1_SQ ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000800ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_L2_LD_DISP ] = {
0x0800000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_L2_DISP_ALL ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x8000000000000000ULL,
0x0000000000000001ULL
},
[ POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = {
0x0000200000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000020ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_BR_MPRED ] = {
0x0000000000000008ULL,
0x0000000000000000ULL,
0x0000046400000000ULL,
0x0000000002000000ULL
},
[ POWER7_PME_PM_VSU_1FLOP ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000070100ULL,
0x2000000000000000ULL
},
[ POWER7_PME_PM_HV_CYC ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000001100000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000040000000ULL
},
[ POWER7_PME_PM_DTLB_MISS_16M ] = {
0x0000000000001000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_MRK_LSU_FIN ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000000000ULL,
0x10c0000000000000ULL
},
[ POWER7_PME_PM_LSU1_LMQ_LHR_MERGE ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000000000400000ULL,
0x0000000000000000ULL
},
[ POWER7_PME_PM_IFU_FIN ] = {
0x0000000000000000ULL,
0x0000000000000000ULL,
0x0000081000000000ULL,
0x0000000000000000ULL
}
};
static const pme_power_entry_t power7_pe[] = {
[ POWER7_PME_PM_NEST_4 ] = {
.pme_name = "PM_NEST_4",
.pme_code = 0x87,
.pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_4],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_4]
},
[ POWER7_PME_PM_IC_DEMAND_L2_BR_ALL ] = {
.pme_name = "PM_IC_DEMAND_L2_BR_ALL",
.pme_code = 0x4898,
.pme_short_desc = " L2 I cache demand request due to BHT or redirect",
.pme_long_desc = " L2 I cache demand request due to BHT or redirect",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_L2_BR_ALL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_L2_BR_ALL]
},
[ POWER7_PME_PM_PMC2_SAVED ] = {
.pme_name = "PM_PMC2_SAVED",
.pme_code = 0x10022,
.pme_short_desc = "PMC2 Rewind Value saved",
.pme_long_desc = "PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC2_SAVED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC2_SAVED]
},
[ POWER7_PME_PM_CMPLU_STALL_DFU ] = {
.pme_name = "PM_CMPLU_STALL_DFU",
.pme_code = 0x2003c,
.pme_short_desc = "Completion stall caused by Decimal Floating Point Unit",
.pme_long_desc = "Completion stall caused by Decimal Floating Point Unit",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_DFU],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_DFU]
},
[ POWER7_PME_PM_VSU0_16FLOP ] = {
.pme_name = "PM_VSU0_16FLOP",
.pme_code = 0xa0a4,
.pme_short_desc = "Sixteen flops operation (SP vector versions of fdiv",
.pme_long_desc = "fsqrt) ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_16FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_16FLOP]
},
[ POWER7_PME_PM_NEST_3 ] = {
.pme_name = "PM_NEST_3",
.pme_code = 0x85,
.pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_3],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_3]
},
[ POWER7_PME_PM_MRK_LSU_DERAT_MISS ] = {
.pme_name = "PM_MRK_LSU_DERAT_MISS",
.pme_code = 0x3d05a,
.pme_short_desc = "Marked DERAT Miss",
.pme_long_desc = "Marked DERAT Miss",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_DERAT_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_DERAT_MISS]
},
[ POWER7_PME_PM_MRK_ST_CMPL ] = {
.pme_name = "PM_MRK_ST_CMPL",
.pme_code = 0x10034,
.pme_short_desc = "marked store finished (was complete)",
.pme_long_desc = "A sampled store has completed (data home)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_ST_CMPL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_ST_CMPL]
},
[ POWER7_PME_PM_L2_ST_DISP ] = {
.pme_name = "PM_L2_ST_DISP",
.pme_code = 0x46180,
.pme_short_desc = "All successful store dispatches",
.pme_long_desc = "All successful store dispatches",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_ST_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_ST_DISP]
},
[ POWER7_PME_PM_L2_CASTOUT_MOD ] = {
.pme_name = "PM_L2_CASTOUT_MOD",
.pme_code = 0x16180,
.pme_short_desc = "L2 Castouts - Modified (M",
.pme_long_desc = " Mu",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_CASTOUT_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_CASTOUT_MOD]
},
[ POWER7_PME_PM_ISEG ] = {
.pme_name = "PM_ISEG",
.pme_code = 0x20a4,
.pme_short_desc = "ISEG Exception",
.pme_long_desc = "ISEG Exception",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_ISEG],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_ISEG]
},
[ POWER7_PME_PM_MRK_INST_TIMEO ] = {
.pme_name = "PM_MRK_INST_TIMEO",
.pme_code = 0x40034,
.pme_short_desc = "marked Instruction finish timeout ",
.pme_long_desc = "The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_INST_TIMEO],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_INST_TIMEO]
},
[ POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2_RCST_DISP_FAIL_ADDR",
.pme_code = 0x36282,
.pme_short_desc = " L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_long_desc = " L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR]
},
[ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM ] = {
.pme_name = "PM_LSU1_DC_PREF_STREAM_CONFIRM",
.pme_code = 0xd0b6,
.pme_short_desc = "LS1 'Dcache prefetch stream confirmed",
.pme_long_desc = "LS1 'Dcache prefetch stream confirmed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM]
},
[ POWER7_PME_PM_IERAT_WR_64K ] = {
.pme_name = "PM_IERAT_WR_64K",
.pme_code = 0x40be,
.pme_short_desc = "large page 64k ",
.pme_long_desc = "large page 64k ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IERAT_WR_64K],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IERAT_WR_64K]
},
[ POWER7_PME_PM_MRK_DTLB_MISS_16M ] = {
.pme_name = "PM_MRK_DTLB_MISS_16M",
.pme_code = 0x4d05e,
.pme_short_desc = "Marked Data TLB misses for 16M page",
.pme_long_desc = "Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DTLB_MISS_16M],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DTLB_MISS_16M]
},
[ POWER7_PME_PM_IERAT_MISS ] = {
.pme_name = "PM_IERAT_MISS",
.pme_code = 0x100f6,
.pme_short_desc = "IERAT Miss (Not implemented as DI on POWER6)",
.pme_long_desc = "A translation request missed the Instruction Effective to Real Address Translation (ERAT) table",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IERAT_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IERAT_MISS]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_LMEM ] = {
.pme_name = "PM_MRK_PTEG_FROM_LMEM",
.pme_code = 0x4d052,
.pme_short_desc = "Marked PTEG loaded from local memory",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on due to a marked load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_LMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_LMEM]
},
[ POWER7_PME_PM_FLOP ] = {
.pme_name = "PM_FLOP",
.pme_code = 0x100f4,
.pme_short_desc = "Floating Point Operation Finished",
.pme_long_desc = "A floating point operation has completed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLOP]
},
[ POWER7_PME_PM_THRD_PRIO_4_5_CYC ] = {
.pme_name = "PM_THRD_PRIO_4_5_CYC",
.pme_code = 0x40b4,
.pme_short_desc = " Cycles thread running at priority level 4 or 5",
.pme_long_desc = " Cycles thread running at priority level 4 or 5",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_PRIO_4_5_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_PRIO_4_5_CYC]
},
[ POWER7_PME_PM_BR_PRED_TA ] = {
.pme_name = "PM_BR_PRED_TA",
.pme_code = 0x40aa,
.pme_short_desc = "Branch predict - target address",
.pme_long_desc = "The target address of a branch instruction was predicted.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_TA],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_TA]
},
[ POWER7_PME_PM_CMPLU_STALL_FXU ] = {
.pme_name = "PM_CMPLU_STALL_FXU",
.pme_code = 0x20014,
.pme_short_desc = "Completion stall caused by FXU instruction",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_FXU],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_FXU]
},
[ POWER7_PME_PM_EXT_INT ] = {
.pme_name = "PM_EXT_INT",
.pme_code = 0x200f8,
.pme_short_desc = "external interrupt",
.pme_long_desc = "An interrupt due to an external exception occurred",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_EXT_INT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_EXT_INT]
},
[ POWER7_PME_PM_VSU_FSQRT_FDIV ] = {
.pme_name = "PM_VSU_FSQRT_FDIV",
.pme_code = 0xa888,
.pme_short_desc = "four flops operation (fdiv",
.pme_long_desc = "fsqrt) Scalar Instructions only!",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FSQRT_FDIV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FSQRT_FDIV]
},
[ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = {
.pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC",
.pme_code = 0x1003e,
.pme_short_desc = "Marked Load exposed Miss ",
.pme_long_desc = "Marked Load exposed Miss ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC]
},
[ POWER7_PME_PM_LSU1_LDF ] = {
.pme_name = "PM_LSU1_LDF",
.pme_code = 0xc086,
.pme_short_desc = "LS1 Scalar Loads ",
.pme_long_desc = "A floating point load was executed by LSU1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_LDF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_LDF]
},
[ POWER7_PME_PM_IC_WRITE_ALL ] = {
.pme_name = "PM_IC_WRITE_ALL",
.pme_code = 0x488c,
.pme_short_desc = "Icache sectors written",
.pme_long_desc = " prefetch + demand",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_WRITE_ALL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_WRITE_ALL]
},
[ POWER7_PME_PM_LSU0_SRQ_STFWD ] = {
.pme_name = "PM_LSU0_SRQ_STFWD",
.pme_code = 0xc0a0,
.pme_short_desc = "LS0 SRQ forwarded data to a load",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_SRQ_STFWD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_SRQ_STFWD]
},
[ POWER7_PME_PM_PTEG_FROM_RL2L3_MOD ] = {
.pme_name = "PM_PTEG_FROM_RL2L3_MOD",
.pme_code = 0x1c052,
.pme_short_desc = "PTEG loaded from remote L2 or L3 modified",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_RL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_RL2L3_MOD]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L31_SHR",
.pme_code = 0x1d04e,
.pme_short_desc = "Marked data loaded from another L3 on same chip shared",
.pme_long_desc = "Marked data loaded from another L3 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L31_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L31_SHR]
},
[ POWER7_PME_PM_DATA_FROM_L21_MOD ] = {
.pme_name = "PM_DATA_FROM_L21_MOD",
.pme_code = 0x3c046,
.pme_short_desc = "Data loaded from another L2 on same chip modified",
.pme_long_desc = "Data loaded from another L2 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L21_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L21_MOD]
},
[ POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED ] = {
.pme_name = "PM_VSU1_SCAL_DOUBLE_ISSUED",
.pme_code = 0xb08a,
.pme_short_desc = "Double Precision scalar instruction issued on Pipe1",
.pme_long_desc = "Double Precision scalar instruction issued on Pipe1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED]
},
[ POWER7_PME_PM_VSU0_8FLOP ] = {
.pme_name = "PM_VSU0_8FLOP",
.pme_code = 0xa0a0,
.pme_short_desc = "eight flops operation (DP vector versions of fdiv",
.pme_long_desc = "fsqrt and SP vector versions of fmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_8FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_8FLOP]
},
[ POWER7_PME_PM_POWER_EVENT1 ] = {
.pme_name = "PM_POWER_EVENT1",
.pme_code = 0x1006e,
.pme_short_desc = "Power Management Event 1",
.pme_long_desc = "Power Management Event 1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_POWER_EVENT1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_POWER_EVENT1]
},
[ POWER7_PME_PM_DISP_CLB_HELD_BAL ] = {
.pme_name = "PM_DISP_CLB_HELD_BAL",
.pme_code = 0x2092,
.pme_short_desc = "Dispatch/CLB Hold: Balance",
.pme_long_desc = "Dispatch/CLB Hold: Balance",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_BAL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_BAL]
},
[ POWER7_PME_PM_VSU1_2FLOP ] = {
.pme_name = "PM_VSU1_2FLOP",
.pme_code = 0xa09a,
.pme_short_desc = "two flops operation (scalar fmadd",
.pme_long_desc = " fnmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_2FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_2FLOP]
},
[ POWER7_PME_PM_LWSYNC_HELD ] = {
.pme_name = "PM_LWSYNC_HELD",
.pme_code = 0x209a,
.pme_short_desc = "LWSYNC held at dispatch",
.pme_long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LWSYNC_HELD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LWSYNC_HELD]
},
[ POWER7_PME_PM_INST_FROM_L21_MOD ] = {
.pme_name = "PM_INST_FROM_L21_MOD",
.pme_code = 0x34046,
.pme_short_desc = "Instruction fetched from another L2 on same chip modified",
.pme_long_desc = "Instruction fetched from another L2 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L21_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L21_MOD]
},
[ POWER7_PME_PM_IC_REQ_ALL ] = {
.pme_name = "PM_IC_REQ_ALL",
.pme_code = 0x4888,
.pme_short_desc = "Icache requests",
.pme_long_desc = " prefetch + demand",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_REQ_ALL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_REQ_ALL]
},
[ POWER7_PME_PM_DSLB_MISS ] = {
.pme_name = "PM_DSLB_MISS",
.pme_code = 0xd090,
.pme_short_desc = "Data SLB Miss - Total of all segment sizes",
.pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DSLB_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DSLB_MISS]
},
[ POWER7_PME_PM_L3_MISS ] = {
.pme_name = "PM_L3_MISS",
.pme_code = 0x1f082,
.pme_short_desc = "L3 Misses ",
.pme_long_desc = "L3 Misses ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_MISS]
},
[ POWER7_PME_PM_LSU0_L1_PREF ] = {
.pme_name = "PM_LSU0_L1_PREF",
.pme_code = 0xd0b8,
.pme_short_desc = " LS0 L1 cache data prefetches",
.pme_long_desc = " LS0 L1 cache data prefetches",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_L1_PREF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_L1_PREF]
},
[ POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED ] = {
.pme_name = "PM_VSU_SCALAR_SINGLE_ISSUED",
.pme_code = 0xb884,
.pme_short_desc = "Single Precision scalar instruction issued on Pipe0",
.pme_long_desc = "Single Precision scalar instruction issued on Pipe0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED]
},
[ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE ] = {
.pme_name = "PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE",
.pme_code = 0xd0be,
.pme_short_desc = "LS1 Dcache Strided prefetch stream confirmed",
.pme_long_desc = "LS1 Dcache Strided prefetch stream confirmed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE]
},
[ POWER7_PME_PM_L2_INST ] = {
.pme_name = "PM_L2_INST",
.pme_code = 0x36080,
.pme_short_desc = "Instruction Load Count",
.pme_long_desc = "Instruction Load Count",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_INST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_INST]
},
[ POWER7_PME_PM_VSU0_FRSP ] = {
.pme_name = "PM_VSU0_FRSP",
.pme_code = 0xa0b4,
.pme_short_desc = "Round to single precision instruction executed",
.pme_long_desc = "Round to single precision instruction executed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FRSP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FRSP]
},
[ POWER7_PME_PM_FLUSH_DISP ] = {
.pme_name = "PM_FLUSH_DISP",
.pme_code = 0x2082,
.pme_short_desc = "Dispatch flush",
.pme_long_desc = "Dispatch flush",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_DISP]
},
[ POWER7_PME_PM_PTEG_FROM_L2MISS ] = {
.pme_name = "PM_PTEG_FROM_L2MISS",
.pme_code = 0x4c058,
.pme_short_desc = "PTEG loaded from L2 miss",
.pme_long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L2MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L2MISS]
},
[ POWER7_PME_PM_VSU1_DQ_ISSUED ] = {
.pme_name = "PM_VSU1_DQ_ISSUED",
.pme_code = 0xb09a,
.pme_short_desc = "128BIT Decimal Issued on Pipe1",
.pme_long_desc = "128BIT Decimal Issued on Pipe1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_DQ_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_DQ_ISSUED]
},
[ POWER7_PME_PM_CMPLU_STALL_LSU ] = {
.pme_name = "PM_CMPLU_STALL_LSU",
.pme_code = 0x20012,
.pme_short_desc = "Completion stall caused by LSU instruction",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_LSU],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_LSU]
},
[ POWER7_PME_PM_MRK_DATA_FROM_DMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_DMEM",
.pme_code = 0x1d04a,
.pme_short_desc = "Marked data loaded from distant memory",
.pme_long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DMEM]
},
[ POWER7_PME_PM_LSU_FLUSH_ULD ] = {
.pme_name = "PM_LSU_FLUSH_ULD",
.pme_code = 0xc8b0,
.pme_short_desc = "Flush: Unaligned Load",
.pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH_ULD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH_ULD]
},
[ POWER7_PME_PM_PTEG_FROM_LMEM ] = {
.pme_name = "PM_PTEG_FROM_LMEM",
.pme_code = 0x4c052,
.pme_short_desc = "PTEG loaded from local memory",
.pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_LMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_LMEM]
},
[ POWER7_PME_PM_MRK_DERAT_MISS_16M ] = {
.pme_name = "PM_MRK_DERAT_MISS_16M",
.pme_code = 0x3d05c,
.pme_short_desc = "Marked DERAT misses for 16M page",
.pme_long_desc = "A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DERAT_MISS_16M],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DERAT_MISS_16M]
},
[ POWER7_PME_PM_THRD_ALL_RUN_CYC ] = {
.pme_name = "PM_THRD_ALL_RUN_CYC",
.pme_code = 0x2000c,
.pme_short_desc = "All Threads in run_cycles",
.pme_long_desc = "Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_ALL_RUN_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_ALL_RUN_CYC]
},
[ POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT ] = {
.pme_name = "PM_MRK_STALL_CMPLU_CYC_COUNT",
.pme_code = 0x3003f,
.pme_short_desc = "Marked Group Completion Stall cycles (use edge detect to count #)",
.pme_long_desc = "Marked Group Completion Stall cycles (use edge detect to count #)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT]
},
[ POWER7_PME_PM_DATA_FROM_DL2L3_MOD ] = {
.pme_name = "PM_DATA_FROM_DL2L3_MOD",
.pme_code = 0x3c04c,
.pme_short_desc = "Data loaded from distant L2 or L3 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_DL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_DL2L3_MOD]
},
[ POWER7_PME_PM_VSU_FRSP ] = {
.pme_name = "PM_VSU_FRSP",
.pme_code = 0xa8b4,
.pme_short_desc = "Round to single precision instruction executed",
.pme_long_desc = "Round to single precision instruction executed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FRSP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FRSP]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L21_MOD",
.pme_code = 0x3d046,
.pme_short_desc = "Marked data loaded from another L2 on same chip modified",
.pme_long_desc = "Marked data loaded from another L2 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L21_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L21_MOD]
},
[ POWER7_PME_PM_PMC1_OVERFLOW ] = {
.pme_name = "PM_PMC1_OVERFLOW",
.pme_code = 0x20010,
.pme_short_desc = "Overflow from counter 1",
.pme_long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC1_OVERFLOW],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC1_OVERFLOW]
},
[ POWER7_PME_PM_VSU0_SINGLE ] = {
.pme_name = "PM_VSU0_SINGLE",
.pme_code = 0xa0a8,
.pme_short_desc = "FPU single precision",
.pme_long_desc = "VSU0 executed single precision instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_SINGLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_SINGLE]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_L3MISS ] = {
.pme_name = "PM_MRK_PTEG_FROM_L3MISS",
.pme_code = 0x2d058,
.pme_short_desc = "Marked PTEG loaded from L3 miss",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L3MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L3MISS]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR ] = {
.pme_name = "PM_MRK_PTEG_FROM_L31_SHR",
.pme_code = 0x2d056,
.pme_short_desc = "Marked PTEG loaded from another L3 on same chip shared",
.pme_long_desc = "Marked PTEG loaded from another L3 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR]
},
[ POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED ] = {
.pme_name = "PM_VSU0_VECTOR_SP_ISSUED",
.pme_code = 0xb090,
.pme_short_desc = "Single Precision vector instruction issued (executed)",
.pme_long_desc = "Single Precision vector instruction issued (executed)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED]
},
[ POWER7_PME_PM_VSU1_FEST ] = {
.pme_name = "PM_VSU1_FEST",
.pme_code = 0xa0ba,
.pme_short_desc = "Estimate instruction executed",
.pme_long_desc = "Estimate instruction executed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FEST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FEST]
},
[ POWER7_PME_PM_MRK_INST_DISP ] = {
.pme_name = "PM_MRK_INST_DISP",
.pme_code = 0x20030,
.pme_short_desc = "marked instruction dispatch",
.pme_long_desc = "A marked instruction was dispatched",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_INST_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_INST_DISP]
},
[ POWER7_PME_PM_VSU0_COMPLEX_ISSUED ] = {
.pme_name = "PM_VSU0_COMPLEX_ISSUED",
.pme_code = 0xb096,
.pme_short_desc = "Complex VMX instruction issued",
.pme_long_desc = "Complex VMX instruction issued",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_COMPLEX_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_COMPLEX_ISSUED]
},
[ POWER7_PME_PM_LSU1_FLUSH_UST ] = {
.pme_name = "PM_LSU1_FLUSH_UST",
.pme_code = 0xc0b6,
.pme_short_desc = "LS1 Flush: Unaligned Store",
.pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_FLUSH_UST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_FLUSH_UST]
},
[ POWER7_PME_PM_INST_CMPL ] = {
.pme_name = "PM_INST_CMPL",
.pme_code = 0x2,
.pme_short_desc = "# PPC Instructions Finished",
.pme_long_desc = "Number of PowerPC Instructions that completed.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_CMPL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_CMPL]
},
[ POWER7_PME_PM_FXU_IDLE ] = {
.pme_name = "PM_FXU_IDLE",
.pme_code = 0x1000e,
.pme_short_desc = "fxu0 idle and fxu1 idle",
.pme_long_desc = "FXU0 and FXU1 are both idle.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU_IDLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU_IDLE]
},
[ POWER7_PME_PM_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_LSU0_FLUSH_ULD",
.pme_code = 0xc0b0,
.pme_short_desc = "LS0 Flush: Unaligned Load",
.pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_FLUSH_ULD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_FLUSH_ULD]
},
[ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD",
.pme_code = 0x3d04c,
.pme_short_desc = "Marked data loaded from distant L2 or L3 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a marked load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD]
},
[ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC",
.pme_code = 0x3001c,
.pme_short_desc = "ALL threads lsu empty (lmq and srq empty)",
.pme_long_desc = "ALL threads lsu empty (lmq and srq empty)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC]
},
[ POWER7_PME_PM_LSU1_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU1_REJECT_LMQ_FULL",
.pme_code = 0xc0a6,
.pme_short_desc = "LS1 Reject: LMQ Full (LHR)",
.pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_REJECT_LMQ_FULL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_REJECT_LMQ_FULL]
},
[ POWER7_PME_PM_INST_PTEG_FROM_L21_MOD ] = {
.pme_name = "PM_INST_PTEG_FROM_L21_MOD",
.pme_code = 0x3e056,
.pme_short_desc = "Instruction PTEG loaded from another L2 on same chip modified",
.pme_long_desc = "Instruction PTEG loaded from another L2 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L21_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L21_MOD]
},
[ POWER7_PME_PM_GCT_UTIL_3TO6_SLOT ] = {
.pme_name = "PM_GCT_UTIL_3-6_SLOT",
.pme_code = 0x209e,
.pme_short_desc = "GCT Utilization 3-6 entries",
.pme_long_desc = "GCT Utilization 3-6 entries",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_UTIL_3TO6_SLOT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_UTIL_3TO6_SLOT]
},
[ POWER7_PME_PM_INST_FROM_RL2L3_MOD ] = {
.pme_name = "PM_INST_FROM_RL2L3_MOD",
.pme_code = 0x14042,
.pme_short_desc = "Instruction fetched from remote L2 or L3 modified",
.pme_long_desc = "An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_RL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_RL2L3_MOD]
},
[ POWER7_PME_PM_SHL_CREATED ] = {
.pme_name = "PM_SHL_CREATED",
.pme_code = 0x5082,
.pme_short_desc = "SHL table entry Created",
.pme_long_desc = "SHL table entry Created",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_SHL_CREATED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_SHL_CREATED]
},
[ POWER7_PME_PM_L2_ST_HIT ] = {
.pme_name = "PM_L2_ST_HIT",
.pme_code = 0x46182,
.pme_short_desc = "All successful store dispatches that were L2Hits",
.pme_long_desc = "A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Total for all slices.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_ST_HIT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_ST_HIT]
},
[ POWER7_PME_PM_DATA_FROM_DMEM ] = {
.pme_name = "PM_DATA_FROM_DMEM",
.pme_code = 0x1c04a,
.pme_short_desc = "Data loaded from distant memory",
.pme_long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_DMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_DMEM]
},
[ POWER7_PME_PM_L3_LD_MISS ] = {
.pme_name = "PM_L3_LD_MISS",
.pme_code = 0x2f082,
.pme_short_desc = "L3 demand LD Miss",
.pme_long_desc = "L3 demand LD Miss",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_LD_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_LD_MISS]
},
[ POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
.pme_name = "PM_FXU1_BUSY_FXU0_IDLE",
.pme_code = 0x4000e,
.pme_short_desc = "fxu0 idle and fxu1 busy. ",
.pme_long_desc = "FXU0 was idle while FXU1 was busy",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE]
},
[ POWER7_PME_PM_DISP_CLB_HELD_RES ] = {
.pme_name = "PM_DISP_CLB_HELD_RES",
.pme_code = 0x2094,
.pme_short_desc = "Dispatch/CLB Hold: Resource",
.pme_long_desc = "Dispatch/CLB Hold: Resource",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_RES],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_RES]
},
[ POWER7_PME_PM_L2_SN_SX_I_DONE ] = {
.pme_name = "PM_L2_SN_SX_I_DONE",
.pme_code = 0x36382,
.pme_short_desc = "SNP dispatched and went from Sx or Tx to Ix",
.pme_long_desc = "SNP dispatched and went from Sx or Tx to Ix",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_SN_SX_I_DONE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_SN_SX_I_DONE]
},
[ POWER7_PME_PM_GRP_CMPL ] = {
.pme_name = "PM_GRP_CMPL",
.pme_code = 0x30004,
.pme_short_desc = "group completed",
.pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_CMPL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_CMPL]
},
[ POWER7_PME_PM_BCPLUS8_CONV ] = {
.pme_name = "PM_BC+8_CONV",
.pme_code = 0x40b8,
.pme_short_desc = "BC+8 Converted",
.pme_long_desc = "BC+8 Converted",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BCPLUS8_CONV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BCPLUS8_CONV]
},
[ POWER7_PME_PM_STCX_CMPL ] = {
.pme_name = "PM_STCX_CMPL",
.pme_code = 0xc098,
.pme_short_desc = "STCX executed",
.pme_long_desc = "Conditional stores with reservation completed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_STCX_CMPL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_STCX_CMPL]
},
[ POWER7_PME_PM_VSU0_2FLOP ] = {
.pme_name = "PM_VSU0_2FLOP",
.pme_code = 0xa098,
.pme_short_desc = "two flops operation (scalar fmadd",
.pme_long_desc = " fnmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_2FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_2FLOP]
},
[ POWER7_PME_PM_L3_PREF_MISS ] = {
.pme_name = "PM_L3_PREF_MISS",
.pme_code = 0x3f082,
.pme_short_desc = "L3 Prefetch Directory Miss",
.pme_long_desc = "L3 Prefetch Directory Miss",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_MISS]
},
[ POWER7_PME_PM_LSU_SRQ_SYNC_CYC ] = {
.pme_name = "PM_LSU_SRQ_SYNC_CYC",
.pme_code = 0xd096,
.pme_short_desc = "A sync is in the SRQ",
.pme_long_desc = "Cycles that a sync instruction is active in the Store Request Queue.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_SYNC_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_SYNC_CYC]
},
[ POWER7_PME_PM_LSU_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU_REJECT_ERAT_MISS",
.pme_code = 0x20064,
.pme_short_desc = "LSU Reject due to ERAT (up to 2 per cycles)",
.pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT_ERAT_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT_ERAT_MISS]
},
[ POWER7_PME_PM_L1_ICACHE_MISS ] = {
.pme_name = "PM_L1_ICACHE_MISS",
.pme_code = 0x200fc,
.pme_short_desc = "Demand iCache Miss",
.pme_long_desc = "An instruction fetch request missed the L1 cache.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L1_ICACHE_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L1_ICACHE_MISS]
},
[ POWER7_PME_PM_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_LSU1_FLUSH_SRQ",
.pme_code = 0xc0be,
.pme_short_desc = "LS1 Flush: SRQ",
.pme_long_desc = "Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_FLUSH_SRQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_FLUSH_SRQ]
},
[ POWER7_PME_PM_LD_REF_L1_LSU0 ] = {
.pme_name = "PM_LD_REF_L1_LSU0",
.pme_code = 0xc080,
.pme_short_desc = "LS0 L1 D cache load references counted at finish",
.pme_long_desc = "Load references to Level 1 Data Cache, by unit 0.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LD_REF_L1_LSU0],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LD_REF_L1_LSU0]
},
[ POWER7_PME_PM_VSU0_FEST ] = {
.pme_name = "PM_VSU0_FEST",
.pme_code = 0xa0b8,
.pme_short_desc = "Estimate instruction executed",
.pme_long_desc = "Estimate instruction executed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FEST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FEST]
},
[ POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED ] = {
.pme_name = "PM_VSU_VECTOR_SINGLE_ISSUED",
.pme_code = 0xb890,
.pme_short_desc = "Single Precision vector instruction issued (executed)",
.pme_long_desc = "Single Precision vector instruction issued (executed)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED]
},
[ POWER7_PME_PM_FREQ_UP ] = {
.pme_name = "PM_FREQ_UP",
.pme_code = 0x4000c,
.pme_short_desc = "Power Management: Above Threshold A",
.pme_long_desc = "Processor frequency was sped up due to power management",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FREQ_UP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FREQ_UP]
},
[ POWER7_PME_PM_DATA_FROM_LMEM ] = {
.pme_name = "PM_DATA_FROM_LMEM",
.pme_code = 0x3c04a,
.pme_short_desc = "Data loaded from local memory",
.pme_long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_LMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_LMEM]
},
[ POWER7_PME_PM_LSU1_LDX ] = {
.pme_name = "PM_LSU1_LDX",
.pme_code = 0xc08a,
.pme_short_desc = "LS1 Vector Loads",
.pme_long_desc = "LS1 Vector Loads",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_LDX],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_LDX]
},
[ POWER7_PME_PM_PMC3_OVERFLOW ] = {
.pme_name = "PM_PMC3_OVERFLOW",
.pme_code = 0x40010,
.pme_short_desc = "Overflow from counter 3",
.pme_long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC3_OVERFLOW],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC3_OVERFLOW]
},
[ POWER7_PME_PM_MRK_BR_MPRED ] = {
.pme_name = "PM_MRK_BR_MPRED",
.pme_code = 0x30036,
.pme_short_desc = "Marked Branch Mispredicted",
.pme_long_desc = "A marked branch was mispredicted",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_BR_MPRED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_BR_MPRED]
},
[ POWER7_PME_PM_SHL_MATCH ] = {
.pme_name = "PM_SHL_MATCH",
.pme_code = 0x5086,
.pme_short_desc = "SHL Table Match",
.pme_long_desc = "SHL Table Match",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_SHL_MATCH],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_SHL_MATCH]
},
[ POWER7_PME_PM_MRK_BR_TAKEN ] = {
.pme_name = "PM_MRK_BR_TAKEN",
.pme_code = 0x10036,
.pme_short_desc = "Marked Branch Taken",
.pme_long_desc = "A marked branch was taken",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_BR_TAKEN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_BR_TAKEN]
},
[ POWER7_PME_PM_ISLB_MISS ] = {
.pme_name = "PM_ISLB_MISS",
.pme_code = 0xd092,
.pme_short_desc = "Instruction SLB Miss - Tota of all segment sizes",
.pme_long_desc = "A SLB miss for an instruction fetch as occurred",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_ISLB_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_ISLB_MISS]
},
[ POWER7_PME_PM_CYC ] = {
.pme_name = "PM_CYC",
.pme_code = 0x1e,
.pme_short_desc = "Cycles",
.pme_long_desc = "Processor Cycles",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CYC]
},
[ POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_DRL2L3_MOD_CYC",
.pme_code = 0x4002a,
.pme_short_desc = "Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node)",
.pme_long_desc = "Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC]
},
[ POWER7_PME_PM_DISP_HELD_THERMAL ] = {
.pme_name = "PM_DISP_HELD_THERMAL",
.pme_code = 0x30006,
.pme_short_desc = "Dispatch Held due to Thermal",
.pme_long_desc = "Dispatch Held due to Thermal",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_HELD_THERMAL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_HELD_THERMAL]
},
[ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR ] = {
.pme_name = "PM_INST_PTEG_FROM_RL2L3_SHR",
.pme_code = 0x2e054,
.pme_short_desc = "Instruction PTEG loaded from remote L2 or L3 shared",
.pme_long_desc = "Instruction PTEG loaded from remote L2 or L3 shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR]
},
[ POWER7_PME_PM_LSU1_SRQ_STFWD ] = {
.pme_name = "PM_LSU1_SRQ_STFWD",
.pme_code = 0xc0a2,
.pme_short_desc = "LS1 SRQ forwarded data to a load",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_SRQ_STFWD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_SRQ_STFWD]
},
[ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED ] = {
.pme_name = "PM_GCT_NOSLOT_BR_MPRED",
.pme_code = 0x4001a,
.pme_short_desc = "GCT empty by branch mispredict",
.pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_NOSLOT_BR_MPRED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_NOSLOT_BR_MPRED]
},
[ POWER7_PME_PM_1PLUS_PPC_CMPL ] = {
.pme_name = "PM_1PLUS_PPC_CMPL",
.pme_code = 0x100f2,
.pme_short_desc = "1 or more ppc insts finished",
.pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_1PLUS_PPC_CMPL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_1PLUS_PPC_CMPL]
},
[ POWER7_PME_PM_PTEG_FROM_DMEM ] = {
.pme_name = "PM_PTEG_FROM_DMEM",
.pme_code = 0x2c052,
.pme_short_desc = "PTEG loaded from distant memory",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_DMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_DMEM]
},
[ POWER7_PME_PM_VSU_2FLOP ] = {
.pme_name = "PM_VSU_2FLOP",
.pme_code = 0xa898,
.pme_short_desc = "two flops operation (scalar fmadd",
.pme_long_desc = " fnmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_2FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_2FLOP]
},
[ POWER7_PME_PM_GCT_FULL_CYC ] = {
.pme_name = "PM_GCT_FULL_CYC",
.pme_code = 0x4086,
.pme_short_desc = "Cycles No room in EAT",
.pme_long_desc = "The Global Completion Table is completely full.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_FULL_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_FULL_CYC]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L3_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L3_CYC",
.pme_code = 0x40020,
.pme_short_desc = "Marked ld latency Data source 0001 (L3)",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L3_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L3_CYC]
},
[ POWER7_PME_PM_LSU_SRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_SRQ_S0_ALLOC",
.pme_code = 0xd09d,
.pme_short_desc = "Slot 0 of SRQ valid",
.pme_long_desc = "Slot 0 of SRQ valid",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_S0_ALLOC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_S0_ALLOC]
},
[ POWER7_PME_PM_MRK_DERAT_MISS_4K ] = {
.pme_name = "PM_MRK_DERAT_MISS_4K",
.pme_code = 0x1d05c,
.pme_short_desc = "Marked DERAT misses for 4K page",
.pme_long_desc = "A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DERAT_MISS_4K],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DERAT_MISS_4K]
},
[ POWER7_PME_PM_BR_MPRED_TA ] = {
.pme_name = "PM_BR_MPRED_TA",
.pme_code = 0x40ae,
.pme_short_desc = "Branch mispredict - target address",
.pme_long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_TA],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_TA]
},
[ POWER7_PME_PM_INST_PTEG_FROM_L2MISS ] = {
.pme_name = "PM_INST_PTEG_FROM_L2MISS",
.pme_code = 0x4e058,
.pme_short_desc = "Instruction PTEG loaded from L2 miss",
.pme_long_desc = "Instruction PTEG loaded from L2 miss",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L2MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L2MISS]
},
[ POWER7_PME_PM_DPU_HELD_POWER ] = {
.pme_name = "PM_DPU_HELD_POWER",
.pme_code = 0x20006,
.pme_short_desc = "Dispatch Held due to Power Management",
.pme_long_desc = "Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DPU_HELD_POWER],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DPU_HELD_POWER]
},
[ POWER7_PME_PM_RUN_INST_CMPL ] = {
.pme_name = "PM_RUN_INST_CMPL",
.pme_code = 0x400fa,
.pme_short_desc = "Run_Instructions",
.pme_long_desc = "Number of run instructions completed. ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_RUN_INST_CMPL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_RUN_INST_CMPL]
},
[ POWER7_PME_PM_MRK_VSU_FIN ] = {
.pme_name = "PM_MRK_VSU_FIN",
.pme_code = 0x30032,
.pme_short_desc = "vsu (fpu) marked instr finish",
.pme_long_desc = "vsu (fpu) marked instr finish",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_VSU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_VSU_FIN]
},
[ POWER7_PME_PM_LSU_SRQ_S0_VALID ] = {
.pme_name = "PM_LSU_SRQ_S0_VALID",
.pme_code = 0xd09c,
.pme_short_desc = "Slot 0 of SRQ valid",
.pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_S0_VALID],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_S0_VALID]
},
[ POWER7_PME_PM_GCT_EMPTY_CYC ] = {
.pme_name = "PM_GCT_EMPTY_CYC",
.pme_code = 0x20008,
.pme_short_desc = "GCT empty",
.pme_long_desc = " all threads",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_EMPTY_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_EMPTY_CYC]
},
[ POWER7_PME_PM_IOPS_DISP ] = {
.pme_name = "PM_IOPS_DISP",
.pme_code = 0x30014,
.pme_short_desc = "IOPS dispatched",
.pme_long_desc = "IOPS dispatched",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IOPS_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IOPS_DISP]
},
[ POWER7_PME_PM_RUN_SPURR ] = {
.pme_name = "PM_RUN_SPURR",
.pme_code = 0x10008,
.pme_short_desc = "Run SPURR",
.pme_long_desc = "Run SPURR",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_RUN_SPURR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_RUN_SPURR]
},
[ POWER7_PME_PM_PTEG_FROM_L21_MOD ] = {
.pme_name = "PM_PTEG_FROM_L21_MOD",
.pme_code = 0x3c056,
.pme_short_desc = "PTEG loaded from another L2 on same chip modified",
.pme_long_desc = "PTEG loaded from another L2 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L21_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L21_MOD]
},
[ POWER7_PME_PM_VSU0_1FLOP ] = {
.pme_name = "PM_VSU0_1FLOP",
.pme_code = 0xa080,
.pme_short_desc = "one flop (fadd",
.pme_long_desc = " fmul",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_1FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_1FLOP]
},
[ POWER7_PME_PM_SNOOP_TLBIE ] = {
.pme_name = "PM_SNOOP_TLBIE",
.pme_code = 0xd0b2,
.pme_short_desc = "TLBIE snoop",
.pme_long_desc = "A tlbie was snooped from another processor.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_SNOOP_TLBIE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_SNOOP_TLBIE]
},
[ POWER7_PME_PM_DATA_FROM_L3MISS ] = {
.pme_name = "PM_DATA_FROM_L3MISS",
.pme_code = 0x2c048,
.pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
.pme_long_desc = "The processor's Data Cache was reloaded from beyond L3 due to a demand load",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L3MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L3MISS]
},
[ POWER7_PME_PM_VSU_SINGLE ] = {
.pme_name = "PM_VSU_SINGLE",
.pme_code = 0xa8a8,
.pme_short_desc = "Vector or Scalar single precision",
.pme_long_desc = "Vector or Scalar single precision",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_SINGLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_SINGLE]
},
[ POWER7_PME_PM_DTLB_MISS_16G ] = {
.pme_name = "PM_DTLB_MISS_16G",
.pme_code = 0x1c05e,
.pme_short_desc = "Data TLB miss for 16G page",
.pme_long_desc = "Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS_16G],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS_16G]
},
[ POWER7_PME_PM_CMPLU_STALL_VECTOR ] = {
.pme_name = "PM_CMPLU_STALL_VECTOR",
.pme_code = 0x2001c,
.pme_short_desc = "Completion stall caused by Vector instruction",
.pme_long_desc = "Completion stall caused by Vector instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_VECTOR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_VECTOR]
},
[ POWER7_PME_PM_FLUSH ] = {
.pme_name = "PM_FLUSH",
.pme_code = 0x400f8,
.pme_short_desc = "Flush (any type)",
.pme_long_desc = "Flushes occurred including LSU and Branch flushes.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH]
},
[ POWER7_PME_PM_L2_LD_HIT ] = {
.pme_name = "PM_L2_LD_HIT",
.pme_code = 0x36182,
.pme_short_desc = "All successful load dispatches that were L2 hits",
.pme_long_desc = "A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Total for all slices",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LD_HIT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LD_HIT]
},
[ POWER7_PME_PM_NEST_2 ] = {
.pme_name = "PM_NEST_2",
.pme_code = 0x83,
.pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_2],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_2]
},
[ POWER7_PME_PM_VSU1_1FLOP ] = {
.pme_name = "PM_VSU1_1FLOP",
.pme_code = 0xa082,
.pme_short_desc = "one flop (fadd",
.pme_long_desc = " fmul",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_1FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_1FLOP]
},
[ POWER7_PME_PM_IC_PREF_REQ ] = {
.pme_name = "PM_IC_PREF_REQ",
.pme_code = 0x408a,
.pme_short_desc = "Instruction prefetch requests",
.pme_long_desc = "An instruction prefetch request has been made.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_REQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_REQ]
},
[ POWER7_PME_PM_L3_LD_HIT ] = {
.pme_name = "PM_L3_LD_HIT",
.pme_code = 0x2f080,
.pme_short_desc = "L3 demand LD Hits",
.pme_long_desc = "L3 demand LD Hits",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_LD_HIT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_LD_HIT]
},
[ POWER7_PME_PM_GCT_NOSLOT_IC_MISS ] = {
.pme_name = "PM_GCT_NOSLOT_IC_MISS",
.pme_code = 0x2001a,
.pme_short_desc = "GCT empty by I cache miss",
.pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_NOSLOT_IC_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_NOSLOT_IC_MISS]
},
[ POWER7_PME_PM_DISP_HELD ] = {
.pme_name = "PM_DISP_HELD",
.pme_code = 0x10006,
.pme_short_desc = "Dispatch Held",
.pme_long_desc = "Dispatch Held",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_HELD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_HELD]
},
[ POWER7_PME_PM_L2_LD ] = {
.pme_name = "PM_L2_LD",
.pme_code = 0x16080,
.pme_short_desc = "Data Load Count",
.pme_long_desc = "Data Load Count",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LD]
},
[ POWER7_PME_PM_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_LSU_FLUSH_SRQ",
.pme_code = 0xc8bc,
.pme_short_desc = "Flush: SRQ",
.pme_long_desc = "Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH_SRQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH_SRQ]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L31_MOD_CYC",
.pme_code = 0x40026,
.pme_short_desc = "Marked ld latency Data source 0111 (L3.1 M same chip)",
.pme_long_desc = "Marked ld latency Data source 0111 (L3.1 M same chip)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC]
},
[ POWER7_PME_PM_L2_RCST_BUSY_RC_FULL ] = {
.pme_name = "PM_L2_RCST_BUSY_RC_FULL",
.pme_code = 0x26282,
.pme_short_desc = " L2 activated Busy to the core for stores due to all RC full",
.pme_long_desc = " L2 activated Busy to the core for stores due to all RC full",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCST_BUSY_RC_FULL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCST_BUSY_RC_FULL]
},
[ POWER7_PME_PM_TB_BIT_TRANS ] = {
.pme_name = "PM_TB_BIT_TRANS",
.pme_code = 0x300f8,
.pme_short_desc = "Time Base bit transition",
.pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_TB_BIT_TRANS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_TB_BIT_TRANS]
},
[ POWER7_PME_PM_THERMAL_MAX ] = {
.pme_name = "PM_THERMAL_MAX",
.pme_code = 0x40006,
.pme_short_desc = "Processor In Thermal MAX",
.pme_long_desc = "The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THERMAL_MAX],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THERMAL_MAX]
},
[ POWER7_PME_PM_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_LSU1_FLUSH_ULD",
.pme_code = 0xc0b2,
.pme_short_desc = "LS 1 Flush: Unaligned Load",
.pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_FLUSH_ULD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_FLUSH_ULD]
},
[ POWER7_PME_PM_LSU1_REJECT_LHS ] = {
.pme_name = "PM_LSU1_REJECT_LHS",
.pme_code = 0xc0ae,
.pme_short_desc = "LS1 Reject: Load Hit Store",
.pme_long_desc = "Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_REJECT_LHS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_REJECT_LHS]
},
[ POWER7_PME_PM_LSU_LRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LRQ_S0_ALLOC",
.pme_code = 0xd09f,
.pme_short_desc = "Slot 0 of LRQ valid",
.pme_long_desc = "Slot 0 of LRQ valid",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LRQ_S0_ALLOC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LRQ_S0_ALLOC]
},
[ POWER7_PME_PM_POWER_EVENT4 ] = {
.pme_name = "PM_POWER_EVENT4",
.pme_code = 0x4006e,
.pme_short_desc = "Power Management Event 4",
.pme_long_desc = "Power Management Event 4",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_POWER_EVENT4],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_POWER_EVENT4]
},
[ POWER7_PME_PM_DATA_FROM_L31_SHR ] = {
.pme_name = "PM_DATA_FROM_L31_SHR",
.pme_code = 0x1c04e,
.pme_short_desc = "Data loaded from another L3 on same chip shared",
.pme_long_desc = "Data loaded from another L3 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L31_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L31_SHR]
},
[ POWER7_PME_PM_BR_UNCOND ] = {
.pme_name = "PM_BR_UNCOND",
.pme_code = 0x409e,
.pme_short_desc = "Unconditional Branch",
.pme_long_desc = "An unconditional branch was executed.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_UNCOND],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_UNCOND]
},
[ POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC ] = {
.pme_name = "PM_LSU1_DC_PREF_STREAM_ALLOC",
.pme_code = 0xd0aa,
.pme_short_desc = "LS 1 D cache new prefetch stream allocated",
.pme_long_desc = "LS 1 D cache new prefetch stream allocated",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC]
},
[ POWER7_PME_PM_PMC4_REWIND ] = {
.pme_name = "PM_PMC4_REWIND",
.pme_code = 0x10020,
.pme_short_desc = "PMC4 Rewind Event",
.pme_long_desc = "PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC4_REWIND],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC4_REWIND]
},
[ POWER7_PME_PM_L2_RCLD_DISP ] = {
.pme_name = "PM_L2_RCLD_DISP",
.pme_code = 0x16280,
.pme_short_desc = " L2 RC load dispatch attempt",
.pme_long_desc = " L2 RC load dispatch attempt",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCLD_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCLD_DISP]
},
[ POWER7_PME_PM_THRD_PRIO_2_3_CYC ] = {
.pme_name = "PM_THRD_PRIO_2_3_CYC",
.pme_code = 0x40b2,
.pme_short_desc = " Cycles thread running at priority level 2 or 3",
.pme_long_desc = " Cycles thread running at priority level 2 or 3",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_PRIO_2_3_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_PRIO_2_3_CYC]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_L2MISS ] = {
.pme_name = "PM_MRK_PTEG_FROM_L2MISS",
.pme_code = 0x4d058,
.pme_short_desc = "Marked PTEG loaded from L2 miss",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L2MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L2MISS]
},
[ POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = {
.pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT",
.pme_code = 0x4098,
.pme_short_desc = " L2 I cache demand request due to BHT redirect",
.pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT]
},
[ POWER7_PME_PM_LSU_DERAT_MISS ] = {
.pme_name = "PM_LSU_DERAT_MISS",
.pme_code = 0x200f6,
.pme_short_desc = "DERAT Reloaded due to a DERAT miss",
.pme_long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_DERAT_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_DERAT_MISS]
},
[ POWER7_PME_PM_IC_PREF_CANCEL_L2 ] = {
.pme_name = "PM_IC_PREF_CANCEL_L2",
.pme_code = 0x4094,
.pme_short_desc = "L2 Squashed request",
.pme_long_desc = "L2 Squashed request",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_CANCEL_L2],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_CANCEL_L2]
},
[ POWER7_PME_PM_GCT_UTIL_7TO10_SLOT ] = {
.pme_name = "PM_GCT_UTIL_7-10_SLOT",
.pme_code = 0x20a0,
.pme_short_desc = "GCT Utilization 7-10 entries",
.pme_long_desc = "GCT Utilization 7-10 entries",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_UTIL_7TO10_SLOT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_UTIL_7TO10_SLOT]
},
[ POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT ] = {
.pme_name = "PM_MRK_FIN_STALL_CYC_COUNT",
.pme_code = 0x1003d,
.pme_short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)",
.pme_long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT]
},
[ POWER7_PME_PM_BR_PRED_CCACHE ] = {
.pme_name = "PM_BR_PRED_CCACHE",
.pme_code = 0x40a0,
.pme_short_desc = "Count Cache Predictions",
.pme_long_desc = "The count value of a Branch and Count instruction was predicted",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_CCACHE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_CCACHE]
},
[ POWER7_PME_PM_MRK_ST_CMPL_INT ] = {
.pme_name = "PM_MRK_ST_CMPL_INT",
.pme_code = 0x30034,
.pme_short_desc = "marked store complete (data home) with intervention",
.pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_ST_CMPL_INT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_ST_CMPL_INT]
},
[ POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC ] = {
.pme_name = "PM_LSU_TWO_TABLEWALK_CYC",
.pme_code = 0xd0a6,
.pme_short_desc = "Cycles when two tablewalks pending on this thread",
.pme_long_desc = "Cycles when two tablewalks pending on this thread",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L3MISS ] = {
.pme_name = "PM_MRK_DATA_FROM_L3MISS",
.pme_code = 0x2d048,
.pme_short_desc = "Marked data loaded from L3 miss",
.pme_long_desc = "DL1 was reloaded from beyond L3 due to a marked load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L3MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L3MISS]
},
[ POWER7_PME_PM_GCT_NOSLOT_CYC ] = {
.pme_name = "PM_GCT_NOSLOT_CYC",
.pme_code = 0x100f8,
.pme_short_desc = "No itags assigned ",
.pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_NOSLOT_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_NOSLOT_CYC]
},
[ POWER7_PME_PM_LSU_SET_MPRED ] = {
.pme_name = "PM_LSU_SET_MPRED",
.pme_code = 0xc0a8,
.pme_short_desc = "Line already in cache at reload time",
.pme_long_desc = "Line already in cache at reload time",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SET_MPRED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SET_MPRED]
},
[ POWER7_PME_PM_FLUSH_DISP_TLBIE ] = {
.pme_name = "PM_FLUSH_DISP_TLBIE",
.pme_code = 0x208a,
.pme_short_desc = "Dispatch Flush: TLBIE",
.pme_long_desc = "Dispatch Flush: TLBIE",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_DISP_TLBIE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_DISP_TLBIE]
},
[ POWER7_PME_PM_VSU1_FCONV ] = {
.pme_name = "PM_VSU1_FCONV",
.pme_code = 0xa0b2,
.pme_short_desc = "Convert instruction executed",
.pme_long_desc = "Convert instruction executed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FCONV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FCONV]
},
[ POWER7_PME_PM_NEST_1 ] = {
.pme_name = "PM_NEST_1",
.pme_code = 0x81,
.pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_1]
},
[ POWER7_PME_PM_DERAT_MISS_16G ] = {
.pme_name = "PM_DERAT_MISS_16G",
.pme_code = 0x4c05c,
.pme_short_desc = "DERAT misses for 16G page",
.pme_long_desc = "A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DERAT_MISS_16G],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DERAT_MISS_16G]
},
[ POWER7_PME_PM_INST_FROM_LMEM ] = {
.pme_name = "PM_INST_FROM_LMEM",
.pme_code = 0x3404a,
.pme_short_desc = "Instruction fetched from local memory",
.pme_long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_LMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_LMEM]
},
[ POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = {
.pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT",
.pme_code = 0x409a,
.pme_short_desc = " L2 I cache demand request due to branch redirect",
.pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT]
},
[ POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG ] = {
.pme_name = "PM_CMPLU_STALL_SCALAR_LONG",
.pme_code = 0x20018,
.pme_short_desc = "Completion stall caused by long latency scalar instruction",
.pme_long_desc = "Completion stall caused by long latency scalar instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG]
},
[ POWER7_PME_PM_INST_PTEG_FROM_L2 ] = {
.pme_name = "PM_INST_PTEG_FROM_L2",
.pme_code = 0x1e050,
.pme_short_desc = "Instruction PTEG loaded from L2",
.pme_long_desc = "Instruction PTEG loaded from L2",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L2],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L2]
},
[ POWER7_PME_PM_PTEG_FROM_L2 ] = {
.pme_name = "PM_PTEG_FROM_L2",
.pme_code = 0x1c050,
.pme_short_desc = "PTEG loaded from L2",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L2],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L2]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L21_SHR_CYC",
.pme_code = 0x20024,
.pme_short_desc = "Marked ld latency Data source 0100 (L2.1 S)",
.pme_long_desc = "Marked load latency Data source 0100 (L2.1 S)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC]
},
[ POWER7_PME_PM_MRK_DTLB_MISS_4K ] = {
.pme_name = "PM_MRK_DTLB_MISS_4K",
.pme_code = 0x2d05a,
.pme_short_desc = "Marked Data TLB misses for 4K page",
.pme_long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DTLB_MISS_4K],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DTLB_MISS_4K]
},
[ POWER7_PME_PM_VSU0_FPSCR ] = {
.pme_name = "PM_VSU0_FPSCR",
.pme_code = 0xb09c,
.pme_short_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
.pme_long_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FPSCR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FPSCR]
},
[ POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED ] = {
.pme_name = "PM_VSU1_VECT_DOUBLE_ISSUED",
.pme_code = 0xb082,
.pme_short_desc = "Double Precision vector instruction issued on Pipe1",
.pme_long_desc = "Double Precision vector instruction issued on Pipe1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = {
.pme_name = "PM_MRK_PTEG_FROM_RL2L3_MOD",
.pme_code = 0x1d052,
.pme_short_desc = "Marked PTEG loaded from remote L2 or L3 modified",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD]
},
[ POWER7_PME_PM_L2_LD_MISS ] = {
.pme_name = "PM_L2_LD_MISS",
.pme_code = 0x26080,
.pme_short_desc = "Data Load Miss",
.pme_long_desc = "Data Load Miss",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LD_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LD_MISS]
},
[ POWER7_PME_PM_VMX_RESULT_SAT_1 ] = {
.pme_name = "PM_VMX_RESULT_SAT_1",
.pme_code = 0xb0a0,
.pme_short_desc = "Valid result with sat=1",
.pme_long_desc = "Valid result with sat=1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VMX_RESULT_SAT_1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VMX_RESULT_SAT_1]
},
[ POWER7_PME_PM_L1_PREF ] = {
.pme_name = "PM_L1_PREF",
.pme_code = 0xd8b8,
.pme_short_desc = "L1 Prefetches",
.pme_long_desc = "A request to prefetch data into the L1 was made",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L1_PREF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L1_PREF]
},
[ POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_LMEM_CYC",
.pme_code = 0x2002c,
.pme_short_desc = "Marked ld latency Data Source 1100 (Local Memory)",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC]
},
[ POWER7_PME_PM_GRP_IC_MISS_NONSPEC ] = {
.pme_name = "PM_GRP_IC_MISS_NONSPEC",
.pme_code = 0x1000c,
.pme_short_desc = "Group experienced non-speculative I cache miss",
.pme_long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_IC_MISS_NONSPEC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_IC_MISS_NONSPEC]
},
[ POWER7_PME_PM_SHL_MERGED ] = {
.pme_name = "PM_SHL_MERGED",
.pme_code = 0x5084,
.pme_short_desc = "SHL table entry merged with existing",
.pme_long_desc = "SHL table entry merged with existing",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_SHL_MERGED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_SHL_MERGED]
},
[ POWER7_PME_PM_DATA_FROM_L3 ] = {
.pme_name = "PM_DATA_FROM_L3",
.pme_code = 0x1c048,
.pme_short_desc = "Data loaded from L3",
.pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L3],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L3]
},
[ POWER7_PME_PM_LSU_FLUSH ] = {
.pme_name = "PM_LSU_FLUSH",
.pme_code = 0x208e,
.pme_short_desc = "Flush initiated by LSU",
.pme_long_desc = "A flush was initiated by the Load Store Unit.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH]
},
[ POWER7_PME_PM_LSU_SRQ_SYNC_COUNT ] = {
.pme_name = "PM_LSU_SRQ_SYNC_COUNT",
.pme_code = 0xd097,
.pme_short_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)",
.pme_long_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_SYNC_COUNT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_SYNC_COUNT]
},
[ POWER7_PME_PM_PMC2_OVERFLOW ] = {
.pme_name = "PM_PMC2_OVERFLOW",
.pme_code = 0x30010,
.pme_short_desc = "Overflow from counter 2",
.pme_long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC2_OVERFLOW],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC2_OVERFLOW]
},
[ POWER7_PME_PM_LSU_LDF ] = {
.pme_name = "PM_LSU_LDF",
.pme_code = 0xc884,
.pme_short_desc = "All Scalar Loads",
.pme_long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LDF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LDF]
},
[ POWER7_PME_PM_POWER_EVENT3 ] = {
.pme_name = "PM_POWER_EVENT3",
.pme_code = 0x3006e,
.pme_short_desc = "Power Management Event 3",
.pme_long_desc = "Power Management Event 3",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_POWER_EVENT3],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_POWER_EVENT3]
},
[ POWER7_PME_PM_DISP_WT ] = {
.pme_name = "PM_DISP_WT",
.pme_code = 0x30008,
.pme_short_desc = "Dispatched Starved (not held",
.pme_long_desc = " nothing to dispatch)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_WT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_WT]
},
[ POWER7_PME_PM_CMPLU_STALL_REJECT ] = {
.pme_name = "PM_CMPLU_STALL_REJECT",
.pme_code = 0x40016,
.pme_short_desc = "Completion stall caused by reject",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_REJECT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_REJECT]
},
[ POWER7_PME_PM_IC_BANK_CONFLICT ] = {
.pme_name = "PM_IC_BANK_CONFLICT",
.pme_code = 0x4082,
.pme_short_desc = "Read blocked due to interleave conflict. ",
.pme_long_desc = "Read blocked due to interleave conflict. ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_BANK_CONFLICT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_BANK_CONFLICT]
},
[ POWER7_PME_PM_BR_MPRED_CR_TA ] = {
.pme_name = "PM_BR_MPRED_CR_TA",
.pme_code = 0x48ae,
.pme_short_desc = "Branch mispredict - taken/not taken and target",
.pme_long_desc = "Branch mispredict - taken/not taken and target",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_CR_TA],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_CR_TA]
},
[ POWER7_PME_PM_L2_INST_MISS ] = {
.pme_name = "PM_L2_INST_MISS",
.pme_code = 0x36082,
.pme_short_desc = "Instruction Load Misses",
.pme_long_desc = "Instruction Load Misses",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_INST_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_INST_MISS]
},
[ POWER7_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
.pme_name = "PM_CMPLU_STALL_ERAT_MISS",
.pme_code = 0x40018,
.pme_short_desc = "Completion stall caused by ERAT miss",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_ERAT_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_ERAT_MISS]
},
[ POWER7_PME_PM_MRK_LSU_FLUSH ] = {
.pme_name = "PM_MRK_LSU_FLUSH",
.pme_code = 0xd08c,
.pme_short_desc = "Flush: (marked) : All Cases",
.pme_long_desc = "Marked flush initiated by LSU",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH]
},
[ POWER7_PME_PM_L2_LDST ] = {
.pme_name = "PM_L2_LDST",
.pme_code = 0x16880,
.pme_short_desc = "Data Load+Store Count",
.pme_long_desc = "Data Load+Store Count",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LDST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LDST]
},
[ POWER7_PME_PM_INST_FROM_L31_SHR ] = {
.pme_name = "PM_INST_FROM_L31_SHR",
.pme_code = 0x1404e,
.pme_short_desc = "Instruction fetched from another L3 on same chip shared",
.pme_long_desc = "Instruction fetched from another L3 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L31_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L31_SHR]
},
[ POWER7_PME_PM_VSU0_FIN ] = {
.pme_name = "PM_VSU0_FIN",
.pme_code = 0xa0bc,
.pme_short_desc = "VSU0 Finished an instruction",
.pme_long_desc = "VSU0 Finished an instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FIN]
},
[ POWER7_PME_PM_LARX_LSU ] = {
.pme_name = "PM_LARX_LSU",
.pme_code = 0xc894,
.pme_short_desc = "Larx Finished",
.pme_long_desc = "Larx Finished",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LARX_LSU],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LARX_LSU]
},
[ POWER7_PME_PM_INST_FROM_RMEM ] = {
.pme_name = "PM_INST_FROM_RMEM",
.pme_code = 0x34042,
.pme_short_desc = "Instruction fetched from remote memory",
.pme_long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_RMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_RMEM]
},
[ POWER7_PME_PM_DISP_CLB_HELD_TLBIE ] = {
.pme_name = "PM_DISP_CLB_HELD_TLBIE",
.pme_code = 0x2096,
.pme_short_desc = "Dispatch Hold: Due to TLBIE",
.pme_long_desc = "Dispatch Hold: Due to TLBIE",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_TLBIE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_TLBIE]
},
[ POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_DMEM_CYC",
.pme_code = 0x2002e,
.pme_short_desc = "Marked ld latency Data Source 1110 (Distant Memory)",
.pme_long_desc = "Marked ld latency Data Source 1110 (Distant Memory)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC]
},
[ POWER7_PME_PM_BR_PRED_CR ] = {
.pme_name = "PM_BR_PRED_CR",
.pme_code = 0x40a8,
.pme_short_desc = "Branch predict - taken/not taken",
.pme_long_desc = "A conditional branch instruction was predicted as taken or not taken.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_CR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_CR]
},
[ POWER7_PME_PM_LSU_REJECT ] = {
.pme_name = "PM_LSU_REJECT",
.pme_code = 0x10064,
.pme_short_desc = "LSU Reject (up to 2 per cycle)",
.pme_long_desc = "The Load Store Unit rejected an instruction. Combined Unit 0 + 1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT]
},
[ POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT ] = {
.pme_name = "PM_CMPLU_STALL_END_GCT_NOSLOT",
.pme_code = 0x10028,
.pme_short_desc = "Count ended because GCT went empty",
.pme_long_desc = "Count ended because GCT went empty",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT]
},
[ POWER7_PME_PM_LSU0_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU0_REJECT_LMQ_FULL",
.pme_code = 0xc0a4,
.pme_short_desc = "LS0 Reject: LMQ Full (LHR)",
.pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_REJECT_LMQ_FULL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_REJECT_LMQ_FULL]
},
[ POWER7_PME_PM_VSU_FEST ] = {
.pme_name = "PM_VSU_FEST",
.pme_code = 0xa8b8,
.pme_short_desc = "Estimate instruction executed",
.pme_long_desc = "Estimate instruction executed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FEST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FEST]
},
[ POWER7_PME_PM_PTEG_FROM_L3 ] = {
.pme_name = "PM_PTEG_FROM_L3",
.pme_code = 0x2c050,
.pme_short_desc = "PTEG loaded from L3",
.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L3],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L3]
},
[ POWER7_PME_PM_POWER_EVENT2 ] = {
.pme_name = "PM_POWER_EVENT2",
.pme_code = 0x2006e,
.pme_short_desc = "Power Management Event 2",
.pme_long_desc = "Power Management Event 2",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_POWER_EVENT2],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_POWER_EVENT2]
},
[ POWER7_PME_PM_IC_PREF_CANCEL_PAGE ] = {
.pme_name = "PM_IC_PREF_CANCEL_PAGE",
.pme_code = 0x4090,
.pme_short_desc = "Prefetch Canceled due to page boundary",
.pme_long_desc = "Prefetch Canceled due to page boundary",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_CANCEL_PAGE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_CANCEL_PAGE]
},
[ POWER7_PME_PM_VSU0_FSQRT_FDIV ] = {
.pme_name = "PM_VSU0_FSQRT_FDIV",
.pme_code = 0xa088,
.pme_short_desc = "four flops operation (fdiv",
.pme_long_desc = "fsqrt",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FSQRT_FDIV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FSQRT_FDIV]
},
[ POWER7_PME_PM_MRK_GRP_CMPL ] = {
.pme_name = "PM_MRK_GRP_CMPL",
.pme_code = 0x40030,
.pme_short_desc = "Marked group complete",
.pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_GRP_CMPL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_GRP_CMPL]
},
[ POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED ] = {
.pme_name = "PM_VSU0_SCAL_DOUBLE_ISSUED",
.pme_code = 0xb088,
.pme_short_desc = "Double Precision scalar instruction issued on Pipe0",
.pme_long_desc = "Double Precision scalar instruction issued on Pipe0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED]
},
[ POWER7_PME_PM_GRP_DISP ] = {
.pme_name = "PM_GRP_DISP",
.pme_code = 0x3000a,
.pme_short_desc = "dispatch_success (Group Dispatched)",
.pme_long_desc = "A group was dispatched",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_DISP]
},
[ POWER7_PME_PM_LSU0_LDX ] = {
.pme_name = "PM_LSU0_LDX",
.pme_code = 0xc088,
.pme_short_desc = "LS0 Vector Loads",
.pme_long_desc = "LS0 Vector Loads",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_LDX],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_LDX]
},
[ POWER7_PME_PM_DATA_FROM_L2 ] = {
.pme_name = "PM_DATA_FROM_L2",
.pme_code = 0x1c040,
.pme_short_desc = "Data loaded from L2",
.pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L2],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L2]
},
[ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD",
.pme_code = 0x1d042,
.pme_short_desc = "Marked data loaded from remote L2 or L3 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a marked load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD]
},
[ POWER7_PME_PM_LD_REF_L1 ] = {
.pme_name = "PM_LD_REF_L1",
.pme_code = 0xc880,
.pme_short_desc = " L1 D cache load references counted at finish",
.pme_long_desc = " L1 D cache load references counted at finish",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LD_REF_L1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LD_REF_L1]
},
[ POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED ] = {
.pme_name = "PM_VSU0_VECT_DOUBLE_ISSUED",
.pme_code = 0xb080,
.pme_short_desc = "Double Precision vector instruction issued on Pipe0",
.pme_long_desc = "Double Precision vector instruction issued on Pipe0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED]
},
[ POWER7_PME_PM_VSU1_2FLOP_DOUBLE ] = {
.pme_name = "PM_VSU1_2FLOP_DOUBLE",
.pme_code = 0xa08e,
.pme_short_desc = "two flop DP vector operation (xvadddp",
.pme_long_desc = " xvmuldp",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_2FLOP_DOUBLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_2FLOP_DOUBLE]
},
[ POWER7_PME_PM_THRD_PRIO_6_7_CYC ] = {
.pme_name = "PM_THRD_PRIO_6_7_CYC",
.pme_code = 0x40b6,
.pme_short_desc = " Cycles thread running at priority level 6 or 7",
.pme_long_desc = " Cycles thread running at priority level 6 or 7",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_PRIO_6_7_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_PRIO_6_7_CYC]
},
[ POWER7_PME_PM_BR_MPRED_CR ] = {
.pme_name = "PM_BR_MPRED_CR",
.pme_code = 0x40ac,
.pme_short_desc = "Branch mispredict - taken/not taken",
.pme_long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_CR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_CR]
},
[ POWER7_PME_PM_LD_MISS_L1 ] = {
.pme_name = "PM_LD_MISS_L1",
.pme_code = 0x400f0,
.pme_short_desc = "Load Missed L1",
.pme_long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LD_MISS_L1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LD_MISS_L1]
},
[ POWER7_PME_PM_DATA_FROM_RL2L3_MOD ] = {
.pme_name = "PM_DATA_FROM_RL2L3_MOD",
.pme_code = 0x1c042,
.pme_short_desc = "Data loaded from remote L2 or L3 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_RL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_RL2L3_MOD]
},
[ POWER7_PME_PM_LSU_SRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_SRQ_FULL_CYC",
.pme_code = 0x1001a,
.pme_short_desc = "Storage Queue is full and is blocking dispatch",
.pme_long_desc = "Cycles the Store Request Queue is full.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_FULL_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_FULL_CYC]
},
[ POWER7_PME_PM_TABLEWALK_CYC ] = {
.pme_name = "PM_TABLEWALK_CYC",
.pme_code = 0x10026,
.pme_short_desc = "Cycles when a tablewalk (I or D) is active",
.pme_long_desc = "Cycles doing instruction or data tablewalks",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_TABLEWALK_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_TABLEWALK_CYC]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_RMEM ] = {
.pme_name = "PM_MRK_PTEG_FROM_RMEM",
.pme_code = 0x3d052,
.pme_short_desc = "Marked PTEG loaded from remote memory",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_RMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_RMEM]
},
[ POWER7_PME_PM_LSU_SRQ_STFWD ] = {
.pme_name = "PM_LSU_SRQ_STFWD",
.pme_code = 0xc8a0,
.pme_short_desc = "Load got data from a store",
.pme_long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_STFWD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_STFWD]
},
[ POWER7_PME_PM_INST_PTEG_FROM_RMEM ] = {
.pme_name = "PM_INST_PTEG_FROM_RMEM",
.pme_code = 0x3e052,
.pme_short_desc = "Instruction PTEG loaded from remote memory",
.pme_long_desc = "Instruction PTEG loaded from remote memory",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_RMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_RMEM]
},
[ POWER7_PME_PM_FXU0_FIN ] = {
.pme_name = "PM_FXU0_FIN",
.pme_code = 0x10004,
.pme_short_desc = "FXU0 Finished",
.pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU0_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU0_FIN]
},
[ POWER7_PME_PM_PTEG_FROM_L31_MOD ] = {
.pme_name = "PM_PTEG_FROM_L31_MOD",
.pme_code = 0x1c054,
.pme_short_desc = "PTEG loaded from another L3 on same chip modified",
.pme_long_desc = "PTEG loaded from another L3 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L31_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L31_MOD]
},
[ POWER7_PME_PM_PMC5_OVERFLOW ] = {
.pme_name = "PM_PMC5_OVERFLOW",
.pme_code = 0x10024,
.pme_short_desc = "Overflow from counter 5",
.pme_long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC5_OVERFLOW],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC5_OVERFLOW]
},
[ POWER7_PME_PM_LD_REF_L1_LSU1 ] = {
.pme_name = "PM_LD_REF_L1_LSU1",
.pme_code = 0xc082,
.pme_short_desc = "LS1 L1 D cache load references counted at finish",
.pme_long_desc = "Load references to Level 1 Data Cache, by unit 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LD_REF_L1_LSU1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LD_REF_L1_LSU1]
},
[ POWER7_PME_PM_INST_PTEG_FROM_L21_SHR ] = {
.pme_name = "PM_INST_PTEG_FROM_L21_SHR",
.pme_code = 0x4e056,
.pme_short_desc = "Instruction PTEG loaded from another L2 on same chip shared",
.pme_long_desc = "Instruction PTEG loaded from another L2 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L21_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L21_SHR]
},
[ POWER7_PME_PM_CMPLU_STALL_THRD ] = {
.pme_name = "PM_CMPLU_STALL_THRD",
.pme_code = 0x1001c,
.pme_short_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
.pme_long_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_THRD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_THRD]
},
[ POWER7_PME_PM_DATA_FROM_RMEM ] = {
.pme_name = "PM_DATA_FROM_RMEM",
.pme_code = 0x3c042,
.pme_short_desc = "Data loaded from remote memory",
.pme_long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_RMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_RMEM]
},
[ POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED ] = {
.pme_name = "PM_VSU0_SCAL_SINGLE_ISSUED",
.pme_code = 0xb084,
.pme_short_desc = "Single Precision scalar instruction issued on Pipe0",
.pme_long_desc = "Single Precision scalar instruction issued on Pipe0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED]
},
[ POWER7_PME_PM_BR_MPRED_LSTACK ] = {
.pme_name = "PM_BR_MPRED_LSTACK",
.pme_code = 0x40a6,
.pme_short_desc = "Branch Mispredict due to Link Stack",
.pme_long_desc = "Branch Mispredict due to Link Stack",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_LSTACK],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_LSTACK]
},
[ POWER7_PME_PM_NEST_8 ] = {
.pme_name = "PM_NEST_8",
.pme_code = 0x8f,
.pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_8],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_8]
},
[ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
.pme_code = 0x40028,
.pme_short_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)",
.pme_long_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC]
},
[ POWER7_PME_PM_LSU0_FLUSH_UST ] = {
.pme_name = "PM_LSU0_FLUSH_UST",
.pme_code = 0xc0b4,
.pme_short_desc = "LS0 Flush: Unaligned Store",
.pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_FLUSH_UST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_FLUSH_UST]
},
[ POWER7_PME_PM_LSU_NCST ] = {
.pme_name = "PM_LSU_NCST",
.pme_code = 0xc090,
.pme_short_desc = "Non-cachable Stores sent to nest",
.pme_long_desc = "Non-cachable Stores sent to nest",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_NCST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_NCST]
},
[ POWER7_PME_PM_BR_TAKEN ] = {
.pme_name = "PM_BR_TAKEN",
.pme_code = 0x20004,
.pme_short_desc = "Branch Taken",
.pme_long_desc = "A branch instruction was taken. This could have been a conditional branch or an unconditional branch",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_TAKEN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_TAKEN]
},
[ POWER7_PME_PM_INST_PTEG_FROM_LMEM ] = {
.pme_name = "PM_INST_PTEG_FROM_LMEM",
.pme_code = 0x4e052,
.pme_short_desc = "Instruction PTEG loaded from local memory",
.pme_long_desc = "Instruction PTEG loaded from local memory",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_LMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_LMEM]
},
[ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS ] = {
.pme_name = "PM_GCT_NOSLOT_BR_MPRED_IC_MISS",
.pme_code = 0x4001c,
.pme_short_desc = "GCT empty by branch mispredict + IC miss",
.pme_long_desc = "No slot in GCT caused by branch mispredict or I cache miss",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS]
},
[ POWER7_PME_PM_DTLB_MISS_4K ] = {
.pme_name = "PM_DTLB_MISS_4K",
.pme_code = 0x2c05a,
.pme_short_desc = "Data TLB miss for 4K page",
.pme_long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS_4K],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS_4K]
},
[ POWER7_PME_PM_PMC4_SAVED ] = {
.pme_name = "PM_PMC4_SAVED",
.pme_code = 0x30022,
.pme_short_desc = "PMC4 Rewind Value saved (matched condition)",
.pme_long_desc = "PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC4_SAVED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC4_SAVED]
},
[ POWER7_PME_PM_VSU1_PERMUTE_ISSUED ] = {
.pme_name = "PM_VSU1_PERMUTE_ISSUED",
.pme_code = 0xb092,
.pme_short_desc = "Permute VMX Instruction Issued",
.pme_long_desc = "Permute VMX Instruction Issued",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_PERMUTE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_PERMUTE_ISSUED]
},
[ POWER7_PME_PM_SLB_MISS ] = {
.pme_name = "PM_SLB_MISS",
.pme_code = 0xd890,
.pme_short_desc = "Data + Instruction SLB Miss - Total of all segment sizes",
.pme_long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_SLB_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_SLB_MISS]
},
[ POWER7_PME_PM_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_LSU1_FLUSH_LRQ",
.pme_code = 0xc0ba,
.pme_short_desc = "LS1 Flush: LRQ",
.pme_long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_FLUSH_LRQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_FLUSH_LRQ]
},
[ POWER7_PME_PM_DTLB_MISS ] = {
.pme_name = "PM_DTLB_MISS",
.pme_code = 0x300fc,
.pme_short_desc = "TLB reload valid",
.pme_long_desc = "Data TLB misses, all page sizes.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS]
},
[ POWER7_PME_PM_VSU1_FRSP ] = {
.pme_name = "PM_VSU1_FRSP",
.pme_code = 0xa0b6,
.pme_short_desc = "Round to single precision instruction executed",
.pme_long_desc = "Round to single precision instruction executed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FRSP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FRSP]
},
[ POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED ] = {
.pme_name = "PM_VSU_VECTOR_DOUBLE_ISSUED",
.pme_code = 0xb880,
.pme_short_desc = "Double Precision vector instruction issued on Pipe0",
.pme_long_desc = "Double Precision vector instruction issued on Pipe0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED]
},
[ POWER7_PME_PM_L2_CASTOUT_SHR ] = {
.pme_name = "PM_L2_CASTOUT_SHR",
.pme_code = 0x16182,
.pme_short_desc = "L2 Castouts - Shared (T",
.pme_long_desc = " Te",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_CASTOUT_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_CASTOUT_SHR]
},
[ POWER7_PME_PM_NEST_7 ] = {
.pme_name = "PM_NEST_7",
.pme_code = 0x8d,
.pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_7],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_7]
},
[ POWER7_PME_PM_DATA_FROM_DL2L3_SHR ] = {
.pme_name = "PM_DATA_FROM_DL2L3_SHR",
.pme_code = 0x3c044,
.pme_short_desc = "Data loaded from distant L2 or L3 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_DL2L3_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_DL2L3_SHR]
},
[ POWER7_PME_PM_VSU1_STF ] = {
.pme_name = "PM_VSU1_STF",
.pme_code = 0xb08e,
.pme_short_desc = "FPU store (SP or DP) issued on Pipe1",
.pme_long_desc = "FPU store (SP or DP) issued on Pipe1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_STF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_STF]
},
[ POWER7_PME_PM_ST_FIN ] = {
.pme_name = "PM_ST_FIN",
.pme_code = 0x200f0,
.pme_short_desc = "Store Instructions Finished",
.pme_long_desc = "Store requests sent to the nest.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_ST_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_ST_FIN]
},
[ POWER7_PME_PM_PTEG_FROM_L21_SHR ] = {
.pme_name = "PM_PTEG_FROM_L21_SHR",
.pme_code = 0x4c056,
.pme_short_desc = "PTEG loaded from another L2 on same chip shared",
.pme_long_desc = "PTEG loaded from another L2 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L21_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L21_SHR]
},
[ POWER7_PME_PM_L2_LOC_GUESS_WRONG ] = {
.pme_name = "PM_L2_LOC_GUESS_WRONG",
.pme_code = 0x26480,
.pme_short_desc = "L2 guess loc and guess was not correct (ie data remote)",
.pme_long_desc = "L2 guess loc and guess was not correct (ie data remote)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LOC_GUESS_WRONG],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LOC_GUESS_WRONG]
},
[ POWER7_PME_PM_MRK_STCX_FAIL ] = {
.pme_name = "PM_MRK_STCX_FAIL",
.pme_code = 0xd08e,
.pme_short_desc = "Marked STCX failed",
.pme_long_desc = "A marked stcx (stwcx or stdcx) failed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_STCX_FAIL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_STCX_FAIL]
},
[ POWER7_PME_PM_LSU0_REJECT_LHS ] = {
.pme_name = "PM_LSU0_REJECT_LHS",
.pme_code = 0xc0ac,
.pme_short_desc = "LS0 Reject: Load Hit Store",
.pme_long_desc = "Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_REJECT_LHS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_REJECT_LHS]
},
[ POWER7_PME_PM_IC_PREF_CANCEL_HIT ] = {
.pme_name = "PM_IC_PREF_CANCEL_HIT",
.pme_code = 0x4092,
.pme_short_desc = "Prefetch Canceled due to icache hit",
.pme_long_desc = "Prefetch Canceled due to icache hit",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_CANCEL_HIT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_CANCEL_HIT]
},
[ POWER7_PME_PM_L3_PREF_BUSY ] = {
.pme_name = "PM_L3_PREF_BUSY",
.pme_code = 0x4f080,
.pme_short_desc = "Prefetch machines >= threshold (8",
.pme_long_desc = "16",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_BUSY],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_BUSY]
},
[ POWER7_PME_PM_MRK_BRU_FIN ] = {
.pme_name = "PM_MRK_BRU_FIN",
.pme_code = 0x2003a,
.pme_short_desc = "bru marked instr finish",
.pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_BRU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_BRU_FIN]
},
[ POWER7_PME_PM_LSU1_NCLD ] = {
.pme_name = "PM_LSU1_NCLD",
.pme_code = 0xc08e,
.pme_short_desc = "LS1 Non-cachable Loads counted at finish",
.pme_long_desc = "A non-cacheable load was executed by Unit 0.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_NCLD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_NCLD]
},
[ POWER7_PME_PM_INST_PTEG_FROM_L31_MOD ] = {
.pme_name = "PM_INST_PTEG_FROM_L31_MOD",
.pme_code = 0x1e054,
.pme_short_desc = "Instruction PTEG loaded from another L3 on same chip modified",
.pme_long_desc = "Instruction PTEG loaded from another L3 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L31_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L31_MOD]
},
[ POWER7_PME_PM_LSU_NCLD ] = {
.pme_name = "PM_LSU_NCLD",
.pme_code = 0xc88c,
.pme_short_desc = "Non-cachable Loads counted at finish",
.pme_long_desc = "A non-cacheable load was executed. Combined Unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_NCLD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_NCLD]
},
[ POWER7_PME_PM_LSU_LDX ] = {
.pme_name = "PM_LSU_LDX",
.pme_code = 0xc888,
.pme_short_desc = "All Vector loads (vsx vector + vmx vector)",
.pme_long_desc = "All Vector loads (vsx vector + vmx vector)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LDX],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LDX]
},
[ POWER7_PME_PM_L2_LOC_GUESS_CORRECT ] = {
.pme_name = "PM_L2_LOC_GUESS_CORRECT",
.pme_code = 0x16480,
.pme_short_desc = "L2 guess loc and guess was correct (ie data local)",
.pme_long_desc = "L2 guess loc and guess was correct (ie data local)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LOC_GUESS_CORRECT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LOC_GUESS_CORRECT]
},
[ POWER7_PME_PM_THRESH_TIMEO ] = {
.pme_name = "PM_THRESH_TIMEO",
.pme_code = 0x10038,
.pme_short_desc = "Threshold timeout event",
.pme_long_desc = "The threshold timer expired",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THRESH_TIMEO],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRESH_TIMEO]
},
[ POWER7_PME_PM_L3_PREF_ST ] = {
.pme_name = "PM_L3_PREF_ST",
.pme_code = 0xd0ae,
.pme_short_desc = "L3 cache ST prefetches",
.pme_long_desc = "L3 cache ST prefetches",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_ST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_ST]
},
[ POWER7_PME_PM_DISP_CLB_HELD_SYNC ] = {
.pme_name = "PM_DISP_CLB_HELD_SYNC",
.pme_code = 0x2098,
.pme_short_desc = "Dispatch/CLB Hold: Sync type instruction",
.pme_long_desc = "Dispatch/CLB Hold: Sync type instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_SYNC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_SYNC]
},
[ POWER7_PME_PM_VSU_SIMPLE_ISSUED ] = {
.pme_name = "PM_VSU_SIMPLE_ISSUED",
.pme_code = 0xb894,
.pme_short_desc = "Simple VMX instruction issued",
.pme_long_desc = "Simple VMX instruction issued",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_SIMPLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_SIMPLE_ISSUED]
},
[ POWER7_PME_PM_VSU1_SINGLE ] = {
.pme_name = "PM_VSU1_SINGLE",
.pme_code = 0xa0aa,
.pme_short_desc = "FPU single precision",
.pme_long_desc = "VSU1 executed single precision instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_SINGLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_SINGLE]
},
[ POWER7_PME_PM_DATA_TABLEWALK_CYC ] = {
.pme_name = "PM_DATA_TABLEWALK_CYC",
.pme_code = 0x3001a,
.pme_short_desc = "Data Tablewalk Active",
.pme_long_desc = "Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_TABLEWALK_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_TABLEWALK_CYC]
},
[ POWER7_PME_PM_L2_RC_ST_DONE ] = {
.pme_name = "PM_L2_RC_ST_DONE",
.pme_code = 0x36380,
.pme_short_desc = "RC did st to line that was Tx or Sx",
.pme_long_desc = "RC did st to line that was Tx or Sx",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RC_ST_DONE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RC_ST_DONE]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD ] = {
.pme_name = "PM_MRK_PTEG_FROM_L21_MOD",
.pme_code = 0x3d056,
.pme_short_desc = "Marked PTEG loaded from another L2 on same chip modified",
.pme_long_desc = "Marked PTEG loaded from another L2 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD]
},
[ POWER7_PME_PM_LARX_LSU1 ] = {
.pme_name = "PM_LARX_LSU1",
.pme_code = 0xc096,
.pme_short_desc = "ls1 Larx Finished",
.pme_long_desc = "A larx (lwarx or ldarx) was executed on side 1 ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LARX_LSU1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LARX_LSU1]
},
[ POWER7_PME_PM_MRK_DATA_FROM_RMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_RMEM",
.pme_code = 0x3d042,
.pme_short_desc = "Marked data loaded from remote memory",
.pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RMEM]
},
[ POWER7_PME_PM_DISP_CLB_HELD ] = {
.pme_name = "PM_DISP_CLB_HELD",
.pme_code = 0x2090,
.pme_short_desc = "CLB Hold: Any Reason",
.pme_long_desc = "CLB Hold: Any Reason",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD]
},
[ POWER7_PME_PM_DERAT_MISS_4K ] = {
.pme_name = "PM_DERAT_MISS_4K",
.pme_code = 0x1c05c,
.pme_short_desc = "DERAT misses for 4K page",
.pme_long_desc = "A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DERAT_MISS_4K],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DERAT_MISS_4K]
},
[ POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2_RCLD_DISP_FAIL_ADDR",
.pme_code = 0x16282,
.pme_short_desc = " L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_long_desc = " L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR]
},
[ POWER7_PME_PM_SEG_EXCEPTION ] = {
.pme_name = "PM_SEG_EXCEPTION",
.pme_code = 0x28a4,
.pme_short_desc = "ISEG + DSEG Exception",
.pme_long_desc = "ISEG + DSEG Exception",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_SEG_EXCEPTION],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_SEG_EXCEPTION]
},
[ POWER7_PME_PM_FLUSH_DISP_SB ] = {
.pme_name = "PM_FLUSH_DISP_SB",
.pme_code = 0x208c,
.pme_short_desc = "Dispatch Flush: Scoreboard",
.pme_long_desc = "Dispatch Flush: Scoreboard",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_DISP_SB],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_DISP_SB]
},
[ POWER7_PME_PM_L2_DC_INV ] = {
.pme_name = "PM_L2_DC_INV",
.pme_code = 0x26182,
.pme_short_desc = "Dcache invalidates from L2 ",
.pme_long_desc = "The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Total for all slices",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_DC_INV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_DC_INV]
},
[ POWER7_PME_PM_PTEG_FROM_DL2L3_MOD ] = {
.pme_name = "PM_PTEG_FROM_DL2L3_MOD",
.pme_code = 0x4c054,
.pme_short_desc = "PTEG loaded from distant L2 or L3 modified",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_DL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_DL2L3_MOD]
},
[ POWER7_PME_PM_DSEG ] = {
.pme_name = "PM_DSEG",
.pme_code = 0x20a6,
.pme_short_desc = "DSEG Exception",
.pme_long_desc = "DSEG Exception",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DSEG],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DSEG]
},
[ POWER7_PME_PM_BR_PRED_LSTACK ] = {
.pme_name = "PM_BR_PRED_LSTACK",
.pme_code = 0x40a2,
.pme_short_desc = "Link Stack Predictions",
.pme_long_desc = "The target address of a Branch to Link instruction was predicted by the link stack.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_LSTACK],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_LSTACK]
},
[ POWER7_PME_PM_VSU0_STF ] = {
.pme_name = "PM_VSU0_STF",
.pme_code = 0xb08c,
.pme_short_desc = "FPU store (SP or DP) issued on Pipe0",
.pme_long_desc = "FPU store (SP or DP) issued on Pipe0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_STF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_STF]
},
[ POWER7_PME_PM_LSU_FX_FIN ] = {
.pme_name = "PM_LSU_FX_FIN",
.pme_code = 0x10066,
.pme_short_desc = "LSU Finished a FX operation (up to 2 per cycle)",
.pme_long_desc = "LSU Finished a FX operation (up to 2 per cycle)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FX_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FX_FIN]
},
[ POWER7_PME_PM_DERAT_MISS_16M ] = {
.pme_name = "PM_DERAT_MISS_16M",
.pme_code = 0x3c05c,
.pme_short_desc = "DERAT misses for 16M page",
.pme_long_desc = "A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DERAT_MISS_16M],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DERAT_MISS_16M]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = {
.pme_name = "PM_MRK_PTEG_FROM_DL2L3_MOD",
.pme_code = 0x4d054,
.pme_short_desc = "Marked PTEG loaded from distant L2 or L3 modified",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a marked load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD]
},
[ POWER7_PME_PM_INST_FROM_L3 ] = {
.pme_name = "PM_INST_FROM_L3",
.pme_code = 0x14048,
.pme_short_desc = "Instruction fetched from L3",
.pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L3],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L3]
},
[ POWER7_PME_PM_MRK_IFU_FIN ] = {
.pme_name = "PM_MRK_IFU_FIN",
.pme_code = 0x3003a,
.pme_short_desc = "IFU non-branch marked instruction finished",
.pme_long_desc = "The Instruction Fetch Unit finished a marked instruction.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_IFU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_IFU_FIN]
},
[ POWER7_PME_PM_ITLB_MISS ] = {
.pme_name = "PM_ITLB_MISS",
.pme_code = 0x400fc,
.pme_short_desc = "ITLB Reloaded (always zero on POWER6)",
.pme_long_desc = "A TLB miss for an Instruction Fetch has occurred",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_ITLB_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_ITLB_MISS]
},
[ POWER7_PME_PM_VSU_STF ] = {
.pme_name = "PM_VSU_STF",
.pme_code = 0xb88c,
.pme_short_desc = "FPU store (SP or DP) issued on Pipe0",
.pme_long_desc = "FPU store (SP or DP) issued on Pipe0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_STF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_STF]
},
[ POWER7_PME_PM_LSU_FLUSH_UST ] = {
.pme_name = "PM_LSU_FLUSH_UST",
.pme_code = 0xc8b4,
.pme_short_desc = "Flush: Unaligned Store",
.pme_long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH_UST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH_UST]
},
[ POWER7_PME_PM_L2_LDST_MISS ] = {
.pme_name = "PM_L2_LDST_MISS",
.pme_code = 0x26880,
.pme_short_desc = "Data Load+Store Miss",
.pme_long_desc = "Data Load+Store Miss",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LDST_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LDST_MISS]
},
[ POWER7_PME_PM_FXU1_FIN ] = {
.pme_name = "PM_FXU1_FIN",
.pme_code = 0x40004,
.pme_short_desc = "FXU1 Finished",
.pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU1_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU1_FIN]
},
[ POWER7_PME_PM_SHL_DEALLOCATED ] = {
.pme_name = "PM_SHL_DEALLOCATED",
.pme_code = 0x5080,
.pme_short_desc = "SHL Table entry deallocated",
.pme_long_desc = "SHL Table entry deallocated",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_SHL_DEALLOCATED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_SHL_DEALLOCATED]
},
[ POWER7_PME_PM_L2_SN_M_WR_DONE ] = {
.pme_name = "PM_L2_SN_M_WR_DONE",
.pme_code = 0x46382,
.pme_short_desc = "SNP dispatched for a write and was M",
.pme_long_desc = "SNP dispatched for a write and was M",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_SN_M_WR_DONE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_SN_M_WR_DONE]
},
[ POWER7_PME_PM_LSU_REJECT_SET_MPRED ] = {
.pme_name = "PM_LSU_REJECT_SET_MPRED",
.pme_code = 0xc8a8,
.pme_short_desc = "Reject: Set Predict Wrong",
.pme_long_desc = "The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT_SET_MPRED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT_SET_MPRED]
},
[ POWER7_PME_PM_L3_PREF_LD ] = {
.pme_name = "PM_L3_PREF_LD",
.pme_code = 0xd0ac,
.pme_short_desc = "L3 cache LD prefetches",
.pme_long_desc = "L3 cache LD prefetches",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_LD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_LD]
},
[ POWER7_PME_PM_L2_SN_M_RD_DONE ] = {
.pme_name = "PM_L2_SN_M_RD_DONE",
.pme_code = 0x46380,
.pme_short_desc = "SNP dispatched for a read and was M",
.pme_long_desc = "SNP dispatched for a read and was M",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_SN_M_RD_DONE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_SN_M_RD_DONE]
},
[ POWER7_PME_PM_MRK_DERAT_MISS_16G ] = {
.pme_name = "PM_MRK_DERAT_MISS_16G",
.pme_code = 0x4d05c,
.pme_short_desc = "Marked DERAT misses for 16G page",
.pme_long_desc = "A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DERAT_MISS_16G],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DERAT_MISS_16G]
},
[ POWER7_PME_PM_VSU_FCONV ] = {
.pme_name = "PM_VSU_FCONV",
.pme_code = 0xa8b0,
.pme_short_desc = "Convert instruction executed",
.pme_long_desc = "Convert instruction executed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FCONV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FCONV]
},
[ POWER7_PME_PM_ANY_THRD_RUN_CYC ] = {
.pme_name = "PM_ANY_THRD_RUN_CYC",
.pme_code = 0x100fa,
.pme_short_desc = "One of threads in run_cycles ",
.pme_long_desc = "One of threads in run_cycles ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_ANY_THRD_RUN_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_ANY_THRD_RUN_CYC]
},
[ POWER7_PME_PM_LSU_LMQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LMQ_FULL_CYC",
.pme_code = 0xd0a4,
.pme_short_desc = "LMQ full",
.pme_long_desc = "The Load Miss Queue was full.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_FULL_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_FULL_CYC]
},
[ POWER7_PME_PM_MRK_LSU_REJECT_LHS ] = {
.pme_name = "PM_MRK_LSU_REJECT_LHS",
.pme_code = 0xd082,
.pme_short_desc = " Reject(marked): Load Hit Store",
.pme_long_desc = "The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_REJECT_LHS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_REJECT_LHS]
},
[ POWER7_PME_PM_MRK_LD_MISS_L1_CYC ] = {
.pme_name = "PM_MRK_LD_MISS_L1_CYC",
.pme_code = 0x4003e,
.pme_short_desc = "L1 data load miss cycles",
.pme_long_desc = "L1 data load miss cycles",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LD_MISS_L1_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LD_MISS_L1_CYC]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L2_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L2_CYC",
.pme_code = 0x20020,
.pme_short_desc = "Marked ld latency Data source 0000 (L2 hit)",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L2_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L2_CYC]
},
[ POWER7_PME_PM_INST_IMC_MATCH_DISP ] = {
.pme_name = "PM_INST_IMC_MATCH_DISP",
.pme_code = 0x30016,
.pme_short_desc = "IMC Matches dispatched",
.pme_long_desc = "IMC Matches dispatched",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_IMC_MATCH_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_IMC_MATCH_DISP]
},
[ POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_RMEM_CYC",
.pme_code = 0x4002c,
.pme_short_desc = "Marked ld latency Data source 1101 (Memory same 4 chip node)",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC]
},
[ POWER7_PME_PM_VSU0_SIMPLE_ISSUED ] = {
.pme_name = "PM_VSU0_SIMPLE_ISSUED",
.pme_code = 0xb094,
.pme_short_desc = "Simple VMX instruction issued",
.pme_long_desc = "Simple VMX instruction issued",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_SIMPLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_SIMPLE_ISSUED]
},
[ POWER7_PME_PM_CMPLU_STALL_DIV ] = {
.pme_name = "PM_CMPLU_STALL_DIV",
.pme_code = 0x40014,
.pme_short_desc = "Completion stall caused by DIV instruction",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_DIV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_DIV]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = {
.pme_name = "PM_MRK_PTEG_FROM_RL2L3_SHR",
.pme_code = 0x2d054,
.pme_short_desc = "Marked PTEG loaded from remote L2 or L3 shared",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR]
},
[ POWER7_PME_PM_VSU_FMA_DOUBLE ] = {
.pme_name = "PM_VSU_FMA_DOUBLE",
.pme_code = 0xa890,
.pme_short_desc = "DP vector version of fmadd",
.pme_long_desc = "fnmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FMA_DOUBLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FMA_DOUBLE]
},
[ POWER7_PME_PM_VSU_4FLOP ] = {
.pme_name = "PM_VSU_4FLOP",
.pme_code = 0xa89c,
.pme_short_desc = "four flops operation (scalar fdiv",
.pme_long_desc = " fsqrt; DP vector version of fmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_4FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_4FLOP]
},
[ POWER7_PME_PM_VSU1_FIN ] = {
.pme_name = "PM_VSU1_FIN",
.pme_code = 0xa0be,
.pme_short_desc = "VSU1 Finished an instruction",
.pme_long_desc = "VSU1 Finished an instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FIN]
},
[ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD ] = {
.pme_name = "PM_INST_PTEG_FROM_RL2L3_MOD",
.pme_code = 0x1e052,
.pme_short_desc = "Instruction PTEG loaded from remote L2 or L3 modified",
.pme_long_desc = "Instruction PTEG loaded from remote L2 or L3 modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD]
},
[ POWER7_PME_PM_RUN_CYC ] = {
.pme_name = "PM_RUN_CYC",
.pme_code = 0x200f4,
.pme_short_desc = "Run_cycles",
.pme_long_desc = "Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_RUN_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_RUN_CYC]
},
[ POWER7_PME_PM_PTEG_FROM_RMEM ] = {
.pme_name = "PM_PTEG_FROM_RMEM",
.pme_code = 0x3c052,
.pme_short_desc = "PTEG loaded from remote memory",
.pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_RMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_RMEM]
},
[ POWER7_PME_PM_LSU_LRQ_S0_VALID ] = {
.pme_name = "PM_LSU_LRQ_S0_VALID",
.pme_code = 0xd09e,
.pme_short_desc = "Slot 0 of LRQ valid",
.pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LRQ_S0_VALID],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LRQ_S0_VALID]
},
[ POWER7_PME_PM_LSU0_LDF ] = {
.pme_name = "PM_LSU0_LDF",
.pme_code = 0xc084,
.pme_short_desc = "LS0 Scalar Loads",
.pme_long_desc = "A floating point load was executed by LSU0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_LDF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_LDF]
},
[ POWER7_PME_PM_FLUSH_COMPLETION ] = {
.pme_name = "PM_FLUSH_COMPLETION",
.pme_code = 0x30012,
.pme_short_desc = "Completion Flush",
.pme_long_desc = "Completion Flush",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_COMPLETION],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_COMPLETION]
},
[ POWER7_PME_PM_ST_MISS_L1 ] = {
.pme_name = "PM_ST_MISS_L1",
.pme_code = 0x300f0,
.pme_short_desc = "L1 D cache store misses",
.pme_long_desc = "A store missed the dcache. Combined Unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_ST_MISS_L1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_ST_MISS_L1]
},
[ POWER7_PME_PM_L2_NODE_PUMP ] = {
.pme_name = "PM_L2_NODE_PUMP",
.pme_code = 0x36480,
.pme_short_desc = "RC req that was a local (aka node) pump attempt",
.pme_long_desc = "RC req that was a local (aka node) pump attempt",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_NODE_PUMP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_NODE_PUMP]
},
[ POWER7_PME_PM_INST_FROM_DL2L3_SHR ] = {
.pme_name = "PM_INST_FROM_DL2L3_SHR",
.pme_code = 0x34044,
.pme_short_desc = "Instruction fetched from distant L2 or L3 shared",
.pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_DL2L3_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_DL2L3_SHR]
},
[ POWER7_PME_PM_MRK_STALL_CMPLU_CYC ] = {
.pme_name = "PM_MRK_STALL_CMPLU_CYC",
.pme_code = 0x3003e,
.pme_short_desc = "Marked Group Completion Stall cycles ",
.pme_long_desc = "Marked Group Completion Stall cycles ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_STALL_CMPLU_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_STALL_CMPLU_CYC]
},
[ POWER7_PME_PM_VSU1_DENORM ] = {
.pme_name = "PM_VSU1_DENORM",
.pme_code = 0xa0ae,
.pme_short_desc = "FPU denorm operand",
.pme_long_desc = "VSU1 received denormalized data",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_DENORM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_DENORM]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L31_SHR_CYC",
.pme_code = 0x20026,
.pme_short_desc = "Marked ld latency Data source 0110 (L3.1 S) ",
.pme_long_desc = "Marked load latency Data source 0110 (L3.1 S) ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC]
},
[ POWER7_PME_PM_GCT_USAGE_1TO2_SLOT ] = {
.pme_name = "PM_GCT_USAGE_1-2_SLOT",
.pme_code = 0x209c,
.pme_short_desc = "GCT Utilization 1-2 entries",
.pme_long_desc = "GCT Utilization 1-2 entries",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_USAGE_1TO2_SLOT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_USAGE_1TO2_SLOT]
},
[ POWER7_PME_PM_NEST_6 ] = {
.pme_name = "PM_NEST_6",
.pme_code = 0x8b,
.pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_6],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_6]
},
[ POWER7_PME_PM_INST_FROM_L3MISS ] = {
.pme_name = "PM_INST_FROM_L3MISS",
.pme_code = 0x24048,
.pme_short_desc = "Instruction fetched missed L3",
.pme_long_desc = "An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L3MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L3MISS]
},
[ POWER7_PME_PM_EE_OFF_EXT_INT ] = {
.pme_name = "PM_EE_OFF_EXT_INT",
.pme_code = 0x2080,
.pme_short_desc = "ee off and external interrupt",
.pme_long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_EE_OFF_EXT_INT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_EE_OFF_EXT_INT]
},
[ POWER7_PME_PM_INST_PTEG_FROM_DMEM ] = {
.pme_name = "PM_INST_PTEG_FROM_DMEM",
.pme_code = 0x2e052,
.pme_short_desc = "Instruction PTEG loaded from distant memory",
.pme_long_desc = "Instruction PTEG loaded from distant memory",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_DMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_DMEM]
},
[ POWER7_PME_PM_INST_FROM_DL2L3_MOD ] = {
.pme_name = "PM_INST_FROM_DL2L3_MOD",
.pme_code = 0x3404c,
.pme_short_desc = "Instruction fetched from distant L2 or L3 modified",
.pme_long_desc = "An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_DL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_DL2L3_MOD]
},
[ POWER7_PME_PM_PMC6_OVERFLOW ] = {
.pme_name = "PM_PMC6_OVERFLOW",
.pme_code = 0x30024,
.pme_short_desc = "Overflow from counter 6",
.pme_long_desc = "Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC6_OVERFLOW],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC6_OVERFLOW]
},
[ POWER7_PME_PM_VSU_2FLOP_DOUBLE ] = {
.pme_name = "PM_VSU_2FLOP_DOUBLE",
.pme_code = 0xa88c,
.pme_short_desc = "DP vector version of fmul",
.pme_long_desc = " fsub",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_2FLOP_DOUBLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_2FLOP_DOUBLE]
},
[ POWER7_PME_PM_TLB_MISS ] = {
.pme_name = "PM_TLB_MISS",
.pme_code = 0x20066,
.pme_short_desc = "TLB Miss (I + D)",
.pme_long_desc = "Total of Data TLB mises + Instruction TLB misses",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_TLB_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_TLB_MISS]
},
[ POWER7_PME_PM_FXU_BUSY ] = {
.pme_name = "PM_FXU_BUSY",
.pme_code = 0x2000e,
.pme_short_desc = "fxu0 busy and fxu1 busy.",
.pme_long_desc = "Cycles when both FXU0 and FXU1 are busy.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU_BUSY],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU_BUSY]
},
[ POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2_RCLD_DISP_FAIL_OTHER",
.pme_code = 0x26280,
.pme_short_desc = " L2 RC load dispatch attempt failed due to other reasons",
.pme_long_desc = " L2 RC load dispatch attempt failed due to other reasons",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER]
},
[ POWER7_PME_PM_LSU_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU_REJECT_LMQ_FULL",
.pme_code = 0xc8a4,
.pme_short_desc = "Reject: LMQ Full (LHR)",
.pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT_LMQ_FULL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT_LMQ_FULL]
},
[ POWER7_PME_PM_IC_RELOAD_SHR ] = {
.pme_name = "PM_IC_RELOAD_SHR",
.pme_code = 0x4096,
.pme_short_desc = "Reloading line to be shared between the threads",
.pme_long_desc = "An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_RELOAD_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_RELOAD_SHR]
},
[ POWER7_PME_PM_GRP_MRK ] = {
.pme_name = "PM_GRP_MRK",
.pme_code = 0x10031,
.pme_short_desc = "IDU Marked Instruction",
.pme_long_desc = "A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_MRK],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_MRK]
},
[ POWER7_PME_PM_MRK_ST_NEST ] = {
.pme_name = "PM_MRK_ST_NEST",
.pme_code = 0x20034,
.pme_short_desc = "marked store sent to Nest",
.pme_long_desc = "A sampled store has been sent to the memory subsystem",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_ST_NEST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_ST_NEST]
},
[ POWER7_PME_PM_VSU1_FSQRT_FDIV ] = {
.pme_name = "PM_VSU1_FSQRT_FDIV",
.pme_code = 0xa08a,
.pme_short_desc = "four flops operation (fdiv",
.pme_long_desc = "fsqrt",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FSQRT_FDIV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FSQRT_FDIV]
},
[ POWER7_PME_PM_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_LSU0_FLUSH_LRQ",
.pme_code = 0xc0b8,
.pme_short_desc = "LS0 Flush: LRQ",
.pme_long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_FLUSH_LRQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_FLUSH_LRQ]
},
[ POWER7_PME_PM_LARX_LSU0 ] = {
.pme_name = "PM_LARX_LSU0",
.pme_code = 0xc094,
.pme_short_desc = "ls0 Larx Finished",
.pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LARX_LSU0],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LARX_LSU0]
},
[ POWER7_PME_PM_IBUF_FULL_CYC ] = {
.pme_name = "PM_IBUF_FULL_CYC",
.pme_code = 0x4084,
.pme_short_desc = "Cycles No room in ibuff",
.pme_long_desc = "Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IBUF_FULL_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IBUF_FULL_CYC]
},
[ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
.pme_code = 0x2002a,
.pme_short_desc = "Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)",
.pme_long_desc = "Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC]
},
[ POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC ] = {
.pme_name = "PM_LSU_DC_PREF_STREAM_ALLOC",
.pme_code = 0xd8a8,
.pme_short_desc = "D cache new prefetch stream allocated",
.pme_long_desc = "D cache new prefetch stream allocated",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC]
},
[ POWER7_PME_PM_GRP_MRK_CYC ] = {
.pme_name = "PM_GRP_MRK_CYC",
.pme_code = 0x10030,
.pme_short_desc = "cycles IDU marked instruction before dispatch",
.pme_long_desc = "cycles IDU marked instruction before dispatch",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_MRK_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_MRK_CYC]
},
[ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
.pme_code = 0x20028,
.pme_short_desc = "Marked ld latency Data Source 1000 (Remote L2.5/L3.5 S)",
.pme_long_desc = "Marked load latency Data Source 1000 (Remote L2.5/L3.5 S)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC]
},
[ POWER7_PME_PM_L2_GLOB_GUESS_CORRECT ] = {
.pme_name = "PM_L2_GLOB_GUESS_CORRECT",
.pme_code = 0x16482,
.pme_short_desc = "L2 guess glb and guess was correct (ie data remote)",
.pme_long_desc = "L2 guess glb and guess was correct (ie data remote)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_GLOB_GUESS_CORRECT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_GLOB_GUESS_CORRECT]
},
[ POWER7_PME_PM_LSU_REJECT_LHS ] = {
.pme_name = "PM_LSU_REJECT_LHS",
.pme_code = 0xc8ac,
.pme_short_desc = "Reject: Load Hit Store",
.pme_long_desc = "The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT_LHS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT_LHS]
},
[ POWER7_PME_PM_MRK_DATA_FROM_LMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_LMEM",
.pme_code = 0x3d04a,
.pme_short_desc = "Marked data loaded from local memory",
.pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_LMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_LMEM]
},
[ POWER7_PME_PM_INST_PTEG_FROM_L3 ] = {
.pme_name = "PM_INST_PTEG_FROM_L3",
.pme_code = 0x2e050,
.pme_short_desc = "Instruction PTEG loaded from L3",
.pme_long_desc = "Instruction PTEG loaded from L3",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L3],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L3]
},
[ POWER7_PME_PM_FREQ_DOWN ] = {
.pme_name = "PM_FREQ_DOWN",
.pme_code = 0x3000c,
.pme_short_desc = "Frequency is being slewed down due to Power Management",
.pme_long_desc = "Processor frequency was slowed down due to power management",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FREQ_DOWN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FREQ_DOWN]
},
[ POWER7_PME_PM_INST_FROM_RL2L3_SHR ] = {
.pme_name = "PM_INST_FROM_RL2L3_SHR",
.pme_code = 0x1404c,
.pme_short_desc = "Instruction fetched from remote L2 or L3 shared",
.pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_RL2L3_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_RL2L3_SHR]
},
[ POWER7_PME_PM_MRK_INST_ISSUED ] = {
.pme_name = "PM_MRK_INST_ISSUED",
.pme_code = 0x10032,
.pme_short_desc = "Marked instruction issued",
.pme_long_desc = "A marked instruction was issued to an execution unit.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_INST_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_INST_ISSUED]
},
[ POWER7_PME_PM_PTEG_FROM_L3MISS ] = {
.pme_name = "PM_PTEG_FROM_L3MISS",
.pme_code = 0x2c058,
.pme_short_desc = "PTEG loaded from L3 miss",
.pme_long_desc = " Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L3MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L3MISS]
},
[ POWER7_PME_PM_RUN_PURR ] = {
.pme_name = "PM_RUN_PURR",
.pme_code = 0x400f4,
.pme_short_desc = "Run_PURR",
.pme_long_desc = "The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_RUN_PURR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_RUN_PURR]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L3 ] = {
.pme_name = "PM_MRK_DATA_FROM_L3",
.pme_code = 0x1d048,
.pme_short_desc = "Marked data loaded from L3",
.pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L3],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L3]
},
[ POWER7_PME_PM_MRK_GRP_IC_MISS ] = {
.pme_name = "PM_MRK_GRP_IC_MISS",
.pme_code = 0x40038,
.pme_short_desc = "Marked group experienced I cache miss",
.pme_long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_GRP_IC_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_GRP_IC_MISS]
},
[ POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
.pme_name = "PM_CMPLU_STALL_DCACHE_MISS",
.pme_code = 0x20016,
.pme_short_desc = " Completion stall caused by D cache miss",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS]
},
[ POWER7_PME_PM_PTEG_FROM_RL2L3_SHR ] = {
.pme_name = "PM_PTEG_FROM_RL2L3_SHR",
.pme_code = 0x2c054,
.pme_short_desc = "PTEG loaded from remote L2 or L3 shared",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_RL2L3_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_RL2L3_SHR]
},
[ POWER7_PME_PM_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_LSU_FLUSH_LRQ",
.pme_code = 0xc8b8,
.pme_short_desc = "Flush: LRQ",
.pme_long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH_LRQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH_LRQ]
},
[ POWER7_PME_PM_MRK_DERAT_MISS_64K ] = {
.pme_name = "PM_MRK_DERAT_MISS_64K",
.pme_code = 0x2d05c,
.pme_short_desc = "Marked DERAT misses for 64K page",
.pme_long_desc = "A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DERAT_MISS_64K],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DERAT_MISS_64K]
},
[ POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD ] = {
.pme_name = "PM_INST_PTEG_FROM_DL2L3_MOD",
.pme_code = 0x4e054,
.pme_short_desc = "Instruction PTEG loaded from distant L2 or L3 modified",
.pme_long_desc = "Instruction PTEG loaded from distant L2 or L3 modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD]
},
[ POWER7_PME_PM_L2_ST_MISS ] = {
.pme_name = "PM_L2_ST_MISS",
.pme_code = 0x26082,
.pme_short_desc = "Data Store Miss",
.pme_long_desc = "Data Store Miss",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_ST_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_ST_MISS]
},
[ POWER7_PME_PM_LWSYNC ] = {
.pme_name = "PM_LWSYNC",
.pme_code = 0xd094,
.pme_short_desc = "lwsync count (easier to use than IMC)",
.pme_long_desc = "lwsync count (easier to use than IMC)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LWSYNC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LWSYNC]
},
[ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE ] = {
.pme_name = "PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE",
.pme_code = 0xd0bc,
.pme_short_desc = "LS0 Dcache Strided prefetch stream confirmed",
.pme_long_desc = "LS0 Dcache Strided prefetch stream confirmed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR ] = {
.pme_name = "PM_MRK_PTEG_FROM_L21_SHR",
.pme_code = 0x4d056,
.pme_short_desc = "Marked PTEG loaded from another L2 on same chip shared",
.pme_long_desc = "Marked PTEG loaded from another L2 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR]
},
[ POWER7_PME_PM_MRK_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU_FLUSH_LRQ",
.pme_code = 0xd088,
.pme_short_desc = "Flush: (marked) LRQ",
.pme_long_desc = "Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH_LRQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH_LRQ]
},
[ POWER7_PME_PM_INST_IMC_MATCH_CMPL ] = {
.pme_name = "PM_INST_IMC_MATCH_CMPL",
.pme_code = 0x100f0,
.pme_short_desc = "IMC Match Count",
.pme_long_desc = "Number of instructions resulting from the marked instructions expansion that completed.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_IMC_MATCH_CMPL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_IMC_MATCH_CMPL]
},
[ POWER7_PME_PM_MRK_INST_FIN ] = {
.pme_name = "PM_MRK_INST_FIN",
.pme_code = 0x30030,
.pme_short_desc = "marked instr finish any unit ",
.pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_INST_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_INST_FIN]
},
[ POWER7_PME_PM_INST_FROM_L31_MOD ] = {
.pme_name = "PM_INST_FROM_L31_MOD",
.pme_code = 0x14044,
.pme_short_desc = "Instruction fetched from another L3 on same chip modified",
.pme_long_desc = "Instruction fetched from another L3 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L31_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L31_MOD]
},
[ POWER7_PME_PM_MRK_DTLB_MISS_64K ] = {
.pme_name = "PM_MRK_DTLB_MISS_64K",
.pme_code = 0x3d05e,
.pme_short_desc = "Marked Data TLB misses for 64K page",
.pme_long_desc = "Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DTLB_MISS_64K],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DTLB_MISS_64K]
},
[ POWER7_PME_PM_LSU_FIN ] = {
.pme_name = "PM_LSU_FIN",
.pme_code = 0x30066,
.pme_short_desc = "LSU Finished an instruction (up to 2 per cycle)",
.pme_long_desc = "LSU Finished an instruction (up to 2 per cycle)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FIN]
},
[ POWER7_PME_PM_MRK_LSU_REJECT ] = {
.pme_name = "PM_MRK_LSU_REJECT",
.pme_code = 0x40064,
.pme_short_desc = "LSU marked reject (up to 2 per cycle)",
.pme_long_desc = "LSU marked reject (up to 2 per cycle)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_REJECT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_REJECT]
},
[ POWER7_PME_PM_L2_CO_FAIL_BUSY ] = {
.pme_name = "PM_L2_CO_FAIL_BUSY",
.pme_code = 0x16382,
.pme_short_desc = " L2 RC Cast Out dispatch attempt failed due to all CO machines busy",
.pme_long_desc = " L2 RC Cast Out dispatch attempt failed due to all CO machines busy",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_CO_FAIL_BUSY],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_CO_FAIL_BUSY]
},
[ POWER7_PME_PM_DATA_FROM_L31_MOD ] = {
.pme_name = "PM_DATA_FROM_L31_MOD",
.pme_code = 0x1c044,
.pme_short_desc = "Data loaded from another L3 on same chip modified",
.pme_long_desc = "Data loaded from another L3 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L31_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L31_MOD]
},
[ POWER7_PME_PM_THERMAL_WARN ] = {
.pme_name = "PM_THERMAL_WARN",
.pme_code = 0x10016,
.pme_short_desc = "Processor in Thermal Warning",
.pme_long_desc = "Processor in Thermal Warning",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THERMAL_WARN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THERMAL_WARN]
},
[ POWER7_PME_PM_VSU0_4FLOP ] = {
.pme_name = "PM_VSU0_4FLOP",
.pme_code = 0xa09c,
.pme_short_desc = "four flops operation (scalar fdiv",
.pme_long_desc = " fsqrt; DP vector version of fmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_4FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_4FLOP]
},
[ POWER7_PME_PM_BR_MPRED_CCACHE ] = {
.pme_name = "PM_BR_MPRED_CCACHE",
.pme_code = 0x40a4,
.pme_short_desc = "Branch Mispredict due to Count Cache prediction",
.pme_long_desc = "A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_CCACHE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_CCACHE]
},
[ POWER7_PME_PM_L1_DEMAND_WRITE ] = {
.pme_name = "PM_L1_DEMAND_WRITE",
.pme_code = 0x408c,
.pme_short_desc = "Instruction Demand sectors wriittent into IL1",
.pme_long_desc = "Instruction Demand sectors wriittent into IL1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L1_DEMAND_WRITE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L1_DEMAND_WRITE]
},
[ POWER7_PME_PM_FLUSH_BR_MPRED ] = {
.pme_name = "PM_FLUSH_BR_MPRED",
.pme_code = 0x2084,
.pme_short_desc = "Flush caused by branch mispredict",
.pme_long_desc = "A flush was caused by a branch mispredict.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_BR_MPRED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_BR_MPRED]
},
[ POWER7_PME_PM_MRK_DTLB_MISS_16G ] = {
.pme_name = "PM_MRK_DTLB_MISS_16G",
.pme_code = 0x1d05e,
.pme_short_desc = "Marked Data TLB misses for 16G page",
.pme_long_desc = "Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DTLB_MISS_16G],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DTLB_MISS_16G]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_DMEM ] = {
.pme_name = "PM_MRK_PTEG_FROM_DMEM",
.pme_code = 0x2d052,
.pme_short_desc = "Marked PTEG loaded from distant memory",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_DMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_DMEM]
},
[ POWER7_PME_PM_L2_RCST_DISP ] = {
.pme_name = "PM_L2_RCST_DISP",
.pme_code = 0x36280,
.pme_short_desc = " L2 RC store dispatch attempt",
.pme_long_desc = " L2 RC store dispatch attempt",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCST_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCST_DISP]
},
[ POWER7_PME_PM_CMPLU_STALL ] = {
.pme_name = "PM_CMPLU_STALL",
.pme_code = 0x4000a,
.pme_short_desc = "No groups completed",
.pme_long_desc = " GCT not empty",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL]
},
[ POWER7_PME_PM_LSU_PARTIAL_CDF ] = {
.pme_name = "PM_LSU_PARTIAL_CDF",
.pme_code = 0xc0aa,
.pme_short_desc = "A partial cacheline was returned from the L3",
.pme_long_desc = "A partial cacheline was returned from the L3",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_PARTIAL_CDF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_PARTIAL_CDF]
},
[ POWER7_PME_PM_DISP_CLB_HELD_SB ] = {
.pme_name = "PM_DISP_CLB_HELD_SB",
.pme_code = 0x20a8,
.pme_short_desc = "Dispatch/CLB Hold: Scoreboard",
.pme_long_desc = "Dispatch/CLB Hold: Scoreboard",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_SB],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_SB]
},
[ POWER7_PME_PM_VSU0_FMA_DOUBLE ] = {
.pme_name = "PM_VSU0_FMA_DOUBLE",
.pme_code = 0xa090,
.pme_short_desc = "four flop DP vector operations (xvmadddp",
.pme_long_desc = " xvnmadddp",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FMA_DOUBLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FMA_DOUBLE]
},
[ POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
.pme_name = "PM_FXU0_BUSY_FXU1_IDLE",
.pme_code = 0x3000e,
.pme_short_desc = "fxu0 busy and fxu1 idle",
.pme_long_desc = "FXU0 is busy while FXU1 was idle",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE]
},
[ POWER7_PME_PM_IC_DEMAND_CYC ] = {
.pme_name = "PM_IC_DEMAND_CYC",
.pme_code = 0x10018,
.pme_short_desc = "Cycles when a demand ifetch was pending",
.pme_long_desc = "Cycles when a demand ifetch was pending",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_CYC]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L21_SHR",
.pme_code = 0x3d04e,
.pme_short_desc = "Marked data loaded from another L2 on same chip shared",
.pme_long_desc = "Marked data loaded from another L2 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L21_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L21_SHR]
},
[ POWER7_PME_PM_MRK_LSU_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU_FLUSH_UST",
.pme_code = 0xd086,
.pme_short_desc = "Flush: (marked) Unaligned Store",
.pme_long_desc = "A marked store was flushed because it was unaligned",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH_UST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH_UST]
},
[ POWER7_PME_PM_INST_PTEG_FROM_L3MISS ] = {
.pme_name = "PM_INST_PTEG_FROM_L3MISS",
.pme_code = 0x2e058,
.pme_short_desc = "Instruction PTEG loaded from L3 miss",
.pme_long_desc = "Instruction PTEG loaded from L3 miss",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L3MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L3MISS]
},
[ POWER7_PME_PM_VSU_DENORM ] = {
.pme_name = "PM_VSU_DENORM",
.pme_code = 0xa8ac,
.pme_short_desc = "Vector or Scalar denorm operand",
.pme_long_desc = "Vector or Scalar denorm operand",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_DENORM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_DENORM]
},
[ POWER7_PME_PM_MRK_LSU_PARTIAL_CDF ] = {
.pme_name = "PM_MRK_LSU_PARTIAL_CDF",
.pme_code = 0xd080,
.pme_short_desc = "A partial cacheline was returned from the L3 for a marked load",
.pme_long_desc = "A partial cacheline was returned from the L3 for a marked load",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_PARTIAL_CDF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_PARTIAL_CDF]
},
[ POWER7_PME_PM_INST_FROM_L21_SHR ] = {
.pme_name = "PM_INST_FROM_L21_SHR",
.pme_code = 0x3404e,
.pme_short_desc = "Instruction fetched from another L2 on same chip shared",
.pme_long_desc = "Instruction fetched from another L2 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L21_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L21_SHR]
},
[ POWER7_PME_PM_IC_PREF_WRITE ] = {
.pme_name = "PM_IC_PREF_WRITE",
.pme_code = 0x408e,
.pme_short_desc = "Instruction prefetch written into IL1",
.pme_long_desc = "Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_WRITE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_WRITE]
},
[ POWER7_PME_PM_BR_PRED ] = {
.pme_name = "PM_BR_PRED",
.pme_code = 0x409c,
.pme_short_desc = "Branch Predictions made",
.pme_long_desc = "A branch prediction was made. This could have been a target prediction, a condition prediction, or both",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED]
},
[ POWER7_PME_PM_INST_FROM_DMEM ] = {
.pme_name = "PM_INST_FROM_DMEM",
.pme_code = 0x1404a,
.pme_short_desc = "Instruction fetched from distant memory",
.pme_long_desc = "An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_DMEM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_DMEM]
},
[ POWER7_PME_PM_IC_PREF_CANCEL_ALL ] = {
.pme_name = "PM_IC_PREF_CANCEL_ALL",
.pme_code = 0x4890,
.pme_short_desc = "Prefetch Canceled due to page boundary or icache hit",
.pme_long_desc = "Prefetch Canceled due to page boundary or icache hit",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_CANCEL_ALL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_CANCEL_ALL]
},
[ POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM ] = {
.pme_name = "PM_LSU_DC_PREF_STREAM_CONFIRM",
.pme_code = 0xd8b4,
.pme_short_desc = "Dcache new prefetch stream confirmed",
.pme_long_desc = "Dcache new prefetch stream confirmed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM]
},
[ POWER7_PME_PM_MRK_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU_FLUSH_SRQ",
.pme_code = 0xd08a,
.pme_short_desc = "Flush: (marked) SRQ",
.pme_long_desc = "Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH_SRQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH_SRQ]
},
[ POWER7_PME_PM_MRK_FIN_STALL_CYC ] = {
.pme_name = "PM_MRK_FIN_STALL_CYC",
.pme_code = 0x1003c,
.pme_short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) ",
.pme_long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_FIN_STALL_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_FIN_STALL_CYC]
},
[ POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT ] = {
.pme_name = "PM_GCT_UTIL_11+_SLOT",
.pme_code = 0x20a2,
.pme_short_desc = "GCT Utilization 11+ entries",
.pme_long_desc = "GCT Utilization 11+ entries",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT]
},
[ POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2_RCST_DISP_FAIL_OTHER",
.pme_code = 0x46280,
.pme_short_desc = " L2 RC store dispatch attempt failed due to other reasons",
.pme_long_desc = " L2 RC store dispatch attempt failed due to other reasons",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER]
},
[ POWER7_PME_PM_VSU1_DD_ISSUED ] = {
.pme_name = "PM_VSU1_DD_ISSUED",
.pme_code = 0xb098,
.pme_short_desc = "64BIT Decimal Issued on Pipe1",
.pme_long_desc = "64BIT Decimal Issued on Pipe1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_DD_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_DD_ISSUED]
},
[ POWER7_PME_PM_PTEG_FROM_L31_SHR ] = {
.pme_name = "PM_PTEG_FROM_L31_SHR",
.pme_code = 0x2c056,
.pme_short_desc = "PTEG loaded from another L3 on same chip shared",
.pme_long_desc = "PTEG loaded from another L3 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L31_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L31_SHR]
},
[ POWER7_PME_PM_DATA_FROM_L21_SHR ] = {
.pme_name = "PM_DATA_FROM_L21_SHR",
.pme_code = 0x3c04e,
.pme_short_desc = "Data loaded from another L2 on same chip shared",
.pme_long_desc = "Data loaded from another L2 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L21_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L21_SHR]
},
[ POWER7_PME_PM_LSU0_NCLD ] = {
.pme_name = "PM_LSU0_NCLD",
.pme_code = 0xc08c,
.pme_short_desc = "LS0 Non-cachable Loads counted at finish",
.pme_long_desc = "A non-cacheable load was executed by unit 0.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_NCLD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_NCLD]
},
[ POWER7_PME_PM_VSU1_4FLOP ] = {
.pme_name = "PM_VSU1_4FLOP",
.pme_code = 0xa09e,
.pme_short_desc = "four flops operation (scalar fdiv",
.pme_long_desc = " fsqrt; DP vector version of fmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_4FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_4FLOP]
},
[ POWER7_PME_PM_VSU1_8FLOP ] = {
.pme_name = "PM_VSU1_8FLOP",
.pme_code = 0xa0a2,
.pme_short_desc = "eight flops operation (DP vector versions of fdiv",
.pme_long_desc = "fsqrt and SP vector versions of fmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_8FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_8FLOP]
},
[ POWER7_PME_PM_VSU_8FLOP ] = {
.pme_name = "PM_VSU_8FLOP",
.pme_code = 0xa8a0,
.pme_short_desc = "eight flops operation (DP vector versions of fdiv",
.pme_long_desc = "fsqrt and SP vector versions of fmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_8FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_8FLOP]
},
[ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
.pme_code = 0x2003e,
.pme_short_desc = "LSU empty (lmq and srq empty)",
.pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC]
},
[ POWER7_PME_PM_DTLB_MISS_64K ] = {
.pme_name = "PM_DTLB_MISS_64K",
.pme_code = 0x3c05e,
.pme_short_desc = "Data TLB miss for 64K page",
.pme_long_desc = "Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS_64K],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS_64K]
},
[ POWER7_PME_PM_THRD_CONC_RUN_INST ] = {
.pme_name = "PM_THRD_CONC_RUN_INST",
.pme_code = 0x300f4,
.pme_short_desc = "Concurrent Run Instructions",
.pme_long_desc = "Instructions completed by this thread when both threads had their run latches set.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_CONC_RUN_INST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_CONC_RUN_INST]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_L2 ] = {
.pme_name = "PM_MRK_PTEG_FROM_L2",
.pme_code = 0x1d050,
.pme_short_desc = "Marked PTEG loaded from L2",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L2],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L2]
},
[ POWER7_PME_PM_VSU_FIN ] = {
.pme_name = "PM_VSU_FIN",
.pme_code = 0xa8bc,
.pme_short_desc = "VSU0 Finished an instruction",
.pme_long_desc = "VSU0 Finished an instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FIN]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L31_MOD",
.pme_code = 0x1d044,
.pme_short_desc = "Marked data loaded from another L3 on same chip modified",
.pme_long_desc = "Marked data loaded from another L3 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L31_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L31_MOD]
},
[ POWER7_PME_PM_THRD_PRIO_0_1_CYC ] = {
.pme_name = "PM_THRD_PRIO_0_1_CYC",
.pme_code = 0x40b0,
.pme_short_desc = " Cycles thread running at priority level 0 or 1",
.pme_long_desc = " Cycles thread running at priority level 0 or 1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_PRIO_0_1_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_PRIO_0_1_CYC]
},
[ POWER7_PME_PM_DERAT_MISS_64K ] = {
.pme_name = "PM_DERAT_MISS_64K",
.pme_code = 0x2c05c,
.pme_short_desc = "DERAT misses for 64K page",
.pme_long_desc = "A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DERAT_MISS_64K],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DERAT_MISS_64K]
},
[ POWER7_PME_PM_PMC2_REWIND ] = {
.pme_name = "PM_PMC2_REWIND",
.pme_code = 0x30020,
.pme_short_desc = "PMC2 Rewind Event (did not match condition)",
.pme_long_desc = "PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC2_REWIND],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC2_REWIND]
},
[ POWER7_PME_PM_INST_FROM_L2 ] = {
.pme_name = "PM_INST_FROM_L2",
.pme_code = 0x14040,
.pme_short_desc = "Instruction fetched from L2",
.pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L2],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L2]
},
[ POWER7_PME_PM_GRP_BR_MPRED_NONSPEC ] = {
.pme_name = "PM_GRP_BR_MPRED_NONSPEC",
.pme_code = 0x1000a,
.pme_short_desc = "Group experienced non-speculative branch redirect",
.pme_long_desc = "Group experienced non-speculative branch redirect",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_BR_MPRED_NONSPEC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_BR_MPRED_NONSPEC]
},
[ POWER7_PME_PM_INST_DISP ] = {
.pme_name = "PM_INST_DISP",
.pme_code = 0x200f2,
.pme_short_desc = "# PPC Dispatched",
.pme_long_desc = "Number of PowerPC instructions successfully dispatched.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_DISP]
},
[ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM ] = {
.pme_name = "PM_LSU0_DC_PREF_STREAM_CONFIRM",
.pme_code = 0xd0b4,
.pme_short_desc = "LS0 Dcache prefetch stream confirmed",
.pme_long_desc = "LS0 Dcache prefetch stream confirmed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM]
},
[ POWER7_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
.pme_code = 0x300f6,
.pme_short_desc = "L1 reload data source valid",
.pme_long_desc = "The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L1_DCACHE_RELOAD_VALID],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L1_DCACHE_RELOAD_VALID]
},
[ POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED ] = {
.pme_name = "PM_VSU_SCALAR_DOUBLE_ISSUED",
.pme_code = 0xb888,
.pme_short_desc = "Double Precision scalar instruction issued on Pipe0",
.pme_long_desc = "Double Precision scalar instruction issued on Pipe0",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED]
},
[ POWER7_PME_PM_L3_PREF_HIT ] = {
.pme_name = "PM_L3_PREF_HIT",
.pme_code = 0x3f080,
.pme_short_desc = "L3 Prefetch Directory Hit",
.pme_long_desc = "L3 Prefetch Directory Hit",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_HIT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_HIT]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD ] = {
.pme_name = "PM_MRK_PTEG_FROM_L31_MOD",
.pme_code = 0x1d054,
.pme_short_desc = "Marked PTEG loaded from another L3 on same chip modified",
.pme_long_desc = "Marked PTEG loaded from another L3 on same chip modified",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD]
},
[ POWER7_PME_PM_MRK_FXU_FIN ] = {
.pme_name = "PM_MRK_FXU_FIN",
.pme_code = 0x20038,
.pme_short_desc = "fxu marked instr finish",
.pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_FXU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_FXU_FIN]
},
[ POWER7_PME_PM_PMC4_OVERFLOW ] = {
.pme_name = "PM_PMC4_OVERFLOW",
.pme_code = 0x10010,
.pme_short_desc = "Overflow from counter 4",
.pme_long_desc = "Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC4_OVERFLOW],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC4_OVERFLOW]
},
[ POWER7_PME_PM_MRK_PTEG_FROM_L3 ] = {
.pme_name = "PM_MRK_PTEG_FROM_L3",
.pme_code = 0x2d050,
.pme_short_desc = "Marked PTEG loaded from L3",
.pme_long_desc = "A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L3],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L3]
},
[ POWER7_PME_PM_LSU0_LMQ_LHR_MERGE ] = {
.pme_name = "PM_LSU0_LMQ_LHR_MERGE",
.pme_code = 0xd098,
.pme_short_desc = "LS0 Load Merged with another cacheline request",
.pme_long_desc = "LS0 Load Merged with another cacheline request",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_LMQ_LHR_MERGE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_LMQ_LHR_MERGE]
},
[ POWER7_PME_PM_BTAC_HIT ] = {
.pme_name = "PM_BTAC_HIT",
.pme_code = 0x508a,
.pme_short_desc = "BTAC Correct Prediction",
.pme_long_desc = "BTAC Correct Prediction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BTAC_HIT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BTAC_HIT]
},
[ POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS ] = {
.pme_name = "PM_IERAT_XLATE_WR_16M+",
.pme_code = 0x40bc,
.pme_short_desc = "large page 16M+",
.pme_long_desc = "large page 16M+",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS]
},
[ POWER7_PME_PM_L3_RD_BUSY ] = {
.pme_name = "PM_L3_RD_BUSY",
.pme_code = 0x4f082,
.pme_short_desc = "Rd machines busy >= threshold (2",
.pme_long_desc = "4",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_RD_BUSY],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_RD_BUSY]
},
[ POWER7_PME_PM_INST_FROM_L2MISS ] = {
.pme_name = "PM_INST_FROM_L2MISS",
.pme_code = 0x44048,
.pme_short_desc = "Instruction fetched missed L2",
.pme_long_desc = "An instruction fetch group was fetched from beyond the local L2.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L2MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L2MISS]
},
[ POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC ] = {
.pme_name = "PM_LSU0_DC_PREF_STREAM_ALLOC",
.pme_code = 0xd0a8,
.pme_short_desc = "LS0 D cache new prefetch stream allocated",
.pme_long_desc = "LS0 D cache new prefetch stream allocated",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC]
},
[ POWER7_PME_PM_L2_ST ] = {
.pme_name = "PM_L2_ST",
.pme_code = 0x16082,
.pme_short_desc = "Data Store Count",
.pme_long_desc = "Data Store Count",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_ST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_ST]
},
[ POWER7_PME_PM_VSU0_DENORM ] = {
.pme_name = "PM_VSU0_DENORM",
.pme_code = 0xa0ac,
.pme_short_desc = "FPU denorm operand",
.pme_long_desc = "VSU0 received denormalized data",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_DENORM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_DENORM]
},
[ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR",
.pme_code = 0x3d044,
.pme_short_desc = "Marked data loaded from distant L2 or L3 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR]
},
[ POWER7_PME_PM_BR_PRED_CR_TA ] = {
.pme_name = "PM_BR_PRED_CR_TA",
.pme_code = 0x48aa,
.pme_short_desc = "Branch predict - taken/not taken and target",
.pme_long_desc = "Both the condition (taken or not taken) and the target address of a branch instruction was predicted.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_CR_TA],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_CR_TA]
},
[ POWER7_PME_PM_VSU0_FCONV ] = {
.pme_name = "PM_VSU0_FCONV",
.pme_code = 0xa0b0,
.pme_short_desc = "Convert instruction executed",
.pme_long_desc = "Convert instruction executed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FCONV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FCONV]
},
[ POWER7_PME_PM_MRK_LSU_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU_FLUSH_ULD",
.pme_code = 0xd084,
.pme_short_desc = "Flush: (marked) Unaligned Load",
.pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH_ULD],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH_ULD]
},
[ POWER7_PME_PM_BTAC_MISS ] = {
.pme_name = "PM_BTAC_MISS",
.pme_code = 0x5088,
.pme_short_desc = "BTAC Mispredicted",
.pme_long_desc = "BTAC Mispredicted",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BTAC_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BTAC_MISS]
},
[ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT ] = {
.pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC_COUNT",
.pme_code = 0x1003f,
.pme_short_desc = "Marked Load exposed Miss (use edge detect to count #)",
.pme_long_desc = "Marked Load exposed Miss (use edge detect to count #)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L2 ] = {
.pme_name = "PM_MRK_DATA_FROM_L2",
.pme_code = 0x1d040,
.pme_short_desc = "Marked data loaded from L2",
.pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L2],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L2]
},
[ POWER7_PME_PM_VSU_FMA ] = {
.pme_name = "PM_VSU_FMA",
.pme_code = 0xa884,
.pme_short_desc = "two flops operation (fmadd",
.pme_long_desc = " fnmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FMA],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FMA]
},
[ POWER7_PME_PM_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_LSU0_FLUSH_SRQ",
.pme_code = 0xc0bc,
.pme_short_desc = "LS0 Flush: SRQ",
.pme_long_desc = "Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_FLUSH_SRQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_FLUSH_SRQ]
},
[ POWER7_PME_PM_LSU1_L1_PREF ] = {
.pme_name = "PM_LSU1_L1_PREF",
.pme_code = 0xd0ba,
.pme_short_desc = " LS1 L1 cache data prefetches",
.pme_long_desc = " LS1 L1 cache data prefetches",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_L1_PREF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_L1_PREF]
},
[ POWER7_PME_PM_IOPS_CMPL ] = {
.pme_name = "PM_IOPS_CMPL",
.pme_code = 0x10014,
.pme_short_desc = "Internal Operations completed",
.pme_long_desc = "Number of internal operations that completed.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IOPS_CMPL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IOPS_CMPL]
},
[ POWER7_PME_PM_L2_SYS_PUMP ] = {
.pme_name = "PM_L2_SYS_PUMP",
.pme_code = 0x36482,
.pme_short_desc = "RC req that was a global (aka system) pump attempt",
.pme_long_desc = "RC req that was a global (aka system) pump attempt",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_SYS_PUMP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_SYS_PUMP]
},
[ POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL ] = {
.pme_name = "PM_L2_RCLD_BUSY_RC_FULL",
.pme_code = 0x46282,
.pme_short_desc = " L2 activated Busy to the core for loads due to all RC full",
.pme_long_desc = " L2 activated Busy to the core for loads due to all RC full",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL]
},
[ POWER7_PME_PM_BCPLUS8_RSLV_TAKEN ] = {
.pme_name = "PM_BC+8_RSLV_TAKEN",
.pme_code = 0x40ba,
.pme_short_desc = "BC+8 Resolve outcome was Taken",
.pme_long_desc = " resulting in the conditional instruction being canceled",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BCPLUS8_RSLV_TAKEN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BCPLUS8_RSLV_TAKEN]
},
[ POWER7_PME_PM_NEST_5 ] = {
.pme_name = "PM_NEST_5",
.pme_code = 0x89,
.pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_5],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_5]
},
[ POWER7_PME_PM_LSU_LMQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LMQ_S0_ALLOC",
.pme_code = 0xd0a1,
.pme_short_desc = "Slot 0 of LMQ valid",
.pme_long_desc = "Slot 0 of LMQ valid",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_S0_ALLOC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_S0_ALLOC]
},
[ POWER7_PME_PM_FLUSH_DISP_SYNC ] = {
.pme_name = "PM_FLUSH_DISP_SYNC",
.pme_code = 0x2088,
.pme_short_desc = "Dispatch Flush: Sync",
.pme_long_desc = "Dispatch Flush: Sync",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_DISP_SYNC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_DISP_SYNC]
},
[ POWER7_PME_PM_L2_IC_INV ] = {
.pme_name = "PM_L2_IC_INV",
.pme_code = 0x26180,
.pme_short_desc = "Icache Invalidates from L2 ",
.pme_long_desc = "Icache Invalidates from L2 ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_IC_INV],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_IC_INV]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L21_MOD_CYC",
.pme_code = 0x40024,
.pme_short_desc = "Marked ld latency Data source 0101 (L2.1 M same chip)",
.pme_long_desc = "Marked ld latency Data source 0101 (L2.1 M same chip)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC]
},
[ POWER7_PME_PM_L3_PREF_LDST ] = {
.pme_name = "PM_L3_PREF_LDST",
.pme_code = 0xd8ac,
.pme_short_desc = "L3 cache prefetches LD + ST",
.pme_long_desc = "L3 cache prefetches LD + ST",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_LDST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_LDST]
},
[ POWER7_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_SRQ_EMPTY_CYC",
.pme_code = 0x40008,
.pme_short_desc = "ALL threads srq empty",
.pme_long_desc = "The Store Request Queue is empty",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_EMPTY_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_EMPTY_CYC]
},
[ POWER7_PME_PM_LSU_LMQ_S0_VALID ] = {
.pme_name = "PM_LSU_LMQ_S0_VALID",
.pme_code = 0xd0a0,
.pme_short_desc = "Slot 0 of LMQ valid",
.pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_S0_VALID],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_S0_VALID]
},
[ POWER7_PME_PM_FLUSH_PARTIAL ] = {
.pme_name = "PM_FLUSH_PARTIAL",
.pme_code = 0x2086,
.pme_short_desc = "Partial flush",
.pme_long_desc = "Partial flush",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_PARTIAL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_PARTIAL]
},
[ POWER7_PME_PM_VSU1_FMA_DOUBLE ] = {
.pme_name = "PM_VSU1_FMA_DOUBLE",
.pme_code = 0xa092,
.pme_short_desc = "four flop DP vector operations (xvmadddp",
.pme_long_desc = " xvnmadddp",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FMA_DOUBLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FMA_DOUBLE]
},
[ POWER7_PME_PM_1PLUS_PPC_DISP ] = {
.pme_name = "PM_1PLUS_PPC_DISP",
.pme_code = 0x400f2,
.pme_short_desc = "Cycles at least one Instr Dispatched",
.pme_long_desc = "",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_1PLUS_PPC_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_1PLUS_PPC_DISP]
},
[ POWER7_PME_PM_DATA_FROM_L2MISS ] = {
.pme_name = "PM_DATA_FROM_L2MISS",
.pme_code = 0x200fe,
.pme_short_desc = "Demand LD - L2 Miss (not L2 hit)",
.pme_long_desc = "The processor's Data Cache was reloaded but not from the local L2.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L2MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L2MISS]
},
[ POWER7_PME_PM_SUSPENDED ] = {
.pme_name = "PM_SUSPENDED",
.pme_code = 0x0,
.pme_short_desc = "Counter OFF",
.pme_long_desc = "The counter is suspended (does not count)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_SUSPENDED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_SUSPENDED]
},
[ POWER7_PME_PM_VSU0_FMA ] = {
.pme_name = "PM_VSU0_FMA",
.pme_code = 0xa084,
.pme_short_desc = "two flops operation (fmadd",
.pme_long_desc = " fnmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FMA],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FMA]
},
[ POWER7_PME_PM_CMPLU_STALL_SCALAR ] = {
.pme_name = "PM_CMPLU_STALL_SCALAR",
.pme_code = 0x40012,
.pme_short_desc = "Completion stall caused by FPU instruction",
.pme_long_desc = "Completion stall caused by FPU instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_SCALAR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_SCALAR]
},
[ POWER7_PME_PM_STCX_FAIL ] = {
.pme_name = "PM_STCX_FAIL",
.pme_code = 0xc09a,
.pme_short_desc = "STCX failed",
.pme_long_desc = "A stcx (stwcx or stdcx) failed",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_STCX_FAIL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_STCX_FAIL]
},
[ POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE ] = {
.pme_name = "PM_VSU0_FSQRT_FDIV_DOUBLE",
.pme_code = 0xa094,
.pme_short_desc = "eight flop DP vector operations (xvfdivdp",
.pme_long_desc = " xvsqrtdp ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE]
},
[ POWER7_PME_PM_DC_PREF_DST ] = {
.pme_name = "PM_DC_PREF_DST",
.pme_code = 0xd0b0,
.pme_short_desc = "Data Stream Touch",
.pme_long_desc = "A prefetch stream was started using the DST instruction.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DC_PREF_DST],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DC_PREF_DST]
},
[ POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED ] = {
.pme_name = "PM_VSU1_SCAL_SINGLE_ISSUED",
.pme_code = 0xb086,
.pme_short_desc = "Single Precision scalar instruction issued on Pipe1",
.pme_long_desc = "Single Precision scalar instruction issued on Pipe1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED]
},
[ POWER7_PME_PM_L3_HIT ] = {
.pme_name = "PM_L3_HIT",
.pme_code = 0x1f080,
.pme_short_desc = "L3 Hits",
.pme_long_desc = "L3 Hits",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_HIT],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_HIT]
},
[ POWER7_PME_PM_L2_GLOB_GUESS_WRONG ] = {
.pme_name = "PM_L2_GLOB_GUESS_WRONG",
.pme_code = 0x26482,
.pme_short_desc = "L2 guess glb and guess was not correct (ie data local)",
.pme_long_desc = "L2 guess glb and guess was not correct (ie data local)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_GLOB_GUESS_WRONG],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_GLOB_GUESS_WRONG]
},
[ POWER7_PME_PM_MRK_DFU_FIN ] = {
.pme_name = "PM_MRK_DFU_FIN",
.pme_code = 0x20032,
.pme_short_desc = "Decimal Unit marked Instruction Finish",
.pme_long_desc = "The Decimal Floating Point Unit finished a marked instruction.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DFU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DFU_FIN]
},
[ POWER7_PME_PM_INST_FROM_L1 ] = {
.pme_name = "PM_INST_FROM_L1",
.pme_code = 0x4080,
.pme_short_desc = "Instruction fetches from L1",
.pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L1]
},
[ POWER7_PME_PM_BRU_FIN ] = {
.pme_name = "PM_BRU_FIN",
.pme_code = 0x10068,
.pme_short_desc = "Branch Instruction Finished ",
.pme_long_desc = "The Branch execution unit finished an instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BRU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BRU_FIN]
},
[ POWER7_PME_PM_IC_DEMAND_REQ ] = {
.pme_name = "PM_IC_DEMAND_REQ",
.pme_code = 0x4088,
.pme_short_desc = "Demand Instruction fetch request",
.pme_long_desc = "Demand Instruction fetch request",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_REQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_REQ]
},
[ POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE ] = {
.pme_name = "PM_VSU1_FSQRT_FDIV_DOUBLE",
.pme_code = 0xa096,
.pme_short_desc = "eight flop DP vector operations (xvfdivdp",
.pme_long_desc = " xvsqrtdp ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE]
},
[ POWER7_PME_PM_VSU1_FMA ] = {
.pme_name = "PM_VSU1_FMA",
.pme_code = 0xa086,
.pme_short_desc = "two flops operation (fmadd",
.pme_long_desc = " fnmadd",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FMA],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FMA]
},
[ POWER7_PME_PM_MRK_LD_MISS_L1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1",
.pme_code = 0x20036,
.pme_short_desc = "Marked DL1 Demand Miss",
.pme_long_desc = "Marked L1 D cache load misses",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LD_MISS_L1],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LD_MISS_L1]
},
[ POWER7_PME_PM_VSU0_2FLOP_DOUBLE ] = {
.pme_name = "PM_VSU0_2FLOP_DOUBLE",
.pme_code = 0xa08c,
.pme_short_desc = "two flop DP vector operation (xvadddp",
.pme_long_desc = " xvmuldp",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_2FLOP_DOUBLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_2FLOP_DOUBLE]
},
[ POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM ] = {
.pme_name = "PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM",
.pme_code = 0xd8bc,
.pme_short_desc = "Dcache Strided prefetch stream confirmed (software + hardware)",
.pme_long_desc = "Dcache Strided prefetch stream confirmed (software + hardware)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM]
},
[ POWER7_PME_PM_INST_PTEG_FROM_L31_SHR ] = {
.pme_name = "PM_INST_PTEG_FROM_L31_SHR",
.pme_code = 0x2e056,
.pme_short_desc = "Instruction PTEG loaded from another L3 on same chip shared",
.pme_long_desc = "Instruction PTEG loaded from another L3 on same chip shared",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L31_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L31_SHR]
},
[ POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = {
.pme_name = "PM_MRK_LSU_REJECT_ERAT_MISS",
.pme_code = 0x30064,
.pme_short_desc = "LSU marked reject due to ERAT (up to 2 per cycle)",
.pme_long_desc = "LSU marked reject due to ERAT (up to 2 per cycle)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS]
},
[ POWER7_PME_PM_MRK_DATA_FROM_L2MISS ] = {
.pme_name = "PM_MRK_DATA_FROM_L2MISS",
.pme_code = 0x4d048,
.pme_short_desc = "Marked data loaded missed L2",
.pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L2MISS],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L2MISS]
},
[ POWER7_PME_PM_DATA_FROM_RL2L3_SHR ] = {
.pme_name = "PM_DATA_FROM_RL2L3_SHR",
.pme_code = 0x1c04c,
.pme_short_desc = "Data loaded from remote L2 or L3 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_RL2L3_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_RL2L3_SHR]
},
[ POWER7_PME_PM_INST_FROM_PREF ] = {
.pme_name = "PM_INST_FROM_PREF",
.pme_code = 0x14046,
.pme_short_desc = "Instruction fetched from prefetch",
.pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_PREF],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_PREF]
},
[ POWER7_PME_PM_VSU1_SQ ] = {
.pme_name = "PM_VSU1_SQ",
.pme_code = 0xb09e,
.pme_short_desc = "Store Vector Issued on Pipe1",
.pme_long_desc = "Store Vector Issued on Pipe1",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_SQ],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_SQ]
},
[ POWER7_PME_PM_L2_LD_DISP ] = {
.pme_name = "PM_L2_LD_DISP",
.pme_code = 0x36180,
.pme_short_desc = "All successful load dispatches",
.pme_long_desc = "All successful load dispatches",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LD_DISP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LD_DISP]
},
[ POWER7_PME_PM_L2_DISP_ALL ] = {
.pme_name = "PM_L2_DISP_ALL",
.pme_code = 0x46080,
.pme_short_desc = "All successful LD/ST dispatches for this thread(i+d)",
.pme_long_desc = "All successful LD/ST dispatches for this thread(i+d)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_DISP_ALL],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_DISP_ALL]
},
[ POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = {
.pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC",
.pme_code = 0x10012,
.pme_short_desc = "Cycles group completed by both threads",
.pme_long_desc = "Cycles that both threads completed.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC]
},
[ POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE ] = {
.pme_name = "PM_VSU_FSQRT_FDIV_DOUBLE",
.pme_code = 0xa894,
.pme_short_desc = "DP vector versions of fdiv",
.pme_long_desc = "fsqrt ",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE]
},
[ POWER7_PME_PM_BR_MPRED ] = {
.pme_name = "PM_BR_MPRED",
.pme_code = 0x400f6,
.pme_short_desc = "Number of Branch Mispredicts",
.pme_long_desc = "A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED]
},
[ POWER7_PME_PM_VSU_1FLOP ] = {
.pme_name = "PM_VSU_1FLOP",
.pme_code = 0xa880,
.pme_short_desc = "one flop (fadd",
.pme_long_desc = " fmul",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_1FLOP],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_1FLOP]
},
[ POWER7_PME_PM_HV_CYC ] = {
.pme_name = "PM_HV_CYC",
.pme_code = 0x2000a,
.pme_short_desc = "cycles in hypervisor mode ",
.pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_HV_CYC],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_HV_CYC]
},
[ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR",
.pme_code = 0x1d04c,
.pme_short_desc = "Marked data loaded from remote L2 or L3 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR]
},
[ POWER7_PME_PM_DTLB_MISS_16M ] = {
.pme_name = "PM_DTLB_MISS_16M",
.pme_code = 0x4c05e,
.pme_short_desc = "Data TLB miss for 16M page",
.pme_long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS_16M],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS_16M]
},
[ POWER7_PME_PM_MRK_LSU_FIN ] = {
.pme_name = "PM_MRK_LSU_FIN",
.pme_code = 0x40032,
.pme_short_desc = "Marked LSU instruction finished",
.pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FIN]
},
[ POWER7_PME_PM_LSU1_LMQ_LHR_MERGE ] = {
.pme_name = "PM_LSU1_LMQ_LHR_MERGE",
.pme_code = 0xd09a,
.pme_short_desc = "LS1 Load Merge with another cacheline request",
.pme_long_desc = "LS1 Load Merge with another cacheline request",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_LMQ_LHR_MERGE],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_LMQ_LHR_MERGE]
},
[ POWER7_PME_PM_IFU_FIN ] = {
.pme_name = "PM_IFU_FIN",
.pme_code = 0x40066,
.pme_short_desc = "IFU Finished a (non-branch) instruction",
.pme_long_desc = "The Instruction Fetch Unit finished an instruction",
.pme_event_ids = power7_event_ids[POWER7_PME_PM_IFU_FIN],
.pme_group_vector = power7_group_vecs[POWER7_PME_PM_IFU_FIN]
}
};
#define POWER7_PME_EVENT_COUNT 517
static const int power7_group_event_ids[][POWER7_NUM_EVENT_COUNTERS] = {
[ 0 ] = { 21, 225, 75, 75, 0, 0 },
[ 1 ] = { 10, 11, 3, 8, 0, 0 },
[ 2 ] = { 9, 9, 9, 13, 0, 0 },
[ 3 ] = { 16, 13, 8, 3, 0, 0 },
[ 4 ] = { 5, 14, 7, 4, 0, 0 },
[ 5 ] = { 12, 4, 8, 11, 0, 0 },
[ 6 ] = { 10, 11, 10, 14, 0, 0 },
[ 7 ] = { 5, 9, 9, 13, 0, 0 },
[ 8 ] = { 8, 9, 9, 13, 0, 0 },
[ 9 ] = { 4, 9, 9, 13, 0, 0 },
[ 10 ] = { 77, 40, 89, 221, 0, 0 },
[ 11 ] = { 18, 244, 38, 87, 0, 0 },
[ 12 ] = { 40, 41, 39, 38, 0, 0 },
[ 13 ] = { 30, 31, 27, 29, 0, 0 },
[ 14 ] = { 80, 31, 27, 29, 0, 0 },
[ 15 ] = { 39, 25, 117, 105, 0, 0 },
[ 16 ] = { 21, 223, 117, 214, 0, 0 },
[ 17 ] = { 21, 223, 117, 212, 0, 0 },
[ 18 ] = { 39, 82, 74, 214, 0, 0 },
[ 19 ] = { 77, 40, 89, 75, 0, 0 },
[ 20 ] = { 223, 85, 218, 81, 0, 0 },
[ 21 ] = { 91, 221, 85, 210, 0, 0 },
[ 22 ] = { 224, 223, 86, 213, 0, 0 },
[ 23 ] = { 93, 220, 220, 213, 0, 0 },
[ 24 ] = { 225, 222, 219, 211, 0, 0 },
[ 25 ] = { 92, 84, 84, 84, 0, 0 },
[ 26 ] = { 92, 86, 84, 82, 0, 0 },
[ 27 ] = { 91, 87, 86, 83, 0, 0 },
[ 28 ] = { 223, 221, 220, 212, 0, 0 },
[ 29 ] = { 223, 221, 74, 23, 0, 0 },
[ 30 ] = { 225, 224, 74, 210, 0, 0 },
[ 31 ] = { 80, 220, 220, 213, 0, 0 },
[ 32 ] = { 222, 38, 48, 47, 0, 0 },
[ 33 ] = { 222, 38, 34, 47, 0, 0 },
[ 34 ] = { 117, 112, 113, 137, 0, 0 },
[ 35 ] = { 46, 48, 44, 40, 0, 0 },
[ 36 ] = { 48, 45, 119, 126, 0, 0 },
[ 37 ] = { 44, 23, 42, 40, 0, 0 },
[ 38 ] = { 126, 122, 120, 114, 0, 0 },
[ 39 ] = { 126, 150, 165, 40, 0, 0 },
[ 40 ] = { 127, 151, 166, 40, 0, 0 },
[ 41 ] = { 124, 148, 163, 40, 0, 0 },
[ 42 ] = { 125, 149, 164, 40, 0, 0 },
[ 43 ] = { 63, 69, 69, 68, 0, 0 },
[ 44 ] = { 0, 0, 0, 0, 0, 0 },
[ 45 ] = { 241, 239, 234, 229, 0, 0 },
[ 46 ] = { 0, 0, 0, 0, 0, 0 },
[ 47 ] = { 0, 0, 0, 0, 0, 0 },
[ 48 ] = { 242, 241, 237, 232, 0, 0 },
[ 49 ] = { 0, 0, 0, 0, 0, 0 },
[ 50 ] = { 49, 50, 49, 48, 0, 0 },
[ 51 ] = { 50, 225, 74, 49, 0, 0 },
[ 52 ] = { 21, 50, 49, 48, 0, 0 },
[ 53 ] = { 49, 50, 17, 75, 0, 0 },
[ 54 ] = { 106, 100, 99, 91, 0, 0 },
[ 55 ] = { 101, 23, 98, 75, 0, 0 },
[ 56 ] = { 106, 100, 100, 92, 0, 0 },
[ 57 ] = { 108, 97, 74, 23, 0, 0 },
[ 58 ] = { 80, 23, 96, 96, 0, 0 },
[ 59 ] = { 80, 23, 95, 95, 0, 0 },
[ 60 ] = { 107, 101, 74, 23, 0, 0 },
[ 61 ] = { 210, 211, 207, 203, 0, 0 },
[ 62 ] = { 214, 215, 211, 207, 0, 0 },
[ 63 ] = { 64, 63, 62, 58, 0, 0 },
[ 64 ] = { 23, 77, 90, 0, 0, 0 },
[ 65 ] = { 24, 23, 90, 75, 0, 0 },
[ 66 ] = { 27, 29, 90, 75, 0, 0 },
[ 67 ] = { 139, 157, 172, 127, 0, 0 },
[ 68 ] = { 139, 134, 137, 131, 0, 0 },
[ 69 ] = { 142, 138, 17, 75, 0, 0 },
[ 70 ] = { 141, 158, 173, 75, 0, 0 },
[ 71 ] = { 136, 156, 171, 75, 0, 0 },
[ 72 ] = { 52, 51, 50, 23, 0, 0 },
[ 73 ] = { 53, 56, 54, 54, 0, 0 },
[ 74 ] = { 99, 94, 74, 23, 0, 0 },
[ 75 ] = { 100, 96, 74, 23, 0, 0 },
[ 76 ] = { 37, 38, 34, 0, 0, 0 },
[ 77 ] = { 238, 38, 34, 226, 0, 0 },
[ 78 ] = { 32, 34, 33, 34, 0, 0 },
[ 79 ] = { 222, 219, 217, 209, 0, 0 },
[ 80 ] = { 0, 77, 56, 0, 0, 0 },
[ 81 ] = { 0, 23, 74, 0, 0, 0 },
[ 82 ] = { 75, 73, 63, 60, 0, 0 },
[ 83 ] = { 71, 66, 65, 63, 0, 0 },
[ 84 ] = { 77, 92, 74, 23, 0, 0 },
[ 85 ] = { 23, 17, 90, 20, 0, 0 },
[ 86 ] = { 49, 19, 55, 19, 0, 0 },
[ 87 ] = { 237, 20, 25, 21, 0, 0 },
[ 88 ] = { 42, 21, 201, 22, 0, 0 },
[ 89 ] = { 19, 22, 202, 18, 0, 0 },
[ 90 ] = { 20, 18, 74, 52, 0, 0 },
[ 91 ] = { 52, 53, 87, 51, 0, 0 },
[ 92 ] = { 23, 26, 24, 27, 0, 0 },
[ 93 ] = { 24, 27, 23, 26, 0, 0 },
[ 94 ] = { 22, 28, 20, 26, 0, 0 },
[ 95 ] = { 25, 29, 18, 24, 0, 0 },
[ 96 ] = { 26, 24, 19, 25, 0, 0 },
[ 97 ] = { 27, 29, 21, 26, 0, 0 },
[ 98 ] = { 28, 28, 18, 24, 0, 0 },
[ 99 ] = { 80, 26, 22, 27, 0, 0 },
[ 100 ] = { 23, 25, 90, 105, 0, 0 },
[ 101 ] = { 27, 29, 19, 24, 0, 0 },
[ 102 ] = { 23, 25, 22, 214, 0, 0 },
[ 103 ] = { 27, 24, 24, 27, 0, 0 },
[ 104 ] = { 30, 76, 19, 24, 0, 0 },
[ 105 ] = { 22, 76, 24, 27, 0, 0 },
[ 106 ] = { 22, 76, 90, 27, 0, 0 },
[ 107 ] = { 83, 80, 81, 79, 0, 0 },
[ 108 ] = { 84, 78, 76, 80, 0, 0 },
[ 109 ] = { 81, 82, 77, 76, 0, 0 },
[ 110 ] = { 85, 81, 79, 78, 0, 0 },
[ 111 ] = { 86, 83, 80, 79, 0, 0 },
[ 112 ] = { 87, 82, 81, 79, 0, 0 },
[ 113 ] = { 88, 83, 77, 76, 0, 0 },
[ 114 ] = { 89, 82, 81, 79, 0, 0 },
[ 115 ] = { 87, 78, 82, 80, 0, 0 },
[ 116 ] = { 83, 80, 74, 23, 0, 0 },
[ 117 ] = { 88, 83, 81, 75, 0, 0 },
[ 118 ] = { 21, 76, 77, 76, 0, 0 },
[ 119 ] = { 81, 76, 82, 80, 0, 0 },
[ 120 ] = { 120, 106, 115, 89, 0, 0 },
[ 121 ] = { 122, 111, 118, 105, 0, 0 },
[ 122 ] = { 270, 291, 263, 280, 0, 0 },
[ 123 ] = { 273, 294, 266, 283, 0, 0 },
[ 124 ] = { 249, 248, 264, 281, 0, 0 },
[ 125 ] = { 280, 302, 249, 75, 0, 0 },
[ 126 ] = { 281, 303, 250, 75, 0, 0 },
[ 127 ] = { 267, 289, 307, 75, 0, 0 },
[ 128 ] = { 253, 274, 291, 75, 0, 0 },
[ 129 ] = { 256, 277, 295, 75, 0, 0 },
[ 130 ] = { 266, 288, 306, 75, 0, 0 },
[ 131 ] = { 265, 287, 304, 255, 0, 0 },
[ 132 ] = { 260, 282, 299, 75, 0, 0 },
[ 133 ] = { 261, 283, 300, 75, 0, 0 },
[ 134 ] = { 262, 284, 302, 75, 0, 0 },
[ 135 ] = { 263, 285, 303, 75, 0, 0 },
[ 136 ] = { 248, 249, 244, 75, 0, 0 },
[ 137 ] = { 268, 290, 274, 75, 0, 0 },
[ 138 ] = { 264, 286, 267, 233, 0, 0 },
[ 139 ] = { 298, 298, 301, 299, 0, 0 },
[ 140 ] = { 254, 275, 293, 75, 0, 0 },
[ 141 ] = { 259, 281, 298, 75, 0, 0 },
[ 142 ] = { 255, 276, 294, 75, 0, 0 },
[ 143 ] = { 16, 225, 74, 242, 0, 0 },
[ 144 ] = { 129, 264, 249, 234, 0, 0 },
[ 145 ] = { 260, 254, 249, 234, 0, 0 },
[ 146 ] = { 42, 254, 247, 234, 0, 0 },
[ 147 ] = { 266, 254, 251, 240, 0, 0 },
[ 148 ] = { 131, 128, 129, 131, 0, 0 },
[ 149 ] = { 128, 132, 118, 112, 0, 0 },
[ 150 ] = { 161, 170, 128, 119, 0, 0 },
[ 151 ] = { 147, 159, 174, 75, 0, 0 },
[ 152 ] = { 149, 142, 140, 75, 0, 0 },
[ 153 ] = { 146, 130, 128, 75, 0, 0 },
[ 154 ] = { 132, 129, 139, 75, 0, 0 },
[ 155 ] = { 98, 152, 167, 75, 0, 0 },
[ 156 ] = { 105, 99, 17, 75, 0, 0 },
[ 157 ] = { 102, 95, 17, 75, 0, 0 },
[ 158 ] = { 90, 79, 83, 75, 0, 0 },
[ 159 ] = { 41, 43, 232, 23, 0, 0 },
[ 160 ] = { 0, 58, 75, 0, 0, 0 },
[ 161 ] = { 58, 53, 17, 52, 0, 0 },
[ 162 ] = { 57, 4, 3, 3, 0, 0 },
[ 163 ] = { 97, 70, 71, 75, 0, 0 },
[ 164 ] = { 246, 58, 17, 74, 0, 0 },
[ 165 ] = { 7, 43, 90, 3, 0, 0 },
[ 166 ] = { 43, 49, 138, 3, 0, 0 },
[ 167 ] = { 144, 114, 92, 57, 0, 0 },
[ 168 ] = { 42, 23, 55, 75, 0, 0 },
[ 169 ] = { 80, 233, 232, 40, 0, 0 },
[ 170 ] = { 52, 233, 38, 3, 0, 0 },
[ 171 ] = { 21, 23, 74, 74, 0, 0 },
[ 172 ] = { 236, 23, 175, 75, 0, 0 },
[ 173 ] = { 94, 23, 87, 75, 0, 0 },
[ 174 ] = { 181, 23, 176, 75, 0, 0 },
[ 175 ] = { 21, 226, 88, 36, 0, 0 },
[ 176 ] = { 109, 103, 103, 23, 0, 0 },
[ 177 ] = { 229, 227, 225, 219, 0, 0 },
[ 178 ] = { 111, 107, 105, 101, 0, 0 },
[ 179 ] = { 110, 104, 106, 97, 0, 0 },
[ 180 ] = { 21, 115, 146, 154, 0, 0 },
[ 181 ] = { 21, 116, 147, 155, 0, 0 },
[ 182 ] = { 29, 114, 145, 153, 0, 0 },
[ 183 ] = { 115, 110, 17, 102, 0, 0 },
[ 184 ] = { 21, 123, 153, 161, 0, 0 },
[ 185 ] = { 21, 124, 154, 162, 0, 0 },
[ 186 ] = { 103, 102, 103, 23, 0, 0 },
[ 187 ] = { 114, 135, 229, 224, 0, 0 },
[ 188 ] = { 17, 16, 229, 224, 0, 0 },
[ 189 ] = { 2, 1, 17, 75, 0, 0 },
[ 190 ] = { 90, 77, 83, 75, 0, 0 },
[ 191 ] = { 104, 98, 94, 90, 0, 0 },
[ 192 ] = { 80, 23, 93, 90, 0, 0 },
[ 193 ] = { 80, 23, 102, 214, 0, 0 },
[ 194 ] = { 80, 23, 101, 94, 0, 0 },
[ 195 ] = { 80, 23, 97, 214, 0, 0 },
[ 196 ] = { 80, 225, 17, 93, 0, 0 },
[ 197 ] = { 77, 75, 72, 75, 0, 0 },
[ 198 ] = { 31, 35, 17, 75, 0, 0 },
[ 199 ] = { 21, 38, 35, 75, 0, 0 },
[ 200 ] = { 226, 225, 17, 215, 0, 0 },
[ 201 ] = { 219, 218, 213, 208, 0, 0 },
[ 202 ] = { 221, 218, 216, 208, 0, 0 },
[ 203 ] = { 220, 225, 214, 75, 0, 0 },
[ 204 ] = { 218, 225, 215, 75, 0, 0 },
[ 205 ] = { 47, 37, 227, 75, 0, 0 },
[ 206 ] = { 77, 92, 228, 105, 0, 0 },
[ 207 ] = { 21, 117, 38, 87, 0, 0 },
[ 208 ] = { 1, 225, 17, 215, 0, 0 },
[ 209 ] = { 42, 225, 17, 214, 0, 0 },
[ 210 ] = { 0, 225, 75, 0, 0, 0 },
[ 211 ] = { 80, 233, 228, 105, 0, 0 },
[ 212 ] = { 80, 25, 90, 105, 0, 0 },
[ 213 ] = { 77, 92, 74, 87, 0, 0 },
[ 214 ] = { 236, 236, 231, 225, 0, 0 },
[ 215 ] = { 80, 43, 232, 23, 0, 0 },
[ 216 ] = { 90, 77, 234, 40, 0, 0 },
[ 217 ] = { 52, 77, 17, 3, 0, 0 },
[ 218 ] = { 183, 195, 177, 75, 0, 0 },
[ 219 ] = { 188, 179, 179, 75, 0, 0 },
[ 220 ] = { 185, 181, 74, 174, 0, 0 },
[ 221 ] = { 187, 76, 180, 177, 0, 0 },
[ 222 ] = { 189, 188, 183, 75, 0, 0 },
[ 223 ] = { 185, 182, 181, 75, 0, 0 },
[ 224 ] = { 186, 186, 74, 175, 0, 0 },
[ 225 ] = { 187, 185, 74, 176, 0, 0 },
[ 226 ] = { 189, 189, 74, 178, 0, 0 },
[ 227 ] = { 80, 178, 178, 171, 0, 0 },
[ 228 ] = { 80, 187, 183, 179, 0, 0 },
[ 229 ] = { 197, 180, 74, 172, 0, 0 },
[ 230 ] = { 201, 200, 74, 23, 0, 0 },
[ 231 ] = { 80, 23, 190, 189, 0, 0 },
[ 232 ] = { 204, 196, 74, 193, 0, 0 },
[ 233 ] = { 195, 194, 187, 75, 0, 0 },
[ 234 ] = { 208, 208, 200, 75, 0, 0 },
[ 235 ] = { 80, 192, 185, 181, 0, 0 },
[ 236 ] = { 192, 192, 185, 75, 0, 0 },
[ 237 ] = { 80, 190, 184, 180, 0, 0 },
[ 238 ] = { 191, 190, 184, 75, 0, 0 },
[ 239 ] = { 196, 76, 188, 185, 0, 0 },
[ 240 ] = { 80, 203, 197, 196, 0, 0 },
[ 241 ] = { 205, 207, 199, 75, 0, 0 },
[ 242 ] = { 80, 205, 197, 195, 0, 0 },
[ 243 ] = { 206, 204, 74, 197, 0, 0 },
[ 244 ] = { 207, 206, 74, 198, 0, 0 },
[ 245 ] = { 209, 76, 186, 184, 0, 0 },
[ 246 ] = { 80, 193, 186, 186, 0, 0 },
[ 247 ] = { 80, 177, 194, 186, 0, 0 },
[ 248 ] = { 193, 76, 204, 183, 0, 0 },
[ 249 ] = { 194, 191, 202, 75, 0, 0 },
[ 250 ] = { 60, 225, 74, 182, 0, 0 },
[ 251 ] = { 204, 76, 195, 193, 0, 0 },
[ 252 ] = { 21, 23, 74, 186, 0, 0 },
[ 253 ] = { 248, 249, 244, 235, 0, 0 },
[ 254 ] = { 80, 233, 228, 106, 0, 0 },
[ 255 ] = { 80, 233, 111, 105, 0, 0 }
};
static pmg_power_group_t power7_groups[] = {
[ 0 ] = {
.pmg_name = "pm_utilization",
.pmg_desc = "CPI and utilization data",
.pmg_event_ids = power7_group_event_ids[0],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000001ef4f202ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 1 ] = {
.pmg_name = "pm_branch1",
.pmg_desc = "Branch operations",
.pmg_event_ids = power7_group_event_ids[1],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x44440000a0a2a4aeULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 2 ] = {
.pmg_name = "pm_branch2",
.pmg_desc = "Branch operations",
.pmg_event_ids = power7_group_event_ids[2],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x444400009ca8a0a2ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 3 ] = {
.pmg_name = "pm_branch3",
.pmg_desc = "Branch operations",
.pmg_event_ids = power7_group_event_ids[3],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0040000068049cf6ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 4 ] = {
.pmg_name = "pm_branch4",
.pmg_desc = "Branch operations",
.pmg_event_ids = power7_group_event_ids[4],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x44440000ac9eaea4ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 5 ] = {
.pmg_name = "pm_branch5",
.pmg_desc = "Branch operations",
.pmg_event_ids = power7_group_event_ids[5],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4444000caaae9ca8ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 6 ] = {
.pmg_name = "pm_branch6",
.pmg_desc = "Branch operations",
.pmg_event_ids = power7_group_event_ids[6],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x44440000a0a2a8aaULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 7 ] = {
.pmg_name = "pm_branch7",
.pmg_desc = "Branch operations",
.pmg_event_ids = power7_group_event_ids[7],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x44440000aca8a0a2ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 8 ] = {
.pmg_name = "pm_branch8",
.pmg_desc = "Branch operations",
.pmg_event_ids = power7_group_event_ids[8],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x44440000aea8a0a2ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 9 ] = {
.pmg_name = "pm_branch9",
.pmg_desc = "Branch operations",
.pmg_event_ids = power7_group_event_ids[9],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x44440000a4a8a0a2ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 10 ] = {
.pmg_name = "pm_slb_miss",
.pmg_desc = "SLB Misses",
.pmg_event_ids = power7_group_event_ids[10],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0ddd0001f6909290ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 11 ] = {
.pmg_name = "pm_tlb_miss",
.pmg_desc = "TLB Misses",
.pmg_event_ids = power7_group_event_ids[11],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x500000008866fcfcULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 12 ] = {
.pmg_name = "pm_dtlb_miss",
.pmg_desc = "DTLB Misses",
.pmg_event_ids = power7_group_event_ids[12],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xcccc00005e5e5e5eULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 13 ] = {
.pmg_name = "pm_derat_miss1",
.pmg_desc = "DERAT misses",
.pmg_event_ids = power7_group_event_ids[13],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xcccc00005c5c5c5cULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 14 ] = {
.pmg_name = "pm_derat_miss2",
.pmg_desc = "DERAT misses",
.pmg_event_ids = power7_group_event_ids[14],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0ccc0000025c5c5cULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 15 ] = {
.pmg_name = "pm_misc_miss1",
.pmg_desc = "Misses",
.pmg_event_ids = power7_group_event_ids[15],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xd0c0000090fe5af0ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 16 ] = {
.pmg_name = "pm_misc_miss2",
.pmg_desc = "Misses",
.pmg_event_ids = power7_group_event_ids[16],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0cc000001e585afaULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 17 ] = {
.pmg_name = "pm_misc_miss3",
.pmg_desc = "Misses",
.pmg_event_ids = power7_group_event_ids[17],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0ccc00001e585a58ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 18 ] = {
.pmg_name = "pm_misc_miss4",
.pmg_desc = "Misses",
.pmg_event_ids = power7_group_event_ids[18],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xd4000000904802faULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 19 ] = {
.pmg_name = "pm_misc_miss5",
.pmg_desc = "Misses",
.pmg_event_ids = power7_group_event_ids[19],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0dd00000f6909202ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 20 ] = {
.pmg_name = "pm_pteg1",
.pmg_desc = "PTEG sources",
.pmg_event_ids = power7_group_event_ids[20],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xcece000050505654ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 21 ] = {
.pmg_name = "pm_pteg2",
.pmg_desc = "PTEG sources",
.pmg_event_ids = power7_group_event_ids[21],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xecec000050505454ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 22 ] = {
.pmg_name = "pm_pteg3",
.pmg_desc = "PTEG sources",
.pmg_event_ids = power7_group_event_ids[22],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xccec000054585252ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 23 ] = {
.pmg_name = "pm_pteg4",
.pmg_desc = "PTEG sources",
.pmg_event_ids = power7_group_event_ids[23],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xeccc000052525252ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 24 ] = {
.pmg_name = "pm_pteg5",
.pmg_desc = "PTEG sources",
.pmg_event_ids = power7_group_event_ids[24],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xcccc000052565456ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 25 ] = {
.pmg_name = "pm_pteg6",
.pmg_desc = "PTEG sources",
.pmg_event_ids = power7_group_event_ids[25],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xeeee000054525652ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 26 ] = {
.pmg_name = "pm_pteg7",
.pmg_desc = "PTEG sources",
.pmg_event_ids = power7_group_event_ids[26],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xeeee000054565656ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 27 ] = {
.pmg_name = "pm_pteg8",
.pmg_desc = "PTEG sources",
.pmg_event_ids = power7_group_event_ids[27],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xeeee000050585258ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 28 ] = {
.pmg_name = "pm_pteg9",
.pmg_desc = "PTEG sources",
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.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000030f40230ULL,
.pmg_mmcra = 0x0000000000000001ULL
},
[ 251 ] = {
.pmg_name = "pm_mrk_misc7",
.pmg_desc = "Marked misc events",
.pmg_event_ids = power7_group_event_ids[251],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xd000000082026464ULL,
.pmg_mmcra = 0x0000000000000001ULL
},
[ 252 ] = {
.pmg_name = "pm_mrk_misc8",
.pmg_desc = "Marked misc events",
.pmg_event_ids = power7_group_event_ids[252],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000001e1e0232ULL,
.pmg_mmcra = 0x0000000000000001ULL
},
[ 253 ] = {
.pmg_name = "pm_vsu15",
.pmg_desc = "FP ops",
.pmg_event_ids = power7_group_event_ids[253],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xaaaa000f809ca098ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 254 ] = {
.pmg_name = "pm_l1_dcache_accesses",
.pmg_desc = "L1 D-Cache accesses",
.pmg_event_ids = power7_group_event_ids[254],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000c000102f0f080ULL,
.pmg_mmcra = 0x0000000000000000ULL
},
[ 255 ] = {
.pmg_name = "pm_loads_and_stores",
.pmg_desc = "Load and Store instructions",
.pmg_event_ids = power7_group_event_ids[255],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00c0000202f080f0ULL,
.pmg_mmcra = 0x0000000000000000ULL
}
};
#endif