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; Copyright (c) 2014-2017, Intel Corporation
;
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;
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; Test MTC and CYC-based TSC estimation.
;
; Variant: CBR-based calibration
;          High CYC threshold resulting in no CYC between MTCs
;
; opt:ptdump --time --time-delta
; opt:ptdump --mtc-freq 4 --nom-freq 1 --cpuid-0x15.eax 1 --cpuid-0x15.ebx 4

org 0x100000
bits 64

; @pt p1:  psb()
; @pt p2:  tsc(0xa0000)
; @pt p3:  tma(0x18, 0x8)
; @pt p4:  cbr(2)
; @pt p5:  psbend()

; @pt p6:  mtc(0x2)
; @pt p7:  cyc(0x80)
; @pt p8:  mtc(0x3)
; @pt p9:  mtc(0x4)
; @pt p10: cyc(0xe0)
; @pt p11: mtc(0x5)


; @pt .exp(ptdump)
;%0p1    psb
;%0p2    tsc a0000       tsc +a0000
;%0p3    tma 18, 8       tsc +0
;%0p4    cbr 2
;%0p5    psbend
;%0p6    mtc 2           tsc +18
;%0p7    cyc 80          tsc +40
;%0p8    mtc 3           tsc +0
;%0p9    mtc 4           tsc +40
;%0p10   cyc e0          tsc +30
;%0p11   mtc 5           tsc +10