{ **************************** { THIS IS OPEN SOURCE CODE { **************************** { (C) COPYRIGHT International Business Machines Corp. 2005 { This file is licensed under the University of Tennessee license. { See LICENSE.txt. { { File: events/power5/events { Author: Maynard Johnson { maynardj@us.ibm.com { Mods: { { counter 1 } #0,v,g,n,n,PM_0INST_CLB_CYC,Cycles no instructions in CLB ##400C0 Cycles no instructions in CLB #1,v,g,n,n,PM_1INST_CLB_CYC,Cycles 1 instruction in CLB ##400C1 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #2,v,g,n,n,PM_1PLUS_PPC_CMPL,One or more PPC instruction completed ##00013 A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. #3,v,g,n,n,PM_2INST_CLB_CYC,Cycles 2 instructions in CLB ##400C2 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #4,v,g,n,n,PM_3INST_CLB_CYC,Cycles 3 instructions in CLB ##400C3 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #5,v,g,n,n,PM_4INST_CLB_CYC,Cycles 4 instructions in CLB ##400C4 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #6,v,g,n,n,PM_5INST_CLB_CYC,Cycles 5 instructions in CLB ##400C5 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #7,v,g,n,n,PM_6INST_CLB_CYC,Cycles 6 instructions in CLB ##400C6 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #8,u,g,n,s,PM_BRQ_FULL_CYC,Cycles branch queue full ##100C5 The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups). #9,v,g,n,n,PM_BR_UNCOND,Unconditional branch ##23087 Unconditional branch #10,v,g,n,n,PM_CLB_FULL_CYC,Cycles CLB full ##220E5 Cycles CLB full #11,v,g,n,s,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full ##100C4 The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. #12,v,g,n,s,PM_CYC,Processor cycles ##0000F Processor cycles #13,v,g,n,n,PM_DATA_FROM_L2,Data loaded from L2 ##C3087 DL1 was reloaded from the local L2 due to a demand load #14,v,g,n,n,PM_DATA_FROM_L25_SHR,Data loaded from L2.5 shared ##C3097 DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load #15,v,g,n,n,PM_DATA_FROM_L275_MOD,Data loaded from L2.75 modified ##C30A3 DL1 was reloaded with modified (M) data from the L2 of another MCM due to a demand load. #16,v,g,n,n,PM_DATA_FROM_L3,Data loaded from L3 ##C308E DL1 was reloaded from the local L3 due to a demand load #17,v,g,n,n,PM_DATA_FROM_L35_SHR,Data loaded from L3.5 shared ##C309E Data loaded from L3.5 shared #18,v,g,n,n,PM_DATA_FROM_L375_MOD,Data loaded from L3.75 modified ##C30A7 Data loaded from L3.75 modified #19,v,g,n,n,PM_DATA_FROM_RMEM,Data loaded from remote memory ##C30A1 Data loaded from remote memory #20,v,g,n,n,PM_DATA_TABLEWALK_CYC,Cycles doing data tablewalks ##800C7 This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried. #21,v,g,n,n,PM_DSLB_MISS,Data SLB misses ##800C5 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve #22,v,g,n,n,PM_DTLB_MISS,Data TLB misses ##800C4 A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction. #23,v,g,n,n,PM_DTLB_MISS_16M,Data TLB miss for 16M page ##C40C4 Data TLB miss for 16M page #24,v,g,n,n,PM_DTLB_MISS_4K,Data TLB miss for 4K page ##C40C0 Data TLB miss for 4K page #25,v,g,n,n,PM_DTLB_REF_16M,Data TLB reference for 16M page ##C40C6 Data TLB reference for 16M page #26,v,g,n,n,PM_DTLB_REF_4K,Data TLB reference for 4K page ##C40C2 Data TLB reference for 4K page #27,v,g,n,s,PM_FAB_CMD_ISSUED,Fabric command issued ##700C7 Fabric command issued #28,v,g,n,s,PM_FAB_DCLAIM_ISSUED,dclaim issued ##720E7 dclaim issued #29,v,g,n,s,PM_FAB_HOLDtoNN_EMPTY,Hold buffer to NN empty ##722E7 Hold buffer to NN empty #30,v,g,n,s,PM_FAB_HOLDtoVN_EMPTY,Hold buffer to VN empty ##721E7 Hold buffer to VN empty #31,v,g,n,s,PM_FAB_M1toP1_SIDECAR_EMPTY,M1 to P1 sidecar empty ##702C7 M1 to P1 sidecar empty #32,v,g,n,s,PM_FAB_P1toM1_SIDECAR_EMPTY,P1 to M1 sidecar empty ##701C7 P1 to M1 sidecar empty #33,v,g,n,s,PM_FAB_PNtoNN_DIRECT,PN to NN beat went straight to its destination ##703C7 PN to NN beat went straight to its destination #34,v,g,n,s,PM_FAB_PNtoVN_DIRECT,PN to VN beat went straight to its destination ##723E7 PN to VN beat went straight to its destination #35,v,g,n,s,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full ##100C1 The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. #36,v,g,n,n,PM_FPU0_1FLOP,FPU0 executed add, mult, sub, cmp or sel instruction ##000C3 This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo #37,v,g,n,n,PM_FPU0_DENORM,FPU0 received denormalized data ##020E0 This signal is active for one cycle when one of the operands is denormalized. #38,v,g,n,n,PM_FPU0_FDIV,FPU0 executed FDIV instruction ##000C0 This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. #39,v,g,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction ##000C1 This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. #40,v,g,n,n,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction ##000C2 This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. #41,v,g,n,s,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full ##100C3 The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped #42,v,g,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction ##020E3 This signal is active for one cycle when fp0 is executing single precision instruction. #43,v,g,n,n,PM_FPU0_STALL3,FPU0 stalled in pipe3 ##020E1 This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. #44,v,g,n,n,PM_FPU0_STF,FPU0 executed store instruction ##020E2 This signal is active for one cycle when fp0 is executing a store instruction. #45,v,g,n,n,PM_FPU1_1FLOP,FPU1 executed add, mult, sub, cmp or sel instruction ##000C7 This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo #46,v,g,n,n,PM_FPU1_DENORM,FPU1 received denormalized data ##020E4 This signal is active for one cycle when one of the operands is denormalized. #47,v,g,n,n,PM_FPU1_FDIV,FPU1 executed FDIV instruction ##000C4 This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. #48,v,g,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction ##000C5 This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. #49,v,g,n,n,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction ##000C6 This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. #50,v,g,n,s,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full ##100C7 The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped #51,v,g,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction ##020E7 This signal is active for one cycle when fp1 is executing single precision instruction. #52,v,g,n,n,PM_FPU1_STALL3,FPU1 stalled in pipe3 ##020E5 This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. #53,v,g,n,n,PM_FPU1_STF,FPU1 executed store instruction ##020E6 This signal is active for one cycle when fp1 is executing a store instruction. #54,v,g,n,n,PM_FPU_DENORM,FPU received denormalized data ##02088 This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1 #55,v,g,n,n,PM_FPU_FDIV,FPU executed FDIV instruction ##00088 This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1 #56,v,g,n,n,PM_FPU_1FLOP,FPU executed one flop instruction ##00090 This event counts the number of one flop instructions. These could be fadd*, fmul*, fsub*, fneg+, fabs+, fnabs+, fres+, frsqrte+, fcmp**, or fsel where XYZ* means XYZ, XYZs, XYZ., XYZs., XYZ+ means XYZ, XYZ., and XYZ** means XYZu, XYZo. #57,c,g,n,n,PM_FPU_FULL_CYC,Cycles FPU issue queue full ##10090 Cycles when one or both FPU issue queues are full #58,v,g,n,n,PM_FPU_SINGLE,FPU executed single precision instruction ##02090 FPU is executing single precision instruction. Combined Unit 0 + Unit 1 #59,u,g,n,n,PM_FXU_IDLE,FXU idle ##00012 FXU0 and FXU1 are both idle #60,v,g,n,n,PM_GCT_NOSLOT_CYC,Cycles no GCT slot allocated ##00004 Cycles this thread does not have any slots allocated in the GCT. #61,v,g,n,n,PM_GCT_FULL_CYC,Cycles GCT full ##100C0 The ISU sends a signal indicating the gct is full. #62,v,g,n,s,PM_GCT_USAGE_00to59_CYC,Cycles GCT less than 60% full ##0001F Cycles GCT less than 60% full #63,v,g,n,n,PM_GRP_BR_REDIR,Group experienced branch redirect ##120E6 Group experienced branch redirect #64,v,g,n,n,PM_GRP_BR_REDIR_NONSPEC,Group experienced non-speculative branch redirect ##120E5 Group experienced non-speculative branch redirect #65,v,g,n,n,PM_GRP_DISP_REJECT,Group dispatch rejected ##120E4 A group that previously attempted dispatch was rejected. #66,v,g,n,n,PM_GRP_DISP_VALID,Group dispatch valid ##120E3 Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject. #67,v,g,n,n,PM_GRP_IC_MISS,Group experienced I cache miss ##120E7 Group experienced I cache miss #68,v,g,n,n,PM_GRP_IC_MISS_BR_REDIR_NONSPEC,Group experienced non-speculative I cache miss or branch redirect ##12091 Group experienced non-speculative I cache miss or branch redirect #69,v,g,n,n,PM_GRP_IC_MISS_NONSPEC,Group experienced non-speculative I cache miss ##12099 Group experienced non-speculative I cache miss #70,v,g,n,n,PM_GRP_MRK,Group marked in IDU ##00014 A group was sampled (marked) #71,v,g,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##220E6 Asserted when a non-canceled prefetch is made to the cache interface unit (CIU). #72,v,g,n,n,PM_IERAT_XLATE_WR,Translation written to ierat ##220E7 This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available). #73,v,g,n,n,PM_INST_CMPL,Instructions completed ##00001 Number of Eligible Instructions that completed. #74,v,g,n,n,PM_INST_DISP,Instructions dispatched ##120E1 The ISU sends the number of instructions dispatched. #75,v,g,n,n,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched ##220E4 Asserted each cycle when the IFU sends at least one instruction to the IDU. #76,v,g,n,n,PM_INST_FROM_L2,Instructions fetched from L2 ##22086 An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions #77,v,g,n,n,PM_INST_FROM_L25_SHR,Instruction fetched from L2.5 shared ##22096 Instruction fetched from L2.5 shared #78,v,g,n,n,PM_INST_FROM_L3,Instruction fetched from L3 ##2208D An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions #79,v,g,n,n,PM_INST_FROM_L35_SHR,Instruction fetched from L3.5 shared ##2209D Instruction fetched from L3.5 shared #80,u,g,n,n,PM_ISLB_MISS,Instruction SLB misses ##800C1 A SLB miss for an instruction fetch as occurred #81,v,g,n,n,PM_ITLB_MISS,Instruction TLB misses ##800C0 A TLB miss for an Instruction Fetch has occurred #82,v,g,n,s,PM_L2SA_MOD_TAG,L2 slice A transition from modified to tagged ##720E0 A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #83,v,g,n,s,PM_L2SA_RCLD_DISP,L2 Slice A RC load dispatch attempt ##701C0 L2 Slice A RC load dispatch attempt #84,v,g,n,s,PM_L2SA_RCLD_DISP_FAIL_RC_FULL,L2 Slice A RC load dispatch attempt failed due to all RC full ##721E0 L2 Slice A RC load dispatch attempt failed due to all RC full #85,v,g,n,s,PM_L2SA_RCST_DISP,L2 Slice A RC store dispatch attempt ##702C0 L2 Slice A RC store dispatch attempt #86,v,g,n,s,PM_L2SA_RCST_DISP_FAIL_RC_FULL,L2 Slice A RC store dispatch attempt failed due to all RC full ##722E0 L2 Slice A RC store dispatch attempt failed due to all RC full #87,v,g,n,s,PM_L2SA_RC_DISP_FAIL_CO_BUSY,L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy ##703C0 L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy #88,v,g,n,s,PM_L2SA_SHR_MOD,L2 slice A transition from shared to modified ##700C0 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. #89,v,g,n,n,PM_L2SA_ST_REQ,L2 slice A store requests ##723E0 A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C. #90,v,g,n,s,PM_L2SB_MOD_TAG,L2 slice B transition from modified to tagged ##720E1 A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #91,v,g,n,s,PM_L2SB_RCLD_DISP,L2 Slice B RC load dispatch attempt ##701C1 L2 Slice B RC load dispatch attempt #92,v,g,n,s,PM_L2SB_RCLD_DISP_FAIL_RC_FULL,L2 Slice B RC load dispatch attempt failed due to all RC full ##721E1 L2 Slice B RC load dispatch attempt failed due to all RC full #93,v,g,n,s,PM_L2SB_RCST_DISP,L2 Slice B RC store dispatch attempt ##702C1 L2 Slice B RC store dispatch attempt #94,v,g,n,s,PM_L2SB_RCST_DISP_FAIL_RC_FULL,L2 Slice B RC store dispatch attempt failed due to all RC full ##722E1 L2 Slice B RC store dispatch attempt failed due to all RC full #95,v,g,n,s,PM_L2SB_RC_DISP_FAIL_CO_BUSY,L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy ##703C1 L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy #96,v,g,n,s,PM_L2SB_SHR_MOD,L2 slice B transition from shared to modified ##700C1 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. #97,v,g,n,n,PM_L2SB_ST_REQ,L2 slice B store requests ##723E1 A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C. #98,v,g,n,s,PM_L2SC_MOD_TAG,L2 slice C transition from modified to tagged ##720E2 A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #99,v,g,n,s,PM_L2SC_RCLD_DISP,L2 Slice C RC load dispatch attempt ##701C2 L2 Slice C RC load dispatch attempt #100,v,g,n,s,PM_L2SC_RCLD_DISP_FAIL_RC_FULL,L2 Slice C RC load dispatch attempt failed due to all RC full ##721E2 L2 Slice C RC load dispatch attempt failed due to all RC full #101,v,g,n,s,PM_L2SC_RCST_DISP,L2 Slice C RC store dispatch attempt ##702C2 L2 Slice C RC store dispatch attempt #102,v,g,n,s,PM_L2SC_RCST_DISP_FAIL_RC_FULL,L2 Slice C RC store dispatch attempt failed due to all RC full ##722E2 L2 Slice C RC store dispatch attempt failed due to all RC full #103,v,g,n,s,PM_L2SC_RC_DISP_FAIL_CO_BUSY,L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy ##703C2 L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy #104,v,g,n,s,PM_L2SC_SHR_MOD,L2 slice C transition from shared to modified ##700C2 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. #105,v,g,n,n,PM_L2SC_ST_REQ,L2 slice C store requests ##723E2 A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C. #106,v,g,n,s,PM_L3SA_ALL_BUSY,L3 slice A active for every cycle all CI/CO machines busy ##721E3 L3 slice A active for every cycle all CI/CO machines busy #107,v,g,n,s,PM_L3SA_MOD_TAG,L3 slice A transition from modified to TAG ##720E3 L3 slice A transition from modified to TAG #108,v,g,n,s,PM_L3SA_REF,L3 slice A references ##701C3 L3 slice A references #109,v,g,n,s,PM_L3SB_ALL_BUSY,L3 slice B active for every cycle all CI/CO machines busy ##721E4 L3 slice B active for every cycle all CI/CO machines busy #110,v,g,n,s,PM_L3SB_MOD_TAG,L3 slice B transition from modified to TAG ##720E4 L3 slice B transition from modified to TAG #111,v,g,n,s,PM_L3SB_REF,L3 slice B references ##701C4 L3 slice B references #112,v,g,n,s,PM_L3SC_ALL_BUSY,L3 slice C active for every cycle all CI/CO machines busy ##721E5 L3 slice C active for every cycle all CI/CO machines busy #113,v,g,n,s,PM_L3SC_MOD_TAG,L3 slice C transition from modified to TAG ##720E5 L3 slice C transition from modified to TAG #114,v,g,n,s,PM_L3SC_REF,L3 slice C references ##701C5 L3 slice C references #115,v,g,n,n,PM_LARX_LSU0,Larx executed on LSU0 ##820E7 A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0) #116,u,g,n,s,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full ##100C6 The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. #117,v,g,n,n,PM_LSU0_BUSY_REJECT,LSU0 busy due to reject ##C20E3 LSU unit 0 busy due to reject #118,v,g,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses ##800C2 A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur. #119,v,g,n,n,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes ##C00C2 A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #120,u,g,n,n,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes ##C00C3 A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #121,v,g,n,n,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes ##C00C0 A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #122,v,g,n,n,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes ##C00C1 A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary) #123,v,g,n,n,PM_LSU0_REJECT_ERAT_MISS,LSU0 reject due to ERAT miss ##C60E3 LSU0 reject due to ERAT miss #124,v,g,n,n,PM_LSU0_REJECT_LMQ_FULL,LSU0 reject due to LMQ full or missed data coming ##C60E1 LSU0 reject due to LMQ full or missed data coming #125,v,g,n,n,PM_LSU0_REJECT_RELOAD_CDF,LSU0 reject due to reload CDF or tag update collision ##C60E2 LSU0 reject due to reload CDF or tag update collision #126,v,g,n,n,PM_LSU0_REJECT_SRQ_LHS,LSU0 SRQ rejects ##C60E0 LSU0 reject due to load hit store #127,u,g,n,n,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded ##C20E0 Data from a store instruction was forwarded to a load on unit 0 #128,v,g,n,n,PM_LSU1_BUSY_REJECT,LSU1 busy due to reject ##C20E7 LSU unit 1 is busy due to reject #129,v,g,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses ##800C6 A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur. #130,v,g,n,n,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes ##C00C6 A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #131,u,g,n,n,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes ##C00C7 A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #132,v,g,n,n,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes ##C00C4 A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #133,u,g,n,n,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes ##C00C5 A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary) #134,v,g,n,n,PM_LSU1_REJECT_ERAT_MISS,LSU1 reject due to ERAT miss ##C60E7 LSU1 reject due to ERAT miss #135,v,g,n,n,PM_LSU1_REJECT_LMQ_FULL,LSU1 reject due to LMQ full or missed data coming ##C60E5 LSU1 reject due to LMQ full or missed data coming #136,v,g,n,n,PM_LSU1_REJECT_RELOAD_CDF,LSU1 reject due to reload CDF or tag update collision ##C60E6 LSU1 reject due to reload CDF or tag update collision #137,v,g,n,n,PM_LSU1_REJECT_SRQ_LHS,LSU1 SRQ rejects ##C60E4 LSU1 reject due to load hit store #138,u,g,n,n,PM_LSU1_SRQ_STFWD,LSU1 SRQ store forwarded ##C20E4 Data from a store instruction was forwarded to a load on unit 1 #139,v,g,n,n,PM_LSU_BUSY_REJECT,LSU busy due to reject ##C2090 LSU (unit 0 + unit 1) is busy due to reject #140,v,g,n,s,PM_LSU_FLUSH_LRQ_FULL,Flush caused by LRQ full ##320E7 Flush caused by LRQ full #141,u,g,n,n,PM_LSU_FLUSH_SRQ,SRQ flushes ##C0090 A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #142,v,g,n,n,PM_LSU_FLUSH_ULD,LRQ unaligned load flushes ##C0088 A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #143,v,g,n,n,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated ##C20E6 LRQ slot zero was allocated #144,v,g,n,n,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid ##C20E2 This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. #145,v,g,n,n,PM_LSU_REJECT_ERAT_MISS,LSU reject due to ERAT miss ##C6090 LSU reject due to ERAT miss #146,v,g,n,n,PM_LSU_REJECT_SRQ_LHS,LSU SRQ rejects ##C6088 LSU reject due to load hit store #147,v,g,n,n,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated ##C20E5 SRQ Slot zero was allocated #148,v,g,n,n,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid ##C20E1 This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. #149,c,g,n,n,PM_LSU_SRQ_STFWD,SRQ store forwarded ##C2088 Data from a store instruction was forwarded to a load #150,v,g,n,s,PM_MEM_FAST_PATH_RD_CMPL,Fast path memory read completed ##722E6 Fast path memory read completed #151,v,g,n,s,PM_MEM_HI_PRIO_PW_CMPL,High priority partial-write completed ##727E6 High priority partial-write completed #152,v,g,n,s,PM_MEM_HI_PRIO_WR_CMPL,High priority write completed ##726E6 High priority write completed #153,v,g,n,s,PM_MEM_PWQ_DISP,Memory partial-write queue dispatched ##704C6 Memory partial-write queue dispatched #154,v,g,n,s,PM_MEM_PWQ_DISP_BUSY2or3,Memory partial-write queue dispatched with 2-3 queues busy ##724E6 Memory partial-write queue dispatched with 2-3 queues busy #155,v,g,n,s,PM_MEM_READ_CMPL,Memory read completed or canceled ##702C6 Memory read completed or canceled #156,v,g,n,s,PM_MEM_RQ_DISP,Memory read queue dispatched ##701C6 Memory read queue dispatched #157,v,g,n,s,PM_MEM_RQ_DISP_BUSY8to15,Memory read queue dispatched with 8-15 queues busy ##721E6 Memory read queue dispatched with 8-15 queues busy #158,v,g,n,s,PM_MEM_WQ_DISP_BUSY1to7,Memory write queue dispatched with 1-7 queues busy ##723E6 Memory write queue dispatched with 1-7 queues busy #159,v,g,n,s,PM_MEM_WQ_DISP_WRITE,Memory write queue dispatched due to write ##703C6 Memory write queue dispatched due to write #160,v,g,n,n,PM_MRK_DATA_FROM_L2,Marked data loaded from L2 ##C7087 DL1 was reloaded from the local L2 due to a marked demand load #161,v,g,n,n,PM_MRK_DATA_FROM_L25_SHR,Marked data loaded from L2.5 shared ##C7097 DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load #162,v,g,n,n,PM_MRK_DATA_FROM_L275_MOD,Marked data loaded from L2.75 modified ##C70A3 DL1 was reloaded with modified (M) data from the L2 of another MCM due to a marked demand load. #163,v,g,n,n,PM_MRK_DATA_FROM_L3,Marked data loaded from L3 ##C708E DL1 was reloaded from the local L3 due to a marked demand load #164,v,g,n,n,PM_MRK_DATA_FROM_L35_SHR,Marked data loaded from L3.5 shared ##C709E Marked data loaded from L3.5 shared #165,v,g,n,n,PM_MRK_DATA_FROM_L375_MOD,Marked data loaded from L3.75 modified ##C70A7 Marked data loaded from L3.75 modified #166,v,g,n,n,PM_MRK_DATA_FROM_RMEM,Marked data loaded from remote memory ##C70A1 Marked data loaded from remote memory #167,v,g,n,n,PM_MRK_DTLB_MISS_16M,Marked Data TLB misses for 16M page ##C40C5 Marked Data TLB misses for 16M page #168,v,g,n,n,PM_MRK_DTLB_MISS_4K,Marked Data TLB misses for 4K page ##C40C1 Marked Data TLB misses for 4K page #169,v,g,n,n,PM_MRK_DTLB_REF_16M,Marked Data TLB reference for 16M page ##C40C7 Marked Data TLB reference for 16M page #170,v,g,n,n,PM_MRK_DTLB_REF_4K,Marked Data TLB reference for 4K page ##C40C3 Marked Data TLB reference for 4K page #171,v,g,n,n,PM_MRK_GRP_DISP,Marked group dispatched ##00002 A group containing a sampled instruction was dispatched #172,v,g,n,n,PM_MRK_GRP_ISSUED,Marked group issued ##00015 A sampled instruction was issued #173,v,g,n,n,PM_MRK_IMR_RELOAD,Marked IMR reloaded ##820E2 A DL1 reload occured due to marked load #174,v,g,n,n,PM_INST_CMPL,Instructions completed ##00009 Number of PPC instructions completed. #175,v,g,n,n,PM_MRK_LD_MISS_L1,Marked L1 D cache load misses ##82088 Marked L1 D cache load misses #176,v,g,n,n,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses ##820E0 A marked load, executing on unit 0, missed the dcache #177,v,g,n,n,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses ##820E4 A marked load, executing on unit 1, missed the dcache #178,v,g,n,n,PM_MRK_STCX_FAIL,Marked STCX failed ##820E6 A marked stcx (stwcx or stdcx) failed #179,v,g,n,n,PM_MRK_ST_CMPL,Marked store instruction completed ##00003 A sampled store has completed (data home) #180,v,g,n,n,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses ##820E3 A marked store missed the dcache #181,v,g,n,n,PM_PMC4_OVERFLOW,PMC4 Overflow ##0000A PMC4 Overflow #182,v,g,n,n,PM_PMC5_OVERFLOW,PMC5 Overflow ##0001A PMC5 Overflow #183,v,g,n,n,PM_PTEG_FROM_L2,PTEG loaded from L2 ##83087 PTEG loaded from L2 #184,v,g,n,n,PM_PTEG_FROM_L25_SHR,PTEG loaded from L2.5 shared ##83097 PTEG loaded from L2.5 shared #185,v,g,n,n,PM_PTEG_FROM_L275_MOD,PTEG loaded from L2.75 modified ##830A3 PTEG loaded from L2.75 modified #186,v,g,n,n,PM_PTEG_FROM_L3,PTEG loaded from L3 ##8308E PTEG loaded from L3 #187,v,g,n,n,PM_PTEG_FROM_L35_SHR,PTEG loaded from L3.5 shared ##8309E PTEG loaded from L3.5 shared #188,v,g,n,n,PM_PTEG_FROM_L375_MOD,PTEG loaded from L3.75 modified ##830A7 PTEG loaded from L3.75 modified #189,v,g,n,n,PM_PTEG_FROM_RMEM,PTEG loaded from remote memory ##830A1 PTEG loaded from remote memory #190,v,g,n,n,PM_RUN_CYC,Run cycles ##00005 Processor Cycles gated by the run latch #191,v,g,n,s,PM_SNOOP_DCLAIM_RETRY_QFULL,Snoop dclaim/flush retry due to write/dclaim queues full ##720E6 Snoop dclaim/flush retry due to write/dclaim queues full #192,v,g,n,s,PM_SNOOP_PW_RETRY_RQ,Snoop partial-write retry due to collision with active read queue ##707C6 Snoop partial-write retry due to collision with active read queue #193,v,g,n,s,PM_SNOOP_RD_RETRY_QFULL,Snoop read retry due to read queue full ##700C6 Snoop read retry due to read queue full #194,v,g,n,s,PM_SNOOP_RD_RETRY_RQ,Snoop read retry due to collision with active read queue ##705C6 Snoop read retry due to collision with active read queue #195,v,g,n,s,PM_SNOOP_RETRY_1AHEAD,Snoop retry due to one ahead collision ##725E6 Snoop retry due to one ahead collision #196,u,g,n,s,PM_SNOOP_TLBIE,Snoop TLBIE ##800C3 A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction. #197,v,g,n,s,PM_SNOOP_WR_RETRY_RQ,Snoop write/dclaim retry due to collision with active read queue ##706C6 Snoop write/dclaim retry due to collision with active read queue #198,v,g,n,n,PM_STCX_FAIL,STCX failed ##820E1 A stcx (stwcx or stdcx) failed #199,v,g,n,n,PM_STCX_PASS,Stcx passes ##820E5 A stcx (stwcx or stdcx) instruction was successful #200,v,g,n,n,PM_SUSPENDED,Suspended ##00000 Suspended #201,u,g,n,n,PM_TB_BIT_TRANS,Time Base bit transition ##00018 When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 #202,v,g,n,s,PM_THRD_ONE_RUN_CYC,One of the threads in run cycles ##0000B One of the threads in run cycles #203,v,g,n,n,PM_THRD_PRIO_1_CYC,Cycles thread running at priority level 1 ##420E0 Cycles thread running at priority level 1 #204,v,g,n,n,PM_THRD_PRIO_2_CYC,Cycles thread running at priority level 2 ##420E1 Cycles thread running at priority level 2 #205,v,g,n,n,PM_THRD_PRIO_3_CYC,Cycles thread running at priority level 3 ##420E2 Cycles thread running at priority level 3 #206,v,g,n,n,PM_THRD_PRIO_4_CYC,Cycles thread running at priority level 4 ##420E3 Cycles thread running at priority level 4 #207,v,g,n,n,PM_THRD_PRIO_5_CYC,Cycles thread running at priority level 5 ##420E4 Cycles thread running at priority level 5 #208,v,g,n,n,PM_THRD_PRIO_6_CYC,Cycles thread running at priority level 6 ##420E5 Cycles thread running at priority level 6 #209,v,g,n,n,PM_THRD_PRIO_7_CYC,Cycles thread running at priority level 7 ##420E6 Cycles thread running at priority level 7 #210,v,g,n,n,PM_TLB_MISS,TLB misses ##80088 TLB misses #211,v,g,n,s,PM_XER_MAP_FULL_CYC,Cycles XER mapper full ##100C2 The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. #212,v,g,n,n,PM_INST_FROM_L2MISS,Instructions fetched missed L2 ##2209B An instruction fetch group was fetched from beyond L2. $$$$$$$$ { counter 2 } #0,v,g,n,n,PM_0INST_CLB_CYC,Cycles no instructions in CLB ##400C0 Cycles no instructions in CLB #1,v,g,n,n,PM_1INST_CLB_CYC,Cycles 1 instruction in CLB ##400C1 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #2,v,g,n,n,PM_2INST_CLB_CYC,Cycles 2 instructions in CLB ##400C2 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #3,v,g,n,n,PM_3INST_CLB_CYC,Cycles 3 instructions in CLB ##400C3 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #4,v,g,n,n,PM_4INST_CLB_CYC,Cycles 4 instructions in CLB ##400C4 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #5,v,g,n,n,PM_5INST_CLB_CYC,Cycles 5 instructions in CLB ##400C5 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #6,v,g,n,n,PM_6INST_CLB_CYC,Cycles 6 instructions in CLB ##400C6 The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue. #7,u,g,n,s,PM_BRQ_FULL_CYC,Cycles branch queue full ##100C5 The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups). #8,v,g,n,n,PM_BR_PRED_TA,A conditional branch was predicted, target prediction ##23087 A conditional branch was predicted, target prediction #9,v,g,n,n,PM_CLB_FULL_CYC,Cycles CLB full ##220E5 Cycles CLB full #10,v,g,n,n,PM_CMPLU_STALL_DCACHE_MISS,Completion stall caused by D cache miss ##1109A Completion stall caused by D cache miss #11,v,g,n,n,PM_CMPLU_STALL_FDIV,Completion stall caused by FDIV or FQRT instruction ##1109B Completion stall caused by FDIV or FQRT instruction #12,v,g,n,n,PM_CMPLU_STALL_FXU,Completion stall caused by FXU instruction ##11099 Completion stall caused by FXU instruction #13,v,g,n,n,PM_CMPLU_STALL_LSU,Completion stall caused by LSU instruction ##11098 Completion stall caused by LSU instruction #14,v,g,n,s,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full ##100C4 The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. #15,v,g,n,s,PM_CYC,Processor cycles ##0000F Processor cycles #16,v,g,n,n,PM_DATA_FROM_L25_MOD,Data loaded from L2.5 modified ##C3097 DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load #17,v,g,n,n,PM_DATA_FROM_L35_MOD,Data loaded from L3.5 modified ##C309E Data loaded from L3.5 modified #18,v,g,n,n,PM_DATA_FROM_LMEM,Data loaded from local memory ##C3087 Data loaded from local memory #19,v,g,n,n,PM_DATA_TABLEWALK_CYC,Cycles doing data tablewalks ##800C7 This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried. #20,v,g,n,n,PM_DSLB_MISS,Data SLB misses ##800C5 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve #21,v,g,n,n,PM_DTLB_MISS,Data TLB misses ##800C4 A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction. #22,v,g,n,n,PM_DTLB_MISS_16M,Data TLB miss for 16M page ##C40C4 Data TLB miss for 16M page #23,v,g,n,n,PM_DTLB_MISS_4K,Data TLB miss for 4K page ##C40C0 Data TLB miss for 4K page #24,v,g,n,n,PM_DTLB_REF_16M,Data TLB reference for 16M page ##C40C6 Data TLB reference for 16M page #25,v,g,n,n,PM_DTLB_REF_4K,Data TLB reference for 4K page ##C40C2 Data TLB reference for 4K page #26,v,g,n,s,PM_FAB_CMD_ISSUED,Fabric command issued ##700C7 Fabric command issued #27,v,g,n,s,PM_FAB_DCLAIM_ISSUED,dclaim issued ##720E7 dclaim issued #28,v,g,n,s,PM_FAB_HOLDtoNN_EMPTY,Hold buffer to NN empty ##722E7 Hold buffer to NN empty #29,v,g,n,s,PM_FAB_HOLDtoVN_EMPTY,Hold buffer to VN empty ##721E7 Hold buffer to VN empty #30,v,g,n,s,PM_FAB_M1toP1_SIDECAR_EMPTY,M1 to P1 sidecar empty ##702C7 M1 to P1 sidecar empty #31,v,g,n,s,PM_FAB_P1toM1_SIDECAR_EMPTY,P1 to M1 sidecar empty ##701C7 P1 to M1 sidecar empty #32,v,g,n,s,PM_FAB_PNtoNN_DIRECT,PN to NN beat went straight to its destination ##703C7 PN to NN beat went straight to its destination #33,v,g,n,s,PM_FAB_PNtoVN_DIRECT,PN to VN beat went straight to its destination ##723E7 PN to VN beat went straight to its destination #34,v,g,n,s,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full ##100C1 The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. #35,v,g,n,n,PM_FPU0_1FLOP,FPU0 executed add, mult, sub, cmp or sel instruction ##000C3 This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo #36,v,g,n,n,PM_FPU0_DENORM,FPU0 received denormalized data ##020E0 This signal is active for one cycle when one of the operands is denormalized. #37,v,g,n,n,PM_FPU0_FDIV,FPU0 executed FDIV instruction ##000C0 This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. #38,v,g,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction ##000C1 This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. #39,v,g,n,n,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction ##000C2 This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. #40,v,g,n,s,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full ##100C3 The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped #41,v,g,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction ##020E3 This signal is active for one cycle when fp0 is executing single precision instruction. #42,v,g,n,n,PM_FPU0_STALL3,FPU0 stalled in pipe3 ##020E1 This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. #43,v,g,n,n,PM_FPU0_STF,FPU0 executed store instruction ##020E2 This signal is active for one cycle when fp0 is executing a store instruction. #44,v,g,n,n,PM_FPU1_1FLOP,FPU1 executed add, mult, sub, cmp or sel instruction ##000C7 This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo #45,v,g,n,n,PM_FPU1_DENORM,FPU1 received denormalized data ##020E4 This signal is active for one cycle when one of the operands is denormalized. #46,v,g,n,n,PM_FPU1_FDIV,FPU1 executed FDIV instruction ##000C4 This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. #47,v,g,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction ##000C5 This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. #48,v,g,n,n,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction ##000C6 This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. #49,v,g,n,s,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full ##100C7 The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped #50,v,g,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction ##020E7 This signal is active for one cycle when fp1 is executing single precision instruction. #51,v,g,n,n,PM_FPU1_STALL3,FPU1 stalled in pipe3 ##020E5 This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. #52,v,g,n,n,PM_FPU1_STF,FPU1 executed store instruction ##020E6 This signal is active for one cycle when fp1 is executing a store instruction. #53,v,g,n,n,PM_FPU_FSQRT,FPU executed FSQRT instruction ##00090 This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1 #54,v,g,n,n,PM_FPU_FMA,FPU executed multiply-add instruction ##00088 This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1 #55,v,g,n,n,PM_FPU_STALL3,FPU stalled in pipe3 ##02088 FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1 #56,v,g,n,n,PM_FPU_STF,FPU executed store instruction ##02090 FPU is executing a store instruction. Combined Unit 0 + Unit 1 #57,u,g,n,n,PM_FXU_BUSY,FXU busy ##00012 FXU0 and FXU1 are both busy #58,v,g,n,n,PM_FXU_FIN,FXU produced a result ##00014 The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete. #59,v,g,n,n,PM_GCT_NOSLOT_IC_MISS,No slot in GCT caused by I cache miss ##1009C This thread has no slot in the GCT because of an I cache miss #60,v,g,n,n,PM_GCT_FULL_CYC,Cycles GCT full ##100C0 The ISU sends a signal indicating the gct is full. #61,v,g,n,s,PM_GCT_USAGE_60to79_CYC,Cycles GCT 60-79% full ##0001F Cycles GCT 60-79% full #62,v,g,n,n,PM_GRP_BR_REDIR,Group experienced branch redirect ##120E6 Group experienced branch redirect #63,v,g,n,n,PM_GRP_BR_REDIR_NONSPEC,Group experienced non-speculative branch redirect ##120E5 Group experienced non-speculative branch redirect #64,v,g,n,n,PM_GRP_DISP,Group dispatches ##00002 A group was dispatched #65,v,g,n,n,PM_GRP_DISP_REJECT,Group dispatch rejected ##120E4 A group that previously attempted dispatch was rejected. #66,v,g,n,n,PM_GRP_DISP_VALID,Group dispatch valid ##120E3 Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject. #67,v,g,n,n,PM_GRP_IC_MISS,Group experienced I cache miss ##120E7 Group experienced I cache miss #68,v,g,n,n,PM_HV_CYC,Hypervisor Cycles ##0000B Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0) #69,v,g,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##220E6 Asserted when a non-canceled prefetch is made to the cache interface unit (CIU). #70,v,g,n,n,PM_IERAT_XLATE_WR,Translation written to ierat ##220E7 This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available). #71,v,g,n,n,PM_INST_CMPL,Instructions completed ##00001 Number of Eligible Instructions that completed. #72,v,g,n,n,PM_INST_DISP,Instructions dispatched ##120E1 The ISU sends the number of instructions dispatched. #73,v,g,n,n,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched ##220E4 Asserted each cycle when the IFU sends at least one instruction to the IDU. #74,v,g,n,n,PM_INST_FROM_L1,Instruction fetched from L1 ##2208D An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions #75,v,g,n,n,PM_INST_FROM_L25_MOD,Instruction fetched from L2.5 modified ##22096 Instruction fetched from L2.5 modified #76,v,g,n,n,PM_INST_FROM_L35_MOD,Instruction fetched from L3.5 modified ##2209D Instruction fetched from L3.5 modified #77,v,g,n,n,PM_INST_FROM_LMEM,Instruction fetched from local memory ##22086 Instruction fetched from local memory #78,u,g,n,n,PM_ISLB_MISS,Instruction SLB misses ##800C1 A SLB miss for an instruction fetch as occurred #79,v,g,n,n,PM_ITLB_MISS,Instruction TLB misses ##800C0 A TLB miss for an Instruction Fetch has occurred #80,v,g,n,s,PM_L2SA_MOD_TAG,L2 slice A transition from modified to tagged ##720E0 A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #81,v,g,n,s,PM_L2SA_RCLD_DISP,L2 Slice A RC load dispatch attempt ##701C0 L2 Slice A RC load dispatch attempt #82,v,g,n,s,PM_L2SA_RCLD_DISP_FAIL_RC_FULL,L2 Slice A RC load dispatch attempt failed due to all RC full ##721E0 L2 Slice A RC load dispatch attempt failed due to all RC full #83,v,g,n,s,PM_L2SA_RCST_DISP,L2 Slice A RC store dispatch attempt ##702C0 L2 Slice A RC store dispatch attempt #84,v,g,n,s,PM_L2SA_RCST_DISP_FAIL_RC_FULL,L2 Slice A RC store dispatch attempt failed due to all RC full ##722E0 L2 Slice A RC store dispatch attempt failed due to all RC full #85,v,g,n,s,PM_L2SA_RC_DISP_FAIL_CO_BUSY,L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy ##703C0 L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy #86,v,g,n,s,PM_L2SA_SHR_MOD,L2 slice A transition from shared to modified ##700C0 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. #87,v,g,n,n,PM_L2SA_ST_REQ,L2 slice A store requests ##723E0 A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C. #88,v,g,n,s,PM_L2SB_MOD_TAG,L2 slice B transition from modified to tagged ##720E1 A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #89,v,g,n,s,PM_L2SB_RCLD_DISP,L2 Slice B RC load dispatch attempt ##701C1 L2 Slice B RC load dispatch attempt #90,v,g,n,s,PM_L2SB_RCLD_DISP_FAIL_RC_FULL,L2 Slice B RC load dispatch attempt failed due to all RC full ##721E1 L2 Slice B RC load dispatch attempt failed due to all RC full #91,v,g,n,s,PM_L2SB_RCST_DISP,L2 Slice B RC store dispatch attempt ##702C1 L2 Slice B RC store dispatch attempt #92,v,g,n,s,PM_L2SB_RCST_DISP_FAIL_RC_FULL,L2 Slice B RC store dispatch attempt failed due to all RC full ##722E1 L2 Slice B RC store dispatch attempt failed due to all RC full #93,v,g,n,s,PM_L2SB_RC_DISP_FAIL_CO_BUSY,L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy ##703C1 L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy #94,v,g,n,s,PM_L2SB_SHR_MOD,L2 slice B transition from shared to modified ##700C1 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. #95,v,g,n,n,PM_L2SB_ST_REQ,L2 slice B store requests ##723E1 A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C. #96,v,g,n,s,PM_L2SC_MOD_TAG,L2 slice C transition from modified to tagged ##720E2 A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #97,v,g,n,s,PM_L2SC_RCLD_DISP,L2 Slice C RC load dispatch attempt ##701C2 L2 Slice C RC load dispatch attempt #98,v,g,n,s,PM_L2SC_RCLD_DISP_FAIL_RC_FULL,L2 Slice C RC load dispatch attempt failed due to all RC full ##721E2 L2 Slice C RC load dispatch attempt failed due to all RC full #99,v,g,n,s,PM_L2SC_RCST_DISP,L2 Slice C RC store dispatch attempt ##702C2 L2 Slice C RC store dispatch attempt #100,v,g,n,s,PM_L2SC_RCST_DISP_FAIL_RC_FULL,L2 Slice C RC store dispatch attempt failed due to all RC full ##722E2 L2 Slice C RC store dispatch attempt failed due to all RC full #101,v,g,n,s,PM_L2SC_RC_DISP_FAIL_CO_BUSY,L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy ##703C2 L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy #102,v,g,n,s,PM_L2SC_SHR_MOD,L2 slice C transition from shared to modified ##700C2 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. #103,v,g,n,n,PM_L2SC_ST_REQ,L2 slice C store requests ##723E2 A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C. #104,v,g,n,s,PM_L3SA_ALL_BUSY,L3 slice A active for every cycle all CI/CO machines busy ##721E3 L3 slice A active for every cycle all CI/CO machines busy #105,v,g,n,s,PM_L3SA_MOD_TAG,L3 slice A transition from modified to TAG ##720E3 L3 slice A transition from modified to TAG #106,v,g,n,s,PM_L3SA_REF,L3 slice A references ##701C3 L3 slice A references #107,v,g,n,s,PM_L3SB_ALL_BUSY,L3 slice B active for every cycle all CI/CO machines busy ##721E4 L3 slice B active for every cycle all CI/CO machines busy #108,v,g,n,s,PM_L3SB_MOD_TAG,L3 slice B transition from modified to TAG ##720E4 L3 slice B transition from modified to TAG #109,v,g,n,s,PM_L3SB_REF,L3 slice B references ##701C4 L3 slice B references #110,v,g,n,s,PM_L3SC_ALL_BUSY,L3 slice C active for every cycle all CI/CO machines busy ##721E5 L3 slice C active for every cycle all CI/CO machines busy #111,v,g,n,s,PM_L3SC_MOD_TAG,L3 slice C transition from modified to TAG ##720E5 L3 slice C transition from modified to TAG #112,v,g,n,s,PM_L3SC_REF,L3 slice C references ##701C5 L3 slice C references #113,v,g,n,n,PM_LARX_LSU0,Larx executed on LSU0 ##820E7 A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0) #114,u,g,n,s,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full ##100C6 The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. #115,v,g,n,n,PM_LSU0_BUSY_REJECT,LSU0 busy due to reject ##C20E3 LSU unit 0 busy due to reject #116,v,g,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses ##800C2 A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur. #117,v,g,n,n,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes ##C00C2 A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #118,u,g,n,n,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes ##C00C3 A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #119,v,g,n,n,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes ##C00C0 A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #120,v,g,n,n,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes ##C00C1 A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary) #121,v,g,n,n,PM_LSU0_REJECT_ERAT_MISS,LSU0 reject due to ERAT miss ##C60E3 LSU0 reject due to ERAT miss #122,v,g,n,n,PM_LSU0_REJECT_LMQ_FULL,LSU0 reject due to LMQ full or missed data coming ##C60E1 LSU0 reject due to LMQ full or missed data coming #123,v,g,n,n,PM_LSU0_REJECT_RELOAD_CDF,LSU0 reject due to reload CDF or tag update collision ##C60E2 LSU0 reject due to reload CDF or tag update collision #124,v,g,n,n,PM_LSU0_REJECT_SRQ_LHS,LSU0 SRQ rejects ##C60E0 LSU0 reject due to load hit store #125,u,g,n,n,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded ##C20E0 Data from a store instruction was forwarded to a load on unit 0 #126,v,g,n,n,PM_LSU1_BUSY_REJECT,LSU1 busy due to reject ##C20E7 LSU unit 1 is busy due to reject #127,v,g,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses ##800C6 A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur. #128,v,g,n,n,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes ##C00C6 A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #129,u,g,n,n,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes ##C00C7 A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #130,v,g,n,n,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes ##C00C4 A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #131,u,g,n,n,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes ##C00C5 A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary) #132,v,g,n,n,PM_LSU1_REJECT_ERAT_MISS,LSU1 reject due to ERAT miss ##C60E7 LSU1 reject due to ERAT miss #133,v,g,n,n,PM_LSU1_REJECT_LMQ_FULL,LSU1 reject due to LMQ full or missed data coming ##C60E5 LSU1 reject due to LMQ full or missed data coming #134,v,g,n,n,PM_LSU1_REJECT_RELOAD_CDF,LSU1 reject due to reload CDF or tag update collision ##C60E6 LSU1 reject due to reload CDF or tag update collision #135,v,g,n,n,PM_LSU1_REJECT_SRQ_LHS,LSU1 SRQ rejects ##C60E4 LSU1 reject due to load hit store #136,u,g,n,n,PM_LSU1_SRQ_STFWD,LSU1 SRQ store forwarded ##C20E4 Data from a store instruction was forwarded to a load on unit 1 #137,v,g,n,n,PM_LSU_DERAT_MISS,DERAT misses ##80090 Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. #138,v,g,n,n,PM_LSU_FLUSH_LRQ,LRQ flushes ##C0090 A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #139,v,g,n,s,PM_LSU_FLUSH_LRQ_FULL,Flush caused by LRQ full ##320E7 Flush caused by LRQ full #140,v,g,n,n,PM_LSU_FLUSH_UST,SRQ unaligned store flushes ##C0088 A store was flushed because it was unaligned #141,u,g,n,n,PM_LSU_LMQ_SRQ_EMPTY_CYC,Cycles LMQ and SRQ empty ##00015 Cycles when both the LMQ and SRQ are empty (LSU is idle) #142,v,g,n,n,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated ##C20E6 LRQ slot zero was allocated #143,v,g,n,n,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid ##C20E2 This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. #144,v,g,n,n,PM_LSU_REJECT_LMQ_FULL,LSU reject due to LMQ full or missed data coming ##C6088 LSU reject due to LMQ full or missed data coming #145,v,g,n,n,PM_LSU_REJECT_RELOAD_CDF,LSU reject due to reload CDF or tag update collision ##C6090 LSU reject due to reload CDF or tag update collision #146,v,g,n,n,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated ##C20E5 SRQ Slot zero was allocated #147,v,g,n,n,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid ##C20E1 This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. #148,v,g,n,s,PM_MEM_FAST_PATH_RD_CMPL,Fast path memory read completed ##722E6 Fast path memory read completed #149,v,g,n,s,PM_MEM_HI_PRIO_PW_CMPL,High priority partial-write completed ##727E6 High priority partial-write completed #150,v,g,n,s,PM_MEM_HI_PRIO_WR_CMPL,High priority write completed ##726E6 High priority write completed #151,v,g,n,s,PM_MEM_PWQ_DISP,Memory partial-write queue dispatched ##704C6 Memory partial-write queue dispatched #152,v,g,n,s,PM_MEM_PWQ_DISP_BUSY2or3,Memory partial-write queue dispatched with 2-3 queues busy ##724E6 Memory partial-write queue dispatched with 2-3 queues busy #153,v,g,n,s,PM_MEM_READ_CMPL,Memory read completed or canceled ##702C6 Memory read completed or canceled #154,v,g,n,s,PM_MEM_RQ_DISP,Memory read queue dispatched ##701C6 Memory read queue dispatched #155,v,g,n,s,PM_MEM_RQ_DISP_BUSY8to15,Memory read queue dispatched with 8-15 queues busy ##721E6 Memory read queue dispatched with 8-15 queues busy #156,v,g,n,s,PM_MEM_WQ_DISP_BUSY1to7,Memory write queue dispatched with 1-7 queues busy ##723E6 Memory write queue dispatched with 1-7 queues busy #157,v,g,n,s,PM_MEM_WQ_DISP_WRITE,Memory write queue dispatched due to write ##703C6 Memory write queue dispatched due to write #158,v,g,n,n,PM_MRK_BRU_FIN,Marked instruction BRU processing finished ##00005 The branch unit finished a marked instruction. Instructions that finish may not necessary complete #159,v,g,n,n,PM_MRK_DATA_FROM_L25_MOD,Marked data loaded from L2.5 modified ##C7097 DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load #160,v,g,n,n,PM_MRK_DATA_FROM_L25_SHR_CYC,Marked load latency from L2.5 shared ##C70A2 Marked load latency from L2.5 shared #161,v,g,n,n,PM_MRK_DATA_FROM_L275_SHR_CYC,Marked load latency from L2.75 shared ##C70A3 Marked load latency from L2.75 shared #162,v,g,n,n,PM_MRK_DATA_FROM_L2_CYC,Marked load latency from L2 ##C70A0 Marked load latency from L2 #163,v,g,n,n,PM_MRK_DATA_FROM_L35_MOD,Marked data loaded from L3.5 modified ##C709E Marked data loaded from L3.5 modified #164,v,g,n,n,PM_MRK_DATA_FROM_L35_SHR_CYC,Marked load latency from L3.5 shared ##C70A6 Marked load latency from L3.5 shared #165,v,g,n,n,PM_MRK_DATA_FROM_L375_SHR_CYC,Marked load latency from L3.75 shared ##C70A7 Marked load latency from L3.75 shared #166,v,g,n,n,PM_MRK_DATA_FROM_L3_CYC,Marked load latency from L3 ##C70A4 Marked load latency from L3 #167,v,g,n,n,PM_MRK_DATA_FROM_LMEM,Marked data loaded from local memory ##C7087 Marked data loaded from local memory #168,v,g,n,n,PM_MRK_DTLB_MISS_16M,Marked Data TLB misses for 16M page ##C40C5 Marked Data TLB misses for 16M page #169,v,g,n,n,PM_MRK_DTLB_MISS_4K,Marked Data TLB misses for 4K page ##C40C1 Marked Data TLB misses for 4K page #170,v,g,n,n,PM_MRK_DTLB_REF_16M,Marked Data TLB reference for 16M page ##C40C7 Marked Data TLB reference for 16M page #171,v,g,n,n,PM_MRK_DTLB_REF_4K,Marked Data TLB reference for 4K page ##C40C3 Marked Data TLB reference for 4K page #172,v,g,n,n,PM_MRK_GRP_BR_REDIR,Group experienced marked branch redirect ##12091 Group experienced marked branch redirect #173,v,g,n,n,PM_MRK_IMR_RELOAD,Marked IMR reloaded ##820E2 A DL1 reload occured due to marked load #174,v,g,n,n,PM_INST_CMPL,Instructions completed ##00009 Number of PPC instructions completed. #175,v,g,n,n,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses ##820E0 A marked load, executing on unit 0, missed the dcache #176,v,g,n,n,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses ##820E4 A marked load, executing on unit 1, missed the dcache #177,v,g,n,n,PM_MRK_STCX_FAIL,Marked STCX failed ##820E6 A marked stcx (stwcx or stdcx) failed #178,v,g,n,n,PM_MRK_ST_GPS,Marked store sent to GPS ##00003 A sampled store has been sent to the memory subsystem #179,v,g,n,n,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses ##820E3 A marked store missed the dcache #180,v,g,n,n,PM_PMC1_OVERFLOW,PMC1 Overflow ##0000A PMC1 Overflow #181,v,g,n,n,PM_PTEG_FROM_L25_MOD,PTEG loaded from L2.5 modified ##83097 PTEG loaded from L2.5 modified #182,v,g,n,n,PM_PTEG_FROM_L35_MOD,PTEG loaded from L3.5 modified ##8309E PTEG loaded from L3.5 modified #183,v,g,n,n,PM_PTEG_FROM_LMEM,PTEG loaded from local memory ##83087 PTEG loaded from local memory #184,v,g,n,n,PM_SLB_MISS,SLB misses ##80088 SLB misses #185,v,g,n,s,PM_SNOOP_DCLAIM_RETRY_QFULL,Snoop dclaim/flush retry due to write/dclaim queues full ##720E6 Snoop dclaim/flush retry due to write/dclaim queues full #186,v,g,n,s,PM_SNOOP_PW_RETRY_RQ,Snoop partial-write retry due to collision with active read queue ##707C6 Snoop partial-write retry due to collision with active read queue #187,v,g,n,s,PM_SNOOP_RD_RETRY_QFULL,Snoop read retry due to read queue full ##700C6 Snoop read retry due to read queue full #188,v,g,n,s,PM_SNOOP_RD_RETRY_RQ,Snoop read retry due to collision with active read queue ##705C6 Snoop read retry due to collision with active read queue #189,v,g,n,s,PM_SNOOP_RETRY_1AHEAD,Snoop retry due to one ahead collision ##725E6 Snoop retry due to one ahead collision #190,u,g,n,s,PM_SNOOP_TLBIE,Snoop TLBIE ##800C3 A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction. #191,v,g,n,s,PM_SNOOP_WR_RETRY_RQ,Snoop write/dclaim retry due to collision with active read queue ##706C6 Snoop write/dclaim retry due to collision with active read queue #192,v,g,n,n,PM_STCX_FAIL,STCX failed ##820E1 A stcx (stwcx or stdcx) failed #193,v,g,n,n,PM_STCX_PASS,Stcx passes ##820E5 A stcx (stwcx or stdcx) instruction was successful #194,v,g,n,n,PM_SUSPENDED,Suspended ##00000 Suspended #195,v,g,n,s,PM_GCT_EMPTY_CYC,Cycles GCT empty ##00004 The Global Completion Table is completely empty #196,v,g,n,n,PM_THRD_GRP_CMPL_BOTH_CYC,Cycles group completed by both threads ##00013 Cycles group completed by both threads #197,v,g,n,n,PM_THRD_PRIO_1_CYC,Cycles thread running at priority level 1 ##420E0 Cycles thread running at priority level 1 #198,v,g,n,n,PM_THRD_PRIO_2_CYC,Cycles thread running at priority level 2 ##420E1 Cycles thread running at priority level 2 #199,v,g,n,n,PM_THRD_PRIO_3_CYC,Cycles thread running at priority level 3 ##420E2 Cycles thread running at priority level 3 #200,v,g,n,n,PM_THRD_PRIO_4_CYC,Cycles thread running at priority level 4 ##420E3 Cycles thread running at priority level 4 #201,v,g,n,n,PM_THRD_PRIO_5_CYC,Cycles thread running at priority level 5 ##420E4 Cycles thread running at priority level 5 #202,v,g,n,n,PM_THRD_PRIO_6_CYC,Cycles thread running at priority level 6 ##420E5 Cycles thread running at priority level 6 #203,v,g,n,n,PM_THRD_PRIO_7_CYC,Cycles thread running at priority level 7 ##420E6 Cycles thread running at priority level 7 #204,v,g,n,s,PM_XER_MAP_FULL_CYC,Cycles XER mapper full ##100C2 The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. $$$$$$$$ { counter 3 } #0,v,g,n,n,PM_BR_ISSUED,Branches issued ##230E4 This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue. #1,v,g,n,n,PM_BR_MPRED_CR,Branch mispredictions due to CR bit setting ##230E5 This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction. #2,v,g,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address ##230E6 branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction. #3,v,g,n,n,PM_BR_PRED_CR,A conditional branch was predicted, CR prediction ##23087,230E2 A conditional branch was predicted, CR prediction #4,v,g,n,n,PM_BR_PRED_TA,A conditional branch was predicted, target prediction ##230E3 A conditional branch was predicted, target prediction #5,u,g,n,s,PM_CRQ_FULL_CYC,Cycles CR issue queue full ##110C1 The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups). #6,v,g,n,s,PM_CYC,Processor cycles ##0000F Processor cycles #7,v,g,n,n,PM_DATA_FROM_L25_MOD,Data loaded from L2.5 modified ##C30A2 DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load #8,v,g,n,n,PM_DATA_FROM_L275_SHR,Data loaded from L2.75 shared ##C3097 DL1 was reloaded with shared (T) data from the L2 of another MCM due to a demand load #9,v,g,n,n,PM_DATA_FROM_L35_MOD,Data loaded from L3.5 modified ##C30A6 Data loaded from L3.5 modified #10,v,g,n,n,PM_DATA_FROM_L375_SHR,Data loaded from L3.75 shared ##C309E Data loaded from L3.75 shared #11,v,g,n,n,PM_DATA_FROM_LMEM,Data loaded from local memory ##C30A0 Data loaded from local memory #12,u,g,n,s,PM_DC_INV_L2,L1 D cache entries invalidated from L2 ##C10C7 A dcache invalidated was received from the L2 because a line in L2 was castout. #13,v,g,n,n,PM_DC_PREF_DST,DST (Data Stream Touch) stream start ##830E6 DST (Data Stream Touch) stream start #14,v,g,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated ##830E7 A new Prefetch Stream was allocated #15,v,g,n,n,PM_EE_OFF,Cycles MSR(EE) bit off ##130E3 The number of Cycles MSR(EE) bit was off. #16,u,g,n,n,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending ##130E7 Cycles MSR(EE) bit off and external interrupt pending #17,v,g,n,n,PM_FAB_CMD_RETRIED,Fabric command retried ##710C7 Fabric command retried #18,v,g,n,s,PM_FAB_DCLAIM_RETRIED,dclaim retried ##730E7 dclaim retried #19,v,g,n,s,PM_FAB_M1toVNorNN_SIDECAR_EMPTY,M1 to VN/NN sidecar empty ##712C7 M1 to VN/NN sidecar empty #20,v,g,n,s,PM_FAB_P1toVNorNN_SIDECAR_EMPTY,P1 to VN/NN sidecar empty ##711C7 P1 to VN/NN sidecar empty #21,v,g,n,s,PM_FAB_PNtoNN_SIDECAR,PN to NN beat went to sidecar first ##713C7 PN to NN beat went to sidecar first #22,v,g,n,s,PM_FAB_PNtoVN_SIDECAR,PN to VN beat went to sidecar first ##733E7 PN to VN beat went to sidecar first #23,v,g,n,s,PM_FAB_VBYPASS_EMPTY,Vertical bypass buffer empty ##731E7 Vertical bypass buffer empty #24,v,g,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##110C6 Flush caused by branch mispredict #25,v,g,n,s,PM_FLUSH_IMBAL,Flush caused by thread GCT imbalance ##330E3 Flush caused by thread GCT imbalance #26,v,g,n,n,PM_FLUSH,Flushes ##110C7 Flushes #27,v,g,n,s,PM_FLUSH_SB,Flush caused by scoreboard operation ##330E2 Flush caused by scoreboard operation #28,v,g,n,s,PM_FLUSH_SYNC,Flush caused by sync ##330E1 Flush caused by sync #29,v,g,n,n,PM_FPU0_FEST,FPU0 executed FEST instruction ##010C2 This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. #30,v,g,n,n,PM_FPU0_FIN,FPU0 produced a result ##010C3 fp0 finished, produced a result This only indicates finish, not completion. #31,v,g,n,n,PM_FPU0_FMOV_FEST,FPU0 executed FMOV or FEST instructions ##010C0 This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ #32,v,g,n,n,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction ##030E0 This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs #33,v,g,n,n,PM_FPU0_FRSP_FCONV,FPU0 executed FRSP or FCONV instructions ##010C1 This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. #34,v,g,n,n,PM_FPU1_FEST,FPU1 executed FEST instruction ##010C6 This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. #35,v,g,n,n,PM_FPU1_FIN,FPU1 produced a result ##010C7 fp1 finished, produced a result. This only indicates finish, not completion. #36,v,g,n,n,PM_FPU1_FMOV_FEST,FPU1 executing FMOV or FEST instructions ##010C4 This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ #37,v,g,n,n,PM_FPU1_FRSP_FCONV,FPU1 executed FRSP or FCONV instructions ##010C5 This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. #38,v,g,n,n,PM_FPU_FMOV_FEST,FPU executing FMOV or FEST instructions ##01088 This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1 #39,v,g,n,n,PM_FPU_FRSP_FCONV,FPU executed FRSP or FCONV instructions ##01090 This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1 #40,v,g,n,s,PM_FXLS0_FULL_CYC,Cycles FXU0/LS0 queue full ##110C0 The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped #41,v,g,n,s,PM_FXLS1_FULL_CYC,Cycles FXU1/LS1 queue full ##110C4 The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped #42,u,g,n,n,PM_FXU0_BUSY_FXU1_IDLE,FXU0 busy FXU1 idle ##00012 FXU0 is busy while FXU1 was idle #43,v,g,n,n,PM_FXU0_FIN,FXU0 produced a result ##130E2 The Fixed Point unit 0 finished an instruction and produced a result #44,v,g,n,n,PM_FXU1_FIN,FXU1 produced a result ##130E6 The Fixed Point unit 1 finished an instruction and produced a result #45,v,g,n,n,PM_FXU_FIN,FXU produced a result ##13088 The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete. #46,v,g,n,n,PM_GCT_NOSLOT_SRQ_FULL,No slot in GCT caused by SRQ full ##10084 This thread has no slot in the GCT because the SRQ is full #47,v,g,n,s,PM_GCT_USAGE_80to99_CYC,Cycles GCT 80-99% full ##0001F Cycles GCT 80-99% full #48,v,g,n,s,PM_GPR_MAP_FULL_CYC,Cycles GPR mapper full ##130E5 The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. #49,v,g,n,n,PM_GRP_CMPL,Group completed ##00013 A group completed. Microcoded instructions that span multiple groups will generate this event once per group. #50,v,g,n,n,PM_GRP_DISP_BLK_SB_CYC,Cycles group dispatch blocked by scoreboard ##130E1 The ISU sends a signal indicating that dispatch is blocked by scoreboard. #51,v,g,n,n,PM_GRP_DISP_SUCCESS,Group dispatch success ##00002 Number of groups sucessfully dispatched (not rejected) #52,v,g,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT,L2 I cache demand request due to BHT redirect ##230E0 L2 I cache demand request due to BHT redirect #53,v,g,n,n,PM_IC_DEMAND_L2_BR_REDIRECT,L2 I cache demand request due to branch redirect ##230E1 L2 I cache demand request due to branch redirect #54,v,g,n,n,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch ##210C7 New line coming into the prefetch buffer #55,v,g,n,n,PM_INST_CMPL,Instructions completed ##00001 Number of Eligible Instructions that completed. #56,v,g,n,n,PM_INST_DISP,Instructions dispatched ##00009 The ISU sends the number of instructions dispatched. #57,v,g,n,n,PM_INST_FROM_L275_SHR,Instruction fetched from L2.75 shared ##22096 Instruction fetched from L2.75 shared #58,v,g,n,n,PM_INST_FROM_L375_SHR,Instruction fetched from L3.75 shared ##2209D Instruction fetched from L3.75 shared #59,v,g,n,n,PM_INST_FROM_PREF,Instructions fetched from prefetch ##2208D An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions #60,v,g,n,n,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid ##C30E4 The data source information is valid #61,v,g,n,n,PM_L1_PREF,L1 cache data prefetches ##C70E7 A request to prefetch data into the L1 was made #62,v,g,n,n,PM_L1_WRITE_CYC,Cycles writing to instruction L1 ##230E7 This signal is asserted each cycle a cache write is active. #63,v,g,n,s,PM_L2SA_MOD_INV,L2 slice A transition from modified to invalid ##730E0 A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #64,v,g,n,s,PM_L2SA_RCLD_DISP_FAIL_ADDR,L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ ##711C0 L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ #65,v,g,n,s,PM_L2SA_RCLD_DISP_FAIL_OTHER,L2 Slice A RC load dispatch attempt failed due to other reasons ##731E0 L2 Slice A RC load dispatch attempt failed due to other reasons #66,v,g,n,s,PM_L2SA_RCST_DISP_FAIL_ADDR,L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ ##712C0 L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ #67,v,g,n,s,PM_L2SA_RCST_DISP_FAIL_OTHER,L2 Slice A RC store dispatch attempt failed due to other reasons ##732E0 L2 Slice A RC store dispatch attempt failed due to other reasons #68,v,g,n,s,PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL,L2 Slice A RC dispatch attempt failed due to all CO busy ##713C0 L2 Slice A RC dispatch attempt failed due to all CO busy #69,v,g,n,s,PM_L2SA_SHR_INV,L2 slice A transition from shared to invalid ##710C0 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted. #70,v,g,n,n,PM_L2SA_ST_HIT,L2 slice A store hits ##733E0 A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C. #71,v,g,n,s,PM_L2SB_MOD_INV,L2 slice B transition from modified to invalid ##730E1 A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #72,v,g,n,s,PM_L2SB_RCLD_DISP_FAIL_ADDR,L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ ##711C1 L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ #73,v,g,n,s,PM_L2SB_RCLD_DISP_FAIL_OTHER,L2 Slice B RC load dispatch attempt failed due to other reasons ##731E1 L2 Slice B RC load dispatch attempt failed due to other reasons #74,v,g,n,s,PM_L2SB_RCST_DISP_FAIL_ADDR,L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ ##712C1 L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ #75,v,g,n,s,PM_L2SB_RCST_DISP_FAIL_OTHER,L2 Slice B RC store dispatch attempt failed due to other reasons ##732E1 L2 Slice B RC store dispatch attempt failed due to other reasons #76,v,g,n,s,PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL,L2 Slice B RC dispatch attempt failed due to all CO busy ##713C1 L2 Slice B RC dispatch attempt failed due to all CO busy #77,v,g,n,s,PM_L2SB_SHR_INV,L2 slice B transition from shared to invalid ##710C1 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted. #78,v,g,n,n,PM_L2SB_ST_HIT,L2 slice B store hits ##733E1 A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C. #79,v,g,n,s,PM_L2SC_MOD_INV,L2 slice C transition from modified to invalid ##730E2 A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #80,v,g,n,s,PM_L2SC_RCLD_DISP_FAIL_ADDR,L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ ##711C2 L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ #81,v,g,n,s,PM_L2SC_RCLD_DISP_FAIL_OTHER,L2 Slice C RC load dispatch attempt failed due to other reasons ##731E2 L2 Slice C RC load dispatch attempt failed due to other reasons #82,v,g,n,s,PM_L2SC_RCST_DISP_FAIL_ADDR,L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ ##712C2 L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ #83,v,g,n,s,PM_L2SC_RCST_DISP_FAIL_OTHER,L2 Slice C RC store dispatch attempt failed due to other reasons ##732E2 L2 Slice C RC store dispatch attempt failed due to other reasons #84,v,g,n,s,PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL,L2 Slice C RC dispatch attempt failed due to all CO busy ##713C2 L2 Slice C RC dispatch attempt failed due to all CO busy #85,v,g,n,s,PM_L2SC_SHR_INV,L2 slice C transition from shared to invalid ##710C2 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted. #86,v,g,n,n,PM_L2SC_ST_HIT,L2 slice C store hits ##733E2 L2 slice C store hits #87,v,g,n,n,PM_L2_PREF,L2 cache prefetches ##C50C3 A request to prefetch data into L2 was made #88,v,g,n,s,PM_L3SA_HIT,L3 slice A hits ##711C3 L3 slice A hits #89,v,g,n,s,PM_L3SA_MOD_INV,L3 slice A transition from modified to invalid ##730E3 L3 slice A transition from modified to invalid #90,v,g,n,s,PM_L3SA_SHR_INV,L3 slice A transition from shared to invalid ##710C3 L3 slice A transition from shared to invalid #91,v,g,n,s,PM_L3SA_SNOOP_RETRY,L3 slice A snoop retries ##731E3 L3 slice A snoop retries #92,v,g,n,s,PM_L3SB_HIT,L3 slice B hits ##711C4 L3 slice B hits #93,v,g,n,s,PM_L3SB_MOD_INV,L3 slice B transition from modified to invalid ##730E4 L3 slice B transition from modified to invalid #94,v,g,n,s,PM_L3SB_SHR_INV,L3 slice B transition from shared to invalid ##710C4 L3 slice B transition from shared to invalid #95,v,g,n,s,PM_L3SB_SNOOP_RETRY,L3 slice B snoop retries ##731E4 L3 slice B snoop retries #96,v,g,n,s,PM_L3SC_HIT,L3 Slice C hits ##711C5 L3 Slice C hits #97,v,g,n,s,PM_L3SC_MOD_INV,L3 slice C transition from modified to invalid ##730E5 L3 slice C transition from modified to invalid #98,v,g,n,s,PM_L3SC_SHR_INV,L3 slice C transition from shared to invalid ##710C5 L3 slice C transition from shared to invalid #99,v,g,n,s,PM_L3SC_SNOOP_RETRY,L3 slice C snoop retries ##731E5 L3 slice C snoop retries #100,v,g,n,n,PM_LD_MISS_L1,L1 D cache load misses ##C1088 Total DL1 Load references that miss the DL1 #101,v,g,n,n,PM_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses ##C10C2 A load, executing on unit 0, missed the dcache #102,v,g,n,n,PM_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses ##C10C6 A load, executing on unit 1, missed the dcache #103,v,g,n,n,PM_LD_REF_L1_LSU0,LSU0 L1 D cache load references ##C10C0 A load executed on unit 0 #104,v,g,n,n,PM_LD_REF_L1_LSU1,LSU1 L1 D cache load references ##C10C4 A load executed on unit 1 #105,v,g,n,n,PM_LSU0_LDF,LSU0 executed Floating Point load instruction ##C50C0 A floating point load was executed from LSU unit 0 #106,v,g,n,n,PM_LSU0_NCLD,LSU0 non-cacheable loads ##C50C1 LSU0 non-cacheable loads #107,v,g,n,n,PM_LSU1_LDF,LSU1 executed Floating Point load instruction ##C50C4 A floating point load was executed from LSU unit 1 #108,v,g,n,n,PM_LSU1_NCLD,LSU1 non-cacheable loads ##C50C5 LSU1 non-cacheable loads #109,v,g,n,n,PM_LSU_FLUSH,Flush initiated by LSU ##110C5 Flush initiated by LSU #110,v,g,n,s,PM_LSU_FLUSH_SRQ_FULL,Flush caused by SRQ full ##330E0 Flush caused by SRQ full #111,u,g,n,s,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full ##C30E7 The LMQ was full #112,v,g,n,n,PM_LSU_LMQ_LHR_MERGE,LMQ LHR merges ##C70E5 A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry. #113,v,g,n,s,PM_LSU_LMQ_S0_ALLOC,LMQ slot 0 allocated ##C30E6 The first entry in the LMQ was allocated. #114,v,g,n,n,PM_LSU_LMQ_S0_VALID,LMQ slot 0 valid ##C30E5 This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO #115,u,g,n,n,PM_LSU_LMQ_SRQ_EMPTY_CYC,Cycles LMQ and SRQ empty ##00015 Cycles when both the LMQ and SRQ are empty (LSU is idle) #116,v,g,n,s,PM_LSU_LRQ_FULL_CYC,Cycles LRQ full ##110C2 The ISU sends this signal when the LRQ is full. #117,u,g,n,n,PM_DC_PREF_STREAM_ALLOC_BLK,D cache out of prefech streams ##C50C2 D cache out of prefech streams #118,v,g,n,s,PM_LSU_SRQ_FULL_CYC,Cycles SRQ full ##110C3 The ISU sends this signal when the srq is full. #119,u,g,n,n,PM_LSU_SRQ_SYNC_CYC,SRQ sync duration ##830E5 This signal is asserted every cycle when a sync is in the SRQ. #120,v,g,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##130E0 LWSYNC held at dispatch #121,v,g,n,s,PM_MEM_LO_PRIO_PW_CMPL,Low priority partial-write completed ##737E6 Low priority partial-write completed #122,v,g,n,s,PM_MEM_LO_PRIO_WR_CMPL,Low priority write completed ##736E6 Low priority write completed #123,v,g,n,s,PM_MEM_PW_CMPL,Memory partial-write completed ##734E6 Memory partial-write completed #124,v,g,n,s,PM_MEM_PW_GATH,Memory partial-write gathered ##714C6 Memory partial-write gathered #125,v,g,n,s,PM_MEM_RQ_DISP_BUSY1to7,Memory read queue dispatched with 1-7 queues busy ##711C6 Memory read queue dispatched with 1-7 queues busy #126,v,g,n,s,PM_MEM_SPEC_RD_CANCEL,Speculative memory read canceled ##712C6 Speculative memory read canceled #127,v,g,n,s,PM_MEM_WQ_DISP_BUSY8to15,Memory write queue dispatched with 8-15 queues busy ##733E6 Memory write queue dispatched with 8-15 queues busy #128,v,g,n,s,PM_MEM_WQ_DISP_DCLAIM,Memory write queue dispatched due to dclaim/flush ##713C6 Memory write queue dispatched due to dclaim/flush #129,v,g,n,n,PM_MRK_DATA_FROM_L25_MOD,Marked data loaded from L2.5 modified ##C70A2 DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load #130,v,g,n,n,PM_MRK_DATA_FROM_L275_SHR,Marked data loaded from L2.75 shared ##C7097 DL1 was reloaded with shared (T) data from the L2 of another MCM due to a marked demand load #131,v,g,n,n,PM_MRK_DATA_FROM_L35_MOD,Marked data loaded from L3.5 modified ##C70A6 Marked data loaded from L3.5 modified #132,v,g,n,n,PM_MRK_DATA_FROM_L375_SHR,Marked data loaded from L3.75 shared ##C709E Marked data loaded from L3.75 shared #133,v,g,n,n,PM_MRK_DATA_FROM_LMEM,Marked data loaded from local memory ##C70A0 Marked data loaded from local memory #134,v,g,n,n,PM_MRK_DSLB_MISS,Marked Data SLB misses ##C50C7 Marked Data SLB misses #135,v,g,n,n,PM_MRK_DTLB_MISS,Marked Data TLB misses ##C50C6 Marked Data TLB misses #136,v,g,n,n,PM_MRK_FPU_FIN,Marked instruction FPU processing finished ##00014 One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete #137,v,g,n,n,PM_MRK_INST_FIN,Marked instruction finished ##00005 One of the execution units finished a marked instruction. Instructions that finish may not necessary complete #138,v,g,n,n,PM_MRK_L1_RELOAD_VALID,Marked L1 reload data source valid ##C70E4 The source information is valid and is for a marked load #139,v,g,n,n,PM_MRK_LSU0_FLUSH_LRQ,LSU0 marked LRQ flushes ##810C2 A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #140,u,g,n,n,PM_MRK_LSU0_FLUSH_SRQ,LSU0 marked SRQ flushes ##810C3 A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #141,v,g,n,n,PM_MRK_LSU0_FLUSH_UST,LSU0 marked unaligned store flushes ##810C1 A marked store was flushed from unit 0 because it was unaligned #142,v,g,n,n,PM_MRK_LSU0_FLUSH_ULD,LSU0 marked unaligned load flushes ##810C0 A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #143,v,g,n,n,PM_MRK_LSU1_FLUSH_LRQ,LSU1 marked LRQ flushes ##810C6 A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #144,u,g,n,n,PM_MRK_LSU1_FLUSH_SRQ,LSU1 marked SRQ flushes ##810C7 A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #145,v,g,n,n,PM_MRK_LSU1_FLUSH_ULD,LSU1 marked unaligned load flushes ##810C4 A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #146,u,g,n,n,PM_MRK_LSU1_FLUSH_UST,LSU1 marked unaligned store flushes ##810C5 A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary) #147,v,g,n,n,PM_MRK_LSU_FLUSH_LRQ,Marked LRQ flushes ##81088 A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #148,v,g,n,n,PM_MRK_LSU_FLUSH_UST,Marked unaligned store flushes ##81090 A marked store was flushed because it was unaligned #149,u,g,n,n,PM_MRK_LSU_SRQ_INST_VALID,Marked instruction valid in SRQ ##C70E6 This signal is asserted every cycle when a marked request is resident in the Store Request Queue #150,v,g,n,n,PM_MRK_ST_CMPL_INT,Marked store completed with intervention ##00003 A marked store previously sent to the memory subsystem completed (data home) after requiring intervention #151,v,g,n,n,PM_PMC2_OVERFLOW,PMC2 Overflow ##0000A PMC2 Overflow #152,v,g,n,n,PM_PMC6_OVERFLOW,PMC6 Overflow ##0001A PMC6 Overflow #153,v,g,n,n,PM_PTEG_FROM_L25_MOD,PTEG loaded from L2.5 modified ##830A2 PTEG loaded from L2.5 modified #154,v,g,n,n,PM_PTEG_FROM_L275_SHR,PTEG loaded from L2.75 shared ##83097 PTEG loaded from L2.75 shared #155,v,g,n,n,PM_PTEG_FROM_L35_MOD,PTEG loaded from L3.5 modified ##830A6 PTEG loaded from L3.5 modified #156,v,g,n,n,PM_PTEG_FROM_L375_SHR,PTEG loaded from L3.75 shared ##8309E PTEG loaded from L3.75 shared #157,v,g,n,n,PM_PTEG_FROM_LMEM,PTEG loaded from local memory ##830A0 PTEG loaded from local memory #158,v,g,n,s,PM_SNOOP_PARTIAL_RTRY_QFULL,Snoop partial write retry due to partial-write queues full ##730E6 Snoop partial write retry due to partial-write queues full #159,v,g,n,s,PM_SNOOP_PW_RETRY_WQ_PWQ,Snoop partial-write retry due to collision with active write or partial-write queue ##717C6 Snoop partial-write retry due to collision with active write or partial-write queue #160,v,g,n,s,PM_SNOOP_RD_RETRY_WQ,Snoop read retry due to collision with active write queue ##715C6 Snoop read retry due to collision with active write queue #161,v,g,n,s,PM_SNOOP_WR_RETRY_QFULL,Snoop read retry due to read queue full ##710C6 Snoop read retry due to read queue full #162,v,g,n,s,PM_SNOOP_WR_RETRY_WQ,Snoop write/dclaim retry due to collision with active write queue ##716C6 Snoop write/dclaim retry due to collision with active write queue #163,v,g,n,n,PM_STOP_COMPLETION,Completion stopped ##00018 RAS Unit has signaled completion to stop #164,v,g,n,n,PM_ST_MISS_L1,L1 D cache store misses ##C10C3 A store missed the dcache #165,v,g,n,n,PM_ST_REF_L1,L1 D cache store references ##C1090 Total DL1 Store references #166,v,g,n,n,PM_ST_REF_L1_LSU0,LSU0 L1 D cache store references ##C10C1 A store executed on unit 0 #167,v,g,n,n,PM_ST_REF_L1_LSU1,LSU1 L1 D cache store references ##C10C5 A store executed on unit 1 #168,v,g,n,n,PM_SUSPENDED,Suspended ##00000 Suspended #169,v,g,n,s,PM_CLB_EMPTY_CYC,Cycles CLB empty ##410C6 Cycles CLB completely empty #170,v,g,n,s,PM_THRD_L2MISS_BOTH_CYC,Cycles both threads in L2 misses ##410C7 Cycles both threads in L2 misses #171,v,g,n,n,PM_THRD_PRIO_DIFF_0_CYC,Cycles no thread priority difference ##430E3 Cycles no thread priority difference #172,v,g,n,n,PM_THRD_PRIO_DIFF_1or2_CYC,Cycles thread priority difference is 1 or 2 ##430E4 Cycles thread priority difference is 1 or 2 #173,v,g,n,n,PM_THRD_PRIO_DIFF_3or4_CYC,Cycles thread priority difference is 3 or 4 ##430E5 Cycles thread priority difference is 3 or 4 #174,v,g,n,n,PM_THRD_PRIO_DIFF_5or6_CYC,Cycles thread priority difference is 5 or 6 ##430E6 Cycles thread priority difference is 5 or 6 #175,v,g,n,n,PM_THRD_PRIO_DIFF_minus1or2_CYC,Cycles thread priority difference is -1 or -2 ##430E2 Cycles thread priority difference is -1 or -2 #176,v,g,n,n,PM_THRD_PRIO_DIFF_minus3or4_CYC,Cycles thread priority difference is -3 or -4 ##430E1 Cycles thread priority difference is -3 or -4 #177,v,g,n,n,PM_THRD_PRIO_DIFF_minus5or6_CYC,Cycles thread priority difference is -5 or -6 ##430E0 Cycles thread priority difference is -5 or -6 #178,v,g,n,s,PM_THRD_SEL_OVER_CLB_EMPTY,Thread selection overides caused by CLB empty ##410C2 Thread selection overides caused by CLB empty #179,v,g,n,s,PM_THRD_SEL_OVER_GCT_IMBAL,Thread selection overides caused by GCT imbalance ##410C4 Thread selection overides caused by GCT imbalance #180,v,g,n,s,PM_THRD_SEL_OVER_ISU_HOLD,Thread selection overides caused by ISU holds ##410C5 Thread selection overides caused by ISU holds #181,v,g,n,s,PM_THRD_SEL_OVER_L2MISS,Thread selection overides caused by L2 misses ##410C3 Thread selection overides caused by L2 misses #182,v,g,n,s,PM_THRD_SEL_T0,Decode selected thread 0 ##410C0 Decode selected thread 0 #183,v,g,n,s,PM_THRD_SEL_T1,Decode selected thread 1 ##410C1 Decode selected thread 1 #184,v,g,n,s,PM_THRD_SMT_HANG,SMT hang detected ##330E7 SMT hang detected #185,v,g,t,n,PM_THRESH_TIMEO,Threshold timeout ##0000B The threshold timer expired #186,v,g,n,n,PM_TLBIE_HELD,TLBIE held at dispatch ##130E4 TLBIE held at dispatch #187,v,g,n,n,PM_DATA_FROM_L2MISS,Data loaded missed L2 ##C309B DL1 was reloaded from beyond L2. #188,v,g,n,n,PM_MRK_DATA_FROM_L2MISS,Marked data loaded missed L2 ##C709B DL1 was reloaded from beyond L2 due to a marked demand load. #189,v,g,n,n,PM_PTEG_FROM_L2MISS,PTEG loaded from L2 miss ##8309B PTEG loaded from L2 miss $$$$$$$$ { counter 4 } #0,v,g,n,n,PM_0INST_FETCH,No instructions fetched ##2208D No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss) #1,v,g,n,n,PM_BR_ISSUED,Branches issued ##230E4 This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue. #2,v,g,n,n,PM_BR_MPRED_CR,Branch mispredictions due to CR bit setting ##230E5 This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction. #3,v,g,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address ##230E6 branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction. #4,v,g,n,n,PM_BR_PRED_CR,A conditional branch was predicted, CR prediction ##230E2 A conditional branch was predicted, CR prediction #5,v,g,n,n,PM_BR_PRED_CR_TA,A conditional branch was predicted, CR and target prediction ##23087 A conditional branch was predicted, CR and target prediction #6,v,g,n,n,PM_BR_PRED_TA,A conditional branch was predicted, target prediction ##230E3 A conditional branch was predicted, target prediction #7,v,g,n,n,PM_CMPLU_STALL_DIV,Completion stall caused by DIV instruction ##11099 Completion stall caused by DIV instruction #8,v,g,n,n,PM_CMPLU_STALL_ERAT_MISS,Completion stall caused by ERAT miss ##1109B Completion stall caused by ERAT miss #9,v,g,n,n,PM_CMPLU_STALL_FPU,Completion stall caused by FPU instruction ##11098 Completion stall caused by FPU instruction #10,v,g,n,n,PM_CMPLU_STALL_REJECT,Completion stall caused by reject ##1109A Completion stall caused by reject #11,u,g,n,s,PM_CRQ_FULL_CYC,Cycles CR issue queue full ##110C1 The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups). #12,v,g,n,s,PM_CYC,Processor cycles ##0000F Processor cycles #13,v,g,n,n,PM_DATA_FROM_L275_MOD,Data loaded from L2.75 modified ##C3097 DL1 was reloaded with modified (M) data from the L2 of another MCM due to a demand load. #14,v,g,n,n,PM_DATA_FROM_L375_MOD,Data loaded from L3.75 modified ##C309E Data loaded from L3.75 modified #15,v,g,n,n,PM_DATA_FROM_RMEM,Data loaded from remote memory ##C3087 Data loaded from remote memory #16,u,g,n,s,PM_DC_INV_L2,L1 D cache entries invalidated from L2 ##C10C7 A dcache invalidated was received from the L2 because a line in L2 was castout. #17,v,g,n,n,PM_DC_PREF_DST,DST (Data Stream Touch) stream start ##830E6 DST (Data Stream Touch) stream start #18,v,g,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated ##830E7 A new Prefetch Stream was allocated #19,v,g,n,n,PM_EE_OFF,Cycles MSR(EE) bit off ##130E3 The number of Cycles MSR(EE) bit was off. #20,u,g,n,n,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending ##130E7 Cycles MSR(EE) bit off and external interrupt pending #21,v,g,n,n,PM_EXT_INT,External interrupts ##00003 An external interrupt occurred #22,v,g,n,n,PM_FAB_CMD_RETRIED,Fabric command retried ##710C7 Fabric command retried #23,v,g,n,s,PM_FAB_DCLAIM_RETRIED,dclaim retried ##730E7 dclaim retried #24,v,g,n,s,PM_FAB_M1toVNorNN_SIDECAR_EMPTY,M1 to VN/NN sidecar empty ##712C7 M1 to VN/NN sidecar empty #25,v,g,n,s,PM_FAB_P1toVNorNN_SIDECAR_EMPTY,P1 to VN/NN sidecar empty ##711C7 P1 to VN/NN sidecar empty #26,v,g,n,s,PM_FAB_PNtoNN_SIDECAR,PN to NN beat went to sidecar first ##713C7 PN to NN beat went to sidecar first #27,v,g,n,s,PM_FAB_PNtoVN_SIDECAR,PN to VN beat went to sidecar first ##733E7 PN to VN beat went to sidecar first #28,v,g,n,s,PM_FAB_VBYPASS_EMPTY,Vertical bypass buffer empty ##731E7 Vertical bypass buffer empty #29,v,g,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##110C6 Flush caused by branch mispredict #30,v,g,n,s,PM_FLUSH_IMBAL,Flush caused by thread GCT imbalance ##330E3 Flush caused by thread GCT imbalance #31,v,g,n,n,PM_FLUSH,Flushes ##110C7 Flushes #32,v,g,n,s,PM_FLUSH_SB,Flush caused by scoreboard operation ##330E2 Flush caused by scoreboard operation #33,v,g,n,s,PM_FLUSH_SYNC,Flush caused by sync ##330E1 Flush caused by sync #34,v,g,n,n,PM_FPU0_FEST,FPU0 executed FEST instruction ##010C2 This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. #35,v,g,n,n,PM_FPU0_FIN,FPU0 produced a result ##010C3 fp0 finished, produced a result This only indicates finish, not completion. #36,v,g,n,n,PM_FPU0_FMOV_FEST,FPU0 executed FMOV or FEST instructions ##010C0 This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ #37,v,g,n,n,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction ##030E0 This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs #38,v,g,n,n,PM_FPU0_FRSP_FCONV,FPU0 executed FRSP or FCONV instructions ##010C1 This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. #39,v,g,n,n,PM_FPU1_FEST,FPU1 executed FEST instruction ##010C6 This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. #40,v,g,n,n,PM_FPU1_FIN,FPU1 produced a result ##010C7 fp1 finished, produced a result. This only indicates finish, not completion. #41,v,g,n,n,PM_FPU1_FMOV_FEST,FPU1 executing FMOV or FEST instructions ##010C4 This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ #42,v,g,n,n,PM_FPU1_FRSP_FCONV,FPU1 executed FRSP or FCONV instructions ##010C5 This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. #43,v,g,n,n,PM_FPU_FEST,FPU executed FEST instruction ##01090 This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1. #44,v,g,n,n,PM_FPU_FIN,FPU produced a result ##01088 FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1 #45,v,g,n,s,PM_FXLS0_FULL_CYC,Cycles FXU0/LS0 queue full ##110C0 The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped #46,v,g,n,s,PM_FXLS1_FULL_CYC,Cycles FXU1/LS1 queue full ##110C4 The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped #47,c,g,n,n,PM_FXLS_FULL_CYC,Cycles FXLS queue is full ##11090 Cycles when one or both FXU/LSU issue queue are full #48,v,g,n,n,PM_FXU0_FIN,FXU0 produced a result ##130E2 The Fixed Point unit 0 finished an instruction and produced a result #49,u,g,n,n,PM_FXU1_BUSY_FXU0_IDLE,FXU1 busy FXU0 idle ##00012 FXU0 was idle while FXU1 was busy #50,v,g,n,n,PM_FXU1_FIN,FXU1 produced a result ##130E6 The Fixed Point unit 1 finished an instruction and produced a result #51,v,g,n,n,PM_GCT_NOSLOT_BR_MPRED,No slot in GCT caused by branch mispredict ##1009C This thread has no slot in the GCT because of branch mispredict #52,v,g,n,n,PM_GCT_FULL_CYC,Cycles GCT full ##0001F The ISU sends a signal indicating the gct is full. #53,v,g,n,s,PM_GPR_MAP_FULL_CYC,Cycles GPR mapper full ##130E5 The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be. #54,v,g,n,n,PM_GRP_DISP_BLK_SB_CYC,Cycles group dispatch blocked by scoreboard ##130E1 The ISU sends a signal indicating that dispatch is blocked by scoreboard. #55,v,g,n,n,PM_GRP_DISP_REJECT,Group dispatch rejected ##00002 A group that previously attempted dispatch was rejected. #56,v,g,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT,L2 I cache demand request due to BHT redirect ##230E0 L2 I cache demand request due to BHT redirect #57,v,g,n,n,PM_IC_DEMAND_L2_BR_REDIRECT,L2 I cache demand request due to branch redirect ##230E1 L2 I cache demand request due to branch redirect #58,v,g,n,n,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch ##210C7 New line coming into the prefetch buffer #59,v,g,n,n,PM_INST_CMPL,Instructions completed ##00001 Number of Eligible Instructions that completed. #60,v,g,n,n,PM_INST_DISP,Instructions dispatched ##00009 The ISU sends the number of instructions dispatched. #61,v,g,n,n,PM_INST_FROM_L275_MOD,Instruction fetched from L2.75 modified ##22096 Instruction fetched from L2.75 modified #62,v,g,n,n,PM_INST_FROM_L375_MOD,Instruction fetched from L3.75 modified ##2209D Instruction fetched from L3.75 modified #63,v,g,n,n,PM_INST_FROM_RMEM,Instruction fetched from remote memory ##22086 Instruction fetched from remote memory #64,v,g,n,n,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid ##C30E4 The data source information is valid #65,v,g,n,n,PM_L1_PREF,L1 cache data prefetches ##C70E7 A request to prefetch data into the L1 was made #66,v,g,n,n,PM_L1_WRITE_CYC,Cycles writing to instruction L1 ##230E7 This signal is asserted each cycle a cache write is active. #67,v,g,n,s,PM_L2SA_MOD_INV,L2 slice A transition from modified to invalid ##730E0 A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #68,v,g,n,s,PM_L2SA_RCLD_DISP_FAIL_ADDR,L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ ##711C0 L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ #69,v,g,n,s,PM_L2SA_RCLD_DISP_FAIL_OTHER,L2 Slice A RC load dispatch attempt failed due to other reasons ##731E0 L2 Slice A RC load dispatch attempt failed due to other reasons #70,v,g,n,s,PM_L2SA_RCST_DISP_FAIL_ADDR,L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ ##712C0 L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ #71,v,g,n,s,PM_L2SA_RCST_DISP_FAIL_OTHER,L2 Slice A RC store dispatch attempt failed due to other reasons ##732E0 L2 Slice A RC store dispatch attempt failed due to other reasons #72,v,g,n,s,PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL,L2 Slice A RC dispatch attempt failed due to all CO busy ##713C0 L2 Slice A RC dispatch attempt failed due to all CO busy #73,v,g,n,s,PM_L2SA_SHR_INV,L2 slice A transition from shared to invalid ##710C0 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted. #74,v,g,n,n,PM_L2SA_ST_HIT,L2 slice A store hits ##733E0 A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C. #75,v,g,n,s,PM_L2SB_MOD_INV,L2 slice B transition from modified to invalid ##730E1 A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #76,v,g,n,s,PM_L2SB_RCLD_DISP_FAIL_ADDR,L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ ##711C1 L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ #77,v,g,n,s,PM_L2SB_RCLD_DISP_FAIL_OTHER,L2 Slice B RC load dispatch attempt failed due to other reasons ##731E1 L2 Slice B RC load dispatch attempt failed due to other reasons #78,v,g,n,s,PM_L2SB_RCST_DISP_FAIL_ADDR,L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ ##712C1 L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ #79,v,g,n,s,PM_L2SB_RCST_DISP_FAIL_OTHER,L2 Slice B RC store dispatch attempt failed due to other reasons ##732E1 L2 Slice B RC store dispatch attempt failed due to other reasons #80,v,g,n,s,PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL,L2 Slice B RC dispatch attempt failed due to all CO busy ##713C1 L2 Slice B RC dispatch attempt failed due to all CO busy #81,v,g,n,s,PM_L2SB_SHR_INV,L2 slice B transition from shared to invalid ##710C1 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted. #82,v,g,n,n,PM_L2SB_ST_HIT,L2 slice B store hits ##733E1 A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C. #83,v,g,n,s,PM_L2SC_MOD_INV,L2 slice C transition from modified to invalid ##730E2 A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C. #84,v,g,n,s,PM_L2SC_RCLD_DISP_FAIL_ADDR,L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ ##711C2 L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ #85,v,g,n,s,PM_L2SC_RCLD_DISP_FAIL_OTHER,L2 Slice C RC load dispatch attempt failed due to other reasons ##731E2 L2 Slice C RC load dispatch attempt failed due to other reasons #86,v,g,n,s,PM_L2SC_RCST_DISP_FAIL_ADDR,L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ ##712C2 L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ #87,v,g,n,s,PM_L2SC_RCST_DISP_FAIL_OTHER,L2 Slice C RC store dispatch attempt failed due to other reasons ##732E2 L2 Slice C RC store dispatch attempt failed due to other reasons #88,v,g,n,s,PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL,L2 Slice C RC dispatch attempt failed due to all CO busy ##713C2 L2 Slice C RC dispatch attempt failed due to all CO busy #89,v,g,n,s,PM_L2SC_SHR_INV,L2 slice C transition from shared to invalid ##710C2 A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted. #90,v,g,n,n,PM_L2SC_ST_HIT,L2 slice C store hits ##733E2 L2 slice C store hits #91,v,g,n,n,PM_L2_PREF,L2 cache prefetches ##C50C3 A request to prefetch data into L2 was made #92,v,g,n,s,PM_L3SA_HIT,L3 slice A hits ##711C3 L3 slice A hits #93,v,g,n,s,PM_L3SA_MOD_INV,L3 slice A transition from modified to invalid ##730E3 L3 slice A transition from modified to invalid #94,v,g,n,s,PM_L3SA_SHR_INV,L3 slice A transition from shared to invalid ##710C3 L3 slice A transition from shared to invalid #95,v,g,n,s,PM_L3SA_SNOOP_RETRY,L3 slice A snoop retries ##731E3 L3 slice A snoop retries #96,v,g,n,s,PM_L3SB_HIT,L3 slice B hits ##711C4 L3 slice B hits #97,v,g,n,s,PM_L3SB_MOD_INV,L3 slice B transition from modified to invalid ##730E4 L3 slice B transition from modified to invalid #98,v,g,n,s,PM_L3SB_SHR_INV,L3 slice B transition from shared to invalid ##710C4 L3 slice B transition from shared to invalid #99,v,g,n,s,PM_L3SB_SNOOP_RETRY,L3 slice B snoop retries ##731E4 L3 slice B snoop retries #100,v,g,n,s,PM_L3SC_HIT,L3 Slice C hits ##711C5 L3 Slice C hits #101,v,g,n,s,PM_L3SC_MOD_INV,L3 slice C transition from modified to invalid ##730E5 L3 slice C transition from modified to invalid #102,v,g,n,s,PM_L3SC_SHR_INV,L3 slice C transition from shared to invalid ##710C5 L3 slice C transition from shared to invalid #103,v,g,n,s,PM_L3SC_SNOOP_RETRY,L3 slice C snoop retries ##731E5 L3 slice C snoop retries #104,v,g,n,n,PM_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses ##C10C2 A load, executing on unit 0, missed the dcache #105,v,g,n,n,PM_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses ##C10C6 A load, executing on unit 1, missed the dcache #106,v,g,n,n,PM_LD_REF_L1,L1 D cache load references ##C1090 Total DL1 Load references #107,v,g,n,n,PM_LD_REF_L1_LSU0,LSU0 L1 D cache load references ##C10C0 A load executed on unit 0 #108,v,g,n,n,PM_LD_REF_L1_LSU1,LSU1 L1 D cache load references ##C10C4 A load executed on unit 1 #109,v,g,n,n,PM_LSU0_LDF,LSU0 executed Floating Point load instruction ##C50C0 A floating point load was executed from LSU unit 0 #110,v,g,n,n,PM_LSU0_NCLD,LSU0 non-cacheable loads ##C50C1 LSU0 non-cacheable loads #111,v,g,n,n,PM_LSU1_LDF,LSU1 executed Floating Point load instruction ##C50C4 A floating point load was executed from LSU unit 1 #112,v,g,n,n,PM_LSU1_NCLD,LSU1 non-cacheable loads ##C50C5 LSU1 non-cacheable loads #113,v,g,n,n,PM_LSU_FLUSH,Flush initiated by LSU ##110C5 Flush initiated by LSU #114,v,g,n,s,PM_LSU_FLUSH_SRQ_FULL,Flush caused by SRQ full ##330E0 Flush caused by SRQ full #115,v,g,n,n,PM_LSU_LDF,LSU executed Floating Point load instruction ##C5090 LSU executed Floating Point load instruction #116,u,g,n,s,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full ##C30E7 The LMQ was full #117,v,g,n,n,PM_LSU_LMQ_LHR_MERGE,LMQ LHR merges ##C70E5 A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry. #118,v,g,n,s,PM_LSU_LMQ_S0_ALLOC,LMQ slot 0 allocated ##C30E6 The first entry in the LMQ was allocated. #119,v,g,n,n,PM_LSU_LMQ_S0_VALID,LMQ slot 0 valid ##C30E5 This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO #120,v,g,n,s,PM_LSU_LRQ_FULL_CYC,Cycles LRQ full ##110C2 The ISU sends this signal when the LRQ is full. #121,u,g,n,n,PM_DC_PREF_STREAM_ALLOC_BLK,D cache out of prefech streams ##C50C2 D cache out of prefech streams #122,u,g,n,n,PM_LSU_SRQ_EMPTY_CYC,Cycles SRQ empty ##00015 The Store Request Queue is empty #123,v,g,n,s,PM_LSU_SRQ_FULL_CYC,Cycles SRQ full ##110C3 The ISU sends this signal when the srq is full. #124,u,g,n,n,PM_LSU_SRQ_SYNC_CYC,SRQ sync duration ##830E5 This signal is asserted every cycle when a sync is in the SRQ. #125,v,g,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##130E0 LWSYNC held at dispatch #126,v,g,n,s,PM_MEM_LO_PRIO_PW_CMPL,Low priority partial-write completed ##737E6 Low priority partial-write completed #127,v,g,n,s,PM_MEM_LO_PRIO_WR_CMPL,Low priority write completed ##736E6 Low priority write completed #128,v,g,n,s,PM_MEM_PW_CMPL,Memory partial-write completed ##734E6 Memory partial-write completed #129,v,g,n,s,PM_MEM_PW_GATH,Memory partial-write gathered ##714C6 Memory partial-write gathered #130,v,g,n,s,PM_MEM_RQ_DISP_BUSY1to7,Memory read queue dispatched with 1-7 queues busy ##711C6 Memory read queue dispatched with 1-7 queues busy #131,v,g,n,s,PM_MEM_SPEC_RD_CANCEL,Speculative memory read canceled ##712C6 Speculative memory read canceled #132,v,g,n,s,PM_MEM_WQ_DISP_BUSY8to15,Memory write queue dispatched with 8-15 queues busy ##733E6 Memory write queue dispatched with 8-15 queues busy #133,v,g,n,s,PM_MEM_WQ_DISP_DCLAIM,Memory write queue dispatched due to dclaim/flush ##713C6 Memory write queue dispatched due to dclaim/flush #134,v,g,n,n,PM_MRK_CRU_FIN,Marked instruction CRU processing finished ##00005 The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete #135,v,g,n,n,PM_MRK_DATA_FROM_L25_MOD_CYC,Marked load latency from L2.5 modified ##C70A2 Marked load latency from L2.5 modified #136,v,g,n,n,PM_MRK_DATA_FROM_L275_MOD,Marked data loaded from L2.75 modified ##C7097 DL1 was reloaded with modified (M) data from the L2 of another MCM due to a marked demand load. #137,v,g,n,n,PM_MRK_DATA_FROM_L275_MOD_CYC,Marked load latency from L2.75 modified ##C70A3 Marked load latency from L2.75 modified #138,v,g,n,n,PM_MRK_DATA_FROM_L35_MOD_CYC,Marked load latency from L3.5 modified ##C70A6 Marked load latency from L3.5 modified #139,v,g,n,n,PM_MRK_DATA_FROM_L375_MOD,Marked data loaded from L3.75 modified ##C709E Marked data loaded from L3.75 modified #140,v,g,n,n,PM_MRK_DATA_FROM_L375_MOD_CYC,Marked load latency from L3.75 modified ##C70A7 Marked load latency from L3.75 modified #141,v,g,n,n,PM_MRK_DATA_FROM_LMEM_CYC,Marked load latency from local memory ##C70A0 Marked load latency from local memory #142,v,g,n,n,PM_MRK_DATA_FROM_RMEM,Marked data loaded from remote memory ##C7087 Marked data loaded from remote memory #143,v,g,n,n,PM_MRK_DATA_FROM_RMEM_CYC,Marked load latency from remote memory ##C70A1 Marked load latency from remote memory #144,v,g,n,n,PM_MRK_DSLB_MISS,Marked Data SLB misses ##C50C7 Marked Data SLB misses #145,v,g,n,n,PM_MRK_DTLB_MISS,Marked Data TLB misses ##C50C6 Marked Data TLB misses #146,v,g,n,n,PM_MRK_GRP_CMPL,Marked group completed ##00013 A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group. #147,v,g,n,n,PM_MRK_GRP_IC_MISS,Group experienced marked I cache miss ##12091 Group experienced marked I cache miss #148,v,g,n,n,PM_MRK_GRP_TIMEO,Marked group completion timeout ##0000B The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor #149,v,g,n,n,PM_MRK_L1_RELOAD_VALID,Marked L1 reload data source valid ##C70E4 The source information is valid and is for a marked load #150,v,g,n,n,PM_MRK_LSU0_FLUSH_LRQ,LSU0 marked LRQ flushes ##810C2 A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #151,u,g,n,n,PM_MRK_LSU0_FLUSH_SRQ,LSU0 marked SRQ flushes ##810C3 A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #152,v,g,n,n,PM_MRK_LSU0_FLUSH_UST,LSU0 marked unaligned store flushes ##810C1 A marked store was flushed from unit 0 because it was unaligned #153,v,g,n,n,PM_MRK_LSU0_FLUSH_ULD,LSU0 marked unaligned load flushes ##810C0 A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #154,v,g,n,n,PM_MRK_LSU1_FLUSH_LRQ,LSU1 marked LRQ flushes ##810C6 A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #155,u,g,n,n,PM_MRK_LSU1_FLUSH_SRQ,LSU1 marked SRQ flushes ##810C7 A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #156,v,g,n,n,PM_MRK_LSU1_FLUSH_ULD,LSU1 marked unaligned load flushes ##810C4 A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #157,u,g,n,n,PM_MRK_LSU1_FLUSH_UST,LSU1 marked unaligned store flushes ##810C5 A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary) #158,c,g,n,n,PM_MRK_LSU_FIN,Marked instruction LSU processing finished ##00014 One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete #159,v,g,n,n,PM_MRK_LSU_FLUSH_SRQ,Marked SRQ flushes ##81088 A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group. #160,v,g,n,n,PM_MRK_LSU_FLUSH_ULD,Marked unaligned load flushes ##81090 A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #161,u,g,n,n,PM_MRK_LSU_SRQ_INST_VALID,Marked instruction valid in SRQ ##C70E6 This signal is asserted every cycle when a marked request is resident in the Store Request Queue #162,v,g,n,n,PM_PMC3_OVERFLOW,PMC3 Overflow ##0000A PMC3 Overflow #163,v,g,n,n,PM_PTEG_FROM_L275_MOD,PTEG loaded from L2.75 modified ##83097 PTEG loaded from L2.75 modified #164,v,g,n,n,PM_PTEG_FROM_L375_MOD,PTEG loaded from L3.75 modified ##8309E PTEG loaded from L3.75 modified #165,v,g,n,n,PM_PTEG_FROM_RMEM,PTEG loaded from remote memory ##83087 PTEG loaded from remote memory #166,v,g,n,s,PM_SNOOP_PARTIAL_RTRY_QFULL,Snoop partial write retry due to partial-write queues full ##730E6 Snoop partial write retry due to partial-write queues full #167,v,g,n,s,PM_SNOOP_PW_RETRY_WQ_PWQ,Snoop partial-write retry due to collision with active write or partial-write queue ##717C6 Snoop partial-write retry due to collision with active write or partial-write queue #168,v,g,n,s,PM_SNOOP_RD_RETRY_WQ,Snoop read retry due to collision with active write queue ##715C6 Snoop read retry due to collision with active write queue #169,v,g,n,s,PM_SNOOP_WR_RETRY_QFULL,Snoop read retry due to read queue full ##710C6 Snoop read retry due to read queue full #170,v,g,n,s,PM_SNOOP_WR_RETRY_WQ,Snoop write/dclaim retry due to collision with active write queue ##716C6 Snoop write/dclaim retry due to collision with active write queue #171,v,g,n,n,PM_ST_MISS_L1,L1 D cache store misses ##C10C3 A store missed the dcache #172,v,g,n,n,PM_ST_REF_L1_LSU0,LSU0 L1 D cache store references ##C10C1 A store executed on unit 0 #173,v,g,n,n,PM_ST_REF_L1_LSU1,LSU1 L1 D cache store references ##C10C5 A store executed on unit 1 #174,v,g,n,n,PM_SUSPENDED,Suspended ##00000 Suspended #175,v,g,n,s,PM_CLB_EMPTY_CYC,Cycles CLB empty ##410C6 Cycles CLB completely empty #176,v,g,n,s,PM_THRD_L2MISS_BOTH_CYC,Cycles both threads in L2 misses ##41084,410C7 Cycles both threads in L2 misses #177,v,g,n,n,PM_THRD_PRIO_DIFF_0_CYC,Cycles no thread priority difference ##430E3 Cycles no thread priority difference #178,v,g,n,n,PM_THRD_PRIO_DIFF_1or2_CYC,Cycles thread priority difference is 1 or 2 ##430E4 Cycles thread priority difference is 1 or 2 #179,v,g,n,n,PM_THRD_PRIO_DIFF_3or4_CYC,Cycles thread priority difference is 3 or 4 ##430E5 Cycles thread priority difference is 3 or 4 #180,v,g,n,n,PM_THRD_PRIO_DIFF_5or6_CYC,Cycles thread priority difference is 5 or 6 ##430E6 Cycles thread priority difference is 5 or 6 #181,v,g,n,n,PM_THRD_PRIO_DIFF_minus1or2_CYC,Cycles thread priority difference is -1 or -2 ##430E2 Cycles thread priority difference is -1 or -2 #182,v,g,n,n,PM_THRD_PRIO_DIFF_minus3or4_CYC,Cycles thread priority difference is -3 or -4 ##430E1 Cycles thread priority difference is -3 or -4 #183,v,g,n,n,PM_THRD_PRIO_DIFF_minus5or6_CYC,Cycles thread priority difference is -5 or -6 ##430E0 Cycles thread priority difference is -5 or -6 #184,v,g,n,s,PM_THRD_SEL_OVER_CLB_EMPTY,Thread selection overides caused by CLB empty ##410C2 Thread selection overides caused by CLB empty #185,v,g,n,s,PM_THRD_SEL_OVER_GCT_IMBAL,Thread selection overides caused by GCT imbalance ##410C4 Thread selection overides caused by GCT imbalance #186,v,g,n,s,PM_THRD_SEL_OVER_ISU_HOLD,Thread selection overides caused by ISU holds ##410C5 Thread selection overides caused by ISU holds #187,v,g,n,s,PM_THRD_SEL_OVER_L2MISS,Thread selection overides caused by L2 misses ##410C3 Thread selection overides caused by L2 misses #188,v,g,n,s,PM_THRD_SEL_T0,Decode selected thread 0 ##410C0 Decode selected thread 0 #189,v,g,n,s,PM_THRD_SEL_T1,Decode selected thread 1 ##410C1 Decode selected thread 1 #190,v,g,n,s,PM_THRD_SMT_HANG,SMT hang detected ##330E7 SMT hang detected #191,v,g,n,n,PM_TLBIE_HELD,TLBIE held at dispatch ##130E4 TLBIE held at dispatch #192,v,g,n,n,PM_WORK_HELD,Work held ##0000C RAS Unit has signaled completion to stop and there are groups waiting to complete $$$$$$$$ { counter 5 } #0,v,g,n,n,PM_INST_CMPL,Instructions completed ##00009 Number of PPC instructions completed. $$$$$$$$ { counter 6 } #0,v,g,n,n,PM_RUN_CYC,Run cycles ##00005 Processor Cycles gated by the run latch