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/* $Id: event_set_p5.c,v 1.1 2003/02/16 21:08:54 mikpe Exp $
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* Performance counter event descriptions for Intel P5 and P5 MMX
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* processors, and Cyrix 6x86/MII/III processors.
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*
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* Copyright (C) 2003 Mikael Pettersson
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*
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* References
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* ----------
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* [IA32, Volume 3] "Intel Architecture Software Developer's Manual,
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* Volume 3: System Programming Guide". Intel document number 245472-009.
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* (at http://developer.intel.com/)
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*
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* [Cyrix 6x86MX] "Cyrix 6x86MX Processor".
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* [Cyrix MII] "Cyrix M II Data Book".
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* [Cyrix III] "Cyrix III Processor DataBook" Ver. 1.0, 1/25/00.
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* Note: This "Cyrix III" was code-named "Joshua", and it was apparently
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* cancelled by VIA due to disappointing performance.
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* (MII and III docs at http://www.viatech.com/)
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*/
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#include <stddef.h> /* for NULL */
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#include "libperfctr.h"
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#include "event_set.h"
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/*
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* Intel Pentium (P5) events.
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*/
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static const struct perfctr_event p5_events[] = {
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{ 0x00, 0x3, NULL, "DATA_READ",
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577717 |
"Number of memory data reads (internal data cache hit and "
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577717 |
"miss combined)." },
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{ 0x01, 0x3, NULL, "DATA_WRITE",
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577717 |
"Number of memory data writes (internal data cache hit and "
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577717 |
"miss combined), I/O is not included." },
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577717 |
{ 0x02, 0x3, NULL, "DATA_TLB_MISS",
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577717 |
"Number of misses to the data cache translation look-aside "
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577717 |
"buffer." },
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577717 |
{ 0x03, 0x3, NULL, "DATA_READ_MISS",
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577717 |
"Number of memory read accesses that miss the internal data "
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"cache whether or not the access is cacheable or noncacheable." },
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577717 |
{ 0x04, 0x3, NULL, "DATA_WRITE_MISS",
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"Number of memory write accesses that miss the internal data "
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"cache whether or not the access is cacheable or noncacheable." },
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577717 |
{ 0x05, 0x3, NULL, "WRITE_HIT_TO_M_OR_E_STATE_LINES",
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577717 |
"Number of write hits to exclusive or modified lines in the "
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"data cache." },
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{ 0x06, 0x3, NULL, "DATA_CACHE_LINES_WRITTEN_BACK",
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"Number of dirty lines (all) that are written back, regardless "
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"of the cause." },
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577717 |
{ 0x07, 0x3, NULL, "EXTERNAL_SNOOPS",
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577717 |
"Number of accepted external snoops whether they hit in the code "
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"cache or data cache or neither." },
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577717 |
{ 0x08, 0x3, NULL, "EXTERNAL_DATA_CACHE_SNOOP_HITS",
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577717 |
"Number of external snoops to the data cache." },
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577717 |
{ 0x09, 0x3, NULL, "MEMORY_ACCESSES_IN_BOTH_PIPES",
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577717 |
"Number of data memory reads or writes that are paired in both "
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577717 |
"pipes of the pipeline." },
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577717 |
{ 0x0A, 0x3, NULL, "BANK_CONFLICTS",
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577717 |
"Number of actual bank conflicts." },
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577717 |
{ 0x0B, 0x3, NULL, "MISALIGNED_DATA_MEMORY_OR_IO_REFERENCES",
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577717 |
"Number of memory or I/O reads or writes that are misaligned." },
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577717 |
{ 0x0C, 0x3, NULL, "CODE_READ",
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577717 |
"Number of instruction reads whether the read is cacheable or "
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"noncacheable." },
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577717 |
{ 0x0D, 0x3, NULL, "CODE_TLB_MISS",
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577717 |
"Number of instruction reads that miss the code TLB whether "
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577717 |
"the read is cacheable or noncacheable." },
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Packit |
577717 |
{ 0x0E, 0x3, NULL, "CODE_CACHE_MISS",
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577717 |
"Number of instruction reads that miss the internal code cache "
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577717 |
"whether the read is cacheable or noncacheable." },
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Packit |
577717 |
{ 0x0F, 0x3, NULL, "ANY_SEGMENT_REGISTER_LOADED",
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577717 |
"Number of writes into any segment register in real or protected "
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577717 |
"mode including the LDTR, GDTR, IDTR, and TR." },
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577717 |
/* 0x10: reserved */
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577717 |
/* 0x11: reserved */
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577717 |
{ 0x12, 0x3, NULL, "BRANCHES",
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577717 |
"Number of taken and not taken branches, including conditional "
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577717 |
"branches, jumps, calls, returns, software interrupts, and "
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"interrupt returns." },
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577717 |
{ 0x13, 0x3, NULL, "BTB_HITS",
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577717 |
"Number of BTB hits that occur." },
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577717 |
{ 0x14, 0x3, NULL, "TAKEN_BRANCH_OR_BTB_HIT",
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577717 |
"Number of taken branches or BTB hits that occur." },
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577717 |
{ 0x15, 0x3, NULL, "PIPELINE_FLUSHES",
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577717 |
"Number of pipeline flushes that occur." },
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Packit |
577717 |
{ 0x16, 0x3, NULL, "INSTRUCTIONS_EXECUTED",
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577717 |
"Number of instructions executed (up to two per clock)." },
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577717 |
{ 0x17, 0x3, NULL, "INSTRUCTIONS_EXECUTED_V_PIPE", /* XXX: was INSTRUCTIONS_EXECUTED_IN_V_PIPE */
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"Number of instructions executed in the V_pipe. It indicates "
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"the number of instructions that were paired." },
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577717 |
{ 0x18, 0x3, NULL, "BUS_CYCLE_DURATION",
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577717 |
"Number of clocks while a bus cycle is in progress." },
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Packit |
577717 |
{ 0x19, 0x3, NULL, "WRITE_BUFFER_FULL_STALL_DURATION",
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577717 |
"Number of clocks while the pipeline is stalled due to full "
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577717 |
"write buffers." },
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Packit |
577717 |
{ 0x1A, 0x3, NULL, "WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION",
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577717 |
"Number of clocks while the pipeline is stalled while waiting "
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577717 |
"for data memory reads." },
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Packit |
577717 |
{ 0x1B, 0x3, NULL, "STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE",
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Packit |
577717 |
"Number of stalls on writes to E- or M-state lines." },
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Packit |
577717 |
{ 0x1C, 0x3, NULL, "LOCKED_BUS_CYCLE",
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Packit |
577717 |
"Number of locked bus cycles that occur as the result of "
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Packit |
577717 |
"LOCK prefix or LOCK instruction, page-table updates, and "
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Packit |
577717 |
"descriptor table updates." },
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Packit |
577717 |
{ 0x1D, 0x3, NULL, "IO_READ_OR_WRITE_CYCLE",
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Packit |
577717 |
"Number of bus cycles directed to I/O space." },
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Packit |
577717 |
{ 0x1E, 0x3, NULL, "NONCACHEABLE_MEMORY_READS",
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Packit |
577717 |
"Number of noncacheable instruction or data memory read bus cycles." },
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Packit |
577717 |
{ 0x1F, 0x3, NULL, "PIPELINE_AGI_STALLS",
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Packit |
577717 |
"Number of adress generation interlock (AGI) stalls." },
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Packit |
577717 |
/* 0x20: reserved */
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577717 |
/* 0x21: reserved */
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577717 |
{ 0x22, 0x3, NULL, "FLOPS",
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Packit |
577717 |
"Number of floating-point operations that occur." },
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Packit |
577717 |
{ 0x23, 0x3, NULL, "BREAKPOINT_MATCH_ON_DR0_REGISTER",
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Packit |
577717 |
"Number of matches on DR0 breakpoint." },
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Packit |
577717 |
{ 0x24, 0x3, NULL, "BREAKPOINT_MATCH_ON_DR1_REGISTER",
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Packit |
577717 |
"Number of matches on DR1 breakpoint." },
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Packit |
577717 |
{ 0x25, 0x3, NULL, "BREAKPOINT_MATCH_ON_DR2_REGISTER",
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Packit |
577717 |
"Number of matches on DR2 breakpoint." },
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Packit |
577717 |
{ 0x26, 0x3, NULL, "BREAKPOINT_MATCH_ON_DR3_REGISTER",
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Packit |
577717 |
"Number of matches on DR3 breakpoint." },
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Packit |
577717 |
{ 0x27, 0x3, NULL, "HARDWARE_INTERRUPTS",
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Packit |
577717 |
"Number of taken INTR and NMI interrupts." },
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Packit |
577717 |
{ 0x28, 0x3, NULL, "DATA_READ_OR_WRITE",
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Packit |
577717 |
"Number of memory data reads and/or writes (internal data cache "
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Packit |
577717 |
"hit and miss combined)." },
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Packit |
577717 |
{ 0x29, 0x3, NULL, "DATA_READ_MISS_OR_WRITE_MISS",
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Packit |
577717 |
"Number of memory read and/or write accesses that miss the "
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577717 |
"internal data cache whether or not the acceess is cacheable "
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"or noncacheable." },
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};
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const struct perfctr_event_set perfctr_p5_event_set = {
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.cpu_type = PERFCTR_X86_INTEL_P5,
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.event_prefix = "P5_",
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.include = NULL,
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.nevents = ARRAY_SIZE(p5_events),
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.events = p5_events,
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577717 |
};
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577717 |
/*
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577717 |
* Intel Pentium MMX (P5MMX) events.
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577717 |
*/
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static const struct perfctr_event p5mmx_and_mii_events[] = {
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577717 |
{ 0x2B, 0x1, NULL, "MMX_INSTRUCTIONS_EXECUTED_U_PIPE",
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577717 |
"Number of MMX instructions executed in the U-pipe." },
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577717 |
{ 0x2B, 0x2, NULL, "MMX_INSTRUCTIONS_EXECUTED_V_PIPE",
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Packit |
577717 |
"Number of MMX instructions executed in the V-pipe." },
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Packit |
577717 |
{ 0x2D, 0x1, NULL, "EMMS_INSTRUCTIONS_EXECUTED",
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Packit |
577717 |
"Number of EMMS instructions executed." },
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Packit |
577717 |
{ 0x2D, 0x2, NULL, "TRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS",
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Packit |
577717 |
"Number of transitions between MMX and floating-point instructions "
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577717 |
"or vice versa." },
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577717 |
{ 0x2F, 0x1, NULL, "SATURATING_MMX_INSTRUCTIONS_EXECUTED",
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Packit |
577717 |
"Number of saturating MMX instructions executed, independently of "
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Packit |
577717 |
"whether they actually saturated." },
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Packit |
577717 |
{ 0x2F, 0x2, NULL, "SATURATIONS_PERFORMED",
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Packit |
577717 |
"Number of MMX instructions that used saturating arithmetic and "
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Packit |
577717 |
"that at least one of its results actually saturated." },
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Packit |
577717 |
{ 0x31, 0x1, NULL, "MMX_INSTRUCTION_DATA_READS",
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Packit |
577717 |
"Number of MMX instruction data reads." },
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Packit |
577717 |
{ 0x32, 0x2, NULL, "TAKEN_BRANCHES",
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Packit |
577717 |
"Number of taken branches." },
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Packit |
577717 |
{ 0x37, 0x1, NULL, "MISPREDICTED_OR_UNPREDICTED_RETURNS",
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Packit |
577717 |
"Number of returns predicted incorrectly or not predicted at all." },
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Packit |
577717 |
{ 0x37, 0x2, NULL, "PREDICTED_RETURNS",
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Packit |
577717 |
"Number of predicted returns (whether they are predicted correctly "
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Packit |
577717 |
"and incorrectly)." },
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Packit |
577717 |
{ 0x38, 0x1, NULL, "MMX_MULTIPLY_UNIT_INTERLOCK",
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Packit |
577717 |
"Number of clocks the pipe is stalled since the destination of "
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Packit |
577717 |
"previous MMX instruction is not ready yet." },
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Packit |
577717 |
{ 0x38, 0x2, NULL, "MOVD_MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION",
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Packit |
577717 |
"Number of clocks a MOVD/MOVQ instruction store is stalled in D2 "
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Packit |
577717 |
"stage due to a previous MMX operation with a destination to be "
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Packit |
577717 |
"used in the store instruction." },
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Packit |
577717 |
{ 0x39, 0x1, NULL, "RETURNS",
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Packit |
577717 |
"Number of returns executed." },
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Packit |
577717 |
{ 0x3A, 0x1, NULL, "BTB_FALSE_ENTRIES",
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Packit |
577717 |
"Number of false entries in the Branch Target Buffer." },
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Packit |
577717 |
{ 0x3A, 0x2, NULL, "BTB_MISS_PREDICTION_ON_NOT_TAKEN_BRANCH",
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Packit |
577717 |
"Number of times the BTB predicted a not-taken branch as taken." },
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Packit |
577717 |
{ 0x3B, 0x1, NULL, "FULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS",
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Packit |
577717 |
"Number of clocks while the pipeline is stalled due to full write "
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Packit |
577717 |
"buffers while executing MMX instructions." },
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Packit |
577717 |
{ 0x3B, 0x2, NULL, "STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE",
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|
Packit |
577717 |
"Number of clocks during stalls on MMX instructions writing "
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Packit |
577717 |
"to E- or M-state lines." },
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Packit |
577717 |
};
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Packit |
577717 |
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577717 |
static const struct perfctr_event_set p5mmx_and_mii_event_set = {
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Packit |
577717 |
.cpu_type = PERFCTR_X86_INTEL_P5MMX,
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Packit |
577717 |
.event_prefix = "P5MMX_",
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Packit |
577717 |
.include = &perfctr_p5_event_set,
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Packit |
577717 |
.nevents = ARRAY_SIZE(p5mmx_and_mii_events),
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Packit |
577717 |
.events = p5mmx_and_mii_events,
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Packit |
577717 |
};
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Packit |
577717 |
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577717 |
static const struct perfctr_event p5mmx_events[] = {
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Packit |
577717 |
{ 0x2A, 0x1, NULL, "BUS_OWNERSHIP_LATENCY",
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|
Packit |
577717 |
"The time from LRM bus ownership request to bus ownership granted." },
|
|
Packit |
577717 |
{ 0x2A, 0x2, NULL, "BUS_OWNERSHIP_TRANSFERS",
|
|
Packit |
577717 |
"The number of bus ownership transfers." },
|
|
Packit |
577717 |
{ 0x2C, 0x1, NULL, "CACHE_M_STATE_LINE_SHARING",
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|
Packit |
577717 |
"Number of times a processor identified a hit to a modified line "
|
|
Packit |
577717 |
"due to a memory access in the other processor." },
|
|
Packit |
577717 |
{ 0x2C, 0x2, NULL, "CACHE_LINE_SHARING",
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|
Packit |
577717 |
"Number of shared data lines in the L1 cache." },
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|
Packit |
577717 |
{ 0x2E, 0x1, NULL, "BUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY",
|
|
Packit |
577717 |
"Number of clocks the bus is busy due to the processor's own activity." },
|
|
Packit |
577717 |
{ 0x2E, 0x2, NULL, "WRITES_TO_NONCACHEABLE_MEMORY",
|
|
Packit |
577717 |
"Number of write accesses to noncacheable memory." },
|
|
Packit |
577717 |
{ 0x30, 0x1, NULL, "NUMBER_OF_CYCLES_NOT_IN_HALT_STATE",
|
|
Packit |
577717 |
"Number of cycles the processor is not idle due to HLT instruction." },
|
|
Packit |
577717 |
{ 0x30, 0x2, NULL, "DATA_CACHE_TLB_MISS_STALL_DURATION",
|
|
Packit |
577717 |
"Number of clocks the pipeline is stalled due to a data cache "
|
|
Packit |
577717 |
"translation look-aside buffer (TLB) miss." },
|
|
Packit |
577717 |
{ 0x31, 0x2, NULL, "MMX_INSTRUCTION_DATA_READ_MISSES",
|
|
Packit |
577717 |
"Number of MMX instruction data read misses." },
|
|
Packit |
577717 |
{ 0x32, 0x1, NULL, "FLOATING_POINT_STALLS_DURATION",
|
|
Packit |
577717 |
"Number of clocks while pipe is stalled due to a floating-point freeze." },
|
|
Packit |
577717 |
{ 0x33, 0x1, NULL, "D1_STARVATION_AND_FIFO_IS_EMPTY",
|
|
Packit |
577717 |
"Number of times D1 stage cannot issue ANY instructions since the "
|
|
Packit |
577717 |
"FIFO buffer is empty." },
|
|
Packit |
577717 |
{ 0x33, 0x2, NULL, "D1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO",
|
|
Packit |
577717 |
"Number of times the D1 stage issues just a single instruction since "
|
|
Packit |
577717 |
"the FIFO buffer had just one instruction ready." },
|
|
Packit |
577717 |
{ 0x34, 0x1, NULL, "MMX_INSTRUCTION_DATA_WRITES",
|
|
Packit |
577717 |
"Number of data writes caused by MMX instructions." },
|
|
Packit |
577717 |
{ 0x34, 0x2, NULL, "MMX_INSTRUCTION_DATA_WRITE_MISSES",
|
|
Packit |
577717 |
"Number of data write misses caused by MMX instructions." },
|
|
Packit |
577717 |
{ 0x35, 0x1, NULL, "PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS",
|
|
Packit |
577717 |
"Number of pipeline flushes due to wrong branch prediction resolved "
|
|
Packit |
577717 |
"in either the E-stage or the WB-stage." },
|
|
Packit |
577717 |
{ 0x35, 0x2, NULL, "PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS_RESOLVED_IN_WB_STAGE",
|
|
Packit |
577717 |
"Number of pipeline flushes due to wrong branch prediction resolved "
|
|
Packit |
577717 |
"in the WB-stage." },
|
|
Packit |
577717 |
{ 0x36, 0x1, NULL, "MISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS",
|
|
Packit |
577717 |
"Number of misaligned data memory references when executing MMX "
|
|
Packit |
577717 |
"instructions." },
|
|
Packit |
577717 |
{ 0x36, 0x2, NULL, "PIPELINE_ISTALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS",
|
|
Packit |
577717 |
"Number of clocks during pipeline stalls caused by waits from MMX "
|
|
Packit |
577717 |
"instructions data memory reads." },
|
|
Packit |
577717 |
/* 0x39, counter 1: reserved */
|
|
Packit |
577717 |
};
|
|
Packit |
577717 |
|
|
Packit |
577717 |
const struct perfctr_event_set perfctr_p5mmx_event_set = {
|
|
Packit |
577717 |
.cpu_type = PERFCTR_X86_INTEL_P5MMX,
|
|
Packit |
577717 |
.event_prefix = "P5MMX_",
|
|
Packit |
577717 |
.include = &p5mmx_and_mii_event_set,
|
|
Packit |
577717 |
.nevents = ARRAY_SIZE(p5mmx_events),
|
|
Packit |
577717 |
.events = p5mmx_events,
|
|
Packit |
577717 |
};
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/*
|
|
Packit |
577717 |
* Cyrix 6x86MX, MII, and III events.
|
|
Packit |
577717 |
*/
|
|
Packit |
577717 |
|
|
Packit |
577717 |
static const struct perfctr_event mii_events[] = {
|
|
Packit |
577717 |
{ 0x039, 0x2, NULL, "RSB_OVERFLOWS" },
|
|
Packit |
577717 |
/* NOTE: The manuals list the following events as having codes 40-48.
|
|
Packit |
577717 |
However, the 7-bit event code is actually split in the CESR, using
|
|
Packit |
577717 |
bits 0-5 and 10, and similarly for the high half of the CESR.
|
|
Packit |
577717 |
Since the driver also parses the other fields (bits 6-9) in a user's
|
|
Packit |
577717 |
evntsel, the events are listed here with their actual in-CESR values. */
|
|
Packit |
577717 |
{ 0x400, 0x3, NULL, "L2_TLB_MISSES" },
|
|
Packit |
577717 |
{ 0x401, 0x3, NULL, "L1_TLB_DATA_MISS" },
|
|
Packit |
577717 |
{ 0x402, 0x3, NULL, "L1_TLB_CODE_MISS" },
|
|
Packit |
577717 |
{ 0x403, 0x3, NULL, "L1_TLB_MISS" },
|
|
Packit |
577717 |
{ 0x404, 0x3, NULL, "TLB_FLUSHES" },
|
|
Packit |
577717 |
{ 0x405, 0x3, NULL, "TLB_PAGE_INVALIDATES" },
|
|
Packit |
577717 |
{ 0x406, 0x3, NULL, "TLB_PAGE_INVALIDATES_THAT_HIT" },
|
|
Packit |
577717 |
{ 0x408, 0x3, NULL, "INSTRUCTIONS_DECODED" },
|
|
Packit |
577717 |
};
|
|
Packit |
577717 |
|
|
Packit |
577717 |
const struct perfctr_event_set perfctr_mii_event_set = {
|
|
Packit |
577717 |
.cpu_type = PERFCTR_X86_CYRIX_MII,
|
|
Packit |
577717 |
.event_prefix = "MII_",
|
|
Packit |
577717 |
.include = &p5mmx_and_mii_event_set,
|
|
Packit |
577717 |
.nevents = ARRAY_SIZE(mii_events),
|
|
Packit |
577717 |
.events = mii_events,
|
|
Packit |
577717 |
};
|