/*

 * pfmlib_montecito.c : support for the Dual-Core Itanium2 processor

 *

 * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.

 * Contributed by Stephane Eranian <eranian@hpl.hp.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#include <sys/types.h>

#include <ctype.h>

#include <string.h>

#include <stdio.h>

#include <stdlib.h>

/* public headers */

#include <perfmon/pfmlib_montecito.h>

/* private headers */

#include "pfmlib_priv.h"		/* library private */

#include "pfmlib_priv_ia64.h"		/* architecture private */

#include "pfmlib_montecito_priv.h"	/* PMU private */

#include "montecito_events.h"		/* PMU private */

#define is_ear(i)	event_is_ear(montecito_pe+(i))

#define is_ear_tlb(i)	event_is_ear_tlb(montecito_pe+(i))

#define is_ear_alat(i)	event_is_ear_alat(montecito_pe+(i))

#define is_ear_cache(i)	event_is_ear_cache(montecito_pe+(i))

#define is_iear(i)	event_is_iear(montecito_pe+(i))

#define is_dear(i)	event_is_dear(montecito_pe+(i))

#define is_etb(i)	event_is_etb(montecito_pe+(i))

#define has_opcm(i)	event_opcm_ok(montecito_pe+(i))

#define has_iarr(i)	event_iarr_ok(montecito_pe+(i))

#define has_darr(i)	event_darr_ok(montecito_pe+(i))

#define has_all(i)	event_all_ok(montecito_pe+(i))

#define has_mesi(i)	event_mesi_ok(montecito_pe+(i))

#define evt_use_opcm(e)		((e)->pfp_mont_opcm1.opcm_used != 0 || (e)->pfp_mont_opcm2.opcm_used !=0)

#define evt_use_irange(e)	((e)->pfp_mont_irange.rr_used)

#define evt_use_drange(e)	((e)->pfp_mont_drange.rr_used)

#define evt_grp(e)	(int)montecito_pe[e].pme_qualifiers.pme_qual.pme_group

#define evt_set(e)	(int)montecito_pe[e].pme_qualifiers.pme_qual.pme_set

#define evt_umask(e)	montecito_pe[e].pme_umask

#define evt_type(e)	(int)montecito_pe[e].pme_type

#define evt_caf(e)	(int)montecito_pe[e].pme_caf

#define FINE_MODE_BOUNDARY_BITS	16

#define FINE_MODE_MASK		~((1U<

/* let's define some handy shortcuts! */

#define pmc_plm		pmc_mont_counter_reg.pmc_plm

#define pmc_ev		pmc_mont_counter_reg.pmc_ev

#define pmc_oi		pmc_mont_counter_reg.pmc_oi

#define pmc_pm		pmc_mont_counter_reg.pmc_pm

#define pmc_es		pmc_mont_counter_reg.pmc_es

#define pmc_umask	pmc_mont_counter_reg.pmc_umask

#define pmc_thres	pmc_mont_counter_reg.pmc_thres

#define pmc_all		pmc_mont_counter_reg.pmc_all

#define pmc_ism		pmc_mont_counter_reg.pmc_ism

#define pmc_m		pmc_mont_counter_reg.pmc_m

#define pmc_e		pmc_mont_counter_reg.pmc_e

#define pmc_s		pmc_mont_counter_reg.pmc_s

#define pmc_i		pmc_mont_counter_reg.pmc_i

#define UNEXISTING_SET	0xff

static char * pfm_mont_get_event_name(unsigned int i);

/*

 * Description of the PMC register mappings use by

 * this module (as reported in pfmlib_reg_t.reg_num):

 *

 * 0 -> PMC0

 * 1 -> PMC1

 * n -> PMCn

 *

 * The following are in the model specific rr_br[]:

 * IBR0 -> 0

 * IBR1 -> 1

 * ...

 * IBR7 -> 7

 * DBR0 -> 0

 * DBR1 -> 1

 * ...

 * DBR7 -> 7

 *

 * We do not use a mapping table, instead we make up the

 * values on the fly given the base.

 */

static int

pfm_mont_detect(void)

{

	int tmp;

	int ret = PFMLIB_ERR_NOTSUPP;

	tmp = pfm_ia64_get_cpu_family();

	if (tmp == 0x20) {

		ret = PFMLIB_SUCCESS;

	}

	return ret;

}

/*

 * Check the event for incompatibilities. This is useful

 * for L1D and L2D related events. Due to wire limitations,

 * some caches events are separated into sets. There

 * are 6 sets for the L1D cache group and 8 sets for L2D group.

 * It is NOT possible to simultaneously measure events from

 * differents sets for L1D. For instance, you cannot

 * measure events from set0 and set1 in L1D cache group. The L2D

 * group allows up to two different sets to be active at the same

 * time. The first set is selected by the event in PMC4 and the second

 * set by the event in PMC6. Once the set is selected for PMC4,

 * the same set is locked for PMC5 and PMC8. Similarly, once the

 * set is selected for PMC6, the same set is locked for PMC7 and 

 * PMC9.

 *

 * This function verifies that only one set of L1D is selected

 * and that no more than 2 sets are selected for L2D

 */

static int

check_cross_groups(pfmlib_input_param_t *inp, unsigned int *l1d_event, 

		unsigned long *l2d_set1_mask, unsigned long *l2d_set2_mask)

{

	int g, s, s1, s2;

	unsigned int cnt = inp->pfp_event_count;

	pfmlib_event_t *e = inp->pfp_events;

	unsigned int i, j;

	unsigned long l2d_mask1 = 0, l2d_mask2 = 0;

	unsigned int l1d_event_idx = UNEXISTING_SET;

	/*

	 * Let check the L1D constraint first

	 *

	 * There is no umask restriction for this group

	 */

	for (i=0; i < cnt; i++) {

		g = evt_grp(e[i].event);

		s = evt_set(e[i].event);

		if (g != PFMLIB_MONT_EVT_L1D_CACHE_GRP) continue;

		DPRINT("i=%u g=%d s=%d\n", i, g, s);

		l1d_event_idx = i;

		for (j=i+1; j < cnt; j++) {

			if (evt_grp(e[j].event) != g) continue;

			/*

			 * if there is another event from the same group

			 * but with a different set, then we return an error

			 */

			if (evt_set(e[j].event) != s) return PFMLIB_ERR_EVTSET;

		}

	}

	/*

	 * Check that we have only up to two distinct 

	 * sets for L2D

	 */

	s1 = s2 = -1;

	for (i=0; i < cnt; i++) {

		g = evt_grp(e[i].event);

		if (g != PFMLIB_MONT_EVT_L2D_CACHE_GRP) continue;

		s = evt_set(e[i].event); 

		/*

		 * we have seen this set before, continue

		 */

		if (s1 == s) {

			l2d_mask1 |= 1UL << i;

			continue;

		}

		if (s2 == s) {

			l2d_mask2 |= 1UL << i;

			continue;

		}

		/*

		 * record first of second set seen

		 */

		if (s1 == -1) {

			s1 = s;

			l2d_mask1 |= 1UL << i;

		} else if (s2 == -1) {

			s2 = s;

			l2d_mask2 |= 1UL << i;

		} else {

			/* 

			 * found a third set, that's not possible

			 */

			return PFMLIB_ERR_EVTSET;

		}

	}

	*l1d_event     = l1d_event_idx;

	*l2d_set1_mask = l2d_mask1;

	*l2d_set2_mask = l2d_mask2;

	return PFMLIB_SUCCESS;

}

/*

 * Certain prefetch events must be treated specially when instruction range restriction

 * is used because they can only be constrained by IBRP1 in fine-mode. Other events

 * will use IBRP0 if tagged as a demand fetch OR IBPR1 if tagged as a prefetch match.

 *

 * Events which can be qualified by the two pairs depending on their tag:

 * 	- ISB_BUNPAIRS_IN

 * 	- L1I_FETCH_RAB_HIT

 *	- L1I_FETCH_ISB_HIT

 * 	- L1I_FILLS

 *

 * This function returns the number of qualifying prefetch events found

 */

static int prefetch_events[]={

	PME_MONT_L1I_PREFETCHES,

	PME_MONT_L1I_STRM_PREFETCHES,

	PME_MONT_L2I_PREFETCHES

};

#define NPREFETCH_EVENTS	sizeof(prefetch_events)/sizeof(int)

static int prefetch_dual_events[]=

{

 PME_MONT_ISB_BUNPAIRS_IN,

 PME_MONT_L1I_FETCH_RAB_HIT,

 PME_MONT_L1I_FETCH_ISB_HIT,

 PME_MONT_L1I_FILLS

};

#define NPREFETCH_DUAL_EVENTS	sizeof(prefetch_dual_events)/sizeof(int)

/*

 * prefetch events must use IBRP1, unless they are dual and the user specified

 * PFMLIB_MONT_IRR_DEMAND_FETCH in rr_flags

 */

static int

check_prefetch_events(pfmlib_input_param_t *inp, pfmlib_mont_input_rr_t *irr, unsigned int *count, int *base_idx, int *dup)

{

	int code;

	int prefetch_codes[NPREFETCH_EVENTS];

	int prefetch_dual_codes[NPREFETCH_DUAL_EVENTS];

	unsigned int i, j;

	int c, flags;

	int found = 0, found_ibrp0 = 0, found_ibrp1 = 0;

	flags = irr->rr_flags & (PFMLIB_MONT_IRR_DEMAND_FETCH|PFMLIB_MONT_IRR_PREFETCH_MATCH);

	for(i=0; i < NPREFETCH_EVENTS; i++) {

		pfm_get_event_code(prefetch_events[i], &code);

		prefetch_codes[i] = code;

	}

	for(i=0; i < NPREFETCH_DUAL_EVENTS; i++) {

		pfm_get_event_code(prefetch_dual_events[i], &code);

		prefetch_dual_codes[i] = code;

	}

	for(i=0; i < inp->pfp_event_count; i++) {

		pfm_get_event_code(inp->pfp_events[i].event, &c);

		for(j=0; j < NPREFETCH_EVENTS; j++) {

			if (c == prefetch_codes[j]) {

				found++;

				found_ibrp1++;

			}

		}

		/*

		 * for the dual events, users must specify one or both of the

		 * PFMLIB_MONT_IRR_DEMAND_FETCH or PFMLIB_MONT_IRR_PREFETCH_MATCH

		 */

		for(j=0; j < NPREFETCH_DUAL_EVENTS; j++) {

			if (c == prefetch_dual_codes[j]) {

				found++;

				if (flags == 0)

					return PFMLIB_ERR_IRRFLAGS;

				if (flags & PFMLIB_MONT_IRR_DEMAND_FETCH)

					found_ibrp0++;

				if (flags & PFMLIB_MONT_IRR_PREFETCH_MATCH)

					found_ibrp1++;

			}

		}

	}

	*count =  found;

	*dup   = 0;

	/*

	 * if both found_ibrp0 and found_ibrp1 > 0, then we need to duplicate

	 * the range in ibrp0 to ibrp1.

	 */

	if (found) {

		*base_idx = found_ibrp0 ? 0 : 2;

		if (found_ibrp1 && found_ibrp0)

			*dup = 1;

	}

	return 0;

}

/*

 * look for CPU_OP_CYCLES_QUAL

 * Return:

 * 	1 if found

 * 	0 otherwise

 */

static int

has_cpu_cycles_qual(pfmlib_input_param_t *inp)

{

	unsigned int i;

	int code, c;

	pfm_get_event_code(PME_MONT_CPU_OP_CYCLES_QUAL, &code);

	for(i=0; i < inp->pfp_event_count; i++) {

		pfm_get_event_code(inp->pfp_events[i].event, &c);

		if (c == code)

			return 1;

	}

	return 0;

}

/*

 * IA64_INST_RETIRED (and subevents) is the only event which can be measured on all

 * 4 IBR when non-fine mode is not possible.

 *

 * This function returns:

 * 	- the number of events match the IA64_INST_RETIRED code

 * 	- in retired_mask to bottom 4 bits indicates which of the 4 INST_RETIRED event

 * 	is present

 */

static unsigned int

check_inst_retired_events(pfmlib_input_param_t *inp, unsigned long *retired_mask)

{

	int code;

	int c;

	unsigned int i, count, found = 0;

	unsigned long umask, mask;

	pfm_get_event_code(PME_MONT_IA64_INST_RETIRED, &code);

	count = inp->pfp_event_count;

	mask  = 0;

	for(i=0; i < count; i++) {

		pfm_get_event_code(inp->pfp_events[i].event, &c);

		if (c == code)  {

			pfm_mont_get_event_umask(inp->pfp_events[i].event, &umask);

			switch(umask) {

				case 0: mask |= 1;

					break;

				case 1: mask |= 2;

					break;

				case 2: mask |= 4;

					break;

				case 3: mask |= 8;

					break;

			}

			found++;

		}

	}

	if (retired_mask) *retired_mask = mask;

	return found;

}

static int

check_fine_mode_possible(pfmlib_mont_input_rr_t *rr, int n)

{

	pfmlib_mont_input_rr_desc_t *lim = rr->rr_limits;

	int i;

	for(i=0; i < n; i++) {

		if ((lim[i].rr_start & FINE_MODE_MASK) != (lim[i].rr_end & FINE_MODE_MASK))

			return 0;

	}

	return 1;

}

/*

 * mode = 0 -> check code (enforce bundle alignment)

 * mode = 1 -> check data

 */

static int

check_intervals(pfmlib_mont_input_rr_t *irr, int mode, unsigned int *n_intervals)

{

	unsigned int i;

	pfmlib_mont_input_rr_desc_t *lim = irr->rr_limits;

	for(i=0; i < 4; i++) {

		/* end marker */

		if (lim[i].rr_start == 0 && lim[i].rr_end == 0) break;

		/* invalid entry */

		if (lim[i].rr_start >= lim[i].rr_end) return PFMLIB_ERR_IRRINVAL;

		if (mode == 0 && (lim[i].rr_start & 0xf || lim[i].rr_end & 0xf))

			return PFMLIB_ERR_IRRALIGN;

	}

	*n_intervals = i;

	return PFMLIB_SUCCESS;

}

/*

 * It is not possible to measure more than one of the

 * L2D_OZQ_CANCELS0, L2D_OZQ_CANCELS1 at the same time.

 */

static int cancel_events[]=

{

	PME_MONT_L2D_OZQ_CANCELS0_ACQ,

	PME_MONT_L2D_OZQ_CANCELS1_ANY

};

#define NCANCEL_EVENTS	sizeof(cancel_events)/sizeof(int)

static int

check_cancel_events(pfmlib_input_param_t *inp)

{

	unsigned int i, j, count;

	int code;

	int cancel_codes[NCANCEL_EVENTS];

	int idx = -1;

	for(i=0; i < NCANCEL_EVENTS; i++) {

		pfm_get_event_code(cancel_events[i], &code);

		cancel_codes[i] = code;

	}

	count = inp->pfp_event_count;

	for(i=0; i < count; i++) {

		for (j=0; j < NCANCEL_EVENTS; j++) {

			pfm_get_event_code(inp->pfp_events[i].event, &code);

			if (code == cancel_codes[j]) {

				if (idx != -1) {

					return PFMLIB_ERR_INVAL;

				}

				idx = inp->pfp_events[i].event;

			}

		}

	}

	return PFMLIB_SUCCESS;

}

/*

 * Automatically dispatch events to corresponding counters following constraints.

 */

static unsigned int l2d_set1_cnts[]={ 4, 5, 8 };

static unsigned int l2d_set2_cnts[]={ 6, 7, 9 };

static int

pfm_mont_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp)

{

	pfmlib_mont_input_param_t *param = mod_in;

	pfm_mont_pmc_reg_t reg;

	pfmlib_event_t *e;

	pfmlib_reg_t *pc, *pd;

	pfmlib_regmask_t avail_cntrs, impl_cntrs;

	unsigned int i,j, k, max_cnt;

	unsigned int assign[PMU_MONT_NUM_COUNTERS];

	unsigned int m, cnt;

	unsigned int l1d_set;

	unsigned long l2d_set1_mask, l2d_set2_mask, evt_mask, mesi;

	unsigned long not_assigned_events, cnt_mask;

	int l2d_set1_p, l2d_set2_p;

	int ret;

	e      = inp->pfp_events;

	pc     = outp->pfp_pmcs;

	pd     = outp->pfp_pmds;

	cnt    = inp->pfp_event_count;

	if (PFMLIB_DEBUG())

		for (m=0; m < cnt; m++) {

			DPRINT("ev[%d]=%s counters=0x%lx\n", m, montecito_pe[e[m].event].pme_name,

				montecito_pe[e[m].event].pme_counters);

		}

	if (cnt > PMU_MONT_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY;

	l1d_set = UNEXISTING_SET;

	ret = check_cross_groups(inp, &l1d_set, &l2d_set1_mask, &l2d_set2_mask);

	if (ret != PFMLIB_SUCCESS) return ret;

	ret = check_cancel_events(inp);

	if (ret != PFMLIB_SUCCESS) return ret;

	/*

	 * at this point, we know that:

	 * 	- we have at most 1 L1D set

	 * 	- we have at most 2 L2D sets

	 * 	- cancel events are compatible

	 */

	DPRINT("l1d_set=%u l2d_set1_mask=0x%lx l2d_set2_mask=0x%lx\n", l1d_set, l2d_set1_mask, l2d_set2_mask);

	/*

	 * first, place L1D cache event in PMC5

	 *

	 * this is the strongest constraint

	 */

	pfm_get_impl_counters(&impl_cntrs);

	pfm_regmask_andnot(&avail_cntrs, &impl_cntrs, &inp->pfp_unavail_pmcs);

	not_assigned_events = 0;

	DPRINT("avail_cntrs=0x%lx\n", avail_cntrs.bits[0]);

	/*

	 * we do not check ALL_THRD here because at least

	 * one event has to be in PMC5 for this group

	 */

	if (l1d_set != UNEXISTING_SET) {

		if (!pfm_regmask_isset(&avail_cntrs, 5))

			return PFMLIB_ERR_NOASSIGN;

		assign[l1d_set] = 5;

		pfm_regmask_clr(&avail_cntrs, 5);

	}

	l2d_set1_p = l2d_set2_p = 0;

	/*

	 * assign L2D set1 and set2 counters

	 */

	for (i=0; i < cnt ; i++) {

			evt_mask = 1UL << i;

			/*

			 * place l2d set1 events. First 3 go to designated

			 * counters, the rest is placed elsewhere in the final

			 * pass

			 */

			if (l2d_set1_p < 3 && (l2d_set1_mask & evt_mask)) {

				assign[i] = l2d_set1_cnts[l2d_set1_p];

				if (!pfm_regmask_isset(&avail_cntrs, assign[i]))

					return PFMLIB_ERR_NOASSIGN;

				pfm_regmask_clr(&avail_cntrs, assign[i]);

				l2d_set1_p++;

				continue;

			}

			/*

			 * same as above but for l2d set2

			 */

			if (l2d_set2_p  < 3 && (l2d_set2_mask & evt_mask)) {

				assign[i] = l2d_set2_cnts[l2d_set2_p];

				if (!pfm_regmask_isset(&avail_cntrs, assign[i]))

					return PFMLIB_ERR_NOASSIGN;

				pfm_regmask_clr(&avail_cntrs, assign[i]);

				l2d_set2_p++;

				continue;

			}

			/*

			 * if not l2d nor l1d, then defer placement until final pass

			 */

			if (i != l1d_set)

				not_assigned_events |= evt_mask;

			DPRINT("phase 1: i=%u avail_cntrs=0x%lx l2d_set1_p=%d l2d_set2_p=%d not_assigned=0x%lx\n", 

				i,

				avail_cntrs.bits[0],

				l2d_set1_p,

				l2d_set2_p,

				not_assigned_events);

	}

	/*

	 * assign BUS_* ER_* events (work only in PMC4-PMC9)

	 */

	evt_mask = not_assigned_events;

	for (i=0; evt_mask ; i++, evt_mask >>=1) {

		if ((evt_mask & 0x1) == 0)

			continue;

		cnt_mask = montecito_pe[e[i].event].pme_counters;

		/*

		 * only interested in events with restricted set of counters

		 */

		if (cnt_mask == 0xfff0)

			continue;

		for(j=0; cnt_mask; j++, cnt_mask >>=1) {

			if ((cnt_mask & 0x1) == 0) 

				continue;

			DPRINT("phase 2: i=%d j=%d cnt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n",

				i, j, cnt_mask, avail_cntrs.bits[0], not_assigned_events);

			if (!pfm_regmask_isset(&avail_cntrs, j))

				continue;

			assign[i] = j;

			not_assigned_events &= ~(1UL << i);

			pfm_regmask_clr(&avail_cntrs, j);

			break;

		}

		if (cnt_mask == 0)

			return PFMLIB_ERR_NOASSIGN;

	}

	/*

	 * assign the rest of the events (no constraints)

	 */

	evt_mask = not_assigned_events;

	max_cnt = PMU_MONT_FIRST_COUNTER + PMU_MONT_NUM_COUNTERS;

	for (i=0, j=0; evt_mask ; i++, evt_mask >>=1) {

		DPRINT("phase 3a: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n",

			i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events);

		if ((evt_mask & 0x1) == 0)

			continue;

		while(j < max_cnt && !pfm_regmask_isset(&avail_cntrs, j)) {

			DPRINT("phase 3: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n",

				i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events);

			j++;

		}

		if (j == max_cnt)

			return PFMLIB_ERR_NOASSIGN;

		assign[i] = j;

		j++;

	}

	for (j=0; j < cnt ; j++ ) {

		mesi = 0;

		/*

		 * XXX: we do not support .all placement just yet

		 */

		if (param && param->pfp_mont_counters[j].flags & PFMLIB_MONT_FL_EVT_ALL_THRD) {

			DPRINT(".all mode is not yet supported by libpfm\n");

			return PFMLIB_ERR_NOTSUPP;

		}

		if (has_mesi(e[j].event)) {

			for(k=0;k< e[j].num_masks; k++) {

				mesi |= 1UL << e[j].unit_masks[k];

			}

			/* by default we capture everything */

			if (mesi == 0)

				mesi = 0xf;

		}

		reg.pmc_val    = 0; /* clear all, bits 26-27 must be zero for proper operations */

		/* if plm is 0, then assume not specified per-event and use default */

		reg.pmc_plm    = inp->pfp_events[j].plm ? inp->pfp_events[j].plm : inp->pfp_dfl_plm;

		reg.pmc_oi     = 0; /* let the user/OS deal with this field */

		reg.pmc_pm     = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0;

		reg.pmc_thres  = param ? param->pfp_mont_counters[j].thres: 0;

		reg.pmc_ism    = 0x2; /* force IA-64 mode */

		reg.pmc_umask  = is_ear(e[j].event) ? 0x0 : montecito_pe[e[j].event].pme_umask;

		reg.pmc_es     = montecito_pe[e[j].event].pme_code;

		reg.pmc_all    = 0; /* XXX force self for now */

		reg.pmc_m      = (mesi>>3) & 0x1;

		reg.pmc_e      = (mesi>>2) & 0x1;

		reg.pmc_s      = (mesi>>1) & 0x1;

		reg.pmc_i      =  mesi     & 0x1;

		/*

		 * Note that we don't force PMC4.pmc_ena = 1 because the kernel takes care of this for us.

		 * This way we don't have to program something in PMC4 even when we don't use it

		 */

		pc[j].reg_num     = assign[j];

		pc[j].reg_value   = reg.pmc_val;

		pc[j].reg_addr    = pc[j].reg_alt_addr = assign[j];

		pd[j].reg_num  = assign[j];

		pd[j].reg_addr = pd[j].reg_alt_addr = assign[j];

		__pfm_vbprintf("[PMC%u(pmc%u)=0x%06lx m=%d e=%d s=%d i=%d thres=%d all=%d es=0x%02x plm=%d umask=0x%x pm=%d ism=0x%x oi=%d] %s\n",

				assign[j],

				assign[j],

				reg.pmc_val,

				reg.pmc_m,

				reg.pmc_e,

				reg.pmc_s,

				reg.pmc_i,

				reg.pmc_thres,

				reg.pmc_all,

				reg.pmc_es,reg.pmc_plm,

				reg.pmc_umask, reg.pmc_pm,

				reg.pmc_ism,

				reg.pmc_oi,

				montecito_pe[e[j].event].pme_name);

		__pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num);

	}

	/* number of PMC registers programmed */

	outp->pfp_pmc_count = cnt;

	outp->pfp_pmd_count = cnt;

	return PFMLIB_SUCCESS;

}

static int

pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp)

{

	pfm_mont_pmc_reg_t reg;

	pfmlib_mont_input_param_t *param = mod_in;

	pfmlib_reg_t *pc, *pd;

	pfmlib_mont_input_param_t fake_param;

	unsigned int pos1, pos2;

	unsigned int i, count;

	pc = outp->pfp_pmcs;

	pd = outp->pfp_pmds;

	pos1 = outp->pfp_pmc_count;

	pos2 = outp->pfp_pmd_count;

	count = inp->pfp_event_count;

	for (i=0; i < count; i++) {

		if (is_iear(inp->pfp_events[i].event)) break;

	}

	if (param == NULL || param->pfp_mont_iear.ear_used == 0) {

		/*

		 * case 3: no I-EAR event, no (or nothing) in param->pfp_mont_iear.ear_used

		 */

		if (i == count) return PFMLIB_SUCCESS;

		memset(&fake_param, 0, sizeof(fake_param));

		param = &fake_param;

		/*

		 * case 1: extract all information for event (name)

		 */

		pfm_mont_get_ear_mode(inp->pfp_events[i].event, &param->pfp_mont_iear.ear_mode);

		param->pfp_mont_iear.ear_umask = evt_umask(inp->pfp_events[i].event);

		DPRINT("I-EAR event with no info\n");

	}

	/*

	 * case 2: ear_used=1, event is defined, we use the param info as it is more precise

	 * case 4: ear_used=1, no event (free running I-EAR), use param info

	 */

	reg.pmc_val = 0;

	if (param->pfp_mont_iear.ear_mode == PFMLIB_MONT_EAR_TLB_MODE) {

		/* if plm is 0, then assume not specified per-event and use default */

		reg.pmc37_mont_tlb_reg.iear_plm     = param->pfp_mont_iear.ear_plm ? param->pfp_mont_iear.ear_plm : inp->pfp_dfl_plm;

		reg.pmc37_mont_tlb_reg.iear_pm      = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0;

		reg.pmc37_mont_tlb_reg.iear_ct      = 0x0;

		reg.pmc37_mont_tlb_reg.iear_umask   = param->pfp_mont_iear.ear_umask;

	} else if (param->pfp_mont_iear.ear_mode == PFMLIB_MONT_EAR_CACHE_MODE) {

		/* if plm is 0, then assume not specified per-event and use default */

		reg.pmc37_mont_cache_reg.iear_plm   = param->pfp_mont_iear.ear_plm ? param->pfp_mont_iear.ear_plm : inp->pfp_dfl_plm;

		reg.pmc37_mont_cache_reg.iear_pm    = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0;

		reg.pmc37_mont_cache_reg.iear_ct    = 0x1;

		reg.pmc37_mont_cache_reg.iear_umask = param->pfp_mont_iear.ear_umask;

	} else {

		DPRINT("ALAT mode not supported in I-EAR mode\n");

		return PFMLIB_ERR_INVAL;

	}

	if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 37))

		return PFMLIB_ERR_NOASSIGN;

	pc[pos1].reg_num     = 37; /* PMC37 is I-EAR config register */

	pc[pos1].reg_value   = reg.pmc_val;

	pc[pos1].reg_addr  = pc[pos1].reg_addr = 37;

	pos1++;

	pd[pos2].reg_num  = 34;

	pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 34; 

	pos2++;

	pd[pos2].reg_num  = 35;

	pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 35; 

	pos2++;

	if (param->pfp_mont_iear.ear_mode == PFMLIB_MONT_EAR_TLB_MODE) {

		__pfm_vbprintf("[PMC37(pmc37)=0x%lx ctb=tlb plm=%d pm=%d umask=0x%x]\n",

			reg.pmc_val,

			reg.pmc37_mont_tlb_reg.iear_plm,

			reg.pmc37_mont_tlb_reg.iear_pm,

			reg.pmc37_mont_tlb_reg.iear_umask);

	} else {

		__pfm_vbprintf("[PMC37(pmc37)=0x%lx ctb=cache plm=%d pm=%d umask=0x%x]\n",

			reg.pmc_val,

			reg.pmc37_mont_cache_reg.iear_plm,

			reg.pmc37_mont_cache_reg.iear_pm,

			reg.pmc37_mont_cache_reg.iear_umask);

	}

	__pfm_vbprintf("[PMD34(pmd34)]\n[PMD35(pmd35)\n");

	/* update final number of entries used */

	outp->pfp_pmc_count = pos1;

	outp->pfp_pmd_count = pos2;

	return PFMLIB_SUCCESS;

}

static int

pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp)

{

	pfm_mont_pmc_reg_t reg;

	pfmlib_mont_input_param_t *param = mod_in;

	pfmlib_reg_t *pc, *pd;

	pfmlib_mont_input_param_t fake_param;

	unsigned int pos1, pos2;

	unsigned int i, count;

	pc = outp->pfp_pmcs;

	pd = outp->pfp_pmds;

	pos1 = outp->pfp_pmc_count;

	pos2 = outp->pfp_pmd_count;

	count = inp->pfp_event_count;

	for (i=0; i < count; i++) {

		if (is_dear(inp->pfp_events[i].event)) break;

	}

	if (param == NULL || param->pfp_mont_dear.ear_used == 0) {

		/*

		 * case 3: no D-EAR event, no (or nothing) in param->pfp_mont_dear.ear_used

		 */

		if (i == count) return PFMLIB_SUCCESS;

		memset(&fake_param, 0, sizeof(fake_param));

		param = &fake_param;

		/*

		 * case 1: extract all information for event (name)

		 */

		pfm_mont_get_ear_mode(inp->pfp_events[i].event, &param->pfp_mont_dear.ear_mode);

		param->pfp_mont_dear.ear_umask = evt_umask(inp->pfp_events[i].event);

		DPRINT("D-EAR event with no info\n");

	}

	/* sanity check on the mode */

	if (   param->pfp_mont_dear.ear_mode != PFMLIB_MONT_EAR_CACHE_MODE

	    && param->pfp_mont_dear.ear_mode != PFMLIB_MONT_EAR_TLB_MODE

	    && param->pfp_mont_dear.ear_mode != PFMLIB_MONT_EAR_ALAT_MODE)

		return PFMLIB_ERR_INVAL;

	/*

	 * case 2: ear_used=1, event is defined, we use the param info as it is more precise

	 * case 4: ear_used=1, no event (free running D-EAR), use param info

	 */

	reg.pmc_val = 0;

	/* if plm is 0, then assume not specified per-event and use default */

	reg.pmc40_mont_reg.dear_plm   = param->pfp_mont_dear.ear_plm ? param->pfp_mont_dear.ear_plm : inp->pfp_dfl_plm;

	reg.pmc40_mont_reg.dear_pm    = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0;

	reg.pmc40_mont_reg.dear_mode  = param->pfp_mont_dear.ear_mode;

	reg.pmc40_mont_reg.dear_umask = param->pfp_mont_dear.ear_umask;

	reg.pmc40_mont_reg.dear_ism   = 0x2; /* force IA-64 mode */

	if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 40))

		return PFMLIB_ERR_NOASSIGN;

	pc[pos1].reg_num     = 40;  /* PMC11 is D-EAR config register */

	pc[pos1].reg_value   = reg.pmc_val;

	pc[pos1].reg_addr  = pc[pos1].reg_alt_addr = 40;

	pos1++;

	pd[pos2].reg_num  = 32;

	pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 32; 

	pos2++;

	pd[pos2].reg_num  = 33;

	pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 33; 

	pos2++;

	pd[pos2].reg_num  = 36;

	pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 36; 

	pos2++;

	__pfm_vbprintf("[PMC40(pmc40)=0x%lx mode=%s plm=%d pm=%d ism=0x%x umask=0x%x]\n",

			reg.pmc_val,