Blame src/libpfm4/lib/pfmlib_intel_snbep_unc_priv.h

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/*
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 * pfmlib_intel_snbep_unc_priv.c : Intel SandyBridge/IvyBridge-EP common definitions
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 *
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 * Copyright (c) 2012 Google, Inc
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 * Contributed by Stephane Eranian <eranian@gmail.com>
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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 * of the Software, and to permit persons to whom the Software is furnished to do so,
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 * subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in all
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 * copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
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 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
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 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 */
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#ifndef __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__
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#define __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__
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/*
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 * Intel x86 specific pmu flags (pmu->flags 16 MSB)
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 */
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#define INTEL_PMU_FL_UNC_OCC 0x10000	/* PMU has occupancy counter filters */
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#define INTEL_PMU_FL_UNC_CBO 0x20000	/* PMU is Cbox */
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#define SNBEP_UNC_ATTR_E		0
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#define SNBEP_UNC_ATTR_I		1
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#define SNBEP_UNC_ATTR_T8		2
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#define SNBEP_UNC_ATTR_T5		3
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#define SNBEP_UNC_ATTR_TF		4
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#define SNBEP_UNC_ATTR_CF		5
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#define SNBEP_UNC_ATTR_NF		6 /* for filter0 */
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#define SNBEP_UNC_ATTR_FF		7
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#define SNBEP_UNC_ATTR_A		8
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#define SNBEP_UNC_ATTR_NF1		9 /* for filter1 */
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#define SNBEP_UNC_ATTR_ISOC	       10 /* isochronous */
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#define SNBEP_UNC_ATTR_NC	       11 /* non-coherent */
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#define SNBEP_UNC_ATTR_CF1	       12 /* core-filter hswep */
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#define _SNBEP_UNC_ATTR_I	(1 << SNBEP_UNC_ATTR_I)
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#define _SNBEP_UNC_ATTR_E	(1 << SNBEP_UNC_ATTR_E)
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#define _SNBEP_UNC_ATTR_T8	(1 << SNBEP_UNC_ATTR_T8)
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#define _SNBEP_UNC_ATTR_T5	(1 << SNBEP_UNC_ATTR_T5)
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#define _SNBEP_UNC_ATTR_TF	(1 << SNBEP_UNC_ATTR_TF)
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#define _SNBEP_UNC_ATTR_CF	(1 << SNBEP_UNC_ATTR_CF)
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#define _SNBEP_UNC_ATTR_NF	(1 << SNBEP_UNC_ATTR_NF)
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#define _SNBEP_UNC_ATTR_FF	(1 << SNBEP_UNC_ATTR_FF)
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#define _SNBEP_UNC_ATTR_A	(1 << SNBEP_UNC_ATTR_A)
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#define _SNBEP_UNC_ATTR_NF1	(1 << SNBEP_UNC_ATTR_NF1)
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#define _SNBEP_UNC_ATTR_ISOC	(1 << SNBEP_UNC_ATTR_ISOC)
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#define _SNBEP_UNC_ATTR_NC	(1 << SNBEP_UNC_ATTR_NC)
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#define _SNBEP_UNC_ATTR_CF1	(1 << SNBEP_UNC_ATTR_CF1)
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#define SNBEP_UNC_IRP_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define HSWEP_UNC_IRP_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I)
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#define BDX_UNC_IRP_ATTRS HSWEP_UNC_IRP_ATTRS
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#define SNBEP_UNC_R3QPI_ATTRS \
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	(_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define HSWEP_UNC_R3QPI_ATTRS SNBEP_UNC_R3QPI_ATTRS
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#define BDX_UNC_R3QPI_ATTRS   SNBEP_UNC_R3QPI_ATTRS
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#define IVBEP_UNC_R3QPI_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define SNBEP_UNC_R2PCIE_ATTRS \
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	(_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define HSWEP_UNC_R2PCIE_ATTRS SNBEP_UNC_R2PCIE_ATTRS
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#define BDX_UNC_R2PCIE_ATTRS   SNBEP_UNC_R2PCIE_ATTRS
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#define IVBEP_UNC_R2PCIE_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define SNBEP_UNC_QPI_ATTRS \
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	(_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define IVBEP_UNC_QPI_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define HSWEP_UNC_QPI_ATTRS SNBEP_UNC_QPI_ATTRS
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#define BDX_UNC_QPI_ATTRS   SNBEP_UNC_QPI_ATTRS
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#define SNBEP_UNC_UBO_ATTRS \
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	(_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define IVBEP_UNC_UBO_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define HSWEP_UNC_UBO_ATTRS SNBEP_UNC_UBO_ATTRS
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#define BDX_UNC_UBO_ATTRS   SNBEP_UNC_UBO_ATTRS
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#define SNBEP_UNC_PCU_ATTRS \
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	(_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T5)
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#define IVBEP_UNC_PCU_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T5)
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#define HSWEP_UNC_PCU_ATTRS SNBEP_UNC_PCU_ATTRS
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#define BDX_UNC_PCU_ATTRS \
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	(_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define SNBEP_UNC_PCU_BAND_ATTRS \
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	(SNBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF)
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#define IVBEP_UNC_PCU_BAND_ATTRS \
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	(IVBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF)
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#define HSWEP_UNC_PCU_BAND_ATTRS SNBEP_UNC_PCU_BAND_ATTRS
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#define BDX_UNC_PCU_BAND_ATTRS   SNBEP_UNC_PCU_BAND_ATTRS
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#define SNBEP_UNC_IMC_ATTRS \
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	(_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define IVBEP_UNC_IMC_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define HSWEP_UNC_IMC_ATTRS SNBEP_UNC_IMC_ATTRS
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#define BDX_UNC_IMC_ATTRS SNBEP_UNC_IMC_ATTRS
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#define SNBEP_UNC_CBO_ATTRS   \
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	(_SNBEP_UNC_ATTR_I   |\
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	 _SNBEP_UNC_ATTR_E   |\
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	 _SNBEP_UNC_ATTR_T8  |\
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	 _SNBEP_UNC_ATTR_CF  |\
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	 _SNBEP_UNC_ATTR_TF)
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#define IVBEP_UNC_CBO_ATTRS   \
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	(_SNBEP_UNC_ATTR_E   |\
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	 _SNBEP_UNC_ATTR_T8  |\
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	 _SNBEP_UNC_ATTR_CF  |\
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	 _SNBEP_UNC_ATTR_TF)
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#define HSWEP_UNC_CBO_ATTRS   \
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	(_SNBEP_UNC_ATTR_E   |\
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	 _SNBEP_UNC_ATTR_T8  |\
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	 _SNBEP_UNC_ATTR_CF1 |\
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	 _SNBEP_UNC_ATTR_TF)
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#define BDX_UNC_CBO_ATTRS HSWEP_UNC_CBO_ATTRS
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#define SNBEP_UNC_CBO_NID_ATTRS	\
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	(SNBEP_UNC_CBO_ATTRS|_SNBEP_UNC_ATTR_NF)
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#define IVBEP_UNC_CBO_NID_ATTRS	\
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	(IVBEP_UNC_CBO_ATTRS|_SNBEP_UNC_ATTR_NF1)
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#define HSWEP_UNC_CBO_NID_ATTRS	\
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	(HSWEP_UNC_CBO_ATTRS | _SNBEP_UNC_ATTR_NF1)
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#define BDX_UNC_CBO_NID_ATTRS HSWEP_UNC_CBO_NID_ATTRS
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#define SNBEP_UNC_HA_ATTRS \
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	(_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define IVBEP_UNC_HA_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
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#define HSWEP_UNC_HA_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I)
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#define BDX_UNC_HA_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I)
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#define SNBEP_UNC_HA_OPC_ATTRS \
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	(SNBEP_UNC_HA_ATTRS|_SNBEP_UNC_ATTR_A)
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#define HSWEP_UNC_SBO_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I)
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#define BDX_UNC_SBO_ATTRS \
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	(_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8|_SNBEP_UNC_ATTR_I)
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#define KNL_UNC_CHA_TOR_ATTRS    _SNBEP_UNC_ATTR_NF1
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typedef union {
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	uint64_t val;
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	struct {
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		unsigned long unc_event:8;	/* event code */
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		unsigned long unc_umask:8;	/* unit mask */
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		unsigned long unc_res1:1;	/* reserved */
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		unsigned long unc_rst:1;	/* reset */
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		unsigned long unc_edge:1;	/* edge detec */
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		unsigned long unc_res2:3;	/* reserved */
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		unsigned long unc_en:1;		/* enable */
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		unsigned long unc_inv:1;	/* invert counter mask */
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		unsigned long unc_thres:8;	/* counter mask */
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		unsigned long unc_res3:32;	/* reserved */
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	} com; /* covers common fields for cbox, ha, imc, ubox, r2pcie, r3qpi, sbox */
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	struct {
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		unsigned long unc_event:8;	/* event code */
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		unsigned long unc_umask:8;	/* unit mask */
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		unsigned long unc_res1:1;	/* reserved */
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		unsigned long unc_rst:1;	/* reset */
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		unsigned long unc_edge:1;	/* edge detect */
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		unsigned long unc_tid:1;	/* tid filter enable */
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		unsigned long unc_res2:2;	/* reserved */
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		unsigned long unc_en:1;		/* enable */
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		unsigned long unc_inv:1;	/* invert counter mask */
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		unsigned long unc_thres:8;	/* counter mask */
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		unsigned long unc_res3:32;	/* reserved */
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	} cbo; /* covers c-box */
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	struct {
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		unsigned long unc_event:8;	/* event code */
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		unsigned long unc_res1:6;	/* reserved */
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		unsigned long unc_occ:2;	/* occ select */
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		unsigned long unc_res2:1;	/* reserved */
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		unsigned long unc_rst:1;	/* reset */
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		unsigned long unc_edge:1;	/* edge detec */
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		unsigned long unc_res3:1;	/* reserved */
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		unsigned long unc_res4:2;	/* reserved */
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		unsigned long unc_en:1;		/* enable */
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		unsigned long unc_inv:1;	/* invert counter mask */
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		unsigned long unc_thres:5;	/* threshold */
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		unsigned long unc_res5:1;	/* reserved */
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		unsigned long unc_occ_inv:1;	/* occupancy invert */
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		unsigned long unc_occ_edge:1;	/* occupancy edge detect */
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		unsigned long unc_res6:32;	/* reserved */
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	} pcu; /* covers pcu */
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	struct {
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		unsigned long unc_event:8;	/* event code */
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		unsigned long unc_res1:6;	/* reserved */
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		unsigned long unc_occ:2;	/* occ select */
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		unsigned long unc_res2:1;	/* reserved */
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		unsigned long unc_rst:1;	/* reset */
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		unsigned long unc_edge:1;	/* edge detec */
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		unsigned long unc_res3:1;	/* reserved */
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		unsigned long unc_ov_en:1;	/* overflow enable */
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		unsigned long unc_sel_ext:1;	/* event_sel extension */
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		unsigned long unc_en:1;		/* enable */
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		unsigned long unc_res4:1;	/* reserved */
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		unsigned long unc_thres:5;	/* threshold */
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		unsigned long unc_res5:1;	/* reserved */
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		unsigned long unc_occ_inv:1;	/* occupancy invert */
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		unsigned long unc_occ_edge:1;	/* occupancy edge detect */
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		unsigned long unc_res6:32;	/* reserved */
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	} ivbep_pcu; /* covers ivb-ep pcu */
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	struct {
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		unsigned long unc_event:8;	/* event code */
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		unsigned long unc_umask:8;	/* unit maks */
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		unsigned long unc_res1:1;	/* reserved */
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		unsigned long unc_rst:1;	/* reset */
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		unsigned long unc_edge:1;	/* edge detec */
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		unsigned long unc_res2:1;	/* reserved */
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		unsigned long unc_res3:1;	/* reserved */
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		unsigned long unc_event_ext:1;	/* event code extension */
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		unsigned long unc_en:1;		/* enable */
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		unsigned long unc_inv:1;	/* invert counter mask */
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		unsigned long unc_thres:8;	/* threshold */
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		unsigned long unc_res4:32;	/* reserved */
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	} qpi; /* covers qpi */
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	struct {
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		unsigned long tid:1;
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		unsigned long cid:3;
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		unsigned long res0:1;
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		unsigned long res1:3;
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		unsigned long res2:2;
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		unsigned long nid:8;
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		unsigned long state:5;
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		unsigned long opc:9;
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		unsigned long res3:1;
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		unsigned long res4:32;
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	} cbo_filt; /* cbox filter */
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	struct {
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		unsigned long tid:1;
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		unsigned long cid:4;
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		unsigned long res0:12;
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		unsigned long state:6;
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		unsigned long res1:9;
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		unsigned long res2:32;
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	} ivbep_cbo_filt0; /* ivbep cbox filter0 */
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	struct {
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		unsigned long nid:16;
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		unsigned long res0:4;
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		unsigned long opc:9;
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		unsigned long res1:1;
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		unsigned long nc:1;
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		unsigned long isoc:1;
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		unsigned long res2:32;
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	} ivbep_cbo_filt1; /* ivbep cbox filter1 */
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	struct {
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		unsigned long tid:1;
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		unsigned long cid:5;
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		unsigned long res0:11;
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		unsigned long state:7;
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		unsigned long res1:8;
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		unsigned long res2:32;
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	} hswep_cbo_filt0; /* hswep cbox filter0 */
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	struct {
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		unsigned long nid:16;
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		unsigned long res0:4;
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		unsigned long opc:9;
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		unsigned long res1:1;
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		unsigned long nc:1;
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		unsigned long isoc:1;
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		unsigned long res2:32;
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	} hswep_cbo_filt1; /* hswep cbox filter1 */
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	struct {
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		unsigned long filt0:8; /* band0 freq filter */
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		unsigned long filt1:8; /* band1 freq filter */
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		unsigned long filt2:8; /* band2 freq filter */
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		unsigned long filt3:8; /* band3 freq filter */
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		unsigned long res1:32; /* reserved */
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	} pcu_filt;
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	struct {
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		unsigned long res1:6;
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		unsigned long lo_addr:26; /* lo order 26b */
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		unsigned long hi_addr:14; /* hi order 14b */
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		unsigned long res2:18; /* reserved */
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	} ha_addr;
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	struct {
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		unsigned long opc:6; /* opcode match */
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		unsigned long res1:26; /* reserved */
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		unsigned long res2:32; /* reserved */
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	} ha_opc;
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	struct {
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		unsigned long unc_event:8;	/* event code */
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		unsigned long unc_umask:8;	/* unit mask */
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		unsigned long unc_res1:1;	/* reserved */
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		unsigned long unc_rst:1;	/* reset */
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		unsigned long unc_edge:1;	/* edge detec */
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		unsigned long unc_res2:3;	/* reserved */
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		unsigned long unc_en:1;		/* enable */
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		unsigned long unc_res3:1;	/* reserved */
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		unsigned long unc_thres:8;	/* counter mask */
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		unsigned long unc_res4:32;	/* reserved */
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	} irp; /* covers irp */
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} pfm_snbep_unc_reg_t;
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extern void pfm_intel_snbep_unc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e);
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extern int  pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e);
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extern const pfmlib_attr_desc_t snbep_unc_mods[];
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extern int  pfm_intel_snbep_unc_detect(void *this);
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extern int  pfm_intel_ivbep_unc_detect(void *this);
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extern int  pfm_intel_hswep_unc_detect(void *this);
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extern int  pfm_intel_knl_unc_detect(void *this);
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extern int  pfm_intel_bdx_unc_detect(void *this);
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extern int  pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e);
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extern int  pfm_intel_snbep_unc_can_auto_encode(void *this, int pidx, int uidx);
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extern int pfm_intel_snbep_unc_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info);
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static inline int
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is_cbo_filt_event(void *this, pfm_intel_x86_reg_t reg)
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{
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	pfmlib_pmu_t *pmu = this;
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	uint64_t sel = reg.sel_event_select;
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	/*
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	 * umask bit 0 must be 1 (OPCODE)
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	 * TOR_INSERT: event code 0x35
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	 * TOR_OCCUPANCY: event code 0x36
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	 * LLC_LOOKUP : event code 0x34
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	 */
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	return (pmu->flags & INTEL_PMU_FL_UNC_CBO)
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		&& (reg.sel_unit_mask & 0x1)
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		&& (sel == 0x35 || sel == 0x36 || sel == 0x34);
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}
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#endif /* __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__ */