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/*
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* pfmlib_intel_atom.c : Intel Atom PMU
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*
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* Copyright (c) 2008 Google, Inc
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* Contributed by Stephane Eranian <eranian@gmail.com>
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*
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* Based on work:
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* Copyright (c) 2006 Hewlett-Packard Development Company, L.P.
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* Contributed by Stephane Eranian <eranian@hpl.hp.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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* PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
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* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
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* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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* This file implements support for Intel Core PMU as specified in the following document:
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* "IA-32 Intel Architecture Software Developer's Manual - Volume 3B: System
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* Programming Guide"
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*
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* Intel Atom = architectural v3 + PEBS
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*/
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/* private headers */
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#include "pfmlib_priv.h"
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#include "pfmlib_intel_x86_priv.h"
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#include "events/intel_atom_events.h"
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static const int atom_models[] = {
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28, /* Pineview/Silverthorne */
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38, /* Lincroft */
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39, /* Penwell */
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53, /* Cloverview */
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54, /* Cedarview */
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0
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};
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static int
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pfm_intel_atom_init(void *this)
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{
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pfm_intel_x86_cfg.arch_version = 3;
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return PFM_SUCCESS;
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}
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pfmlib_pmu_t intel_atom_support={
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.desc = "Intel Atom",
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.name = "atom",
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.pmu = PFM_PMU_INTEL_ATOM,
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.pme_count = LIBPFM_ARRAY_SIZE(intel_atom_pe),
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.type = PFM_PMU_TYPE_CORE,
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.num_cntrs = 2,
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.num_fixed_cntrs = 3,
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.max_encoding = 1,
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.pe = intel_atom_pe,
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.atdesc = intel_x86_mods,
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.flags = PFMLIB_PMU_FL_RAW_UMASK,
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.supported_plm = INTEL_X86_PLM,
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.cpu_family = 6,
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.cpu_models = atom_models,
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.pmu_detect = pfm_intel_x86_model_detect,
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.pmu_init = pfm_intel_atom_init,
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.get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding,
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PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding),
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.get_event_first = pfm_intel_x86_get_event_first,
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.get_event_next = pfm_intel_x86_get_event_next,
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.event_is_valid = pfm_intel_x86_event_is_valid,
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.validate_table = pfm_intel_x86_validate_table,
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.get_event_info = pfm_intel_x86_get_event_info,
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.get_event_attr_info = pfm_intel_x86_get_event_attr_info,
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PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs),
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.get_event_nattrs = pfm_intel_x86_get_event_nattrs,
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};
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