/*

 * Copyright (c) 2011 Google, Inc

 * Contributed by Stephane Eranian <eranian@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 * This file is part of libpfm, a performance monitoring support library for

 * applications on Linux.

 *

 * This file has been automatically generated.

 *

 * PMU: wsm_unc (Intel Westmere uncore)

 */

static const intel_x86_umask_t wsm_unc_unc_dram_open[]={

   { .uname  = "CH0",

     .udesc  = "DRAM Channel 0 open commands issued for read or write",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "DRAM Channel 1 open commands issued for read or write",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "DRAM Channel 2 open commands issued for read or write",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_gc_occupancy[]={

   { .uname  = "READ_TRACKER",

     .udesc  = "In the read tracker",

     .ucode = 0x100,

     .uflags= INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_dram_page_close[]={

   { .uname  = "CH0",

     .udesc  = "DRAM Channel 0 page close",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "DRAM Channel 1 page close",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "DRAM Channel 2 page close",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_dram_page_miss[]={

   { .uname  = "CH0",

     .udesc  = "DRAM Channel 0 page miss",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "DRAM Channel 1 page miss",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "DRAM Channel 2 page miss",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_dram_pre_all[]={

   { .uname  = "CH0",

     .udesc  = "DRAM Channel 0 precharge all commands",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "DRAM Channel 1 precharge all commands",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "DRAM Channel 2 precharge all commands",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_dram_read_cas[]={

   { .uname  = "CH0",

     .udesc  = "DRAM Channel 0 read CAS commands",

     .ucode = 0x100,

   },

   { .uname  = "AUTOPRE_CH0",

     .udesc  = "DRAM Channel 0 read CAS auto page close commands",

     .ucode = 0x200,

   },

   { .uname  = "CH1",

     .udesc  = "DRAM Channel 1 read CAS commands",

     .ucode = 0x400,

   },

   { .uname  = "AUTOPRE_CH1",

     .udesc  = "DRAM Channel 1 read CAS auto page close commands",

     .ucode = 0x800,

   },

   { .uname  = "CH2",

     .udesc  = "DRAM Channel 2 read CAS commands",

     .ucode = 0x1000,

   },

   { .uname  = "AUTOPRE_CH2",

     .udesc  = "DRAM Channel 2 read CAS auto page close commands",

     .ucode = 0x2000,

   },

};

static const intel_x86_umask_t wsm_unc_unc_dram_refresh[]={

   { .uname  = "CH0",

     .udesc  = "DRAM Channel 0 refresh commands",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "DRAM Channel 1 refresh commands",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "DRAM Channel 2 refresh commands",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_dram_write_cas[]={

   { .uname  = "CH0",

     .udesc  = "DRAM Channel 0 write CAS commands",

     .ucode = 0x100,

   },

   { .uname  = "AUTOPRE_CH0",

     .udesc  = "DRAM Channel 0 write CAS auto page close commands",

     .ucode = 0x200,

   },

   { .uname  = "CH1",

     .udesc  = "DRAM Channel 1 write CAS commands",

     .ucode = 0x400,

   },

   { .uname  = "AUTOPRE_CH1",

     .udesc  = "DRAM Channel 1 write CAS auto page close commands",

     .ucode = 0x800,

   },

   { .uname  = "CH2",

     .udesc  = "DRAM Channel 2 write CAS commands",

     .ucode = 0x1000,

   },

   { .uname  = "AUTOPRE_CH2",

     .udesc  = "DRAM Channel 2 write CAS auto page close commands",

     .ucode = 0x2000,

   },

};

static const intel_x86_umask_t wsm_unc_unc_gq_alloc[]={

   { .uname  = "READ_TRACKER",

     .udesc  = "GQ read tracker requests",

     .ucode = 0x100,

   },

   { .uname  = "RT_LLC_MISS",

     .udesc  = "GQ read tracker LLC misses",

     .ucode = 0x200,

   },

   { .uname  = "RT_TO_LLC_RESP",

     .udesc  = "GQ read tracker LLC requests",

     .ucode = 0x400,

   },

   { .uname  = "RT_TO_RTID_ACQUIRED",

     .udesc  = "GQ read tracker LLC miss to RTID acquired",

     .ucode = 0x800,

   },

   { .uname  = "WT_TO_RTID_ACQUIRED",

     .udesc  = "GQ write tracker LLC miss to RTID acquired",

     .ucode = 0x1000,

   },

   { .uname  = "WRITE_TRACKER",

     .udesc  = "GQ write tracker LLC misses",

     .ucode = 0x2000,

   },

   { .uname  = "PEER_PROBE_TRACKER",

     .udesc  = "GQ peer probe tracker requests",

     .ucode = 0x4000,

   },

};

static const intel_x86_umask_t wsm_unc_unc_gq_cycles_full[]={

   { .uname  = "READ_TRACKER",

     .udesc  = "Cycles GQ read tracker is full.",

     .ucode = 0x100,

   },

   { .uname  = "WRITE_TRACKER",

     .udesc  = "Cycles GQ write tracker is full.",

     .ucode = 0x200,

   },

   { .uname  = "PEER_PROBE_TRACKER",

     .udesc  = "Cycles GQ peer probe tracker is full.",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_gq_cycles_not_empty[]={

   { .uname  = "READ_TRACKER",

     .udesc  = "Cycles GQ read tracker is busy",

     .ucode = 0x100,

   },

   { .uname  = "WRITE_TRACKER",

     .udesc  = "Cycles GQ write tracker is busy",

     .ucode = 0x200,

   },

   { .uname  = "PEER_PROBE_TRACKER",

     .udesc  = "Cycles GQ peer probe tracker is busy",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_gq_data_from[]={

   { .uname  = "QPI",

     .udesc  = "Cycles GQ data is imported from Quickpath interface",

     .ucode = 0x100,

   },

   { .uname  = "QMC",

     .udesc  = "Cycles GQ data is imported from Quickpath memory interface",

     .ucode = 0x200,

   },

   { .uname  = "LLC",

     .udesc  = "Cycles GQ data is imported from LLC",

     .ucode = 0x400,

   },

   { .uname  = "CORES_02",

     .udesc  = "Cycles GQ data is imported from Cores 0 and 2",

     .ucode = 0x800,

   },

   { .uname  = "CORES_13",

     .udesc  = "Cycles GQ data is imported from Cores 1 and 3",

     .ucode = 0x1000,

   },

};

static const intel_x86_umask_t wsm_unc_unc_gq_data_to[]={

   { .uname  = "QPI_QMC",

     .udesc  = "Cycles GQ data sent to the QPI or QMC",

     .ucode = 0x100,

   },

   { .uname  = "LLC",

     .udesc  = "Cycles GQ data sent to LLC",

     .ucode = 0x200,

   },

   { .uname  = "CORES",

     .udesc  = "Cycles GQ data sent to cores",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_llc_hits[]={

   { .uname  = "READ",

     .udesc  = "Number of LLC read hits",

     .ucode = 0x100,

   },

   { .uname  = "WRITE",

     .udesc  = "Number of LLC write hits",

     .ucode = 0x200,

   },

   { .uname  = "PROBE",

     .udesc  = "Number of LLC peer probe hits",

     .ucode = 0x400,

   },

   { .uname  = "ANY",

     .udesc  = "Number of LLC hits",

     .ucode = 0x300,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_llc_lines_in[]={

   { .uname  = "M_STATE",

     .udesc  = "LLC lines allocated in M state",

     .ucode = 0x100,

   },

   { .uname  = "E_STATE",

     .udesc  = "LLC lines allocated in E state",

     .ucode = 0x200,

   },

   { .uname  = "S_STATE",

     .udesc  = "LLC lines allocated in S state",

     .ucode = 0x400,

   },

   { .uname  = "F_STATE",

     .udesc  = "LLC lines allocated in F state",

     .ucode = 0x800,

   },

   { .uname  = "ANY",

     .udesc  = "LLC lines allocated",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_llc_lines_out[]={

   { .uname  = "M_STATE",

     .udesc  = "LLC lines victimized in M state",

     .ucode = 0x100,

   },

   { .uname  = "E_STATE",

     .udesc  = "LLC lines victimized in E state",

     .ucode = 0x200,

   },

   { .uname  = "S_STATE",

     .udesc  = "LLC lines victimized in S state",

     .ucode = 0x400,

   },

   { .uname  = "I_STATE",

     .udesc  = "LLC lines victimized in I state",

     .ucode = 0x800,

   },

   { .uname  = "F_STATE",

     .udesc  = "LLC lines victimized in F state",

     .ucode = 0x1000,

   },

   { .uname  = "ANY",

     .udesc  = "LLC lines victimized",

     .ucode = 0x1f00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_llc_miss[]={

   { .uname  = "READ",

     .udesc  = "Number of LLC read misses",

     .ucode = 0x100,

   },

   { .uname  = "WRITE",

     .udesc  = "Number of LLC write misses",

     .ucode = 0x200,

   },

   { .uname  = "PROBE",

     .udesc  = "Number of LLC peer probe misses",

     .ucode = 0x400,

   },

   { .uname  = "ANY",

     .udesc  = "Number of LLC misses",

     .ucode = 0x300,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qhl_address_conflicts[]={

   { .uname  = "2WAY",

     .udesc  = "QHL 2 way address conflicts",

     .ucode = 0x200,

   },

   { .uname  = "3WAY",

     .udesc  = "QHL 3 way address conflicts",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qhl_conflict_cycles[]={

   { .uname  = "IOH",

     .udesc  = "QHL IOH Tracker conflict cycles",

     .ucode = 0x100,

   },

   { .uname  = "REMOTE",

     .udesc  = "QHL Remote Tracker conflict cycles",

     .ucode = 0x200,

   },

   { .uname  = "LOCAL",

     .udesc  = "QHL Local Tracker conflict cycles",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qhl_cycles_full[]={

   { .uname  = "REMOTE",

     .udesc  = "Cycles QHL  Remote Tracker is full",

     .ucode = 0x200,

   },

   { .uname  = "LOCAL",

     .udesc  = "Cycles QHL Local Tracker is full",

     .ucode = 0x400,

   },

   { .uname  = "IOH",

     .udesc  = "Cycles QHL IOH Tracker is full",

     .ucode = 0x100,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qhl_cycles_not_empty[]={

   { .uname  = "IOH",

     .udesc  = "Cycles QHL IOH is busy",

     .ucode = 0x100,

   },

   { .uname  = "REMOTE",

     .udesc  = "Cycles QHL Remote Tracker is busy",

     .ucode = 0x200,

   },

   { .uname  = "LOCAL",

     .udesc  = "Cycles QHL Local Tracker is busy",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qhl_frc_ack_cnflts[]={

   { .uname  = "LOCAL",

     .udesc  = "QHL FrcAckCnflts sent to local home",

     .ucode = 0x400,

     .uflags= INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qhl_sleeps[]={

   { .uname  = "IOH_ORDER",

     .udesc  = "Due to IOH ordering (write after read) conflicts",

     .ucode = 0x100,

   },

   { .uname  = "REMOTE_ORDER",

     .udesc  = "Due to remote socket ordering (write after read) conflicts",

     .ucode = 0x200,

   },

   { .uname  = "LOCAL_ORDER",

     .udesc  = "Due to local socket ordering (write after read) conflicts",

     .ucode = 0x400,

   },

   { .uname  = "IOH_CONFLICT",

     .udesc  = "Due to IOH address conflicts",

     .ucode = 0x800,

   },

   { .uname  = "REMOTE_CONFLICT",

     .udesc  = "Due to remote socket address conflicts",

     .ucode = 0x1000,

   },

   { .uname  = "LOCAL_CONFLICT",

     .udesc  = "Due to local socket address conflicts",

     .ucode = 0x2000,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qhl_occupancy[]={

   { .uname  = "IOH",

     .udesc  = "Cycles QHL IOH Tracker Allocate to Deallocate Read Occupancy",

     .ucode = 0x100,

   },

   { .uname  = "REMOTE",

     .udesc  = "Cycles QHL Remote Tracker Allocate to Deallocate Read Occupancy",

     .ucode = 0x200,

   },

   { .uname  = "LOCAL",

     .udesc  = "Cycles QHL Local Tracker Allocate to Deallocate Read Occupancy",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qhl_requests[]={

   { .uname  = "LOCAL_READS",

     .udesc  = "Quickpath Home Logic local read requests",

     .ucode = 0x1000,

   },

   { .uname  = "LOCAL_WRITES",

     .udesc  = "Quickpath Home Logic local write requests",

     .ucode = 0x2000,

   },

   { .uname  = "REMOTE_READS",

     .udesc  = "Quickpath Home Logic remote read requests",

     .ucode = 0x400,

   },

   { .uname  = "IOH_READS",

     .udesc  = "Quickpath Home Logic IOH read requests",

     .ucode = 0x100,

   },

   { .uname  = "IOH_WRITES",

     .udesc  = "Quickpath Home Logic IOH write requests",

     .ucode = 0x200,

   },

   { .uname  = "REMOTE_WRITES",

     .udesc  = "Quickpath Home Logic remote write requests",

     .ucode = 0x800,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qmc_busy[]={

   { .uname  = "READ_CH0",

     .udesc  = "Cycles QMC channel 0 busy with a read request",

     .ucode = 0x100,

   },

   { .uname  = "READ_CH1",

     .udesc  = "Cycles QMC channel 1 busy with a read request",

     .ucode = 0x200,

   },

   { .uname  = "READ_CH2",

     .udesc  = "Cycles QMC channel 2 busy with a read request",

     .ucode = 0x400,

   },

   { .uname  = "WRITE_CH0",

     .udesc  = "Cycles QMC channel 0 busy with a write request",

     .ucode = 0x800,

   },

   { .uname  = "WRITE_CH1",

     .udesc  = "Cycles QMC channel 1 busy with a write request",

     .ucode = 0x1000,

   },

   { .uname  = "WRITE_CH2",

     .udesc  = "Cycles QMC channel 2 busy with a write request",

     .ucode = 0x2000,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qmc_cancel[]={

   { .uname  = "CH0",

     .udesc  = "QMC channel 0 cancels",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "QMC channel 1 cancels",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "QMC channel 2 cancels",

     .ucode = 0x400,

   },

   { .uname  = "ANY",

     .udesc  = "QMC cancels",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qmc_critical_priority_reads[]={

   { .uname  = "CH0",

     .udesc  = "QMC channel 0 critical priority read requests",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "QMC channel 1 critical priority read requests",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "QMC channel 2 critical priority read requests",

     .ucode = 0x400,

   },

   { .uname  = "ANY",

     .udesc  = "QMC critical priority read requests",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qmc_high_priority_reads[]={

   { .uname  = "CH0",

     .udesc  = "QMC channel 0 high priority read requests",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "QMC channel 1 high priority read requests",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "QMC channel 2 high priority read requests",

     .ucode = 0x400,

   },

   { .uname  = "ANY",

     .udesc  = "QMC high priority read requests",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qmc_isoc_full[]={

   { .uname  = "READ_CH0",

     .udesc  = "Cycles DRAM channel 0 full with isochronous read requests",

     .ucode = 0x100,

   },

   { .uname  = "READ_CH1",

     .udesc  = "Cycles DRAM channel 1 full with isochronous read requests",

     .ucode = 0x200,

   },

   { .uname  = "READ_CH2",

     .udesc  = "Cycles DRAM channel 2 full with isochronous read requests",

     .ucode = 0x400,

   },

   { .uname  = "WRITE_CH0",

     .udesc  = "Cycles DRAM channel 0 full with isochronous write requests",

     .ucode = 0x800,

   },

   { .uname  = "WRITE_CH1",

     .udesc  = "Cycles DRAM channel 1 full with isochronous write requests",

     .ucode = 0x1000,

   },

   { .uname  = "WRITE_CH2",

     .udesc  = "Cycles DRAM channel 2 full with isochronous write requests",

     .ucode = 0x2000,

   },

};

static const intel_x86_umask_t wsm_unc_unc_imc_isoc_occupancy[]={

   { .uname  = "CH0",

     .udesc  = "IMC channel 0 isochronous read request occupancy",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "IMC channel 1 isochronous read request occupancy",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "IMC channel 2 isochronous read request occupancy",

     .ucode = 0x400,

   },

   { .uname  = "ANY",

     .udesc  = "IMC isochronous read request occupancy",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qmc_normal_reads[]={

   { .uname  = "CH0",

     .udesc  = "QMC channel 0 normal read requests",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "QMC channel 1 normal read requests",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "QMC channel 2 normal read requests",

     .ucode = 0x400,

   },

   { .uname  = "ANY",

     .udesc  = "QMC normal read requests",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qmc_occupancy[]={

   { .uname  = "CH0",

     .udesc  = "IMC channel 0 normal read request occupancy",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "IMC channel 1 normal read request occupancy",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "IMC channel 2 normal read request occupancy",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qmc_priority_updates[]={

   { .uname  = "CH0",

     .udesc  = "QMC channel 0 priority updates",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "QMC channel 1 priority updates",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "QMC channel 2 priority updates",

     .ucode = 0x400,

   },

   { .uname  = "ANY",

     .udesc  = "QMC priority updates",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_imc_retry[]={

   { .uname  = "CH0",

     .udesc  = "Channel 0",

     .ucode = 0x100,

   },

   { .uname  = "CH1",

     .udesc  = "Channel 1",

     .ucode = 0x200,

   },

   { .uname  = "CH2",

     .udesc  = "Channel 2",

     .ucode = 0x400,

   },

   { .uname  = "ANY",

     .udesc  = "Any channel",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qmc_writes[]={

   { .uname  = "FULL_CH0",

     .udesc  = "QMC channel 0 full cache line writes",

     .ucode = 0x100,

     .grpid = 0,

   },

   { .uname  = "FULL_CH1",

     .udesc  = "QMC channel 1 full cache line writes",

     .ucode = 0x200,

     .grpid = 0,

   },

   { .uname  = "FULL_CH2",

     .udesc  = "QMC channel 2 full cache line writes",

     .ucode = 0x400,

     .grpid = 0,

   },

   { .uname  = "FULL_ANY",

     .udesc  = "QMC full cache line writes",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 0,

   },

   { .uname  = "PARTIAL_CH0",

     .udesc  = "QMC channel 0 partial cache line writes",

     .ucode = 0x800,

     .grpid = 1,

   },

   { .uname  = "PARTIAL_CH1",

     .udesc  = "QMC channel 1 partial cache line writes",

     .ucode = 0x1000,

     .grpid = 1,

   },

   { .uname  = "PARTIAL_CH2",

     .udesc  = "QMC channel 2 partial cache line writes",

     .ucode = 0x2000,

     .grpid = 1,

   },

   { .uname  = "PARTIAL_ANY",

     .udesc  = "QMC partial cache line writes",

     .ucode = 0x3800,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 1,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qpi_rx_no_ppt_credit[]={

   { .uname  = "STALLS_LINK_0",

     .udesc  = "Link 0 snoop stalls due to no PPT entry",

     .ucode = 0x100,

   },

   { .uname  = "STALLS_LINK_1",

     .udesc  = "Link 1 snoop stalls due to no PPT entry",

     .ucode = 0x200,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qpi_tx_header[]={

   { .uname  = "BUSY_LINK_0",

     .udesc  = "Cycles link 0 outbound header busy",

     .ucode = 0x200,

   },

   { .uname  = "BUSY_LINK_1",

     .udesc  = "Cycles link 1 outbound header busy",

     .ucode = 0x800,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qpi_tx_stalled_multi_flit[]={

   { .uname  = "DRS_LINK_0",

     .udesc  = "Cycles QPI outbound link 0 DRS stalled",

     .ucode = 0x100,

   },

   { .uname  = "NCB_LINK_0",

     .udesc  = "Cycles QPI outbound link 0 NCB stalled",

     .ucode = 0x200,

   },

   { .uname  = "NCS_LINK_0",

     .udesc  = "Cycles QPI outbound link 0 NCS stalled",

     .ucode = 0x400,

   },

   { .uname  = "DRS_LINK_1",

     .udesc  = "Cycles QPI outbound link 1 DRS stalled",

     .ucode = 0x800,

   },

   { .uname  = "NCB_LINK_1",

     .udesc  = "Cycles QPI outbound link 1 NCB stalled",

     .ucode = 0x1000,

   },

   { .uname  = "NCS_LINK_1",

     .udesc  = "Cycles QPI outbound link 1 NCS stalled",

     .ucode = 0x2000,

   },

   { .uname  = "LINK_0",

     .udesc  = "Cycles QPI outbound link 0 multi flit stalled",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "LINK_1",

     .udesc  = "Cycles QPI outbound link 1 multi flit stalled",

     .ucode = 0x3800,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t wsm_unc_unc_qpi_tx_stalled_single_flit[]={

   { .uname  = "HOME_LINK_0",

     .udesc  = "Cycles QPI outbound link 0 HOME stalled",

     .ucode = 0x100,

   },

   { .uname  = "SNOOP_LINK_0",

     .udesc  = "Cycles QPI outbound link 0 SNOOP stalled",

     .ucode = 0x200,

   },

   { .uname  = "NDR_LINK_0",

     .udesc  = "Cycles QPI outbound link 0 NDR stalled",

     .ucode = 0x400,

   },

   { .uname  = "HOME_LINK_1",

     .udesc  = "Cycles QPI outbound link 1 HOME stalled",

     .ucode = 0x800,

   },

   { .uname  = "SNOOP_LINK_1",

     .udesc  = "Cycles QPI outbound link 1 SNOOP stalled",

     .ucode = 0x1000,

   },

   { .uname  = "NDR_LINK_1",

     .udesc  = "Cycles QPI outbound link 1 NDR stalled",

     .ucode = 0x2000,

   },

   { .uname  = "LINK_0",

     .udesc  = "Cycles QPI outbound link 0 single flit stalled",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "LINK_1",

     .udesc  = "Cycles QPI outbound link 1 single flit stalled",

     .ucode = 0x3800,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t wsm_unc_unc_snp_resp_to_local_home[]={

   { .uname  = "I_STATE",

     .udesc  = "Local home snoop response - LLC does not have cache line",

     .ucode = 0x100,

   },

   { .uname  = "S_STATE",

     .udesc  = "Local home snoop response - LLC has  cache line in S state",

     .ucode = 0x200,

   },

   { .uname  = "FWD_S_STATE",

     .udesc  = "Local home snoop response - LLC forwarding cache line in S state.",

     .ucode = 0x400,

   },

   { .uname  = "FWD_I_STATE",

     .udesc  = "Local home snoop response - LLC has forwarded a modified cache line",

     .ucode = 0x800,

   },

   { .uname  = "CONFLICT",

     .udesc  = "Local home conflict snoop response",

     .ucode = 0x1000,

   },

   { .uname  = "WB",

     .udesc  = "Local home snoop response - LLC has cache line in the M state",

     .ucode = 0x2000,

   },

};

static const intel_x86_umask_t wsm_unc_unc_snp_resp_to_remote_home[]={

   { .uname  = "I_STATE",

     .udesc  = "Remote home snoop response - LLC does not have cache line",

     .ucode = 0x100,

   },

   { .uname  = "S_STATE",

     .udesc  = "Remote home snoop response - LLC has  cache line in S state",

     .ucode = 0x200,

   },

   { .uname  = "FWD_S_STATE",

     .udesc  = "Remote home snoop response - LLC forwarding cache line in S state.",

     .ucode = 0x400,