/*

 * Contributed by Stephane Eranian <eranian@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 * This file is part of libpfm, a performance monitoring support library for

 * applications on Linux.

 *

 * PMU: skl (Intel SkyLake)

 */

static const intel_x86_umask_t skl_baclears[]={

  { .uname = "ANY",

    .udesc  = "Number of front-end re-steers due to BPU misprediction",

    .ucode  = 0x0100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_br_inst_retired[]={

  { .uname = "CONDITIONAL",

    .udesc  = "Counts all taken and not taken macro conditional branch instructions",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "COND",

    .udesc  = "Counts all taken and not taken macro conditional branch instructions",

    .ucode  = 0x100,

    .uequiv = "CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "NEAR_CALL",

    .udesc  = "Counts all macro direct and indirect near calls",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "ALL_BRANCHES",

    .udesc  = "Counts all taken and not taken macro branches including far branches (architectural event)",

    .ucode  = 0x0,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_PEBS,

  },

  { .uname = "NEAR_RETURN",

    .udesc  = "Counts the number of near ret instructions retired",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "NOT_TAKEN",

    .udesc  = "Counts all not taken macro branch instructions retired",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "NEAR_TAKEN",

    .udesc  = "Counts the number of near branch taken instructions retired",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "FAR_BRANCH",

    .udesc  = "Counts the number of far branch instructions retired",

    .ucode  = 0x4000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

};

static const intel_x86_umask_t skl_br_misp_retired[]={

  { .uname = "CONDITIONAL",

    .udesc  = "All mispredicted macro conditional branch instructions",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "COND",

    .udesc  = "All mispredicted macro conditional branch instructions",

    .ucode  = 0x100,

    .uequiv = "CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "ALL_BRANCHES",

    .udesc  = "All mispredicted macro branches (architectural event)",

    .ucode  = 0x0, /* architectural encoding */

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL,

  },

  { .uname = "NEAR_TAKEN",

    .udesc  = "Number of near branch instructions retired that were mispredicted and taken",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "NEAR_CALL",

    .udesc  = "Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

};

static const intel_x86_umask_t skl_cpu_clk_thread_unhalted[]={

  { .uname = "REF_XCLK",

    .udesc  = "Count Xclk pulses (100Mhz) when the core is unhalted",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "REF_XCLK_ANY",

    .udesc  = "Count Xclk pulses (100Mhz) when the at least one thread on the physical core is unhalted",

    .ucode  = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */

    .uequiv = "REF_XCLK:t",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_T,

  },

  { .uname  = "REF_P",

    .udesc  = "Cycles when the core is unhalted (count at 100 Mhz)",

    .ucode = 0x100,

    .uequiv = "REF_XCLK",

    .uflags= INTEL_X86_NCOMBO,

  },

  { .uname  = "THREAD_P",

    .udesc  = "Cycles when thread is not halted",

    .ucode = 0x000,

    .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

  { .uname  = "ONE_THREAD_ACTIVE",

    .udesc  = "Counts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is halted",

    .ucode  = 0x200,

    .uflags= INTEL_X86_NCOMBO,

  },

  { .uname  = "RING0_TRANS",

    .udesc  = "Counts when the current privilege level transitions from ring 1, 2 or 3 to ring 0 (kernel)",

    .ucode  = 0x000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "THREAD_P:e:c=1",

    .uflags= INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_cycle_activity[]={

   { .uname  = "CYCLES_L2_MISS",

     .udesc  = "Cycles with pending L2 miss demand loads outstanding",

     .ucode  = 0x0100 | (0x1 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "CYCLES_L2_PENDING",

     .udesc  = "Cycles with pending L2 miss demand loads outstanding",

     .ucode  = 0x0100 | (0x1 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

     .uequiv = "CYCLES_L2_MISS",

   },

   { .uname  = "CYCLES_L3_MISS",

     .udesc  = "Cycles with L3 cache miss demand loads outstanding",

     .ucode  = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "CYCLES_LDM_PENDING",

     .udesc  = "Cycles with L3 cache miss demand loads outstanding",

     .ucode  = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT),

     .uequiv = "CYCLES_L3_MISS",

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "CYCLES_L1D_MISS",

     .udesc  = "Cycles with pending L1D load cache misses",

     .ucode  = 0x0800 | (0x8 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "CYCLES_L1D_PENDING",

     .udesc  = "Cycles with pending L1D load cache misses",

     .ucode  = 0x0800 | (0x8 << INTEL_X86_CMASK_BIT),

     .uequiv = "CYCLES_L1D_MISS",

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "CYCLES_MEM_ANY",

     .udesc  = "Cycles when memory subsystem has at least one outstanding load",

     .ucode  = 0x1000 | (0x10 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "STALLS_L1D_MISS",

     .udesc  = "Execution stalls while at least one L1D demand load cache miss is outstanding",

     .ucode  = 0x0c00 | (0xc << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .ucntmsk= 0x4,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "STALLS_L2_MISS",

     .udesc  = "Execution stalls while at least one L2 demand load is outstanding",

     .ucode  = 0x0500 | (0x5 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .ucntmsk= 0xf,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "STALLS_L3_MISS",

     .udesc  = "Execution stalls while at least one L3 demand load is outstanding",

     .ucode  = 0x0600 | (0x6 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "STALLS_MEM_ANY",

     .udesc  = "Execution stalls while at least one demand load is outstanding in the memory subsystem",

     .ucode  = 0x1400 | (20 << INTEL_X86_CMASK_BIT), /* cnt=20 */

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "STALLS_TOTAL",

     .udesc  = "Total execution stalls in cycles",

     .ucode  = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t skl_dtlb_load_misses[]={

  { .uname = "MISS_CAUSES_A_WALK",

    .udesc  = "Misses in all DTLB levels that cause page walks",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED",

    .udesc  = "Number of misses in all TLB levels causing a page walk of any page size that completes",

    .ucode  = 0xe00,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_4K",

    .udesc  = "Number of misses in all TLB levels causing a page walk of 4KB page size that completes",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_2M_4M",

    .udesc  = "Number of misses in all TLB levels causing a page walk of 2MB/4MB page size that completes",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_1G",

    .udesc  = "Number of misses in all TLB levels causing a page walk of 1GB page size that completes",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_ACTIVE",

    .udesc  = "Cycles with at least one hardware walker active for a load",

    .ucode  = 0x1000 | (0x1 <<  INTEL_X86_CMASK_BIT),

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_DURATION",

    .udesc  = "Cycles when hardware page walker is busy with page walks",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_PENDING",

    .udesc  = "Cycles when hardware page walker is busy with page walks",

    .ucode  = 0x1000,

    .uequiv = "WALK_DURATION",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "STLB_HIT",

    .udesc  = "Number of cache load STLB hits. No page walk",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_itlb_misses[]={

  { .uname = "MISS_CAUSES_A_WALK",

    .udesc  = "Misses in all DTLB levels that cause page walks",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED",

    .udesc  = "Number of misses in all TLB levels causing a page walk of any page size that completes",

    .ucode  = 0xe00,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_4K",

    .udesc  = "Number of misses in all TLB levels causing a page walk of 4KB page size that completes",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_2M_4M",

    .udesc  = "Number of misses in all TLB levels causing a page walk of 2MB/4MB page size that completes",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_1G",

    .udesc  = "Number of misses in all TLB levels causing a page walk of 1GB page size that completes",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_DURATION",

    .udesc  = "Cycles when PMH is busy with page walks",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_PENDING",

    .udesc  = "Cycles when PMH is busy with page walks",

    .ucode  = 0x1000,

    .uequiv = "WALK_DURATION",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "STLB_HIT",

    .udesc  = "Number of cache load STLB hits. No page walk",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_fp_assist[]={

  { .uname = "ANY",

    .udesc  = "Cycles with any input/output SEE or FP assists",

    .ucode  = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

    .modhw  = _INTEL_X86_ATTR_C,

  },

};

static const intel_x86_umask_t skl_icache_16b[]={

  { .uname = "IFDATA_STALL",

    .udesc  = "Cycles where a code fetch is stalled due to L1 instruction cache miss",

    .ucode  = 0x400,

    .uflags = INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_icache_64b[]={

  { .uname = "IFTAG_HIT",

    .udesc  = "Number of instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "IFTAG_MISS",

    .udesc  = "Number of instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "IFTAG_STALL",

    .udesc  = "Cycles where a code fetch is stalled due to L1 instruction cache tag miss",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_idq[]={

  { .uname = "MITE_UOPS",

    .udesc  = "Number of uops delivered to Instruction Decode Queue (IDQ) from MITE path",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "DSB_UOPS",

    .udesc  = "Number of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MS_DSB_UOPS",

    .udesc  = "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MS_MITE_UOPS",

    .udesc  = "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MS_UOPS",

    .udesc  = "Number of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITE",

    .ucode  = 0x3000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MS_UOPS_CYCLES",

    .udesc  = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE",

    .ucode  = 0x3000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "MS_UOPS:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "MS_SWITCHES",

    .udesc  = "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

     .ucode  = 0x3000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "MS_UOPS:c=1:e",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

  { .uname = "MITE_UOPS_CYCLES",

    .udesc  = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

    .ucode  = 0x400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "MITE_UOPS:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "DSB_UOPS_CYCLES",

    .udesc  = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

    .ucode  = 0x800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "DSB_UOPS:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "MS_DSB_UOPS_CYCLES",

    .udesc  = "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

    .ucode  = 0x1000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "MS_DSB_UOPS:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "MS_DSB_OCCUR",

    .udesc  = "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",

    .ucode  = 0x1000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "MS_DSB_UOPS:c=1:e=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_DSB_CYCLES_4_UOPS",

    .udesc  = "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

    .ucode  = 0x1800 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_DSB_CYCLES_ANY_UOPS",

    .udesc  = "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

    .ucode  = 0x1800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_MITE_CYCLES_4_UOPS",

    .udesc  = "Cycles MITE is delivering 4 Uops",

    .ucode  = 0x2400 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_MITE_CYCLES_ANY_UOPS",

    .udesc  = "Cycles MITE is delivering any Uop",

    .ucode  = 0x2400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_MITE_UOPS",

    .udesc  = "Number of uops delivered to Instruction Decode Queue (IDQ) from any path",

    .ucode  = 0x3c00,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_idq_uops_not_delivered[]={

  { .uname = "CORE",

    .udesc  = "Count number of non-delivered uops to Resource Allocation Table (RAT)",

    .ucode  = 0x100,

    .uflags = INTEL_X86_DFL,

  },

  { .uname = "CYCLES_0_UOPS_DELIV_CORE",

    .udesc  = "Number of uops not delivered to Resource Allocation Table (RAT) per thread when backend is not stalled",

    .ucode  = 0x100 | (4 << INTEL_X86_CMASK_BIT),

    .modhw  = _INTEL_X86_ATTR_C,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "CYCLES_FE_WAS_OK",

    .udesc  = "Count cycles front-end (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling front-end",

    .ucode  = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 inv=1 */

    .uequiv = "CORE:c=1:i",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_I,

  },

  { .uname = "CYCLES_LE_1_UOPS_DELIV_CORE",

    .udesc  = "Count cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend is not stalled",

    .ucode  = 0x100 | (3 << INTEL_X86_CMASK_BIT),

    .modhw  = _INTEL_X86_ATTR_C,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "CYCLES_LE_2_UOPS_DELIV_CORE",

    .udesc  = "Count cycles with less than 2 uops delivered by the front-end",

    .ucode  = 0x100 | (2 << INTEL_X86_CMASK_BIT),

    .modhw  = _INTEL_X86_ATTR_C,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "CYCLES_LE_3_UOPS_DELIV_CORE",

    .udesc  = "Count cycles with less then 3 uops delivered by the front-end",

    .ucode  = 0x100 | (1 << INTEL_X86_CMASK_BIT),

    .modhw  = _INTEL_X86_ATTR_C,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_inst_retired[]={

  { .uname = "ANY_P",

    .udesc  = "Number of instructions retired. General Counter - architectural event",

    .ucode  = 0x000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

  { .uname = "ALL",

    .udesc  = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise Event)",

    .ucode  = 0x100,

    .uequiv = "PREC_DIST",

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "TOTAL_CYCLES",

    .udesc  = "Number of cycles using always true condition",

    .ucode  = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=10 */

    .uequiv = "PREC_DIST:i=1:c=10",

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

    .modhw  = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C,

  },

  { .uname = "PREC_DIST",

    .udesc  = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise event)",

    .ucode  = 0x100,

    .ucntmsk= 0x2,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

};

static const intel_x86_umask_t skl_int_misc[]={

  { .uname = "RECOVERY_CYCLES",

    .udesc  = "Cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "RECOVERY_CYCLES_ANY",

    .udesc  = "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

    .ucode  = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */

    .uequiv = "RECOVERY_CYCLES:t",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_T,

  },

  { .uname = "RECOVERY_STALLS_COUNT",

    .udesc  = "Number of occurrences waiting for Machine Clears",

    .ucode  = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "RECOVERY_CYCLES:e:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E,

  },

  { .uname = "CLEAR_RESTEER_CYCLES",

    .udesc  = "Number of cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events",

    .ucode  = 0x8000,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_itlb[]={

  { .uname = "ITLB_FLUSH",

    .udesc  = "Flushing of the Instruction TLB (ITLB) pages independent of page size",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_l1d[]={

  { .uname = "REPLACEMENT",

    .udesc  = "L1D Data line replacements",

    .ucode  = 0x100,

    .uflags = INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_sq_misc[]={

  { .uname = "SPLIT_LOCK",

    .udesc  = "Number of split locks in the super queue (SQ)",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_l1d_pend_miss[]={

  { .uname = "PENDING",

    .udesc  = "Cycles with L1D load misses outstanding",

    .ucode  = 0x100,

    .ucntmsk = 0x4,

    .uflags = INTEL_X86_DFL,

  },

  { .uname = "FB_FULL",

    .udesc  = "Number of times a request needed a fill buffer (FB) entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands load, store or SW prefetch",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "PENDING_CYCLES",

    .udesc  = "Cycles with L1D load misses outstanding",

    .ucode  = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "PENDING:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "PENDING_CYCLES_ANY",

    .udesc  = "Cycles with L1D load misses outstanding from any thread",

    .ucode  = 0x100 | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, /* cnt=1 any=1 */

    .uequiv = "PENDING:c=1:t",

    .ucntmsk = 0x4,

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T,

  },

  { .uname = "OCCURRENCES",

    .udesc  = "Number L1D miss outstanding",

    .ucode  = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "PENDING:c=1:e=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

  { .uname = "EDGE",

    .udesc  = "Number L1D miss outstanding",

    .ucode  = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "PENDING:c=1:e=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

};

static const intel_x86_umask_t skl_l2_lines_in[]={

  { .uname = "ALL",

    .udesc  = "L2 cache lines filling L2",

    .ucode  = 0x1f00,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

  { .uname = "ANY",

    .udesc  = "L2 cache lines filling L2",

    .uequiv = "ALL",

    .ucode  = 0x1f00,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_l2_lines_out[]={

  { .uname = "NON_SILENT",

    .udesc  = "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped ",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "USELESS_HWPREF",

    .udesc  = "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",

    .ucode  = 0x400,

    .uequiv = "USELESS_HWPF",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "USELESS_HWPF",

    .udesc  = "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "SILENT",

    .udesc  = "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. This is a per-core event.",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_l2_rqsts[]={

  { .uname = "DEMAND_DATA_RD_MISS",

    .udesc  = "Demand Data Read requests that miss L2 cache",

    .ucode  = 0x2100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "DEMAND_DATA_RD_HIT",

    .udesc  = "Demand Data Read requests that hit L2 cache",

    .ucode  = 0x4100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "DEMAND_RFO_MISS",

    .udesc  = "RFO requests that miss L2 cache",

    .ucode  = 0x2200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "RFO_MISS",

    .udesc  = "RFO requests that miss L2 cache",

    .ucode  = 0x2200,

    .uequiv = "DEMAND_RFO_MISS",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "DEMAND_RFO_HIT",

    .udesc  = "RFO requests that hit L2 cache",

    .ucode  = 0x4200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "RFO_HIT",

    .udesc  = "RFO requests that hit L2 cache",

    .ucode  = 0x4200,

    .uequiv = "DEMAND_RFO_HIT",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "CODE_RD_MISS",

    .udesc  = "L2 cache misses when fetching instructions",

    .ucode  = 0x2400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_DEMAND_MISS",

    .udesc  = "All demand requests that miss the L2 cache",

    .ucode  = 0x2700,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "CODE_RD_HIT",

    .udesc  = "L2 cache hits when fetching instructions, code reads",

    .ucode  = 0x4400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MISS",

    .udesc  = "All requests that miss the L2 cache",

    .ucode  = 0x3f00,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "PF_MISS",

    .udesc  = "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",

    .ucode  = 0x3800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "PF_HIT",

    .udesc  = "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",

    .ucode  = 0xd800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_DEMAND_DATA_RD",

    .udesc  = "Any data read request to L2 cache",

    .ucode  = 0xe100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_RFO",

    .udesc  = "Any data RFO request to L2 cache",

    .ucode  = 0xe200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_CODE_RD",

    .udesc  = "Any code read request to L2 cache",

    .ucode  = 0xe400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_DEMAND_REFERENCES",

    .udesc  = "All demand requests to L2 cache ",

    .ucode  = 0xe700,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_PF",

    .udesc  = "Any L2 HW prefetch request to L2 cache",

    .ucode  = 0xf800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "REFERENCES",

    .udesc  = "All requests to L2 cache",

    .ucode  = 0xff00,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_l2_trans[]={

  { .uname = "L2_WB",

    .udesc  = "L2 writebacks that access L2 cache",

    .ucode  = 0x4000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_ld_blocks[]={

  { .uname = "STORE_FORWARD",

    .udesc  = "Counts the number of loads blocked by overlapping with store buffer entries that cannot be forwarded",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "NO_SR",

    .udesc  = "number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_ld_blocks_partial[]={

  { .uname = "ADDRESS_ALIAS",

    .udesc  = "False dependencies in MOB due to partial compare on address",

    .ucode  = 0x100,

    .uflags = INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_load_hit_pre[]={

  { .uname = "SW_PF",

    .udesc  = "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch",

    .ucode  = 0x100,

    .uflags = INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_lock_cycles[]={

  { .uname = "CACHE_LOCK_DURATION",

    .udesc  = "cycles that the L1D is locked",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t skl_longest_lat_cache[]={

  { .uname = "MISS",

    .udesc  = "Core-originated cacheable demand requests missed LLC - architectural event",

    .ucode  = 0x4100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "REFERENCE",

    .udesc  = "Core-originated cacheable demand requests that refer to LLC - architectural event",

    .ucode  = 0x4f00,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_machine_clears[]={

  { .uname = "COUNT",

    .udesc  = "Number of machine clears (Nukes) of any type",

    .ucode  = 0x100| (1 << INTEL_X86_CMASK_BIT) | (1 << INTEL_X86_EDGE_BIT),

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MEMORY_ORDERING",

    .udesc  = "Number of Memory Ordering Machine Clears detected",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "SMC",

    .udesc  = "Number of Self-modifying code (SMC) Machine Clears detected",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t skl_mem_load_l3_hit_retired[]={

  { .uname = "XSNP_MISS",

    .udesc  = "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "XSNP_HIT",

    .udesc  = "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "XSNP_HITM",

    .udesc  = "Load had HitM Response from a core on same socket (shared L3). (Non PEBS",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "XSNP_NONE",

    .udesc  = "Retired load uops which data sources were hits in L3 without snoops required",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

};

static const intel_x86_umask_t skl_mem_load_l3_miss_retired[]={

  { .uname = "LOCAL_DRAM",

    .udesc  = "Retired load instructions which data sources missed L3 but serviced from local dram",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "REMOTE_DRAM",

    .udesc  = "Retired load instructions which data sources missed L3 but serviced from remote dram",

    .ucode  = 0x200,

    .umodel = PFM_PMU_INTEL_SKX,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "REMOTE_HITM",

    .udesc  = "Retired load instructions whose data sources was remote HITM",

    .ucode  = 0x400,

    .umodel = PFM_PMU_INTEL_SKX,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "REMOTE_FWD",

    .udesc  = "Retired load instructions whose data sources was remote HITM",

    .ucode  = 0x800,

    .umodel = PFM_PMU_INTEL_SKX,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

};

static const intel_x86_umask_t skl_mem_load_retired[]={

  { .uname = "L1_HIT",

    .udesc  = "Retired load uops with L1 cache hits as data source",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "L2_HIT",