/*

 * Copyright (c) 2011 Google, Inc

 * Contributed by Stephane Eranian <eranian@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 * This file is part of libpfm, a performance monitoring support library for

 * applications on Linux.

 *

 * This file has been automatically generated.

 *

 * PMU: nhm (Intel Nehalem)

 */

static const intel_x86_umask_t nhm_arith[]={

   { .uname  = "CYCLES_DIV_BUSY",

     .udesc  = "Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DIV",

     .udesc  = "Counts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.",

     .uequiv = "CYCLES_DIV_BUSY:c=1:i=1:e=1",

     .ucode = 0x100 | INTEL_X86_MOD_EDGE | INTEL_X86_MOD_INV | (0x1 << INTEL_X86_CMASK_BIT),

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "MUL",

     .udesc  = "Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD.",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_baclear[]={

   { .uname  = "BAD_TARGET",

     .udesc  = "BACLEAR asserted with bad target address",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "CLEAR",

     .udesc  = "BACLEAR asserted, regardless of cause",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_bpu_clears[]={

   { .uname  = "EARLY",

     .udesc  = "Early Branch Prediction Unit clears",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "LATE",

     .udesc  = "Late Branch Prediction Unit clears",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "ANY",

     .udesc  = "Count any Branch Prediction Unit clears",

     .ucode = 0x300,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t nhm_br_inst_exec[]={

   { .uname  = "ANY",

     .udesc  = "Branch instructions executed",

     .ucode = 0x7f00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "COND",

     .udesc  = "Conditional branch instructions executed",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DIRECT",

     .udesc  = "Unconditional branches executed",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DIRECT_NEAR_CALL",

     .udesc  = "Unconditional call branches executed",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "INDIRECT_NEAR_CALL",

     .udesc  = "Indirect call branches executed",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "INDIRECT_NON_CALL",

     .udesc  = "Indirect non call branches executed",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "NEAR_CALLS",

     .udesc  = "Call branches executed",

     .ucode = 0x3000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "NON_CALLS",

     .udesc  = "All non call branches executed",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "RETURN_NEAR",

     .udesc  = "Indirect return branches executed",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "TAKEN",

     .udesc  = "Taken branches executed",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_br_inst_retired[]={

   { .uname  = "ALL_BRANCHES",

     .udesc  = "Retired branch instructions (Precise Event)",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL,

   },

   { .uname  = "CONDITIONAL",

     .udesc  = "Retired conditional branch instructions (Precise Event)",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS,

   },

   { .uname  = "NEAR_CALL",

     .udesc  = "Retired near call instructions (Precise Event)",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS,

   },

};

static const intel_x86_umask_t nhm_br_misp_exec[]={

   { .uname  = "ANY",

     .udesc  = "Mispredicted branches executed",

     .ucode = 0x7f00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "COND",

     .udesc  = "Mispredicted conditional branches executed",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DIRECT",

     .udesc  = "Mispredicted unconditional branches executed",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DIRECT_NEAR_CALL",

     .udesc  = "Mispredicted non call branches executed",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "INDIRECT_NEAR_CALL",

     .udesc  = "Mispredicted indirect call branches executed",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "INDIRECT_NON_CALL",

     .udesc  = "Mispredicted indirect non call branches executed",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "NEAR_CALLS",

     .udesc  = "Mispredicted call branches executed",

     .ucode = 0x3000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "NON_CALLS",

     .udesc  = "Mispredicted non call branches executed",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "RETURN_NEAR",

     .udesc  = "Mispredicted return branches executed",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "TAKEN",

     .udesc  = "Mispredicted taken branches executed",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_br_misp_retired[]={

   { .uname  = "NEAR_CALL",

     .udesc  = "Counts mispredicted direct and indirect near unconditional retired calls",

     .ucode = 0x200,

     .uflags= INTEL_X86_PEBS | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t nhm_cache_lock_cycles[]={

   { .uname  = "L1D",

     .udesc  = "Cycles L1D locked",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "L1D_L2",

     .udesc  = "Cycles L1D and L2 locked",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_cpu_clk_unhalted[]={

   { .uname  = "THREAD_P",

     .udesc  = "Cycles when thread is not halted (programmable counter)",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "REF_P",

     .udesc  = "Reference base clock (133 Mhz) cycles when thread is not halted",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "TOTAL_CYCLES",

     .udesc  = "Total number of elapsed cycles. Does not work when C-state enabled",

     .uequiv = "THREAD_P:c=2:i=1",

     .ucode = 0x0 | INTEL_X86_MOD_INV | (0x2 << INTEL_X86_CMASK_BIT),

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_dtlb_load_misses[]={

   { .uname  = "ANY",

     .udesc  = "DTLB load misses",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "PDE_MISS",

     .udesc  = "DTLB load miss caused by low part of address",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "WALK_COMPLETED",

     .udesc  = "DTLB load miss page walks complete",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "STLB_HIT",

     .udesc  = "DTLB second level hit",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PDP_MISS",

     .udesc  = "Number of DTLB cache load misses where the high part of the linear to physical address translation was missed",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "LARGE_WALK_COMPLETED",

     .udesc  = "Counts number of completed large page walks due to load miss in the STLB",

     .ucode = 0x8000,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_dtlb_misses[]={

   { .uname  = "ANY",

     .udesc  = "DTLB misses",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "STLB_HIT",

     .udesc  = "DTLB first level misses but second level hit",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "WALK_COMPLETED",

     .udesc  = "DTLB miss page walks",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PDE_MISS",

     .udesc  = "Number of DTLB cache misses where the low part of the linear to physical address translation was missed",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PDP_MISS",

     .udesc  = "Number of DTLB misses where the high part of the linear to physical address translation was missed",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "LARGE_WALK_COMPLETED",

     .udesc  = "Counts number of completed large page walks due to misses in the STLB",

     .ucode = 0x8000,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_ept[]={

   { .uname  = "EPDE_MISS",

     .udesc  = "Extended Page Directory Entry miss",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "EPDPE_MISS",

     .udesc  = "Extended Page Directory Pointer miss",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "EPDPE_HIT",

     .udesc  = "Extended Page Directory Pointer hit",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_fp_assist[]={

   { .uname  = "ALL",

     .udesc  = "Floating point assists (Precise Event)",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL,

   },

   { .uname  = "INPUT",

     .udesc  = "Floating point assists for invalid input value (Precise Event)",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS,

   },

   { .uname  = "OUTPUT",

     .udesc  = "Floating point assists for invalid output value (Precise Event)",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS,

   },

};

static const intel_x86_umask_t nhm_fp_comp_ops_exe[]={

   { .uname  = "MMX",

     .udesc  = "MMX Uops",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "SSE_DOUBLE_PRECISION",

     .udesc  = "SSE* FP double precision Uops",

     .ucode = 0x8000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "SSE_FP",

     .udesc  = "SSE and SSE2 FP Uops",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "SSE_FP_PACKED",

     .udesc  = "SSE FP packed Uops",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "SSE_FP_SCALAR",

     .udesc  = "SSE FP scalar Uops",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "SSE_SINGLE_PRECISION",

     .udesc  = "SSE* FP single precision Uops",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "SSE2_INTEGER",

     .udesc  = "SSE2 integer Uops",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "X87",

     .udesc  = "Computational floating-point operations executed",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_fp_mmx_trans[]={

   { .uname  = "ANY",

     .udesc  = "All Floating Point to and from MMX transitions",

     .ucode = 0x300,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "TO_FP",

     .udesc  = "Transitions from MMX to Floating Point instructions",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "TO_MMX",

     .udesc  = "Transitions from Floating Point to MMX instructions",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_ifu_ivc[]={

   { .uname  = "FULL",

     .udesc  = "Instruction Fetche unit victim cache full",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "L1I_EVICTION",

     .udesc  = "L1 Instruction cache evictions",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_ild_stall[]={

   { .uname  = "ANY",

     .udesc  = "Any Instruction Length Decoder stall cycles",

     .uequiv = "IQ_FULL:LCP:MRU:REGEN",

     .ucode = 0xf00,

     .uflags= INTEL_X86_DFL,

   },

   { .uname  = "IQ_FULL",

     .udesc  = "Instruction Queue full stall cycles",

     .ucode = 0x400,

   },

   { .uname  = "LCP",

     .udesc  = "Length Change Prefix stall cycles",

     .ucode = 0x100,

   },

   { .uname  = "MRU",

     .udesc  = "Stall cycles due to BPU MRU bypass",

     .ucode = 0x200,

   },

   { .uname  = "REGEN",

     .udesc  = "Regen stall cycles",

     .ucode = 0x800,

   },

};

static const intel_x86_umask_t nhm_inst_decoded[]={

   { .uname  = "DEC0",

     .udesc  = "Instructions that must be decoded by decoder 0",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t nhm_inst_retired[]={

   { .uname  = "ANY_P",

     .udesc  = "Instructions Retired (Precise Event)",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL,

   },

   { .uname  = "X87",

     .udesc  = "Retired floating-point operations (Precise Event)",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS,

   },

};

static const intel_x86_umask_t nhm_l1d[]={

   { .uname  = "M_EVICT",

     .udesc  = "L1D cache lines replaced in M state",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "M_REPL",

     .udesc  = "L1D cache lines allocated in the M state",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "M_SNOOP_EVICT",

     .udesc  = "L1D snoop eviction of cache lines in M state",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "REPL",

     .udesc  = "L1 data cache lines allocated",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l1d_all_ref[]={

   { .uname  = "ANY",

     .udesc  = "All references to the L1 data cache",

     .ucode = 0x100,

     .uflags= INTEL_X86_DFL,

   },

   { .uname  = "CACHEABLE",

     .udesc  = "L1 data cacheable reads and writes",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l1d_cache_ld[]={

   { .uname  = "E_STATE",

     .udesc  = "L1 data cache read in E state",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "I_STATE",

     .udesc  = "L1 data cache read in I state (misses)",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "M_STATE",

     .udesc  = "L1 data cache read in M state",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "MESI",

     .udesc  = "L1 data cache reads",

     .ucode = 0xf00,

     .uflags= INTEL_X86_DFL,

   },

   { .uname  = "S_STATE",

     .udesc  = "L1 data cache read in S state",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l1d_cache_lock[]={

   { .uname  = "E_STATE",

     .udesc  = "L1 data cache load locks in E state",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "HIT",

     .udesc  = "L1 data cache load lock hits",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "M_STATE",

     .udesc  = "L1 data cache load locks in M state",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "S_STATE",

     .udesc  = "L1 data cache load locks in S state",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l1d_cache_st[]={

   { .uname  = "E_STATE",

     .udesc  = "L1 data cache stores in E state",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "I_STATE",

     .udesc  = "L1 data cache store in the I state",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "M_STATE",

     .udesc  = "L1 data cache stores in M state",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "S_STATE",

     .udesc  = "L1 data cache stores in S state",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "MESI",

     .udesc  = "L1 data cache store in all states",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t nhm_l1d_prefetch[]={

   { .uname  = "MISS",

     .udesc  = "L1D hardware prefetch misses",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "REQUESTS",

     .udesc  = "L1D hardware prefetch requests",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "TRIGGERS",

     .udesc  = "L1D hardware prefetch requests triggered",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l1d_wb_l2[]={

   { .uname  = "E_STATE",

     .udesc  = "L1 writebacks to L2 in E state",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "I_STATE",

     .udesc  = "L1 writebacks to L2 in I state (misses)",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "M_STATE",

     .udesc  = "L1 writebacks to L2 in M state",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "S_STATE",

     .udesc  = "L1 writebacks to L2 in S state",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "MESI",

     .udesc  = "All L1 writebacks to L2",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t nhm_l1i[]={

   { .uname  = "CYCLES_STALLED",

     .udesc  = "L1I instruction fetch stall cycles",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "HITS",

     .udesc  = "L1I instruction fetch hits",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "MISSES",

     .udesc  = "L1I instruction fetch misses",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "READS",

     .udesc  = "L1I Instruction fetches",

     .ucode = 0x300,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l2_data_rqsts[]={

   { .uname  = "ANY",

     .udesc  = "All L2 data requests",

     .ucode = 0xff00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "DEMAND_E_STATE",

     .udesc  = "L2 data demand loads in E state",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DEMAND_I_STATE",

     .udesc  = "L2 data demand loads in I state (misses)",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DEMAND_M_STATE",

     .udesc  = "L2 data demand loads in M state",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DEMAND_MESI",

     .udesc  = "L2 data demand requests",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DEMAND_S_STATE",

     .udesc  = "L2 data demand loads in S state",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCH_E_STATE",

     .udesc  = "L2 data prefetches in E state",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCH_I_STATE",

     .udesc  = "L2 data prefetches in the I state (misses)",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCH_M_STATE",

     .udesc  = "L2 data prefetches in M state",

     .ucode = 0x8000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCH_MESI",

     .udesc  = "All L2 data prefetches",

     .ucode = 0xf000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCH_S_STATE",

     .udesc  = "L2 data prefetches in the S state",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l2_hw_prefetch[]={

   { .uname  = "HIT",

     .udesc  = "Count L2 HW prefetcher detector hits",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "ALLOC",

     .udesc  = "Count L2 HW prefetcher allocations",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DATA_TRIGGER",

     .udesc  = "Count L2 HW data prefetcher triggered",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "CODE_TRIGGER",

     .udesc  = "Count L2 HW code prefetcher triggered",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DCA_TRIGGER",

     .udesc  = "Count L2 HW DCA prefetcher triggered",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "KICK_START",

     .udesc  = "Count L2 HW prefetcher kick started",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l2_lines_in[]={

   { .uname  = "ANY",

     .udesc  = "L2 lines allocated",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "E_STATE",

     .udesc  = "L2 lines allocated in the E state",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "S_STATE",

     .udesc  = "L2 lines allocated in the S state",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l2_lines_out[]={

   { .uname  = "ANY",

     .udesc  = "L2 lines evicted",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "DEMAND_CLEAN",

     .udesc  = "L2 lines evicted by a demand request",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "DEMAND_DIRTY",

     .udesc  = "L2 modified lines evicted by a demand request",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCH_CLEAN",

     .udesc  = "L2 lines evicted by a prefetch request",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCH_DIRTY",

     .udesc  = "L2 modified lines evicted by a prefetch request",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l2_rqsts[]={

   { .uname  = "MISS",

     .udesc  = "All L2 misses",

     .ucode = 0xaa00,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "REFERENCES",

     .udesc  = "All L2 requests",

     .ucode = 0xff00,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "IFETCH_HIT",

     .udesc  = "L2 instruction fetch hits",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "IFETCH_MISS",

     .udesc  = "L2 instruction fetch misses",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "IFETCHES",

     .udesc  = "L2 instruction fetches",

     .ucode = 0x3000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "LD_HIT",

     .udesc  = "L2 load hits",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "LD_MISS",

     .udesc  = "L2 load misses",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "LOADS",

     .udesc  = "L2 requests",

     .ucode = 0x300,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCH_HIT",

     .udesc  = "L2 prefetch hits",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCH_MISS",

     .udesc  = "L2 prefetch misses",

     .ucode = 0x8000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "PREFETCHES",

     .udesc  = "All L2 prefetches",

     .ucode = 0xc000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "RFO_HIT",

     .udesc  = "L2 RFO hits",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "RFO_MISS",

     .udesc  = "L2 RFO misses",

     .ucode = 0x800,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "RFOS",

     .udesc  = "L2 RFO requests",

     .ucode = 0xc00,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t nhm_l2_transactions[]={

   { .uname  = "ANY",

     .udesc  = "All L2 transactions",

     .ucode = 0x8000,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "FILL",

     .udesc  = "L2 fill transactions",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "IFETCH",

     .udesc  = "L2 instruction fetch transactions",

     .ucode = 0x400,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "L1D_WB",

     .udesc  = "L1D writeback to L2 transactions",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,