/*

 * Copyright (c) 2011 Google, Inc

 * Contributed by Stephane Eranian <eranian@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 * This file is part of libpfm, a performance monitoring support library for

 * applications on Linux.

 *

 * This file has been automatically generated.

 *

 * PMU: core (Intel Core)

 */

static const intel_x86_umask_t core_rs_uops_dispatched_cycles[]={

   { .uname  = "PORT_0",

     .udesc  = "On port 0",

     .ucode = 0x100,

   },

   { .uname  = "PORT_1",

     .udesc  = "On port 1",

     .ucode = 0x200,

   },

   { .uname  = "PORT_2",

     .udesc  = "On port 2",

     .ucode = 0x400,

   },

   { .uname  = "PORT_3",

     .udesc  = "On port 3",

     .ucode = 0x800,

   },

   { .uname  = "PORT_4",

     .udesc  = "On port 4",

     .ucode = 0x1000,

   },

   { .uname  = "PORT_5",

     .udesc  = "On port 5",

     .ucode = 0x2000,

   },

   { .uname  = "ANY",

     .udesc  = "On any port",

     .uequiv = "PORT_0:PORT_1:PORT_2:PORT_3:PORT_4:PORT_5",

     .ucode = 0x3f00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t core_load_block[]={

   { .uname  = "STA",

     .udesc  = "Loads blocked by a preceding store with unknown address",

     .ucode = 0x200,

   },

   { .uname  = "STD",

     .udesc  = "Loads blocked by a preceding store with unknown data",

     .ucode = 0x400,

   },

   { .uname  = "OVERLAP_STORE",

     .udesc  = "Loads that partially overlap an earlier store, or 4K equived with a previous store",

     .ucode = 0x800,

   },

   { .uname  = "UNTIL_RETIRE",

     .udesc  = "Loads blocked until retirement",

     .ucode = 0x1000,

   },

   { .uname  = "L1D",

     .udesc  = "Loads blocked by the L1 data cache",

     .ucode = 0x2000,

   },

};

static const intel_x86_umask_t core_store_block[]={

   { .uname  = "ORDER",

     .udesc  = "Cycles while store is waiting for a preceding store to be globally observed",

     .ucode = 0x200,

   },

   { .uname  = "SNOOP",

     .udesc  = "A store is blocked due to a conflict with an external or internal snoop",

     .ucode = 0x800,

   },

};

static const intel_x86_umask_t core_sse_pre_exec[]={

   { .uname  = "NTA",

     .udesc  = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "L1",

     .udesc  = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "L2",

     .udesc  = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "STORES",

     .udesc  = "Streaming SIMD Extensions (SSE) Weakly-ordered store instructions executed",

     .ucode = 0x300,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t core_dtlb_misses[]={

   { .uname  = "ANY",

     .udesc  = "Any memory access that missed the DTLB",

     .ucode = 0x100,

     .uflags= INTEL_X86_DFL,

   },

   { .uname  = "MISS_LD",

     .udesc  = "DTLB misses due to load operations",

     .ucode = 0x200,

   },

   { .uname  = "L0_MISS_LD",

     .udesc  = "L0 DTLB misses due to load operations",

     .ucode = 0x400,

   },

   { .uname  = "MISS_ST",

     .udesc  = "DTLB misses due to store operations",

     .ucode = 0x800,

   },

};

static const intel_x86_umask_t core_memory_disambiguation[]={

   { .uname  = "RESET",

     .udesc  = "Memory disambiguation reset cycles",

     .ucode = 0x100,

   },

   { .uname  = "SUCCESS",

     .udesc  = "Number of loads that were successfully disambiguated",

     .ucode = 0x200,

   },

};

static const intel_x86_umask_t core_page_walks[]={

   { .uname  = "COUNT",

     .udesc  = "Number of page-walks executed",

     .ucode = 0x100,

   },

   { .uname  = "CYCLES",

     .udesc  = "Duration of page-walks in core cycles",

     .ucode = 0x200,

   },

};

static const intel_x86_umask_t core_delayed_bypass[]={

   { .uname  = "FP",

     .udesc  = "Delayed bypass to FP operation",

     .ucode = 0x0,

   },

   { .uname  = "SIMD",

     .udesc  = "Delayed bypass to SIMD operation",

     .ucode = 0x100,

   },

   { .uname  = "LOAD",

     .udesc  = "Delayed bypass to load operation",

     .ucode = 0x200,

   },

};

static const intel_x86_umask_t core_l2_ads[]={

   { .uname  = "SELF",

     .udesc  = "This core",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "BOTH_CORES",

     .udesc  = "Both cores",

     .ucode = 0xc000,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t core_l2_lines_in[]={

   { .uname  = "SELF",

     .udesc  = "This core",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 0,

   },

   { .uname  = "BOTH_CORES",

     .udesc  = "Both cores",

     .ucode = 0xc000,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 0,

   },

   { .uname  = "ANY",

     .udesc  = "All inclusive",

     .ucode = 0x3000,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 1,

   },

   { .uname  = "PREFETCH",

     .udesc  = "Hardware prefetch only",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 1,

   },

   { .uname  = "EXCL_PREFETCH",

     .udesc  = "Exclude hardware prefetch",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 1,

   },

};

static const intel_x86_umask_t core_l2_ifetch[]={

   { .uname  = "SELF",

     .udesc  = "This core",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 0,

   },

   { .uname  = "BOTH_CORES",

     .udesc  = "Both cores",

     .ucode = 0xc000,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 0,

   },

   { .uname  = "MESI",

     .udesc  = "Any cacheline access",

     .uequiv = "M_STATE:E_STATE:S_STATE:I_STATE",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 1,

   },

   { .uname  = "I_STATE",

     .udesc  = "Invalid cacheline",

     .ucode = 0x100,

     .grpid = 1,

   },

   { .uname  = "S_STATE",

     .udesc  = "Shared cacheline",

     .ucode = 0x200,

     .grpid = 1,

   },

   { .uname  = "E_STATE",

     .udesc  = "Exclusive cacheline",

     .ucode = 0x400,

     .grpid = 1,

   },

   { .uname  = "M_STATE",

     .udesc  = "Modified cacheline",

     .ucode = 0x800,

     .grpid = 1,

   },

};

static const intel_x86_umask_t core_l2_ld[]={

   { .uname  = "SELF",

     .udesc  = "This core",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 0,

   },

   { .uname  = "BOTH_CORES",

     .udesc  = "Both cores",

     .ucode = 0xc000,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 0,

   },

   { .uname  = "ANY",

     .udesc  = "All inclusive",

     .ucode = 0x3000,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 1,

   },

   { .uname  = "PREFETCH",

     .udesc  = "Hardware prefetch only",

     .ucode = 0x1000,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 1,

   },

   { .uname  = "EXCL_PREFETCH",

     .udesc  = "Exclude hardware prefetch",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 1,

   },

   { .uname  = "MESI",

     .udesc  = "Any cacheline access",

     .uequiv = "M_STATE:E_STATE:S_STATE:I_STATE",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 2,

   },

   { .uname  = "I_STATE",

     .udesc  = "Invalid cacheline",

     .ucode = 0x100,

     .grpid = 2,

   },

   { .uname  = "S_STATE",

     .udesc  = "Shared cacheline",

     .ucode = 0x200,

     .grpid = 2,

   },

   { .uname  = "E_STATE",

     .udesc  = "Exclusive cacheline",

     .ucode = 0x400,

     .grpid = 2,

   },

   { .uname  = "M_STATE",

     .udesc  = "Modified cacheline",

     .ucode = 0x800,

     .grpid = 2,

   },

};

static const intel_x86_umask_t core_cpu_clk_unhalted[]={

   { .uname  = "CORE_P",

     .udesc  = "Core cycles when core is not halted",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "BUS",

     .udesc  = "Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio",

     .ucode = 0x100,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "NO_OTHER",

     .udesc  = "Bus cycles when core is active and the other is halted",

     .ucode = 0x200,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t core_l1d_cache_ld[]={

   { .uname  = "MESI",

     .udesc  = "Any cacheline access",

     .uequiv = "M_STATE:E_STATE:S_STATE:I_STATE",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "I_STATE",

     .udesc  = "Invalid cacheline",

     .ucode = 0x100,

   },

   { .uname  = "S_STATE",

     .udesc  = "Shared cacheline",

     .ucode = 0x200,

   },

   { .uname  = "E_STATE",

     .udesc  = "Exclusive cacheline",

     .ucode = 0x400,

   },

   { .uname  = "M_STATE",

     .udesc  = "Modified cacheline",

     .ucode = 0x800,

   },

};

static const intel_x86_umask_t core_l1d_split[]={

   { .uname  = "LOADS",

     .udesc  = "Cache line split loads from the L1 data cache",

     .ucode = 0x100,

   },

   { .uname  = "STORES",

     .udesc  = "Cache line split stores to the L1 data cache",

     .ucode = 0x200,

   },

};

static const intel_x86_umask_t core_sse_pre_miss[]={

   { .uname  = "NTA",

     .udesc  = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions missing all cache levels",

     .ucode = 0x0,

   },

   { .uname  = "L1",

     .udesc  = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions missing all cache levels",

     .ucode = 0x100,

   },

   { .uname  = "L2",

     .udesc  = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions missing all cache levels",

     .ucode = 0x200,

   },

};

static const intel_x86_umask_t core_l1d_prefetch[]={

   { .uname  = "REQUESTS",

     .udesc  = "L1 data cache prefetch requests",

     .ucode = 0x1000,

     .uflags= INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t core_bus_request_outstanding[]={

   { .uname  = "SELF",

     .udesc  = "This core",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 0,

   },

   { .uname  = "BOTH_CORES",

     .udesc  = "Both cores",

     .ucode = 0xc000,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 0,

   },

   { .uname  = "THIS_AGENT",

     .udesc  = "This agent",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 1,

   },

   { .uname  = "ALL_AGENTS",

     .udesc  = "Any agent on the bus",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 1,

   },

};

static const intel_x86_umask_t core_bus_bnr_drv[]={

   { .uname  = "THIS_AGENT",

     .udesc  = "This agent",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "ALL_AGENTS",

     .udesc  = "Any agent on the bus",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t core_ext_snoop[]={

   { .uname  = "ANY",

     .udesc  = "Any external snoop response",

     .ucode = 0xb00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 0,

   },

   { .uname  = "CLEAN",

     .udesc  = "External snoop CLEAN response",

     .ucode = 0x100,

     .grpid = 0,

   },

   { .uname  = "HIT",

     .udesc  = "External snoop HIT response",

     .ucode = 0x200,

     .grpid = 0,

   },

   { .uname  = "HITM",

     .udesc  = "External snoop HITM response",

     .ucode = 0x800,

     .grpid = 0,

   },

   { .uname  = "THIS_AGENT",

     .udesc  = "This agent",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 1,

   },

   { .uname  = "ALL_AGENTS",

     .udesc  = "Any agent on the bus",

     .ucode = 0x2000,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 1,

   },

};

static const intel_x86_umask_t core_cmp_snoop[]={

   { .uname  = "ANY",

     .udesc  = "L1 data cache is snooped by other core",

     .ucode = 0x300,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 0,

   },

   { .uname  = "SHARE",

     .udesc  = "L1 data cache is snooped for sharing by other core",

     .ucode = 0x100,

     .grpid = 0,

   },

   { .uname  = "INVALIDATE",

     .udesc  = "L1 data cache is snooped for Invalidation by other core",

     .ucode = 0x200,

     .grpid = 0,

   },

   { .uname  = "SELF",

     .udesc  = "This core",

     .ucode = 0x4000,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

     .grpid = 1,

   },

   { .uname  = "BOTH_CORES",

     .udesc  = "Both cores",

     .ucode = 0xc000,

     .uflags= INTEL_X86_NCOMBO,

     .grpid = 1,

   },

};

static const intel_x86_umask_t core_itlb[]={

   { .uname  = "SMALL_MISS",

     .udesc  = "ITLB small page misses",

     .ucode = 0x200,

   },

   { .uname  = "LARGE_MISS",

     .udesc  = "ITLB large page misses",

     .ucode = 0x1000,

   },

   { .uname  = "FLUSH",

     .udesc  = "ITLB flushes",

     .ucode = 0x4000,

   },

   { .uname  = "MISSES",

     .udesc  = "ITLB misses",

     .ucode = 0x1200,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t core_inst_queue[]={

   { .uname  = "FULL",

     .udesc  = "Cycles during which the instruction queue is full",

     .ucode = 0x200,

     .uflags= INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t core_macro_insts[]={

   { .uname  = "DECODED",

     .udesc  = "Instructions decoded",

     .ucode = 0x100,

   },

   { .uname  = "CISC_DECODED",

     .udesc  = "CISC instructions decoded",

     .ucode = 0x800,

   },

};

static const intel_x86_umask_t core_esp[]={

   { .uname  = "SYNCH",

     .udesc  = "ESP register content synchronization",

     .ucode = 0x100,

   },

   { .uname  = "ADDITIONS",

     .udesc  = "ESP register automatic additions",

     .ucode = 0x200,

   },

};

static const intel_x86_umask_t core_simd_uop_type_exec[]={

   { .uname  = "MUL",

     .udesc  = "SIMD packed multiply micro-ops executed",

     .ucode = 0x100,

   },

   { .uname  = "SHIFT",

     .udesc  = "SIMD packed shift micro-ops executed",

     .ucode = 0x200,

   },

   { .uname  = "PACK",

     .udesc  = "SIMD pack micro-ops executed",

     .ucode = 0x400,

   },

   { .uname  = "UNPACK",

     .udesc  = "SIMD unpack micro-ops executed",

     .ucode = 0x800,

   },

   { .uname  = "LOGICAL",

     .udesc  = "SIMD packed logical micro-ops executed",

     .ucode = 0x1000,

   },

   { .uname  = "ARITHMETIC",

     .udesc  = "SIMD packed arithmetic micro-ops executed",

     .ucode = 0x2000,

   },

};

static const intel_x86_umask_t core_inst_retired[]={

   { .uname  = "ANY_P",

     .udesc  = "Instructions retired (Precise Event)",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL,

   },

   { .uname  = "LOADS",

     .udesc  = "Instructions retired, which contain a load",

     .ucode = 0x100,

   },

   { .uname  = "STORES",

     .udesc  = "Instructions retired, which contain a store",

     .ucode = 0x200,

   },

   { .uname  = "OTHER",

     .udesc  = "Instructions retired, with no load or store operation",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t core_x87_ops_retired[]={

   { .uname  = "FXCH",

     .udesc  = "FXCH instructions retired",

     .ucode = 0x100,

   },

   { .uname  = "ANY",

     .udesc  = "Retired floating-point computational operations (Precise Event)",

     .ucode = 0xfe00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t core_uops_retired[]={

   { .uname  = "LD_IND_BR",

     .udesc  = "Fused load+op or load+indirect branch retired",

     .ucode = 0x100,

   },

   { .uname  = "STD_STA",

     .udesc  = "Fused store address + data retired",

     .ucode = 0x200,

   },

   { .uname  = "MACRO_FUSION",

     .udesc  = "Retired instruction pairs fused into one micro-op",

     .ucode = 0x400,

   },

   { .uname  = "NON_FUSED",

     .udesc  = "Non-fused micro-ops retired",

     .ucode = 0x800,

   },

   { .uname  = "FUSED",

     .udesc  = "Fused micro-ops retired",

     .ucode = 0x700,

     .uflags= INTEL_X86_NCOMBO,

   },

   { .uname  = "ANY",

     .udesc  = "Micro-ops retired",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t core_machine_nukes[]={

   { .uname  = "SMC",

     .udesc  = "Self-Modifying Code detected",

     .ucode = 0x100,

   },

   { .uname  = "MEM_ORDER",

     .udesc  = "Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction",

     .ucode = 0x400,

   },

};

static const intel_x86_umask_t core_br_inst_retired[]={

   { .uname  = "ANY",

     .udesc  = "Retired branch instructions",

     .ucode = 0x0,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

   { .uname  = "PRED_NOT_TAKEN",

     .udesc  = "Retired branch instructions that were predicted not-taken",

     .ucode = 0x100,

   },

   { .uname  = "MISPRED_NOT_TAKEN",

     .udesc  = "Retired branch instructions that were mispredicted not-taken",

     .ucode = 0x200,

   },

   { .uname  = "PRED_TAKEN",

     .udesc  = "Retired branch instructions that were predicted taken",

     .ucode = 0x400,

   },

   { .uname  = "MISPRED_TAKEN",

     .udesc  = "Retired branch instructions that were mispredicted taken",

     .ucode = 0x800,

   },

   { .uname  = "TAKEN",

     .udesc  = "Retired taken branch instructions",

     .ucode = 0xc00,

     .uflags= INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t core_simd_inst_retired[]={

   { .uname  = "PACKED_SINGLE",

     .udesc  = "Retired Streaming SIMD Extensions (SSE) packed-single instructions",

     .ucode = 0x100,

   },

   { .uname  = "SCALAR_SINGLE",

     .udesc  = "Retired Streaming SIMD Extensions (SSE) scalar-single instructions",

     .ucode = 0x200,

   },

   { .uname  = "PACKED_DOUBLE",

     .udesc  = "Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions",

     .ucode = 0x400,

   },

   { .uname  = "SCALAR_DOUBLE",

     .udesc  = "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions",

     .ucode = 0x800,

   },

   { .uname  = "VECTOR",

     .udesc  = "Retired Streaming SIMD Extensions 2 (SSE2) vector integer instructions",

     .ucode = 0x1000,

   },

   { .uname  = "ANY",

     .udesc  = "Retired Streaming SIMD instructions (Precise Event)",

     .ucode = 0x1f00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t core_simd_comp_inst_retired[]={

   { .uname  = "PACKED_SINGLE",

     .udesc  = "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions",

     .ucode = 0x100,

   },

   { .uname  = "SCALAR_SINGLE",

     .udesc  = "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions",

     .ucode = 0x200,

   },

   { .uname  = "PACKED_DOUBLE",

     .udesc  = "Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions",

     .ucode = 0x400,

   },

   { .uname  = "SCALAR_DOUBLE",

     .udesc  = "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions",

     .ucode = 0x800,

   },

};

static const intel_x86_umask_t core_mem_load_retired[]={

   { .uname  = "L1D_MISS",

     .udesc  = "Retired loads that miss the L1 data cache (Precise Event)",

     .ucode = 0x100,

     .uflags= INTEL_X86_PEBS,

   },

   { .uname  = "L1D_LINE_MISS",

     .udesc  = "L1 data cache line missed by retired loads (Precise Event)",

     .ucode = 0x200,

     .uflags= INTEL_X86_PEBS,

   },

   { .uname  = "L2_MISS",

     .udesc  = "Retired loads that miss the L2 cache (Precise Event)",

     .ucode = 0x400,

     .uflags= INTEL_X86_PEBS,

   },

   { .uname  = "L2_LINE_MISS",

     .udesc  = "L2 cache line missed by retired loads (Precise Event)",

     .ucode = 0x800,

     .uflags= INTEL_X86_PEBS,

   },

   { .uname  = "DTLB_MISS",

     .udesc  = "Retired loads that miss the DTLB (Precise Event)",

     .ucode = 0x1000,

     .uflags= INTEL_X86_PEBS,

   },

};

static const intel_x86_umask_t core_fp_mmx_trans[]={

   { .uname  = "TO_FP",

     .udesc  = "Transitions from MMX (TM) Instructions to Floating Point Instructions",

     .ucode = 0x200,

   },

   { .uname  = "TO_MMX",

     .udesc  = "Transitions from Floating Point to MMX (TM) Instructions",

     .ucode = 0x100,

   },

};

static const intel_x86_umask_t core_rat_stalls[]={

   { .uname  = "ROB_READ_PORT",

     .udesc  = "ROB read port stalls cycles",

     .ucode = 0x100,

   },

   { .uname  = "PARTIAL_CYCLES",

     .udesc  = "Partial register stall cycles",

     .ucode = 0x200,

   },

   { .uname  = "FLAGS",

     .udesc  = "Flag stall cycles",

     .ucode = 0x400,

   },

   { .uname  = "FPSW",

     .udesc  = "FPU status word stall",

     .ucode = 0x800,

   },

   { .uname  = "ANY",

     .udesc  = "All RAT stall cycles",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t core_seg_rename_stalls[]={

   { .uname  = "ES",

     .udesc  = "Segment rename stalls - ES ",

     .ucode = 0x100,

   },

   { .uname  = "DS",

     .udesc  = "Segment rename stalls - DS",

     .ucode = 0x200,

   },

   { .uname  = "FS",

     .udesc  = "Segment rename stalls - FS",

     .ucode = 0x400,

   },

   { .uname  = "GS",

     .udesc  = "Segment rename stalls - GS",

     .ucode = 0x800,

   },

   { .uname  = "ANY",

     .udesc  = "Any (ES/DS/FS/GS) segment rename stall",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t core_seg_reg_renames[]={

   { .uname  = "ES",

     .udesc  = "Segment renames - ES",

     .ucode = 0x100,

   },

   { .uname  = "DS",

     .udesc  = "Segment renames - DS",

     .ucode = 0x200,

   },

   { .uname  = "FS",

     .udesc  = "Segment renames - FS",

     .ucode = 0x400,

   },

   { .uname  = "GS",

     .udesc  = "Segment renames - GS",

     .ucode = 0x800,

   },

   { .uname  = "ANY",

     .udesc  = "Any (ES/DS/FS/GS) segment rename",

     .ucode = 0xf00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_umask_t core_resource_stalls[]={

   { .uname  = "ROB_FULL",

     .udesc  = "Cycles during which the ROB is full",

     .ucode = 0x100,

   },

   { .uname  = "RS_FULL",

     .udesc  = "Cycles during which the RS is full",

     .ucode = 0x200,

   },

   { .uname  = "LD_ST",

     .udesc  = "Cycles during which the pipeline has exceeded load or store limit or waiting to commit all stores",

     .ucode = 0x400,

   },

   { .uname  = "FPCW",

     .udesc  = "Cycles stalled due to FPU control word write",

     .ucode = 0x800,

   },

   { .uname  = "BR_MISS_CLEAR",

     .udesc  = "Cycles stalled due to branch misprediction",

     .ucode = 0x1000,

   },

   { .uname  = "ANY",

     .udesc  = "Resource related stalls",

     .ucode = 0x1f00,

     .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

   },

};

static const intel_x86_entry_t intel_core_pe[]={

{ .name   = "UNHALTED_CORE_CYCLES",

  .desc   = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)",

  .modmsk = INTEL_X86_ATTRS,

  .cntmsk = 0x200000003ull,

  .code = 0x3c,

},