/*

 * Contributed by Stephane Eranian <eranian@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 * This file is part of libpfm, a performance monitoring support library for

 * applications on Linux.

 *

 * PMU: bdw (Intel Broadwell)

 */

static const intel_x86_umask_t bdw_baclears[]={

  { .uname = "ANY",

    .udesc  = "Number of front-end re-steers due to BPU misprediction",

    .ucode  = 0x1f00,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t bdw_br_inst_exec[]={

  { .uname = "NONTAKEN_CONDITIONAL",

    .udesc  = "All macro conditional nontaken branch instructions",

    .ucode  = 0x4100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "NONTAKEN_COND",

    .udesc  = "All macro conditional nontaken branch instructions",

    .ucode  = 0x4100,

    .uequiv = "NONTAKEN_CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_CONDITIONAL",

    .udesc  = "Taken speculative and retired macro-conditional branches",

    .ucode  = 0x8100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_COND",

    .udesc  = "Taken speculative and retired macro-conditional branches",

    .ucode  = 0x8100,

    .uequiv = "TAKEN_CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_DIRECT_JUMP",

    .udesc  = "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

    .ucode  = 0x8200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET",

    .udesc  = "Taken speculative and retired indirect branches excluding calls and returns",

    .ucode  = 0x8400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_INDIRECT_NEAR_RETURN",

    .udesc  = "Taken speculative and retired indirect branches with return mnemonic",

    .ucode  = 0x8800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_DIRECT_NEAR_CALL",

    .udesc  = "Taken speculative and retired direct near calls",

    .ucode  = 0x9000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_CONDITIONAL",

    .udesc  = "Speculative and retired macro-conditional branches",

    .ucode  = 0xc100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_COND",

    .udesc  = "Speculative and retired macro-conditional branches",

    .ucode  = 0xc100,

    .uequiv = "ALL_CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ANY_COND",

    .udesc  = "Speculative and retired macro-conditional branches",

    .ucode  = 0xc100,

    .uequiv = "ALL_CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_DIRECT_JMP",

    .udesc  = "Speculative and retired macro-unconditional branches excluding calls and indirects",

    .ucode  = 0xc200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_INDIRECT_JUMP_NON_CALL_RET",

    .udesc  = "Speculative and retired indirect branches excluding calls and returns",

    .ucode  = 0xc400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_INDIRECT_NEAR_RETURN",

    .udesc  = "Speculative and retired indirect return branches",

    .ucode  = 0xc800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_DIRECT_NEAR_CALL",

    .udesc  = "Speculative and retired direct near calls",

    .ucode  = 0xd000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_INDIRECT_NEAR_CALL",

    .udesc  = "All indirect calls, including both register and memory indirect",

    .ucode  = 0xa000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_BRANCHES",

    .udesc  = "All branch instructions executed",

    .ucode  = 0xff00,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t bdw_br_inst_retired[]={

  { .uname = "CONDITIONAL",

    .udesc  = "Counts all taken and not taken macro conditional branch instructions",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "COND",

    .udesc  = "Counts all taken and not taken macro conditional branch instructions",

    .ucode  = 0x100,

    .uequiv = "CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "NEAR_CALL",

    .udesc  = "Counts all macro direct and indirect near calls",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "ALL_BRANCHES",

    .udesc  = "Counts all taken and not taken macro branches including far branches (architectural event)",

    .ucode  = 0x0,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_PEBS,

  },

  { .uname = "NEAR_RETURN",

    .udesc  = "Counts the number of near ret instructions retired",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "NOT_TAKEN",

    .udesc  = "Counts all not taken macro branch instructions retired",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "NEAR_TAKEN",

    .udesc  = "Counts the number of near branch taken instructions retired",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "FAR_BRANCH",

    .udesc  = "Counts the number of far branch instructions retired",

    .ucode  = 0x4000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

};

static const intel_x86_umask_t bdw_br_misp_exec[]={

  { .uname = "NONTAKEN_CONDITIONAL",

    .udesc  = "Not taken speculative and retired mispredicted macro conditional branches",

    .ucode  = 0x4100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "NONTAKEN_COND",

    .udesc  = "Not taken speculative and retired mispredicted macro conditional branches",

    .ucode  = 0x4100,

    .uequiv = "NONTAKEN_CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_CONDITIONAL",

    .udesc  = "Taken speculative and retired mispredicted macro conditional branches",

    .ucode  = 0x8100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_COND",

    .udesc  = "Taken speculative and retired mispredicted macro conditional branches",

    .ucode  = 0x8100,

    .uequiv = "TAKEN_CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET",

    .udesc  = "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

    .ucode  = 0x8400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_CONDITIONAL",

    .udesc  = "Speculative and retired mispredicted macro conditional branches",

    .ucode  = 0xc100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ANY_COND",

    .udesc  = "Speculative and retired mispredicted macro conditional branches",

    .ucode  = 0xc100,

    .uequiv = "ALL_CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_INDIRECT_JUMP_NON_CALL_RET",

    .udesc  = "All mispredicted indirect branches that are not calls nor returns",

    .ucode  = 0xc400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL_BRANCHES",

    .udesc  = "Speculative and retired mispredicted macro conditional branches",

    .ucode  = 0xff00,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

  { .uname = "TAKEN_INDIRECT_NEAR_CALL",

    .udesc  = "Taken speculative and retired mispredicted indirect calls",

    .ucode  = 0xa000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "TAKEN_RETURN_NEAR",

    .udesc  = "Taken speculative and retired mispredicted direct returns",

    .ucode  = 0x8800,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t bdw_br_misp_retired[]={

  { .uname = "CONDITIONAL",

    .udesc  = "All mispredicted macro conditional branch instructions",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "COND",

    .udesc  = "All mispredicted macro conditional branch instructions",

    .ucode  = 0x100,

    .uequiv = "CONDITIONAL",

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "ALL_BRANCHES",

    .udesc  = "All mispredicted macro branches (architectural event)",

    .ucode  = 0x0, /* architectural encoding */

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL,

  },

  { .uname = "NEAR_TAKEN",

    .udesc  = "Number of near branch instructions retired that were mispredicted and taken",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "RET",

    .udesc  = "Number of mispredicted ret instructions retired",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

};

static const intel_x86_umask_t bdw_cpl_cycles[]={

  { .uname = "RING0",

    .udesc  = "Unhalted core cycles when the thread is in ring 0",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "RING123",

    .udesc  = "Unhalted core cycles when thread is in rings 1, 2, or 3",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "RING0_TRANS",

    .udesc  = "Number of intervals between processor halts while thread is in ring 0",

    .ucode  = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

};

static const intel_x86_umask_t bdw_cpu_clk_thread_unhalted[]={

  { .uname = "REF_XCLK",

    .udesc  = "Count Xclk pulses (100Mhz) when the core is unhalted",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "REF_XCLK_ANY",

    .udesc  = "Count Xclk pulses (100Mhz) when the at least one thread on the physical core is unhalted",

    .ucode  = 0x100 | INTEL_X86_MOD_ANY, /* any=1 */

    .uequiv = "REF_XCLK:t",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_T,

  },

  { .uname  = "REF_P",

    .udesc  = "Cycles when the core is unhalted (count at 100 Mhz)",

    .ucode = 0x100,

    .uequiv = "REF_XCLK",

    .uflags= INTEL_X86_NCOMBO,

  },

  { .uname  = "THREAD_P",

    .udesc  = "Cycles when thread is not halted",

    .ucode = 0x000,

    .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

  { .uname = "ONE_THREAD_ACTIVE",

    .udesc  = "Counts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is halted",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t bdw_cycle_activity[]={

   { .uname  = "CYCLES_L2_PENDING",

     .udesc  = "Cycles with pending L2 miss loads (must use with HT off only)",

     .ucode  = 0x0100 | (0x1 << INTEL_X86_CMASK_BIT),

     .uflags = INTEL_X86_NCOMBO,

     .modhw  = _INTEL_X86_ATTR_C,

     .ucntmsk= 0xf,

   },

   { .uname  = "CYCLES_LDM_PENDING",

     .udesc  = "Cycles with pending memory loads",

     .ucode  = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uequiv = "CYCLES_MEM_ANY",

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "CYCLES_MEM_ANY",

     .udesc  = "Cycles with pending memory loads",

     .ucode  = 0x0200 | (0x2 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "CYCLES_L1D_PENDING",

     .udesc  = "Cycles with pending L1D load cache misses",

     .ucode  = 0x0800 | (0x8 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .ucntmsk= 0x4,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "STALLS_LDM_PENDING",

     .udesc  = "Executions stalls when there is at least one pending demand load request",

     .ucode  = 0x0600 | (0x6 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .ucntmsk= 0x4,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "STALLS_L1D_PENDING",

     .udesc  = "Executions stalls while there is at least one L1D demand load outstanding",

     .ucode  = 0x0c00 | (0xc << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .ucntmsk= 0x4,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "STALLS_L2_PENDING",

     .udesc  = "Execution stalls while there is at least one L2 demand load pending outstanding",

     .ucode  = 0x0500 | (0x5 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .ucntmsk= 0xf,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "STALLS_TOTAL",

     .udesc  = "Cycles during which no instructions were executed in the execution stage of the pipeline",

     .ucode  = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .ucntmsk= 0xf,

     .uflags = INTEL_X86_NCOMBO,

   },

   { .uname  = "CYCLES_NO_EXECUTE",

     .udesc  = "Cycles during which no instructions were executed in the execution stage of the pipeline",

     .ucode  = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT),

     .modhw  = _INTEL_X86_ATTR_C,

     .uequiv = "STALLS_TOTAL",

     .ucntmsk= 0xf,

     .uflags = INTEL_X86_NCOMBO,

   },

};

static const intel_x86_umask_t bdw_dtlb_load_misses[]={

  { .uname = "MISS_CAUSES_A_WALK",

    .udesc  = "Misses in all DTLB levels that cause page walks",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_4K",

    .udesc  = "Misses in all TLB levels causes a page walk that completes (4K)",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_2M_4M",

    .udesc  = "Misses in all TLB levels causes a page walk of 2MB/4MB page sizes that completes",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_1G",

    .udesc  = "Misses in all TLB levels causes a page walk of 1GB page sizes that completes",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED",

    .udesc  = "Misses in all TLB levels causes a page walk of any page size that completes",

    .ucode  = 0xe00,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_DURATION",

    .udesc  = "Cycles when PMH is busy with page walks",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "STLB_HIT_4K",

    .udesc  = "Misses that miss the DTLB and hit the STLB (4KB)",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "STLB_HIT_2M",

    .udesc  = "Misses that miss the DTLB and hit the STLB (2MB)",

    .ucode  = 0x4000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "STLB_HIT",

    .udesc  = "Number of cache load STLB hits. No page walk",

    .ucode  = 0x6000,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t bdw_itlb_misses[]={

  { .uname = "MISS_CAUSES_A_WALK",

    .udesc  = "Misses in all DTLB levels that cause page walks",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_4K",

    .udesc  = "Misses in all TLB levels causes a page walk that completes (4KB)",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_2M_4M",

    .udesc  = "Misses in all TLB levels causes a page walk that completes (2MB/4MB)",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED_1G",

    .udesc  = "Misses in all TLB levels causes a page walk that completes (1GB)",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_COMPLETED",

    .udesc  = "Misses in all TLB levels causes a page walk of any page size that completes",

    .ucode  = 0xe00,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "WALK_DURATION",

    .udesc  = "Cycles when PMH is busy with page walks",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "STLB_HIT_4K",

    .udesc  = "Misses that miss the DTLB and hit the STLB (4KB)",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "STLB_HIT_2M",

    .udesc  = "Misses that miss the DTLB and hit the STLB (2MB)",

    .ucode  = 0x4000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "STLB_HIT",

    .udesc  = "Number of cache load STLB hits. No page walk",

    .ucode  = 0x6000,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t bdw_fp_assist[]={

  { .uname = "X87_OUTPUT",

    .udesc  = "Number of X87 FP assists due to output values",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "X87_INPUT",

    .udesc  = "Number of X87 FP assists due to input values",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "SIMD_OUTPUT",

    .udesc  = "Number of SIMD FP assists due to output values",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "SIMD_INPUT",

    .udesc  = "Number of SIMD FP assists due to input values",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ANY",

    .udesc  = "Cycles with any input/output SEE or FP assists",

    .ucode  = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL",

    .udesc  = "Cycles with any input and output SSE or FP assist",

    .ucode  = 0x1e00 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "ANY",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

};

static const intel_x86_umask_t bdw_icache[]={

  { .uname = "MISSES",

    .udesc  = "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "IFDATA_STALL",

    .udesc  = "Number of cycles where a code fetch is stalled due to L1 miss",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "HIT",

    .udesc  = "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetches",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t bdw_idq[]={

  { .uname = "EMPTY",

    .udesc  = "Cycles the Instruction Decode Queue (IDQ) is empty",

    .ucode  = 0x200,

    .ucntmsk= 0xf,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MITE_UOPS",

    .udesc  = "Number of uops delivered to Instruction Decode Queue (IDQ) from MITE path",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "DSB_UOPS",

    .udesc  = "Number of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MS_DSB_UOPS",

    .udesc  = "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MS_MITE_UOPS",

    .udesc  = "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

    .ucode  = 0x2000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MS_UOPS",

    .udesc  = "Number of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITE",

    .ucode  = 0x3000,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "MS_UOPS_CYCLES",

    .udesc  = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE",

    .ucode  = 0x3000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "MS_UOPS:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "MS_SWITCHES",

    .udesc  = "Number of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITE",

    .ucode  = 0x3000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "MS_UOPS:c=1:e",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

  { .uname = "MITE_UOPS_CYCLES",

    .udesc  = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

    .ucode  = 0x400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "MITE_UOPS:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "DSB_UOPS_CYCLES",

    .udesc  = "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

    .ucode  = 0x800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "DSB_UOPS:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "MS_DSB_UOPS_CYCLES",

    .udesc  = "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

    .ucode  = 0x1000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "MS_DSB_UOPS:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "MS_DSB_OCCUR",

    .udesc  = "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",

    .ucode  = 0x1000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "MS_DSB_UOPS:c=1:e=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_DSB_CYCLES_4_UOPS",

    .udesc  = "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

    .ucode  = 0x1800 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_DSB_CYCLES_ANY_UOPS",

    .udesc  = "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

    .ucode  = 0x1800 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_MITE_CYCLES_4_UOPS",

    .udesc  = "Cycles MITE is delivering 4 Uops",

    .ucode  = 0x2400 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_MITE_CYCLES_ANY_UOPS",

    .udesc  = "Cycles MITE is delivering any Uop",

    .ucode  = 0x2400 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "ALL_MITE_UOPS",

    .udesc  = "Number of uops delivered to Instruction Decode Queue (IDQ) from any path",

    .ucode  = 0x3c00,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t bdw_idq_uops_not_delivered[]={

  { .uname = "CORE",

    .udesc  = "Count number of non-delivered uops to Resource Allocation Table (RAT)",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "CYCLES_0_UOPS_DELIV_CORE",

    .udesc  = "Cycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled",

    .ucode  = 0x100 | (4 << INTEL_X86_CMASK_BIT), /* cnt=4 */

    .uflags = INTEL_X86_NCOMBO,

    .uequiv = "CORE:c=4",

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "CYCLES_LE_1_UOP_DELIV_CORE",

    .udesc  = "Cycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalled",

    .ucode  = 0x100 | (3 << INTEL_X86_CMASK_BIT), /* cnt=3 */

    .uequiv = "CORE:c=3",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "CYCLES_LE_2_UOP_DELIV_CORE",

    .udesc  = "Cycles with less than 2 uops delivered by the front end",

    .ucode  = 0x100 | (2 << INTEL_X86_CMASK_BIT), /* cnt=2 */

    .uequiv = "CORE:c=2",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "CYCLES_LE_3_UOP_DELIV_CORE",

    .udesc  = "Cycles with less than 3 uops delivered by the front end",

    .ucode  = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "CORE:c=1",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "CYCLES_FE_WAS_OK",

    .udesc  = "Cycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FE",

    .ucode  = 0x100 | INTEL_X86_MOD_INV | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 inv=1 */

    .uequiv = "CORE:c=1:i",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_I,

  },

};

static const intel_x86_umask_t bdw_inst_retired[]={

  { .uname = "ANY_P",

    .udesc  = "Number of instructions retired. General Counter - architectural event",

    .ucode  = 0x000,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

  { .uname = "ALL",

    .udesc  = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise Event)",

    .ucode  = 0x100,

    .uequiv = "PREC_DIST",

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "TOTAL_CYCLES",

    .udesc  = "Number of cycles using always true condition",

    .ucode  = 0x100 | INTEL_X86_MOD_INV | (10 << INTEL_X86_CMASK_BIT), /* inv=1 cnt=10 */

    .uequiv = "PREC_DIST:i=1:c=10",

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

    .modhw  = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C,

  },

  { .uname = "PREC_DIST",

    .udesc  = "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise event)",

    .ucode  = 0x100,

    .ucntmsk= 0x2,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS,

  },

  { .uname = "X87",

    .udesc  = "Number of FPU operations retired (instructions with no exceptions)",

    .ucode  = 0x200,

    .ucntmsk= 0x2,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t bdw_int_misc[]={

  { .uname = "RECOVERY_CYCLES",

    .udesc  = "Cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

    .ucode  = 0x300 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "RECOVERY_CYCLES_ANY",

    .udesc  = "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

    .ucode  = 0x300 | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, /* cnt=1 any=1 */

    .uequiv = "RECOVERY_CYCLES:t",

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T,

  },

  { .uname = "RECOVERY_STALLS_COUNT",

    .udesc  = "Number of occurrences waiting for Machine Clears",

    .ucode  = 0x300 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

  { .uname = "RAT_STALL_CYCLES",

    .udesc  = "Cycles when the Resource Allocation Table (RAT) external stall event is sent to the Instruction Decode Queue (IDQ) for the thread. Also includes cycles when the allocator is serving another thread",

    .ucode  = 0x800,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t bdw_itlb[]={

  { .uname = "ITLB_FLUSH",

    .udesc  = "Flushing of the Instruction TLB (ITLB) pages independent of page size",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t bdw_l1d[]={

  { .uname = "REPLACEMENT",

    .udesc  = "L1D Data line replacements",

    .ucode  = 0x100,

    .uflags = INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t bdw_sq_misc[]={

  { .uname = "SPLIT_LOCK",

    .udesc  = "Number of split locks in the super queue (SQ)",

    .ucode  = 0x1000,

    .uflags = INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t bdw_l1d_pend_miss[]={

  { .uname = "PENDING",

    .udesc  = "Cycles with L1D load misses outstanding",

    .ucode  = 0x100,

    .ucntmsk = 0x4,

    .uflags = INTEL_X86_DFL,

  },

  { .uname = "PENDING_CYCLES",

    .udesc  = "Cycles with L1D load misses outstanding",

    .ucode  = 0x100 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uequiv = "PENDING:c=1",

    .ucntmsk = 0x4,

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

  { .uname = "PENDING_CYCLES_ANY",

    .udesc  = "Cycles with L1D load misses outstanding from any thread",

    .ucode  = 0x100 | (1 << INTEL_X86_CMASK_BIT) | INTEL_X86_MOD_ANY, /* cnt=1 any=1 */

    .uequiv = "PENDING:c=1:t",

    .ucntmsk = 0x4,

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C | _INTEL_X86_ATTR_T,

  },

  { .uname = "OCCURRENCES",

    .udesc  = "Number L1D miss outstanding",

    .ucode  = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "PENDING:c=1:e=1",

    .ucntmsk = 0x4,

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

  { .uname = "EDGE",

    .udesc  = "Number L1D miss outstanding",

    .ucode  = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */

    .uequiv = "PENDING:c=1:e=1",

    .ucntmsk = 0x4,

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C,

  },

  { .uname = "FB_FULL",

    .udesc  = "Number of cycles a demand request was blocked due to Fill Buffer (FB) unavailability",

    .ucode  = 0x200 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */

    .uflags = INTEL_X86_NCOMBO,

    .modhw  = _INTEL_X86_ATTR_C,

  },

};

static const intel_x86_umask_t bdw_l2_demand_rqsts[]={

  { .uname = "WB_HIT",

    .udesc  = "WB requests that hit L2 cache",

    .ucode  = 0x5000,

    .uflags = INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t bdw_l2_lines_in[]={

  { .uname = "I",

    .udesc  = "L2 cache lines in I state filling L2",

    .ucode  = 0x100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "S",

    .udesc  = "L2 cache lines in S state filling L2",

    .ucode  = 0x200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "E",

    .udesc  = "L2 cache lines in E state filling L2",

    .ucode  = 0x400,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "ALL",

    .udesc  = "L2 cache lines filling L2",

    .ucode  = 0x700,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

  { .uname = "ANY",

    .udesc  = "L2 cache lines filling L2",

    .uequiv = "ALL",

    .ucode  = 0x700,

    .uflags = INTEL_X86_NCOMBO,

  },

};

static const intel_x86_umask_t bdw_l2_lines_out[]={

  { .uname = "DEMAND_CLEAN",

    .udesc  = "Number of clean L2 cachelines evicted by demand",

    .ucode  = 0x500,

    .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL,

  },

};

static const intel_x86_umask_t bdw_l2_rqsts[]={

  { .uname = "DEMAND_DATA_RD_MISS",

    .udesc  = "Demand Data Read requests that miss L2 cache",

    .ucode  = 0x2100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "DEMAND_DATA_RD_HIT",

    .udesc  = "Demand Data Read requests that hit L2 cache",

    .ucode  = 0x4100,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "DEMAND_RFO_MISS",

    .udesc  = "RFO requests that miss L2 cache",

    .ucode  = 0x2200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "RFO_MISS",

    .udesc  = "RFO requests that miss L2 cache",

    .ucode  = 0x2200,

    .uequiv = "DEMAND_RFO_MISS",

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "DEMAND_RFO_HIT",

    .udesc  = "RFO requests that hit L2 cache",

    .ucode  = 0x4200,

    .uflags = INTEL_X86_NCOMBO,

  },

  { .uname = "RFO_HIT",