/*

 * Copyright (c) 2007 TOSHIBA CORPORATION based on code from

 * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P.

 * Contributed by Stephane Eranian <eranian@hpl.hp.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

static pme_cell_entry_t cell_pe[] = {

	{.pme_name = "CYCLES",

	 .pme_desc = "CPU cycles",

	 .pme_code = 0x0, /* 0 */

	 .pme_enable_word = WORD_NONE,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "BRANCH_COMMIT_TH0",

	 .pme_desc = "Branch instruction committed.",

	 .pme_code = 0x834, /* 2100 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "BRANCH_FLUSH_TH0",

	 .pme_desc = "Branch instruction that caused a misprediction flush is committed. Branch misprediction includes",

	 .pme_code = 0x835, /* 2101 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "INST_BUFF_EMPTY_TH0",

	 .pme_desc = "Instruction buffer empty.",

	 .pme_code = 0x836, /* 2102 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "INST_ERAT_MISS_TH0",

	 .pme_desc = "Instruction effective-address-to-real-address translation (I-ERAT) miss.",

	 .pme_code = 0x837, /* 2103 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L1_ICACHE_MISS_CYCLES_TH0",

	 .pme_desc = "L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions.",

	 .pme_code = 0x838, /* 2104 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "DISPATCH_BLOCKED_TH0",

	 .pme_desc = "Valid instruction available for dispatch, but dispatch is blocked.",

	 .pme_code = 0x83a, /* 2106 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "INST_FLUSH_TH0",

	 .pme_desc = "Instruction in pipeline stage EX7 causes a flush.",

	 .pme_code = 0x83d, /* 2109 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "PPC_INST_COMMIT_TH0",

	 .pme_desc = "Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.",

	 .pme_code = 0x83f, /* 2111 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "BRANCH_COMMIT_TH1",

	 .pme_desc = "Branch instruction committed.",

	 .pme_code = 0x847, /* 2119 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "BRANCH_FLUSH_TH1",

	 .pme_desc = "Branch instruction that caused a misprediction flush is committed. Branch misprediction includes",

	 .pme_code = 0x848, /* 2120 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "INST_BUFF_EMPTY_TH1",

	 .pme_desc = "Instruction buffer empty.",

	 .pme_code = 0x849, /* 2121 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "INST_ERAT_MISS_TH1",

	 .pme_desc = "Instruction effective-address-to-real-address translation (I-ERAT) miss.",

	 .pme_code = 0x84a, /* 2122 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L1_ICACHE_MISS_CYCLES_TH1",

	 .pme_desc = "L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions.",

	 .pme_code = 0x84b, /* 2123 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "DISPATCH_BLOCKED_TH1",

	 .pme_desc = "Valid instruction available for dispatch, but dispatch is blocked.",

	 .pme_code = 0x84d, /* 2125 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "INST_FLUSH_TH1",

	 .pme_desc = "Instruction in pipeline stage EX7 causes a flush.",

	 .pme_code = 0x850, /* 2128 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "PPC_INST_COMMIT_TH1",

	 .pme_desc = "Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.",

	 .pme_code = 0x852, /* 2130 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "DATA_ERAT_MISS_TH0",

	 .pme_desc = "Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.",

	 .pme_code = 0x89a, /* 2202 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "ST_REQ_TH0",

	 .pme_desc = "Store request counted at the L2 interface. Counts microcoded PPE sequences more than once. (Thread 0 and 1)",

	 .pme_code = 0x89b, /* 2203 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "LD_VALID_TH0",

	 .pme_desc = "Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.",

	 .pme_code = 0x89c, /* 2204 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "L1_DCACHE_MISS_TH0",

	 .pme_desc = "L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.",

	 .pme_code = 0x89d, /* 2205 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "DATA_ERAT_MISS_TH1",

	 .pme_desc = "Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.",

	 .pme_code = 0x8aa, /* 2218 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "LD_VALID_TH1",

	 .pme_desc = "Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.",

	 .pme_code = 0x8ac, /* 2220 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "DATA_ERAT_MISS_TH1",

	 .pme_desc = "L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.",

	 .pme_code = 0x8ad, /* 2221 */

	 .pme_enable_word = WORD_0_AND_1,

	 .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "LD_MFC_MMIO",

	 .pme_desc = "Load from MFC memory-mapped I/O (MMIO) space.",

	 .pme_code = 0xc1c, /* 3100 */

	 .pme_enable_word = WORD_2_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "ST_MFC_MMIO",

	 .pme_desc = "Stores to MFC MMIO space.",

	 .pme_code = 0xc1d, /* 3101 */

	 .pme_enable_word = WORD_2_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "REQ_TOKEN_TYPE",

	 .pme_desc = "Request token for even memory bank numbers 0-14.",

	 .pme_code = 0xc22, /* 3106 */

	 .pme_enable_word = WORD_2_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "RCV_8BEAT_DATA",

	 .pme_desc = "Receive 8-beat data from the Element Interconnect Bus (EIB).",

	 .pme_code = 0xc2b, /* 3115 */

	 .pme_enable_word = WORD_2_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "SEND_8BEAT_DATA",

	 .pme_desc = "Send 8-beat data to the EIB.",

	 .pme_code = 0xc2c, /* 3116 */

	 .pme_enable_word = WORD_2_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "SEND_CMD",

	 .pme_desc = "Send a command to the EIB; includes retried commands.",

	 .pme_code = 0xc2d, /* 3117 */

	 .pme_enable_word = WORD_2_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "DATA_GRANT_CYCLES",

	 .pme_desc = "Cycles between data request and data grant.",

	 .pme_code = 0xc2e, /* 3118 */

	 .pme_enable_word = WORD_2_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "NCU_ST_Q_NOT_EMPTY_CYCLES",

	 .pme_desc = "The five-entry Non-Cacheable Unit (NCU) Store Command queue not empty.",

	 .pme_code = 0xc33, /* 3123 */

	 .pme_enable_word = WORD_2_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "L2_CACHE_HIT",

	 .pme_desc = "Cache hit for core interface unit (CIU) loads and stores.",

	 .pme_code = 0xc80, /* 3200 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_CACHE_MISS",

	 .pme_desc = "Cache miss for CIU loads and stores.",

	 .pme_code = 0xc81, /* 3201 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_LD_MISS",

	 .pme_desc = "CIU load miss.",

	 .pme_code = 0xc84, /* 3204 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_ST_MISS",

	 .pme_desc = "CIU store to Invalid state (miss).",

	 .pme_code = 0xc85, /* 3205 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_LWARX_LDARX_MISS_TH0",

	 .pme_desc = "Load word and reserve indexed (lwarx/ldarx) for Thread 0 hits Invalid cache state",

	 .pme_code = 0xc87, /* 3207 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_STWCX_STDCX_MISS_TH0",

	 .pme_desc = "Store word conditional indexed (stwcx/stdcx) for Thread 0 hits Invalid cache state when reservation is set.",

	 .pme_code = 0xc8e, /* 3214 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_ALL_SNOOP_SM_BUSY",

	 .pme_desc = "All four snoop state machines busy.",

	 .pme_code = 0xc99, /* 3225 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "L2_DCLAIM_GOOD",

	 .pme_desc = "Data line claim (dclaim) that received good combined response; includes store/stcx/dcbz to Shared (S), Shared Last (SL),or Tagged (T) cache state; does not include dcbz to Invalid (I) cache state.",

	 .pme_code = 0xce8, /* 3304 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_DCLAIM_TO_RWITM",

	 .pme_desc = "Dclaim converted into rwitm; may still not get to the bus if stcx is aborted .",

	 .pme_code = 0xcef, /* 3311 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_ST_TO_M_MU_E",

	 .pme_desc = "Store to modified (M), modified unsolicited (MU), or exclusive (E) cache state.",

	 .pme_code = 0xcf0, /* 3312 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_ST_Q_FULL",

	 .pme_desc = "8-entry store queue (STQ) full.",

	 .pme_code = 0xcf1, /* 3313 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "L2_ST_TO_RC_ACKED",

	 .pme_desc = "Store dispatched to RC machine is acknowledged.",

	 .pme_code = 0xcf2, /* 3314 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_GATHERABLE_ST",

	 .pme_desc = "Gatherable store (type = 00000) received from CIU.",

	 .pme_code = 0xcf3, /* 3315 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_SNOOP_PUSH",

	 .pme_desc = "Snoop push.",

	 .pme_code = 0xcf6, /* 3318 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_INTERVENTION_FROM_SL_E_SAME_MODE",

	 .pme_desc = "Send intervention from (SL | E) cache state to a destination within the same CBE chip.",

	 .pme_code = 0xcf7, /* 3319 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_INTERVENTION_FROM_M_MU_SAME_MODE",

	 .pme_desc = "Send intervention from (M | MU) cache state to a destination within the same CBE chip.",

	 .pme_code = 0xcf8, /* 3320 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_SNOOP_RETRY_CONFLICTS",

	 .pme_desc = "Respond with Retry to a snooped request due to one of the following conflicts",

	 .pme_code = 0xcfd, /* 3325 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_SNOOP_RETRY_BUSY",

	 .pme_desc = "Respond with Retry to a snooped request because all snoop machines are busy.",

	 .pme_code = 0xcfe, /* 3326 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_SNOOP_RESP_MMU_TO_EST",

	 .pme_desc = "Snooped response causes a cache state transition from (M | MU) to (E | S | T).",

	 .pme_code = 0xcff, /* 3327 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_SNOOP_RESP_E_TO_S",

	 .pme_desc = "Snooped response causes a cache state transition from E to S.",

	 .pme_code = 0xd00, /* 3328 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_SNOOP_RESP_ESLST_TO_I",

	 .pme_desc = "Snooped response causes a cache state transition from (E | SL | S | T) to Invalid (I).",

	 .pme_code = 0xd01, /* 3329 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_SNOOP_RESP_MMU_TO_I",

	 .pme_desc = "Snooped response causes a cache state transition from (M | MU) to I.",

	 .pme_code = 0xd02, /* 3330 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_LWARX_LDARX_MISS_TH1",

	 .pme_desc = "Load and reserve indexed (lwarx/ldarx) for Thread 1 hits Invalid cache state.",

	 .pme_code = 0xd54, /* 3412 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "L2_STWCX_STDCX_MISS_TH1",

	 .pme_desc = "Store conditional indexed (stwcx/stdcx) for Thread 1 hits Invalid cache state.",

	 .pme_code = 0xd5b, /* 3419 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "NCU_NON_CACHEABLE_ST_ALL",

	 .pme_desc = "Non-cacheable store request received from CIU; includes all synchronization operations such as sync and eieio.",

	 .pme_code = 0xdac, /* 3500 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "NCU_SYNC_REQ",

	 .pme_desc = "sync received from CIU.",

	 .pme_code = 0xdad, /* 3501 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "NCU_NON_CACHEABLE_ST",

	 .pme_desc = "Non-cacheable store request received from CIU; includes only stores.",

	 .pme_code = 0xdb0, /* 3504 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "NCU_EIEIO_REQ",

	 .pme_desc = "eieio received from CIU.",

	 .pme_code = 0xdb2, /* 3506 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "NCU_TLBIE_REQ",

	 .pme_desc = "tlbie received from CIU.",

	 .pme_code = 0xdb3, /* 3507 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "NCU_SYNC_WAIT",

	 .pme_desc = "sync at the bottom of the store queue, while waiting on st_done signal from the Bus Interface Unit (BIU) and sync_done signal from L2.",

	 .pme_code = 0xdb4, /* 3508 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "NCU_LWSYNC_WAIT",

	 .pme_desc = "lwsync at the bottom of the store queue, while waiting for a sync_done signal from the L2.",

	 .pme_code = 0xdb5, /* 3509 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "NCU_EIEIO_WAIT",

	 .pme_desc = "eieio at the bottom of the store queue, while waiting for a st_done signal from the BIU and a sync_done signal from the L2.",

	 .pme_code = 0xdb6, /* 3510 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "NCU_TLBIE_WAIT",

	 .pme_desc = "tlbie at the bottom of the store queue, while waiting for a st_done signal from the BIU.",

	 .pme_code = 0xdb7, /* 3511 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "NCU_COMBINED_NON_CACHEABLE_ST",

	 .pme_desc = "Non-cacheable store combined with the previous non-cacheable store with a contiguous address.",

	 .pme_code = 0xdb8, /* 3512 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "NCU_ALL_ST_GATHER_BUFFS_FULL",

	 .pme_desc = "All four store-gather buffers full.",

	 .pme_code = 0xdbb, /* 3515 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "NCU_LD_REQ",

	 .pme_desc = "Non-cacheable load request received from CIU; includes instruction and data fetches.",

	 .pme_code = 0xdbc, /* 3516 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "NCU_ST_Q_NOT_EMPTY",

	 .pme_desc = "The four-deep store queue not empty.",

	 .pme_code = 0xdbd, /* 3517 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "NCU_ST_Q_FULL",

	 .pme_desc = "The four-deep store queue full.",

	 .pme_code = 0xdbe, /* 3518 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "NCU_AT_LEAST_ONE_ST_GATHER_BUFF_NOT_EMPTY",

	 .pme_desc = "At least one store gather buffer not empty.",

	 .pme_code = 0xdbf, /* 3519 */

	 .pme_enable_word = WORD_0_ONLY,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_DUAL_INST_COMMITTED",

	 .pme_desc = "A dual instruction is committed.",

	 .pme_code = 0x1004, /* 4100 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_SINGLE_INST_COMMITTED",

	 .pme_desc = "A single instruction is committed.",

	 .pme_code = 0x1005, /* 4101 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_PIPE0_INST_COMMITTED",

	 .pme_desc = "A pipeline 0 instruction is committed.",

	 .pme_code = 0x1006, /* 4102 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_PIPE1_INST_COMMITTED",

	 .pme_desc = "A pipeline 1 instruction is committed.",

	 .pme_code = 0x1007, /* 4103 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_LS_BUSY",

	 .pme_desc = "Local storage is busy.",

	 .pme_code = 0x1009, /* 4105 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_DMA_CONFLICT_LD_ST",

	 .pme_desc = "A direct memory access (DMA) might conflict with a load or store.",

	 .pme_code = 0x100a, /* 4106 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_LS_ST",

	 .pme_desc = "A store instruction to local storage is issued.",

	 .pme_code = 0x100b, /* 4107 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_LS_LD",

	 .pme_desc = "A load instruction from local storage is issued.",

	 .pme_code = 0x100c, /* 4108 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_FP_EXCEPTION",

	 .pme_desc = "A floating-point unit exception occurred.",

	 .pme_code = 0x100d, /* 4109 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_BRANCH_COMMIT",

	 .pme_desc = "A branch instruction is committed.",

	 .pme_code = 0x100e, /* 4110 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_NON_SEQ_PC",

	 .pme_desc = "A nonsequential change of the SPU program counter has occurred. This can be caused by branch, asynchronous interrupt, stalled wait on channel, error-correction code (ECC) error, and so forth.",

	 .pme_code = 0x100f, /* 4111 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_BRANCH_NOT_TAKEN",

	 .pme_desc = "A branch was not taken.",

	 .pme_code = 0x1010, /* 4112 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_BRANCH_MISS_PREDICTION",

	 .pme_desc = "Branch miss prediction. This count is not exact. Certain other code sequences can cause additional pulses on this signal.",

	 .pme_code = 0x1011, /* 4113 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_BRANCH_HINT_MISS_PREDICTION",

	 .pme_desc = "Branch hint miss prediction. This count is not exact. Certain other code sequences can cause additional pulses on this signal.",

	 .pme_code = 0x1012, /* 4114 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_INST_SEQ_ERROR",

	 .pme_desc = "Instruction sequence error",

	 .pme_code = 0x1013, /* 4115 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "SPU_STALL_CH_WRITE",

	 .pme_desc = "Stalled waiting on any blocking channel write.",

	 .pme_code = 0x1015, /* 4117 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_STALL_EXTERNAL_EVENT_CH0",

	 .pme_desc = "Stalled waiting on external event status (Channel 0).",

	 .pme_code = 0x1016, /* 4118 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_STALL_SIGNAL_1_CH3",

	 .pme_desc = "Stalled waiting on SPU Signal Notification 1 (Channel 3).",

	 .pme_code = 0x1017, /* 4119 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_STALL_SIGNAL_2_CH4",

	 .pme_desc = "Stalled waiting on SPU Signal Notification 2 (Channel 4).",

	 .pme_code = 0x1018, /* 4120 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_STALL_DMA_CH21",

	 .pme_desc = "Stalled waiting on DMA Command Opcode or ClassID Register (Channel 21).",

	 .pme_code = 0x1019, /* 4121 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_STALL_MFC_READ_CH24",

	 .pme_desc = "Stalled waiting on memory flow control (MFC) Read Tag-Group Status (Channel 24).",

	 .pme_code = 0x101a, /* 4122 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_STALL_MFC_READ_CH25",

	 .pme_desc = "Stalled waiting on MFC Read List Stall-and-Notify Tag Status (Channel 25).",

	 .pme_code = 0x101b, /* 4123 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_STALL_OUTBOUND_MAILBOX_WRITE_CH28",

	 .pme_desc = "Stalled waiting on SPU Write Outbound Mailbox (Channel 28).",

	 .pme_code = 0x101c, /* 4124 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_STALL_MAILBOX_CH29",

	 .pme_desc = "Stalled waiting on SPU Mailbox (Channel 29).",

	 .pme_code = 0x1022, /* 4130 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_TR_STALL_CH",

	 .pme_desc = "Stalled waiting on a channel operation.",

	 .pme_code = 0x10a1, /* 4257 */

	 .pme_enable_word = WORD_NONE,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_EV_INST_FETCH_STALL",

	 .pme_desc = "Instruction fetch stall",

	 .pme_code = 0x1107, /* 4359 */

	 .pme_enable_word = WORD_NONE,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_BOTH_TYPE,

	},

	{.pme_name = "SPU_EV_ADDR_TRACE",

	 .pme_desc = "Serialized SPU address (program counter) trace.",

	 .pme_code = 0x110b, /* 4363 */

	 .pme_enable_word = 0xF,

	 .pme_freq = PFM_CELL_PME_FREQ_SPU,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ATOMIC_LD",

	 .pme_desc = "An atomic load was received from direct memory access controller (DMAC).",

	 .pme_code = 0x13ed, /* 5101 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ATOMIC_DCLAIM",

	 .pme_desc = "An atomic dclaim was sent to synergistic bus interface (SBI); includes retried requests.",

	 .pme_code = 0x13ee, /* 5102 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ATOMIC_RWITM",

	 .pme_desc = "An atomic rwitm performed was sent to SBI; includes retried requests.",

	 .pme_code = 0x13ef, /* 5103 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_MU",

	 .pme_desc = "An atomic load miss caused MU cache state.",

	 .pme_code = 0x13f0, /* 5104 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_E",

	 .pme_desc = "An atomic load miss caused E cache state.",

	 .pme_code = 0x13f1, /* 5105 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_SL",

	 .pme_desc = "An atomic load miss caused SL cache state.",

	 .pme_code = 0x13f2, /* 5106 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ATOMIC_LD_CACHE_HIT",

	 .pme_desc = "An atomic load hits cache.",

	 .pme_code = 0x13f3, /* 5107 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_INTERVENTION",

	 .pme_desc = "Atomic load misses cache with data intervention; sum of signals 4 and 6 in this group.",

	 .pme_code = 0x13f4, /* 5108 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ATOMIC_PUTLLXC_CACHE_MISS_WO_INTERVENTION",

	 .pme_desc = "putllc or putlluc misses cache without data intervention; for putllc, counts only when reservation is set for the address.",

	 .pme_code = 0x13fa, /* 5114 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_SNOOP_MACHINE_BUSY",

	 .pme_desc = "Snoop machine busy.",

	 .pme_code = 0x13fd, /* 5117 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "MFC_SNOOP_MMU_TO_I",

	 .pme_desc = "A snoop caused cache transition from [M | MU] to I.",

	 .pme_code = 0x13ff, /* 5119 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_SNOOP_ESSL_TO_I",

	 .pme_desc = "A snoop caused cache transition from [E | S | SL] to I.",

	 .pme_code = 0x1401, /* 5121 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_SNOOP_MU_TO_T",

	 .pme_desc = "A snoop caused cache transition from MU to T cache state.",

	 .pme_code = 0x1403, /* 5123 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_SENT_INTERVENTION_LOCAL",

	 .pme_desc = "Sent modified data intervention to a destination within the same CBE chip.",

	 .pme_code = 0x1407, /* 5127 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ANY_DMA_GET",

	 .pme_desc = "Any flavor of DMA get[] command issued to Synergistic Bus Interface (SBI); sum of signals 17-25 in this group.",

	 .pme_code = 0x1450, /* 5200 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ANY_DMA_PUT",

	 .pme_desc = "Any flavor of DMA put[] command issued to SBI; sum of signals 2-16 in this group.",

	 .pme_code = 0x1451, /* 5201 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_DMA_PUT",

	 .pme_desc = "DMA put (put) is issued to SBI.",

	 .pme_code = 0x1452, /* 5202 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_DMA_GET",

	 .pme_desc = "DMA get data from effective address to local storage (get) issued to SBI.",

	 .pme_code = 0x1461, /* 5217 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_LD_REQ",

	 .pme_desc = "Load request sent to element interconnect bus (EIB); includes read, read atomic, rwitm, rwitm atomic, and retried commands.",

	 .pme_code = 0x14b8, /* 5304 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_ST_REQ",

	 .pme_desc = "Store request sent to EIB; includes wwf, wwc, wwk, dclaim, dclaim atomic, and retried commands.",

	 .pme_code = 0x14b9, /* 5305 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_RECV_DATA",

	 .pme_desc = "Received data from EIB, including partial cache line data.",

	 .pme_code = 0x14ba, /* 5306 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_SENT_DATA",

	 .pme_desc = "Sent data to EIB, both as a master and a snooper.",

	 .pme_code = 0x14bb, /* 5307 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_OCCURRENCE,

	},

	{.pme_name = "MFC_SBI_Q_NOT_EMPTY",

	 .pme_desc = "16-deep synergistic bus interface (SBI) queue with outgoing requests not empty; does not include atomic requests.",

	 .pme_code = 0x14bc, /* 5308 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "MFC_SBI_Q_FULL",

	 .pme_desc = "16-deep SBI queue with outgoing requests full; does not include atomic requests.",

	 .pme_code = 0x14bd, /* 5309 */

	 .pme_enable_word = WORD_0_AND_2,

	 .pme_freq = PFM_CELL_PME_FREQ_HALF,

	 .pme_type = COUNT_TYPE_CUMULATIVE_LEN,

	},

	{.pme_name = "MFC_SENT_REQ",