/*

 * Copyright (c) 2011 University of Tennessee

 * Contributed by Vince Weaver <vweaver1@utk.edu>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 * This file is part of libpfm, a performance monitoring support library for

 * applications on Linux.

 *

 * PMU: amd64_fam12h (AMD64 Fam12h)

 */

static const amd64_umask_t amd64_fam12h_dispatched_fpu[]={

   { .uname  = "OPS_ADD",

     .udesc  = "Add pipe ops excluding load ops and SSE move ops",

     .ucode = 0x1,

   },

   { .uname  = "OPS_MULTIPLY",

     .udesc  = "Multiply pipe ops excluding load ops and SSE move ops",

     .ucode = 0x2,

   },

   { .uname  = "OPS_STORE",

     .udesc  = "Store pipe ops excluding load ops and SSE move ops",

     .ucode = 0x4,

   },

   { .uname  = "OPS_ADD_PIPE_LOAD_OPS",

     .udesc  = "Add pipe load ops and SSE move ops",

     .ucode = 0x8,

   },

   { .uname  = "OPS_MULTIPLY_PIPE_LOAD_OPS",

     .udesc  = "Multiply pipe load ops and SSE move ops",

     .ucode = 0x10,

   },

   { .uname  = "OPS_STORE_PIPE_LOAD_OPS",

     .udesc  = "Store pipe load ops and SSE move ops",

     .ucode = 0x20,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x3f,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_retired_sse_operations[]={

   { .uname  = "SINGLE_ADD_SUB_OPS",

     .udesc  = "Single precision add/subtract ops",

     .ucode = 0x1,

   },

   { .uname  = "SINGLE_MUL_OPS",

     .udesc  = "Single precision multiply ops",

     .ucode = 0x2,

   },

   { .uname  = "SINGLE_DIV_OPS",

     .udesc  = "Single precision divide/square root ops",

     .ucode = 0x4,

   },

   { .uname  = "DOUBLE_ADD_SUB_OPS",

     .udesc  = "Double precision add/subtract ops",

     .ucode = 0x8,

   },

   { .uname  = "DOUBLE_MUL_OPS",

     .udesc  = "Double precision multiply ops",

     .ucode = 0x10,

   },

   { .uname  = "DOUBLE_DIV_OPS",

     .udesc  = "Double precision divide/square root ops",

     .ucode = 0x20,

   },

   { .uname  = "OP_TYPE",

     .udesc  = "Op type: 0=uops. 1=FLOPS",

     .ucode = 0x40,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x7f,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_retired_move_ops[]={

   { .uname  = "LOW_QW_MOVE_UOPS",

     .udesc  = "Merging low quadword move uops",

     .ucode = 0x1,

   },

   { .uname  = "HIGH_QW_MOVE_UOPS",

     .udesc  = "Merging high quadword move uops",

     .ucode = 0x2,

   },

   { .uname  = "ALL_OTHER_MERGING_MOVE_UOPS",

     .udesc  = "All other merging move uops",

     .ucode = 0x4,

   },

   { .uname  = "ALL_OTHER_MOVE_UOPS",

     .udesc  = "All other move uops",

     .ucode = 0x8,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xf,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_retired_serializing_ops[]={

   { .uname  = "SSE_BOTTOM_EXECUTING_UOPS",

     .udesc  = "SSE bottom-executing uops retired",

     .ucode = 0x1,

   },

   { .uname  = "SSE_BOTTOM_SERIALIZING_UOPS",

     .udesc  = "SSE bottom-serializing uops retired",

     .ucode = 0x2,

   },

   { .uname  = "X87_BOTTOM_EXECUTING_UOPS",

     .udesc  = "X87 bottom-executing uops retired",

     .ucode = 0x4,

   },

   { .uname  = "X87_BOTTOM_SERIALIZING_UOPS",

     .udesc  = "X87 bottom-serializing uops retired",

     .ucode = 0x8,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xf,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_fp_scheduler_cycles[]={

   { .uname  = "BOTTOM_EXECUTE_CYCLES",

     .udesc  = "Number of cycles a bottom-execute uop is in the FP scheduler",

     .ucode = 0x1,

   },

   { .uname  = "BOTTOM_SERIALIZING_CYCLES",

     .udesc  = "Number of cycles a bottom-serializing uop is in the FP scheduler",

     .ucode = 0x2,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x3,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_segment_register_loads[]={

   { .uname  = "ES",

     .udesc  = "ES",

     .ucode = 0x1,

   },

   { .uname  = "CS",

     .udesc  = "CS",

     .ucode = 0x2,

   },

   { .uname  = "SS",

     .udesc  = "SS",

     .ucode = 0x4,

   },

   { .uname  = "DS",

     .udesc  = "DS",

     .ucode = 0x8,

   },

   { .uname  = "FS",

     .udesc  = "FS",

     .ucode = 0x10,

   },

   { .uname  = "GS",

     .udesc  = "GS",

     .ucode = 0x20,

   },

   { .uname  = "HS",

     .udesc  = "HS",

     .ucode = 0x40,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x7f,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_locked_ops[]={

   { .uname  = "EXECUTED",

     .udesc  = "The number of locked instructions executed",

     .ucode = 0x1,

   },

   { .uname  = "CYCLES_SPECULATIVE_PHASE",

     .udesc  = "The number of cycles spent in speculative phase",

     .ucode = 0x2,

   },

   { .uname  = "CYCLES_NON_SPECULATIVE_PHASE",

     .udesc  = "The number of cycles spent in non-speculative phase (including cache miss penalty)",

     .ucode = 0x4,

   },

   { .uname  = "CYCLES_WAITING",

     .udesc  = "The number of cycles waiting for a cache hit (cache miss penalty).",

     .ucode = 0x8,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xf,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_cancelled_store_to_load_forward_operations[]={

   { .uname  = "ADDRESS_MISMATCHES",

     .udesc  = "Address mismatches (starting byte not the same).",

     .ucode = 0x1,

   },

   { .uname  = "STORE_IS_SMALLER_THAN_LOAD",

     .udesc  = "Store is smaller than load.",

     .ucode = 0x2,

   },

   { .uname  = "MISALIGNED",

     .udesc  = "Misaligned.",

     .ucode = 0x4,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x7,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_data_cache_refills[]={

   { .uname  = "SYSTEM",

     .udesc  = "Refill from the Northbridge",

     .ucode = 0x1,

   },

   { .uname  = "L2_SHARED",

     .udesc  = "Shared-state line from L2",

     .ucode = 0x2,

   },

   { .uname  = "L2_EXCLUSIVE",

     .udesc  = "Exclusive-state line from L2",

     .ucode = 0x4,

   },

   { .uname  = "L2_OWNED",

     .udesc  = "Owned-state line from L2",

     .ucode = 0x8,

   },

   { .uname  = "L2_MODIFIED",

     .udesc  = "Modified-state line from L2",

     .ucode = 0x10,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x1f,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_data_cache_refills_from_northbridge[]={

   { .uname  = "INVALID",

     .udesc  = "Invalid",

     .ucode = 0x1,

   },

   { .uname  = "SHARED",

     .udesc  = "Shared",

     .ucode = 0x2,

   },

   { .uname  = "EXCLUSIVE",

     .udesc  = "Exclusive",

     .ucode = 0x4,

   },

   { .uname  = "OWNED",

     .udesc  = "Owned",

     .ucode = 0x8,

   },

   { .uname  = "MODIFIED",

     .udesc  = "Modified",

     .ucode = 0x10,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x1f,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_data_cache_lines_evicted[]={

   { .uname  = "INVALID",

     .udesc  = "Invalid",

     .ucode = 0x1,

   },

   { .uname  = "SHARED",

     .udesc  = "Shared",

     .ucode = 0x2,

   },

   { .uname  = "EXCLUSIVE",

     .udesc  = "Exclusive",

     .ucode = 0x4,

   },

   { .uname  = "OWNED",

     .udesc  = "Owned",

     .ucode = 0x8,

   },

   { .uname  = "MODIFIED",

     .udesc  = "Modified",

     .ucode = 0x10,

   },

   { .uname  = "BY_PREFETCHNTA",

     .udesc  = "Cache line evicted was brought into the cache with by a PrefetchNTA instruction.",

     .ucode = 0x20,

   },

   { .uname  = "NOT_BY_PREFETCHNTA",

     .udesc  = "Cache line evicted was not brought into the cache with by a PrefetchNTA instruction.",

     .ucode = 0x40,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x7f,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit[]={

   { .uname  = "L2_4K_TLB_HIT",

     .udesc  = "L2 4K TLB hit",

     .ucode = 0x1,

   },

   { .uname  = "L2_2M_TLB_HIT",

     .udesc  = "L2 2M TLB hit",

     .ucode = 0x2,

   },

   { .uname  = "L2_1G_TLB_HIT",

     .udesc  = "L2 1G TLB hit",

     .ucode = 0x4,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x7,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, 

   },

};

static const amd64_umask_t amd64_fam12h_l1_dtlb_and_l2_dtlb_miss[]={

   { .uname  = "4K_TLB_RELOAD",

     .udesc  = "4K TLB reload",

     .ucode = 0x1,

   },

   { .uname  = "2M_TLB_RELOAD",

     .udesc  = "2M TLB reload",

     .ucode = 0x2,

   },

   { .uname  = "1G_TLB_RELOAD",

     .udesc  = "1G TLB reload",

     .ucode = 0x4,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x7,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_prefetch_instructions_dispatched[]={

   { .uname  = "LOAD",

     .udesc  = "Load (Prefetch, PrefetchT0/T1/T2)",

     .ucode = 0x1,

   },

   { .uname  = "STORE",

     .udesc  = "Store (PrefetchW)",

     .ucode = 0x2,

   },

   { .uname  = "NTA",

     .udesc  = "NTA (PrefetchNTA)",

     .ucode = 0x4,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x7,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_dcache_misses_by_locked_instructions[]={

   { .uname  = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS",

     .udesc  = "Data cache misses by locked instructions",

     .ucode = 0x2,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x2,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_l1_dtlb_hit[]={

   { .uname  = "L1_4K_TLB_HIT",

     .udesc  = "L1 4K TLB hit",

     .ucode = 0x1,

   },

   { .uname  = "L1_2M_TLB_HIT",

     .udesc  = "L1 2M TLB hit",

     .ucode = 0x2,

   },

   { .uname  = "L1_1G_TLB_HIT",

     .udesc  = "L1 1G TLB hit",

     .ucode = 0x4,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x7,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_ineffective_sw_prefetches[]={

   { .uname  = "SW_PREFETCH_HIT_IN_L1",

     .udesc  = "Software prefetch hit in the L1.",

     .ucode = 0x1,

   },

   { .uname  = "SW_PREFETCH_HIT_IN_L2",

     .udesc  = "Software prefetch hit in L2.",

     .ucode = 0x8,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x9,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_memory_requests[]={

   { .uname  = "NON_CACHEABLE",

     .udesc  = "Requests to non-cacheable (UC) memory",

     .ucode = 0x1,

   },

   { .uname  = "WRITE_COMBINING",

     .udesc  = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory",

     .ucode = 0x2,

   },

   { .uname  = "CACHE_DISABLED",

     .udesc  = "Requests to cache-disabled (CD) memory",

     .ucode = 0x4,

   },

   { .uname  = "STREAMING_STORE",

     .udesc  = "Streaming store (SS) requests",

     .ucode = 0x80,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x87,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_data_prefetches[]={

   { .uname  = "CANCELLED",

     .udesc  = "Cancelled prefetches",

     .ucode = 0x1,

   },

   { .uname  = "ATTEMPTED",

     .udesc  = "Prefetch attempts",

     .ucode = 0x2,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x3,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_northbridge_read_responses[]={

   { .uname  = "EXCLUSIVE",

     .udesc  = "Exclusive",

     .ucode = 0x1,

   },

   { .uname  = "MODIFIED",

     .udesc  = "Modified",

     .ucode = 0x2,

   },

   { .uname  = "SHARED",

     .udesc  = "Shared",

     .ucode = 0x4,

   },

   { .uname  = "OWNED",

     .udesc  = "Owned",

     .ucode = 0x8,

   },

   { .uname  = "DATA_ERROR",

     .udesc  = "Data Error",

     .ucode = 0x10,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x1f,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_octwords_written_to_system[]={

   { .uname  = "OCTWORD_WRITE_TRANSFER",

     .udesc  = "Octword write transfer",

     .ucode = 0x1,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x1,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_requests_to_l2[]={

   { .uname  = "INSTRUCTIONS",

     .udesc  = "IC fill",

     .ucode = 0x1,

   },

   { .uname  = "DATA",

     .udesc  = "DC fill",

     .ucode = 0x2,

   },

   { .uname  = "TLB_WALK",

     .udesc  = "TLB fill (page table walks)",

     .ucode = 0x4,

   },

   { .uname  = "SNOOP",

     .udesc  = "Tag snoop request",

     .ucode = 0x8,

   },

   { .uname  = "CANCELLED",

     .udesc  = "Cancelled request",

     .ucode = 0x10,

   },

   { .uname  = "HW_PREFETCH_FROM_DC",

     .udesc  = "Hardware prefetch from DC",

     .ucode = 0x20,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x3f,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_l2_cache_miss[]={

   { .uname  = "INSTRUCTIONS",

     .udesc  = "IC fill",

     .ucode = 0x1,

   },

   { .uname  = "DATA",

     .udesc  = "DC fill (includes possible replays, whereas EventSelect 041h does not)",

     .ucode = 0x2,

   },

   { .uname  = "TLB_WALK",

     .udesc  = "TLB page table walk",

     .ucode = 0x4,

   },

   { .uname  = "HW_PREFETCH_FROM_DC",

     .udesc  = "Hardware prefetch from DC",

     .ucode = 0x8,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xf,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_l2_fill_writeback[]={

   { .uname  = "L2_FILLS",

     .udesc  = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)",

     .ucode = 0x1,

   },

   { .uname  = "L2_WRITEBACKS",

     .udesc  = "L2 Writebacks to system.",

     .ucode = 0x2,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x3,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss[]={

   { .uname  = "4K_PAGE_FETCHES",

     .udesc  = "Instruction fetches to a 4K page.",

     .ucode = 0x1,

   },

   { .uname  = "2M_PAGE_FETCHES",

     .udesc  = "Instruction fetches to a 2M page.",

     .ucode = 0x2,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x3,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_instruction_cache_lines_invalidated[]={

   { .uname  = "INVALIDATING_PROBE_NO_IN_FLIGHT",

     .udesc  = "Invalidating probe that did not hit any in-flight instructions.",

     .ucode = 0x1,

   },

   { .uname  = "INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHT",

     .udesc  = "Invalidating probe that hit one or more in-flight instructions.",

     .ucode = 0x2,

   },

   { .uname  = "SMC_NO_INFLIGHT",

     .udesc  = "SMC that did not hit any in-flight instructions.",

     .ucode = 0x4,

   },

   { .uname  = "SMC_INFLIGHT",

     .udesc  = "SMC that hit one or more in-flight instructions.",

     .ucode = 0x8,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xf,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_retired_mmx_and_fp_instructions[]={

   { .uname  = "X87",

     .udesc  = "X87 instructions",

     .ucode = 0x1,

   },

   { .uname  = "MMX_AND_3DNOW",

     .udesc  = "MMX and 3DNow! instructions",

     .ucode = 0x2,

   },

   { .uname  = "SSE_AND_SSE2",

     .udesc  = "SSE and SSE2 instructions",

     .ucode = 0x4,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x7,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_interrupt_events[]={

   { .uname  = "FIXED_AND_LPA",

     .udesc  = "Fixed and LPA",

     .ucode = 0x1,

   },

   { .uname  = "LPA",

     .udesc  = "LPA",

     .ucode = 0x2,

   },

   { .uname  = "SMI",

     .udesc  = "SMI",

     .ucode = 0x4,

   },

   { .uname  = "NMI",

     .udesc  = "NMI",

     .ucode = 0x8,

   },

   { .uname  = "INIT",

     .udesc  = "INIT",

     .ucode = 0x10,

   },

   { .uname  = "STARTUP",

     .udesc  = "STARTUP",

     .ucode = 0x20,

   },

   { .uname  = "INT",

     .udesc  = "INT",

     .ucode = 0x40,

   },

   { .uname  = "EOI",

     .udesc  = "EOI",

     .ucode = 0x80,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xff,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_sideband_signals[]={

   { .uname  = "STOPGRANT",

     .udesc  = "STOPGRANT",

     .ucode = 0x2,

   },

   { .uname  = "SHUTDOWN",

     .udesc  = "SHUTDOWN",

     .ucode = 0x4,

   },

   { .uname  = "WBINVD",

     .udesc  = "WBINVD",

     .ucode = 0x8,

   },

   { .uname  = "INVD",

     .udesc  = "INVD",

     .ucode = 0x10,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x1e,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_fpu_exceptions[]={

   { .uname  = "X87_RECLASS_MICROFAULTS",

     .udesc  = "X87 reclass microfaults",

     .ucode = 0x1,

   },

   { .uname  = "SSE_RETYPE_MICROFAULTS",

     .udesc  = "SSE retype microfaults",

     .ucode = 0x2,

   },

   { .uname  = "SSE_RECLASS_MICROFAULTS",

     .udesc  = "SSE reclass microfaults",

     .ucode = 0x4,

   },

   { .uname  = "SSE_AND_X87_MICROTRAPS",

     .udesc  = "SSE and x87 microtraps",

     .ucode = 0x8,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xf,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_dram_accesses_page[]={

   { .uname  = "DCT0_HIT",

     .udesc  = "DCT0 Page hit",

     .ucode = 0x1,

   },

   { .uname  = "DCT0_MISS",

     .udesc  = "DCT0 Page Miss",

     .ucode = 0x2,

   },

   { .uname  = "DCT0_CONFLICT",

     .udesc  = "DCT0 Page Conflict",

     .ucode = 0x4,

   },

   { .uname  = "DCT1_PAGE_HIT",

     .udesc  = "DCT1 Page hit",

     .ucode = 0x8,

   },

   { .uname  = "DCT1_PAGE_MISS",

     .udesc  = "DCT1 Page Miss",

     .ucode = 0x10,

   },

   { .uname  = "DCT1_PAGE_CONFLICT",

     .udesc  = "DCT1 Page Conflict",

     .ucode = 0x20,

   },

   { .uname  = "WRITE_REQUEST",

     .udesc  = "Write request.",

     .ucode = 0x40,

   },

   { .uname  = "READ_REQUEST",

     .udesc  = "Read request.",

     .ucode = 0x80,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xff,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_memory_controller_page_table_events[]={

   { .uname  = "PAGE_TABLE_OVERFLOW",

     .udesc  = "Page Table Overflow",

     .ucode = 0x1,

   },

   { .uname  = "STALE_TABLE_ENTRY_HITS",

     .udesc  = "Number of stale table entry hits. (hit on a page closed too soon).",

     .ucode = 0x2,

   },

   { .uname  = "PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTED",

     .udesc  = "Page table idle cycle limit incremented.",

     .ucode = 0x4,

   },

   { .uname  = "PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTED",

     .udesc  = "Page table idle cycle limit decremented.",

     .ucode = 0x8,

   },

   { .uname  = "PAGE_TABLE_CLOSED_INACTIVITY",

     .udesc  = "Page table is closed due to row inactivity.",

     .ucode = 0x10,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x1f,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_memory_controller_slot_misses[]={

   { .uname  = "DCT0_RBD",

     .udesc  = "DCT0 RBD.",

     .ucode = 0x10,

   },

   { .uname  = "DCT1_RBD",

     .udesc  = "DCT1 RBD.",

     .ucode = 0x20,

   },

   { .uname  = "DCT0_PREFETCH",

     .udesc  = "DCT0 Prefetch.",

     .ucode = 0x40,

   },

   { .uname  = "DCT1_PREFETCH",

     .udesc  = "DCT1 Prefetch.",

     .ucode = 0x80,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xf0,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_memory_controller_turnarounds[]={

   { .uname  = "DCT0_READ_TO_WRITE",

     .udesc  = "DCT0 read-to-write turnaround.",

     .ucode = 0x1,

   },

   { .uname  = "DCT0_WRITE_TO_READ",

     .udesc  = "DCT0 write-to-read turnaround",

     .ucode = 0x2,

   },

   { .uname  = "DCT1_READ_TO_WRITE",

     .udesc  = "DCT1 read-to-write turnaround.",

     .ucode = 0x8,

   },

   { .uname  = "DCT1_WRITE_TO_READ",

     .udesc  = "DCT1 write-to-read turnaround",

     .ucode = 0x10,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0x1b,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_memory_rbd_queue[]={

   { .uname  = "COUNTER_REACHED",

     .udesc  = "D18F2x[1,0]94[DcqBypassMax] counter reached.",

     .ucode = 0x4,

   },

   { .uname  = "BANK_CLOSED",

     .udesc  = "Bank is closed due to bank conflict with an outstanding request in the RBD queue.",

     .ucode = 0x8,

   },

   { .uname  = "ALL",

     .udesc  = "All sub-events selected",

     .ucode = 0xc,

     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,

   },

};

static const amd64_umask_t amd64_fam12h_thermal_status[]={

   { .uname  = "MEMHOT_L_ASSERTIONS",

     .udesc  = "MEMHOT_L assertions.",

     .ucode = 0x1,

   },

   { .uname  = "HTC_TRANSITIONS",

     .udesc  = "Number of times the HTC transitions from inactive to active.",

     .ucode = 0x4,

   },