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.TH LIBPFM 3 "September, 2009" "" "Linux Programmer's Manual"
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.SH NAME
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libpfm_intel_wsm - support for Intel Westmere core PMU
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.SH SYNOPSIS
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.nf
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.B #include <perfmon/pfmlib.h>
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.sp
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.B PMU name: wsm
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.B PMU desc: Intel Westmere
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.B PMU name: wsm_dp
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.B PMU desc: Intel Westmere DP
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.sp
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.SH DESCRIPTION
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The library supports the Intel Westmere core PMU. It should be noted that
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this PMU model only covers the each core's PMU and not the socket level
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PMU. It is provided separately. Support is provided for the Intel Core i7
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and Core i5 processors (models 37, 44).
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.SH MODIFIERS
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The following modifiers are supported on Intel Westmere processors:
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.TP
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.B u
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Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR.
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This is a boolean modifier.
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.TP
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.B k
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Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR.
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This is a boolean modifier.
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.TP
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.B i
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Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR
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occurring. This is a boolean modifier
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.TP
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.B e
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Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event
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to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one.
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This is a boolean modifier.
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.TP
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.B c
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Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles
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in which the number of occurrences of the event is greater or equal to the threshold. This is an integer
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modifier with values in the range [0:255].
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.TP
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.B t
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Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier.
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.TP
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.B ldlat
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Pass a latency threshold to the MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD event.
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This is an integer attribute that must be in the range [3:65535]. It is required
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for this event. Note that the event must be used with precise sampling (PEBS).
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.SH OFFCORE_RESPONSE events
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The library is able to encode the OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1 events.
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Those are special events because they, each, need a second MSR (0x1a6 and 0x1a7 respectively)
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to be programmed for the event to count properly. Thus two values are necessary for each event.
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The first value can be programmed on any of the generic counters. The second value goes into
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the dedicated MSR (0x1a6 or 0x1a7).
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The OFFCORE_RESPONSE events are exposed as normal events with several umasks which are divided in
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two groups: request and response. The user must provide \fBat least\fR one umask from each group.
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For instance, OFFCORE_RESPONSE_0:ANY_DATA:LOCAL_DRAM.
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When using \fBpfm_get_event_encoding()\fR, two 64-bit values are returned. The first value
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corresponds to what needs to be programmed into any of the generic counters. The second value
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must be programmed into the corresponding dedicated MSR (0x1a6 or 0x1a7).
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When using an OS-specific encoding routine, the way the event is encoded is OS specific. Refer to
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the corresponding man page for more information.
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.SH AUTHORS
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.nf
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Stephane Eranian <eranian@gmail.com>
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.if
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.PP
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