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/*
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* These definitions were taken from the reg.h file which, until Linux
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* 2.6.18, resided in /usr/include/asm-ppc64. Most of the unneeded
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* definitions have been removed, but there are still a few in this file
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* that are currently unused by libpfm.
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*/
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#ifndef _POWER_REG_H
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#define _POWER_REG_H
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#define __stringify_1(x) #x
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#define __stringify(x) __stringify_1(x)
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#define mfspr(rn) ({unsigned long rval; \
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asm volatile("mfspr %0," __stringify(rn) \
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: "=r" (rval)); rval;})
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/* Special Purpose Registers (SPRNs)*/
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#define SPRN_PVR 0x11F /* Processor Version Register */
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/* Performance monitor SPRs */
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#define SPRN_MMCR0 795
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#define MMCR0_FC 0x80000000UL /* freeze counters */
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#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
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#define MMCR0_KERNEL_DISABLE MMCR0_FCS
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#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
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#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
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#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
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#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
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#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
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#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
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#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
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#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
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#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
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#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
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#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
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#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
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#define MMCR0_FC1_4 0x00000020UL /* freeze counters 1 - 4 on POWER5/5+ */
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#define MMCR0_FC5_6 0x00000010UL /* freeze counters 5 & 6 on POWER5/5+ */
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#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
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#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
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#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
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#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
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#define SPRN_MMCR1 798
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#define SPRN_MMCRA 0x312
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#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
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#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
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#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
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#define SPRN_PMC1 787
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#define SPRN_PMC2 788
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#define SPRN_PMC3 789
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#define SPRN_PMC4 790
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#define SPRN_PMC5 791
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#define SPRN_PMC6 792
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#define SPRN_PMC7 793
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#define SPRN_PMC8 794
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#define SPRN_SIAR 780
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#define SPRN_SDAR 781
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/* Processor Version Register (PVR) field extraction */
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#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
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#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
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#define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
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/* 64-bit processors */
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/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
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#define PV_NORTHSTAR 0x0033
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#define PV_PULSAR 0x0034
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#define PV_POWER4 0x0035
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#define PV_ICESTAR 0x0036
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#define PV_SSTAR 0x0037
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#define PV_POWER4p 0x0038
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#define PV_970 0x0039
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#define PV_POWER5 0x003A
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#define PV_POWER5p 0x003B
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#define PV_970FX 0x003C
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#define PV_POWER6 0x003E
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#define PV_POWER7 0x003F
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#define PV_630 0x0040
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#define PV_630p 0x0041
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#define PV_970MP 0x0044
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#define PV_970GX 0x0045
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#define PV_BE 0x0070
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#endif /* _POWER_REG_H */
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