/*

 * pfmlib_itanium2.c : support for the Itanium2 PMU family

 *

 * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P.

 * Contributed by Stephane Eranian <eranian@hpl.hp.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#include <sys/types.h>

#include <ctype.h>

#include <string.h>

#include <stdio.h>

/* public headers */

#include <perfmon/pfmlib_itanium2.h>

/* private headers */

#include "pfmlib_priv.h"		/* library private */

#include "pfmlib_priv_ia64.h"		/* architecture private */

#include "pfmlib_itanium2_priv.h"	/* PMU private */

#include "itanium2_events.h"		/* PMU private */

#define is_ear(i)	event_is_ear(itanium2_pe+(i))

#define is_ear_tlb(i)	event_is_ear_tlb(itanium2_pe+(i))

#define is_ear_alat(i)	event_is_ear_alat(itanium2_pe+(i))

#define is_ear_cache(i)	event_is_ear_cache(itanium2_pe+(i))

#define is_iear(i)	event_is_iear(itanium2_pe+(i))

#define is_dear(i)	event_is_dear(itanium2_pe+(i))

#define is_btb(i)	event_is_btb(itanium2_pe+(i))

#define has_opcm(i)	event_opcm_ok(itanium2_pe+(i))

#define has_iarr(i)	event_iarr_ok(itanium2_pe+(i))

#define has_darr(i)	event_darr_ok(itanium2_pe+(i))

#define evt_use_opcm(e)		((e)->pfp_ita2_pmc8.opcm_used != 0 || (e)->pfp_ita2_pmc9.opcm_used !=0)

#define evt_use_irange(e)	((e)->pfp_ita2_irange.rr_used)

#define evt_use_drange(e)	((e)->pfp_ita2_drange.rr_used)

#define evt_grp(e)	(int)itanium2_pe[e].pme_qualifiers.pme_qual.pme_group

#define evt_set(e)	(int)itanium2_pe[e].pme_qualifiers.pme_qual.pme_set

#define evt_umask(e)	itanium2_pe[e].pme_umask

#define FINE_MODE_BOUNDARY_BITS	12

#define FINE_MODE_MASK		~((1U<<12)-1)

/* let's define some handy shortcuts! */

#define pmc_plm		pmc_ita2_counter_reg.pmc_plm

#define pmc_ev		pmc_ita2_counter_reg.pmc_ev

#define pmc_oi		pmc_ita2_counter_reg.pmc_oi

#define pmc_pm		pmc_ita2_counter_reg.pmc_pm

#define pmc_es		pmc_ita2_counter_reg.pmc_es

#define pmc_umask	pmc_ita2_counter_reg.pmc_umask

#define pmc_thres	pmc_ita2_counter_reg.pmc_thres

#define pmc_ism		pmc_ita2_counter_reg.pmc_ism

static char * pfm_ita2_get_event_name(unsigned int i);

/*

 * Description of the PMC register mappings use by

 * this module (as reported in pfmlib_reg_t.reg_num):

 *

 * 0 -> PMC0

 * 1 -> PMC1

 * n -> PMCn

 *

 * The following are in the model specific rr_br[]:

 * IBR0 -> 0

 * IBR1 -> 1

 * ...

 * IBR7 -> 7

 * DBR0 -> 0

 * DBR1 -> 1

 * ...

 * DBR7 -> 7

 *

 * We do not use a mapping table, instead we make up the

 * values on the fly given the base.

 */

/*

 * The Itanium2 PMU has a bug in the fine mode implementation.

 * It only sees ranges with a granularity of two bundles.

 * So we prepare for the day they fix it.

 */

static int has_fine_mode_bug;

static int

pfm_ita2_detect(void)

{

	int tmp;

	int ret = PFMLIB_ERR_NOTSUPP;

	tmp = pfm_ia64_get_cpu_family();

	if (tmp == 0x1f) {

		has_fine_mode_bug = 1;

		ret = PFMLIB_SUCCESS;

	}

	return ret;

}

/*

 * Check the event for incompatibilities. This is useful

 * for L1 and L2 related events. Due to wire limitations,

 * some caches events are separated into sets. There

 * are 5 sets for the L1D cache group and 6 sets for L2 group.

 * It is NOT possible to simultaneously measure events from

 * differents sets within a group. For instance, you cannot

 * measure events from set0 and set1 in L1D cache group. However

 * it is possible to measure set0 in L1D and set1 in L2 at the same

 * time.

 *

 * This function verifies that the set constraint are respected.

 */

static int

check_cross_groups_and_umasks(pfmlib_input_param_t *inp)

{

	unsigned long ref_umask, umask;

	int g, s;

	unsigned int cnt = inp->pfp_event_count;

	pfmlib_event_t *e = inp->pfp_events;

	unsigned int i, j;

	/*

	 * XXX: could possibly be optimized

	 */

	for (i=0; i < cnt; i++) {

		g = evt_grp(e[i].event);

		s = evt_set(e[i].event);

		if (g == PFMLIB_ITA2_EVT_NO_GRP) continue;

		ref_umask = evt_umask(e[i].event);

		for (j=i+1; j < cnt; j++) {

			if (evt_grp(e[j].event) != g) continue;

			if (evt_set(e[j].event) != s) return PFMLIB_ERR_EVTSET;

			/* only care about L2 cache group */

			if (g != PFMLIB_ITA2_EVT_L2_CACHE_GRP || (s == 1 || s == 2)) continue;

			umask = evt_umask(e[j].event);

			/*

			 * there is no assignement possible if the event in PMC4

			 * has a umask (ref_umask) and an event (from the same

			 * set) also has a umask AND it is different. For some

			 * sets, the umasks are shared, therefore the value

			 * programmed into PMC4 determines the umask for all

			 * the other events (with umask) from the set.

			 */

			if (umask && ref_umask != umask) return PFMLIB_ERR_NOASSIGN;

		}

	}

	return PFMLIB_SUCCESS;

}

/*

 * Certain prefetch events must be treated specially when instruction range restriction

 * is in use because they can only be constrained by IBRP1 in fine-mode. Other events

 * will use IBRP0 if tagged as a demand fetch OR IBPR1 if tagged as a prefetch match.

 * From the library's point of view there is no way of distinguishing this, so we leave

 * it up to the user to interpret the results.

 *

 * Events which can be qualified by the two pairs depending on their tag:

 * 	- IBP_BUNPAIRS_IN

 * 	- L1I_FETCH_RAB_HIT

 *	- L1I_FETCH_ISB_HIT

 * 	- L1I_FILLS

 *

 * This function returns the number of qualifying prefetch events found

 *

 * XXX: not clear which events do qualify as prefetch events.

 */

static int prefetch_events[]={

	PME_ITA2_L1I_PREFETCHES,

	PME_ITA2_L1I_STRM_PREFETCHES,

	PME_ITA2_L2_INST_PREFETCHES

};

#define NPREFETCH_EVENTS	sizeof(prefetch_events)/sizeof(int)

static int

check_prefetch_events(pfmlib_input_param_t *inp)

{

	int code;

	int prefetch_codes[NPREFETCH_EVENTS];

	unsigned int i, j, count;

	int c;

	int found = 0;

	for(i=0; i < NPREFETCH_EVENTS; i++) {

		pfm_get_event_code(prefetch_events[i], &code);

		prefetch_codes[i] = code;

	}

	count = inp->pfp_event_count;

	for(i=0; i < count; i++) {

		pfm_get_event_code(inp->pfp_events[i].event, &c);

		for(j=0; j < NPREFETCH_EVENTS; j++) {

			if (c == prefetch_codes[j]) found++;

		}

	}

	return found;

}

/*

 * IA64_INST_RETIRED (and subevents) is the only event which can be measured on all

 * 4 IBR when non-fine mode is not possible.

 *

 * This function returns:

 * 	- the number of events matching the IA64_INST_RETIRED code

 * 	- in retired_mask the bottom 4 bits indicates which of the 4 INST_RETIRED event

 * 	is present

 */

static unsigned int

check_inst_retired_events(pfmlib_input_param_t *inp, unsigned long *retired_mask)

{

	int code;

	int c, ret;

	unsigned int i, count, found = 0;

	unsigned long umask, mask;

	pfm_get_event_code(PME_ITA2_IA64_INST_RETIRED_THIS, &code);

	count = inp->pfp_event_count;

	mask  = 0;

	for(i=0; i < count; i++) {

		ret = pfm_get_event_code(inp->pfp_events[i].event, &c);

		if (c == code)  {

			ret = pfm_ita2_get_event_umask(inp->pfp_events[i].event, &umask);

			if (ret != PFMLIB_SUCCESS)

				break;

			switch(umask) {

				case 0: mask |= 1;

					break;

				case 1: mask |= 2;

					break;

				case 2: mask |= 4;

					break;

				case 3: mask |= 8;

					break;

			}

			found++;

		}

	}

	if (retired_mask) *retired_mask = mask;

	return found;

}

static int

check_fine_mode_possible(pfmlib_ita2_input_rr_t *rr, int n)

{

	pfmlib_ita2_input_rr_desc_t *lim = rr->rr_limits;

	int i;

	for(i=0; i < n; i++) {

		if ((lim[i].rr_start & FINE_MODE_MASK) != (lim[i].rr_end & FINE_MODE_MASK))

			return 0;

	}

	return 1;

}

/*

 * mode = 0 -> check code (enforce bundle alignment)

 * mode = 1 -> check data

 */

static int

check_intervals(pfmlib_ita2_input_rr_t *irr, int mode, unsigned int *n_intervals)

{

	unsigned int i;

	pfmlib_ita2_input_rr_desc_t *lim = irr->rr_limits;

	for(i=0; i < 4; i++) {

		/* end marker */

		if (lim[i].rr_start == 0 && lim[i].rr_end == 0) break;

		/* invalid entry */

		if (lim[i].rr_start >= lim[i].rr_end) return PFMLIB_ERR_IRRINVAL;

		if (mode == 0 && (lim[i].rr_start & 0xf || lim[i].rr_end & 0xf))

			return PFMLIB_ERR_IRRALIGN;

	}

	*n_intervals = i;

	return PFMLIB_SUCCESS;

}

static int

valid_assign(pfmlib_event_t *e, unsigned int *as, pfmlib_regmask_t *r_pmcs, unsigned int cnt)

{

	unsigned long pmc4_umask = 0, umask;

	char *name;

	int l1_grp_present = 0, l2_grp_present = 0;

	unsigned int i;

	int c, failure;

	int need_pmc5, need_pmc4;

  	int pmc5_evt = -1, pmc4_evt = -1;

	if (PFMLIB_DEBUG()) {

		unsigned int j;

		for(j=0;j

			name = pfm_ita2_get_event_name(e[j].event);

			printf("%-2u (%d,%d): %s\n",

				as[j],

				evt_grp(e[j].event) == PFMLIB_ITA2_EVT_NO_GRP ? -1 : evt_grp(e[j].event),

				evt_set(e[j].event) == 0xf ? -1 : evt_set(e[j].event),

				name);

		}

	}

	failure = 1;

	/*

	 * first: check that all events have an assigned counter

	 */

	for(i=0; i < cnt; i++) {

		if (as[i]==0) goto do_failure;

		/*

		 * take care of restricted PMC registers

		 */

		if (pfm_regmask_isset(r_pmcs, as[i]))

			goto do_failure;

	}

	/*

	 * second: scan list of events for the presence of groups

	 * at this point, we know that there can be no set crossing per group

	 * because this has been tested earlier.

	 */

	for(i=0; i < cnt; i++) {

		c = e[i].event;

		if (evt_grp(c) == PFMLIB_ITA2_EVT_L1_CACHE_GRP) l1_grp_present = 1;

		if (evt_grp(c) == PFMLIB_ITA2_EVT_L2_CACHE_GRP) l2_grp_present = 1;

	}

	/*

	 * third: scan assignements and make sure that there is at least one

	 * member of a special group assigned to either PMC4 or PMC5 depending

	 * on the constraint for that group

	 */

	if (l1_grp_present || l2_grp_present) {

		need_pmc5 = l1_grp_present;

		need_pmc4 = l2_grp_present;

		for(i=0; i < cnt; i++) {

			if (need_pmc5 && as[i] == 5 && evt_grp(e[i].event) == PFMLIB_ITA2_EVT_L1_CACHE_GRP) {

				need_pmc5 = 0;

				pmc5_evt = e[i].event;

			}

			if (need_pmc4 && as[i] == 4 && evt_grp(e[i].event) == PFMLIB_ITA2_EVT_L2_CACHE_GRP) {

				need_pmc4 = 0;

				pmc4_evt = e[i].event;

			}

			if (need_pmc4 == 0 && need_pmc5 == 0) break;

		}

		failure = 2;

		if (need_pmc4) goto do_failure;

		failure = 3;

		if (need_pmc5) goto do_failure;

	}

	/*

	 * fourth: for the L2 cache event group, you must make sure that there is no

	 * umask conflict, except for sets 1 and 2 which do not suffer from this restriction.

	 * The umask in PMC4 determines the umask for all the other events in the same set.

	 * It is ignored if the event does no belong to a set or if the event has no

	 * umask (don't care umask).

	 *

	 * XXX: redudant, already checked in check_cross_groups_and_umasks(pfmlib_param_t *evt)

	 */

	if (l2_grp_present && evt_set(pmc4_evt) != 1 && evt_set(pmc4_evt) != 2) {

		/*

		 * extract the umask of the "key" event

		 */

		pmc4_umask = evt_umask(pmc4_evt);

		failure = 4;

		for(i=0; i < cnt; i++) {

			umask = evt_umask(e[i].event);

			DPRINT("pmc4_evt=%d pmc4_umask=0x%lx cnt_list[%d]=%d grp=%d umask=0x%lx\n", pmc4_evt, pmc4_umask, i, e[i].event,evt_grp(e[i].event), umask);

			if (as[i] != 4 && evt_grp(e[i].event) == PFMLIB_ITA2_EVT_L2_CACHE_GRP && umask != 0 && umask != pmc4_umask) break;

		}

		if (i != cnt) goto do_failure;

	}

	return PFMLIB_SUCCESS;

do_failure:

	DPRINT("%s : failure %d\n", __FUNCTION__, failure);

	return PFMLIB_ERR_NOASSIGN;

}

/*

 * It is not possible to measure more than one of the

 * L2_OZQ_CANCELS0, L2_OZQ_CANCELS1, L2_OZQ_CANCELS2 at the

 * same time.

 */

static int cancel_events[]=

{

	PME_ITA2_L2_OZQ_CANCELS0_ANY,

	PME_ITA2_L2_OZQ_CANCELS1_REL,

	PME_ITA2_L2_OZQ_CANCELS2_ACQ

};

#define NCANCEL_EVENTS	sizeof(cancel_events)/sizeof(int)

static int

check_cancel_events(pfmlib_input_param_t *inp)

{

	unsigned int i, j, count;

	int code;

	int cancel_codes[NCANCEL_EVENTS];

	int idx = -1;

	for(i=0; i < NCANCEL_EVENTS; i++) {

		pfm_get_event_code(cancel_events[i], &code);

		cancel_codes[i] = code;

	}

	count = inp->pfp_event_count;

	for(i=0; i < count; i++) {

		for (j=0; j < NCANCEL_EVENTS; j++) {

			pfm_get_event_code(inp->pfp_events[i].event, &code);

			if (code == cancel_codes[j]) {

				if (idx != -1) {

					return PFMLIB_ERR_INVAL;

				}

				idx = inp->pfp_events[i].event;

			}

		}

	}

	return PFMLIB_SUCCESS;

}

/*

 * Automatically dispatch events to corresponding counters following constraints.

 * Upon return the pfarg_regt structure is ready to be submitted to kernel

 */

static int

pfm_ita2_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp)

{

#define	has_counter(e,b)	(itanium2_pe[e].pme_counters & (1 << (b)) ? (b) : 0)

	pfmlib_ita2_input_param_t *param = mod_in;

	pfm_ita2_pmc_reg_t reg;

	pfmlib_event_t *e;

	pfmlib_reg_t *pc, *pd;

	pfmlib_regmask_t *r_pmcs;

	unsigned int i,j,k,l;

	int ret;

	unsigned int max_l0, max_l1, max_l2, max_l3;

	unsigned int assign[PMU_ITA2_NUM_COUNTERS];

	unsigned int m, cnt;

	e      = inp->pfp_events;

	pc     = outp->pfp_pmcs;

	pd     = outp->pfp_pmds;

	cnt    = inp->pfp_event_count;

	r_pmcs = &inp->pfp_unavail_pmcs;

	if (PFMLIB_DEBUG())

		for (m=0; m < cnt; m++) {

			DPRINT("ev[%d]=%s counters=0x%lx\n", m, itanium2_pe[e[m].event].pme_name,

				itanium2_pe[e[m].event].pme_counters);

		}

	if (cnt > PMU_ITA2_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY;

	ret = check_cross_groups_and_umasks(inp);

	if (ret != PFMLIB_SUCCESS) return ret;

	ret = check_cancel_events(inp);

	if (ret != PFMLIB_SUCCESS) return ret;

	max_l0 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS;

	max_l1 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>1);

	max_l2 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>2);

	max_l3 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>3);

	DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3);

	/*

	 *  For now, worst case in the loop nest: 4! (factorial)

	 */

	for (i=PMU_ITA2_FIRST_COUNTER; i < max_l0; i++) {

		assign[0] = has_counter(e[0].event,i);

		if (max_l1 == PMU_ITA2_FIRST_COUNTER && valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done;

		for (j=PMU_ITA2_FIRST_COUNTER; j < max_l1; j++) {

			if (j == i) continue;

			assign[1] = has_counter(e[1].event,j);

			if (max_l2 == PMU_ITA2_FIRST_COUNTER && valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done;

			for (k=PMU_ITA2_FIRST_COUNTER; k < max_l2; k++) {

				if(k == i || k == j) continue;

				assign[2] = has_counter(e[2].event,k);

				if (max_l3 == PMU_ITA2_FIRST_COUNTER && valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done;

				for (l=PMU_ITA2_FIRST_COUNTER; l < max_l3; l++) {

					if(l == i || l == j || l == k) continue;

					assign[3] = has_counter(e[3].event,l);

					if (valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done;

				}

			}

		}

	}

	/* we cannot satisfy the constraints */

	return PFMLIB_ERR_NOASSIGN;

done:

	for (j=0; j < cnt ; j++ ) {

		reg.pmc_val    = 0; /* clear all, bits 26-27 must be zero for proper operations */

		/* if plm is 0, then assume not specified per-event and use default */

		reg.pmc_plm    = inp->pfp_events[j].plm ? inp->pfp_events[j].plm : inp->pfp_dfl_plm;

		reg.pmc_oi     = 1; /* overflow interrupt */

		reg.pmc_pm     = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0;

		reg.pmc_thres  = param ? param->pfp_ita2_counters[j].thres: 0;

		reg.pmc_ism    = param ? param->pfp_ita2_counters[j].ism : PFMLIB_ITA2_ISM_BOTH;

		reg.pmc_umask  = is_ear(e[j].event) ? 0x0 : itanium2_pe[e[j].event].pme_umask;

		reg.pmc_es     = itanium2_pe[e[j].event].pme_code;

		/*

		 * Note that we don't force PMC4.pmc_ena = 1 because the kernel takes care of this for us.

		 * This way we don't have to program something in PMC4 even when we don't use it

		 */

		pc[j].reg_num     = assign[j];

		pc[j].reg_value   = reg.pmc_val;

		pc[j].reg_addr    = pc[j].reg_alt_addr = assign[j];

		pd[j].reg_num  = assign[j];

		pd[j].reg_addr = pd[j].reg_alt_addr = assign[j];

		__pfm_vbprintf("[PMC%u(pmc%u)=0x%06lx thres=%d es=0x%02x plm=%d umask=0x%x pm=%d ism=0x%x oi=%d] %s\n",

				assign[j],

				assign[j],

				reg.pmc_val,

				reg.pmc_thres,

				reg.pmc_es,reg.pmc_plm,

				reg.pmc_umask, reg.pmc_pm,

				reg.pmc_ism,

				reg.pmc_oi,

				itanium2_pe[e[j].event].pme_name);

		__pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num);

	}

	/* number of PMC registers programmed */

	outp->pfp_pmc_count = cnt;

	outp->pfp_pmd_count = cnt;

	return PFMLIB_SUCCESS;

}

static int

pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp)

{

	pfm_ita2_pmc_reg_t reg;

	pfmlib_ita2_input_param_t *param = mod_in;

	pfmlib_reg_t *pc, *pd;

	pfmlib_ita2_input_param_t fake_param;

	unsigned int pos1, pos2;

	unsigned int i, count;

	pc = outp->pfp_pmcs;

	pd = outp->pfp_pmds;

	pos1 = outp->pfp_pmc_count;

	pos2 = outp->pfp_pmd_count;

	count = inp->pfp_event_count;

	for (i=0; i < count; i++) {

		if (is_iear(inp->pfp_events[i].event)) break;

	}

	if (param == NULL || param->pfp_ita2_iear.ear_used == 0) {

		/*

		 * case 3: no I-EAR event, no (or nothing) in param->pfp_ita2_iear.ear_used

		 */

		if (i == count) return PFMLIB_SUCCESS;

		memset(&fake_param, 0, sizeof(fake_param));

		param = &fake_param;

		/*

		 * case 1: extract all information for event (name)

		 */

		pfm_ita2_get_ear_mode(inp->pfp_events[i].event, &param->pfp_ita2_iear.ear_mode);

		param->pfp_ita2_iear.ear_umask = evt_umask(inp->pfp_events[i].event);

		param->pfp_ita2_iear.ear_ism   = PFMLIB_ITA2_ISM_BOTH; /* force both instruction sets */

		DPRINT("I-EAR event with no info\n");

	}

	/*

	 * case 2: ear_used=1, event is defined, we use the param info as it is more precise

	 * case 4: ear_used=1, no event (free running I-EAR), use param info

	 */

	reg.pmc_val = 0;

	if (param->pfp_ita2_iear.ear_mode == PFMLIB_ITA2_EAR_TLB_MODE) {

		/* if plm is 0, then assume not specified per-event and use default */

		reg.pmc10_ita2_tlb_reg.iear_plm     = param->pfp_ita2_iear.ear_plm ? param->pfp_ita2_iear.ear_plm : inp->pfp_dfl_plm;

		reg.pmc10_ita2_tlb_reg.iear_pm      = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0;

		reg.pmc10_ita2_tlb_reg.iear_ct      = 0x0;

		reg.pmc10_ita2_tlb_reg.iear_umask   = param->pfp_ita2_iear.ear_umask;

		reg.pmc10_ita2_tlb_reg.iear_ism     = param->pfp_ita2_iear.ear_ism;

	} else if (param->pfp_ita2_iear.ear_mode == PFMLIB_ITA2_EAR_CACHE_MODE) {

		/* if plm is 0, then assume not specified per-event and use default */

		reg.pmc10_ita2_cache_reg.iear_plm   = param->pfp_ita2_iear.ear_plm ? param->pfp_ita2_iear.ear_plm : inp->pfp_dfl_plm;

		reg.pmc10_ita2_cache_reg.iear_pm    = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0;

		reg.pmc10_ita2_cache_reg.iear_ct    = 0x1;

		reg.pmc10_ita2_cache_reg.iear_umask = param->pfp_ita2_iear.ear_umask;

		reg.pmc10_ita2_cache_reg.iear_ism   = param->pfp_ita2_iear.ear_ism;

	} else {

		DPRINT("ALAT mode not supported in I-EAR mode\n");

		return PFMLIB_ERR_INVAL;

	}

	if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 10))

		return PFMLIB_ERR_NOASSIGN;

	pc[pos1].reg_num     = 10; /* PMC10 is I-EAR config register */

	pc[pos1].reg_value   = reg.pmc_val;

	pc[pos1].reg_addr  = pc[pos1].reg_alt_addr = 10;

	pos1++;

	pd[pos2].reg_num     = 0; 

	pd[pos2].reg_addr  = pd[pos2].reg_alt_addr= 0;

	pos2++;

	pd[pos2].reg_num     = 1; 

	pd[pos2].reg_addr  = pd[pos2].reg_alt_addr = 1;

	pos2++;

	if (param->pfp_ita2_iear.ear_mode == PFMLIB_ITA2_EAR_TLB_MODE) {

		__pfm_vbprintf("[PMC10(pmc10)=0x%lx ctb=tlb plm=%d pm=%d ism=0x%x umask=0x%x]\n",

			reg.pmc_val,

			reg.pmc10_ita2_tlb_reg.iear_plm,

			reg.pmc10_ita2_tlb_reg.iear_pm,

			reg.pmc10_ita2_tlb_reg.iear_ism,

			reg.pmc10_ita2_tlb_reg.iear_umask);

	} else {

		__pfm_vbprintf("[PMC10(pmc10)=0x%lx ctb=cache plm=%d pm=%d ism=0x%x umask=0x%x]\n",

			reg.pmc_val,

			reg.pmc10_ita2_cache_reg.iear_plm,

			reg.pmc10_ita2_cache_reg.iear_pm,

			reg.pmc10_ita2_cache_reg.iear_ism,

			reg.pmc10_ita2_cache_reg.iear_umask);

	}

	__pfm_vbprintf("[PMD0(pmd0)]\n[PMD1(pmd1)\n");

	/* update final number of entries used */

	outp->pfp_pmc_count = pos1;

	outp->pfp_pmd_count = pos2;

	return PFMLIB_SUCCESS;

}

static int

pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp)

{

	pfm_ita2_pmc_reg_t reg;

	pfmlib_ita2_input_param_t *param = mod_in;

	pfmlib_reg_t *pc, *pd;

	pfmlib_ita2_input_param_t fake_param;

	unsigned int pos1, pos2;

	unsigned int i, count;

	pc = outp->pfp_pmcs;

	pd = outp->pfp_pmds;

	pos1 = outp->pfp_pmc_count;

	pos2 = outp->pfp_pmd_count;

	count = inp->pfp_event_count;

	for (i=0; i < count; i++) {

		if (is_dear(inp->pfp_events[i].event)) break;

	}

	if (param == NULL || param->pfp_ita2_dear.ear_used == 0) {

		/*

		 * case 3: no D-EAR event, no (or nothing) in param->pfp_ita2_dear.ear_used

		 */

		if (i == count) return PFMLIB_SUCCESS;

		memset(&fake_param, 0, sizeof(fake_param));

		param = &fake_param;

		/*

		 * case 1: extract all information for event (name)

		 */

		pfm_ita2_get_ear_mode(inp->pfp_events[i].event, &param->pfp_ita2_dear.ear_mode);

		param->pfp_ita2_dear.ear_umask = evt_umask(inp->pfp_events[i].event);

		param->pfp_ita2_dear.ear_ism   = PFMLIB_ITA2_ISM_BOTH; /* force both instruction sets */

		DPRINT("D-EAR event with no info\n");

	}

	/* sanity check on the mode */

	if (   param->pfp_ita2_dear.ear_mode != PFMLIB_ITA2_EAR_CACHE_MODE

	    && param->pfp_ita2_dear.ear_mode != PFMLIB_ITA2_EAR_TLB_MODE

	    && param->pfp_ita2_dear.ear_mode != PFMLIB_ITA2_EAR_ALAT_MODE)

		return PFMLIB_ERR_INVAL;

	/*

	 * case 2: ear_used=1, event is defined, we use the param info as it is more precise

	 * case 4: ear_used=1, no event (free running D-EAR), use param info

	 */

	reg.pmc_val = 0;

	/* if plm is 0, then assume not specified per-event and use default */

	reg.pmc11_ita2_reg.dear_plm   = param->pfp_ita2_dear.ear_plm ? param->pfp_ita2_dear.ear_plm : inp->pfp_dfl_plm;

	reg.pmc11_ita2_reg.dear_pm    = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0;

	reg.pmc11_ita2_reg.dear_mode  = param->pfp_ita2_dear.ear_mode;

	reg.pmc11_ita2_reg.dear_umask = param->pfp_ita2_dear.ear_umask;

	reg.pmc11_ita2_reg.dear_ism   = param->pfp_ita2_dear.ear_ism;

	if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 11))

		return PFMLIB_ERR_NOASSIGN;

	pc[pos1].reg_num     = 11;  /* PMC11 is D-EAR config register */

	pc[pos1].reg_value   = reg.pmc_val;

	pc[pos1].reg_addr  = pc[pos1].reg_alt_addr = 11;

	pos1++;

	pd[pos2].reg_num     = 2; 

	pd[pos2].reg_addr  = pd[pos2].reg_alt_addr = 2;

	pos2++;

	pd[pos2].reg_num     = 3; 

	pd[pos2].reg_addr  = pd[pos2].reg_alt_addr = 3;

	pos2++;

	pd[pos2].reg_num     = 17; 

	pd[pos2].reg_addr  = pd[pos2].reg_alt_addr = 17;

	pos2++;

	__pfm_vbprintf("[PMC11(pmc11)=0x%lx mode=%s plm=%d pm=%d ism=0x%x umask=0x%x]\n",

			reg.pmc_val,

			reg.pmc11_ita2_reg.dear_mode == 0 ? "L1D" :

			(reg.pmc11_ita2_reg.dear_mode == 1 ? "L1DTLB" : "ALAT"),

			reg.pmc11_ita2_reg.dear_plm,	

			reg.pmc11_ita2_reg.dear_pm,

			reg.pmc11_ita2_reg.dear_ism,

			reg.pmc11_ita2_reg.dear_umask);

	__pfm_vbprintf("[PMD2(pmd2)]\n[PMD3(pmd3)\nPMD17(pmd17)\n");

	/* update final number of entries used */

	outp->pfp_pmc_count = pos1;

	outp->pfp_pmd_count = pos2;

	return PFMLIB_SUCCESS;

}

static int

pfm_dispatch_opcm(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita2_output_param_t *mod_out)

{

	pfmlib_ita2_input_param_t *param = mod_in;

	pfmlib_reg_t *pc = outp->pfp_pmcs;

	pfm_ita2_pmc_reg_t reg, pmc15;

	unsigned int i, has_1st_pair, has_2nd_pair, count;

	unsigned int pos = outp->pfp_pmc_count;

	if (param == NULL) return PFMLIB_SUCCESS;

	/* not constrained by PMC8 nor PMC9 */

	pmc15.pmc_val = 0xffffffff; /* XXX: use PAL instead. PAL value is 0xfffffff0 */

	if (param->pfp_ita2_irange.rr_used && mod_out == NULL) return PFMLIB_ERR_INVAL;

	if (param->pfp_ita2_pmc8.opcm_used || (param->pfp_ita2_irange.rr_used && mod_out->pfp_ita2_irange.rr_nbr_used!=0) ) {

		reg.pmc_val = param->pfp_ita2_pmc8.opcm_used ? param->pfp_ita2_pmc8.pmc_val : 0xffffffff3fffffff;

		if (param->pfp_ita2_irange.rr_used) {

			reg.pmc8_9_ita2_reg.opcm_ig_ad = 0;

			reg.pmc8_9_ita2_reg.opcm_inv   = param->pfp_ita2_irange.rr_flags & PFMLIB_ITA2_RR_INV ? 1 : 0;

		} else {

			/* clear range restriction fields when none is used */

			reg.pmc8_9_ita2_reg.opcm_ig_ad = 1;

			reg.pmc8_9_ita2_reg.opcm_inv   = 0;

		}

		/* force bit 2 to 1 */

		reg.pmc8_9_ita2_reg.opcm_bit2 = 1;

		if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 8))

			return PFMLIB_ERR_NOASSIGN;

		pc[pos].reg_num     = 8;

		pc[pos].reg_value   = reg.pmc_val;

		pc[pos].reg_addr  = pc[pos].reg_alt_addr = 8;

		pos++;

		/*

		 * will be constrained by PMC8

		 */

		if (param->pfp_ita2_pmc8.opcm_used) {

			has_1st_pair = has_2nd_pair = 0;

			count = inp->pfp_event_count;

			for(i=0; i < count; i++) {

				if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8) has_1st_pair=1;

				if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8) has_2nd_pair=1;

			}

			if (has_1st_pair || has_2nd_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp0_pmc8 = 0;

			if (has_2nd_pair || has_1st_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp2_pmc8 = 0;

		}

		__pfm_vbprintf("[PMC8(pmc8)=0x%lx m=%d i=%d f=%d b=%d match=0x%x mask=0x%x inv=%d ig_ad=%d]\n",

				reg.pmc_val,

				reg.pmc8_9_ita2_reg.opcm_m,

				reg.pmc8_9_ita2_reg.opcm_i,

				reg.pmc8_9_ita2_reg.opcm_f,

				reg.pmc8_9_ita2_reg.opcm_b,

				reg.pmc8_9_ita2_reg.opcm_match,

				reg.pmc8_9_ita2_reg.opcm_mask,

				reg.pmc8_9_ita2_reg.opcm_inv,

				reg.pmc8_9_ita2_reg.opcm_ig_ad);

	}

	if (param->pfp_ita2_pmc9.opcm_used) {

		/*

		 * PMC9 can only be used to qualify IA64_INST_RETIRED_* events

		 */

		if (check_inst_retired_events(inp, NULL) != inp->pfp_event_count) return PFMLIB_ERR_FEATCOMB;

		reg.pmc_val = param->pfp_ita2_pmc9.pmc_val;

		/* ig_ad, inv are ignored for PMC9, to avoid confusion we force default values */

		reg.pmc8_9_ita2_reg.opcm_ig_ad = 1;

		reg.pmc8_9_ita2_reg.opcm_inv   = 0;

		/* force bit 2 to 1 */

		reg.pmc8_9_ita2_reg.opcm_bit2 = 1;

		if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 9))

			return PFMLIB_ERR_NOASSIGN;

		pc[pos].reg_num    = 9;

		pc[pos].reg_value  = reg.pmc_val;

		pc[pos].reg_addr = pc[pos].reg_alt_addr = 9;

		pos++;

		/*

		 * will be constrained by PMC9

		 */

		has_1st_pair = has_2nd_pair = 0;

		count = inp->pfp_event_count;

		for(i=0; i < count; i++) {

			if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9) has_1st_pair=1;

			if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9) has_2nd_pair=1;

		}