/*

 * Copyright (c) 2006 IBM Corp.

 * Contributed by Kevin Corry <kevcorry@us.ibm.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

 * IN THE SOFTWARE.

 *

 * pentium4_events.h

 *

 * This header contains arrays to describe the Event-Selection-Control

 * Registers (ESCRs), Counter-Configuration-Control Registers (CCCRs),

 * and countable events on Pentium4/Xeon/EM64T systems.

 *

 * For more details, see:

 * - IA-32 Intel Architecture Software Developer's Manual,

 *   Volume 3B: System Programming Guide, Part 2

 *   (available at: http://www.intel.com/design/Pentium4/manuals/253669.htm)

 *   - Chapter 18.10: Performance Monitoring Overview

 *   - Chapter 18.13: Performance Monitoring - Pentium4 and Xeon Processors

 *   - Chapter 18.14: Performance Monitoring and Hyper-Threading Technology

 *   - Appendix A.1: Pentium4 and Xeon Processor Performance-Monitoring Events

 *

 * This header also contains an array to describe how the Perfmon PMCs map to

 * the ESCRs and CCCRs.

 */

#ifndef _PENTIUM4_EVENTS_H_

#define _PENTIUM4_EVENTS_H_

/**

 * pentium4_escrs

 *

 * Array of event-selection-control registers that are available

 * on Pentium4.

 **/

pentium4_escr_reg_t pentium4_escrs[] = {

	{.name = "BPU_ESCR0",

	 .pmc = 0,

	 .allowed_cccrs = { 0, 9, -1, },

	},

	{.name = "IS_ESCR0",

	 .pmc = 1,

	 .allowed_cccrs = { 0, 9, -1, },

	},

	{.name = "MOB_ESCR0",

	 .pmc = 2,

	 .allowed_cccrs = { 0, 9, -1, },

	},

	{.name = "ITLB_ESCR0",

	 .pmc = 3,

	 .allowed_cccrs = { 0, 9, -1, },

	},

	{.name = "PMH_ESCR0",

	 .pmc = 4,

	 .allowed_cccrs = { 0, 9, -1, },

	},

	{.name = "IX_ESCR0",

	 .pmc = 5,

	 .allowed_cccrs = { 0, 9, -1, },

	},

	{.name = "FSB_ESCR0",

	 .pmc = 6,

	 .allowed_cccrs = { 0, 9, -1, },

	},

	{.name = "BSU_ESCR0",

	 .pmc = 7,

	 .allowed_cccrs = { 0, 9, -1, },

	},

	{.name = "MS_ESCR0",

	 .pmc = 8,

	 .allowed_cccrs = { 2, 11, -1, },

	},

	{.name = "TC_ESCR0",

	 .pmc = 9,

	 .allowed_cccrs = { 2, 11, -1, },

	},

	{.name = "TBPU_ESCR0",

	 .pmc = 10,

	 .allowed_cccrs = { 2, 11, -1, },

	},

	{.name = "FLAME_ESCR0",

	 .pmc = 11,

	 .allowed_cccrs = { 4, 13, -1, },

	},

	{.name = "FIRM_ESCR0",

	 .pmc = 12,

	 .allowed_cccrs = { 4, 13, -1, },

	},

	{.name = "SAAT_ESCR0",

	 .pmc = 13,

	 .allowed_cccrs = { 4, 13, -1, },

	},

	{.name = "U2L_ESCR0",

	 .pmc = 14,

	 .allowed_cccrs = { 4, 13, -1, },

	},

	{.name = "DAC_ESCR0",

	 .pmc = 15,

	 .allowed_cccrs = { 4, 13, -1, },

	},

	{.name = "IQ_ESCR0",

	 .pmc = 16,

	 .allowed_cccrs = { 6, 8, 15, },

	},

	{.name = "ALF_ESCR0",

	 .pmc = 17,

	 .allowed_cccrs = { 6, 8, 15, },

	},

	{.name = "RAT_ESCR0",

	 .pmc = 18,

	 .allowed_cccrs = { 6, 8, 15, },

	},

	{.name = "SSU_ESCR0",

	 .pmc = 19,

	 .allowed_cccrs = { 6, 8, 15, },

	},

	{.name = "CRU_ESCR0",

	 .pmc = 20,

	 .allowed_cccrs = { 6, 8, 15, },

	},

	{.name = "CRU_ESCR2",

	 .pmc = 21,

	 .allowed_cccrs = { 6, 8, 15, },

	},

	{.name = "CRU_ESCR4",

	 .pmc = 22,

	 .allowed_cccrs = { 6, 8, 15, },

	},

	{.name = "BPU_ESCR1",

	 .pmc = 32,

	 .allowed_cccrs = { 1, 10, -1, },

	},

	{.name = "IS_ESCR1",

	 .pmc = 33,

	 .allowed_cccrs = { 1, 10, -1, },

	},

	{.name = "MOB_ESCR1",

	 .pmc = 34,

	 .allowed_cccrs = { 1, 10, -1, },

	},

	{.name = "ITLB_ESCR1",

	 .pmc = 35,

	 .allowed_cccrs = { 1, 10, -1, },

	},

	{.name = "PMH_ESCR1",

	 .pmc = 36,

	 .allowed_cccrs = { 1, 10, -1, },

	},

	{.name = "IX_ESCR1",

	 .pmc = 37,

	 .allowed_cccrs = { 1, 10, -1, },

	},

	{.name = "FSB_ESCR1",

	 .pmc = 38,

	 .allowed_cccrs = { 1, 10, -1, },

	},

	{.name = "BSU_ESCR1",

	 .pmc = 39,

	 .allowed_cccrs = { 1, 10, -1, },

	},

	{.name = "MS_ESCR1",

	 .pmc = 40,

	 .allowed_cccrs = { 3, 12, -1, },

	},

	{.name = "TC_ESCR1",

	 .pmc = 41,

	 .allowed_cccrs = { 3, 12, -1, },

	},

	{.name = "TBPU_ESCR1",

	 .pmc = 42,

	 .allowed_cccrs = { 3, 12, -1, },

	},

	{.name = "FLAME_ESCR1",

	 .pmc = 43,

	 .allowed_cccrs = { 5, 14, -1, },

	},

	{.name = "FIRM_ESCR1",

	 .pmc = 44,

	 .allowed_cccrs = { 5, 14, -1, },

	},

	{.name = "SAAT_ESCR1",

	 .pmc = 45,

	 .allowed_cccrs = { 5, 14, -1, },

	},

	{.name = "U2L_ESCR1",

	 .pmc = 46,

	 .allowed_cccrs = { 5, 14, -1, },

	},

	{.name = "DAC_ESCR1",

	 .pmc = 47,

	 .allowed_cccrs = { 5, 14, -1, },

	},

	{.name = "IQ_ESCR1",

	 .pmc = 48,

	 .allowed_cccrs = { 7, 16, 17, },

	},

	{.name = "ALF_ESCR1",

	 .pmc = 49,

	 .allowed_cccrs = { 7, 16, 17, },

	},

	{.name = "RAT_ESCR1",

	 .pmc = 50,

	 .allowed_cccrs = { 7, 16, 17, },

	},

	{.name = "CRU_ESCR1",

	 .pmc = 51,

	 .allowed_cccrs = { 7, 16, 17, },

	},

	{.name = "CRU_ESCR3",

	 .pmc = 52,

	 .allowed_cccrs = { 7, 16, 17, },

	},

	{.name = "CRU_ESCR5",

	 .pmc = 53,

	 .allowed_cccrs = { 7, 16, 17, },

	},

};

#define PENTIUM4_NUM_ESCRS (sizeof(pentium4_escrs)/sizeof(pentium4_escrs[0]))

/**

 * pentium4_cccrs

 *

 * Array of counter-configuration-control registers that are available

 * on Pentium4.

 **/

pentium4_cccr_reg_t pentium4_cccrs[] = {

	{.name = "BPU_CCCR0",

	 .pmc = 23,

	 .pmd = 0,

	 .allowed_escrs = { 0, 1, 2, 3, 4, 5, 6, 7 },

	},

	{.name = "BPU_CCCR2",

	 .pmc = 24,

	 .pmd = 9,

	 .allowed_escrs = { 23, 24, 25, 26, 27, 28, 29, 30 },

	},

	{.name = "MS_CCCR0",

	 .pmc = 25,

	 .pmd = 2,

	 .allowed_escrs = { 8, 9, 10, -1, -1, -1, -1, -1, },

	},

	{.name = "MS_CCCR2",

	 .pmc = 56,

	 .pmd = 11,

	 .allowed_escrs = { 31, 32, 33, -1, -1, -1, -1, -1, },

	},

	{.name = "FLAME_CCCR0",

	 .pmc = 27,

	 .pmd = 4,

	 .allowed_escrs = { 11, 12, 13, 14, -1, 15, -1, -1 },

	},

	{.name = "FLAME_CCCR2",

	 .pmc = 58,

	 .pmd = 13,

	 .allowed_escrs = { 34, 35, 36, 37, -1, 38, -1, -1 },

	},

	{.name = "IQ_CCCR0",

	 .pmc = 29,

	 .pmd = 6,

	 .allowed_escrs = { 16, 17, 18, 19, 20, 21, 22, -1 },

	},

	{.name = "IQ_CCCR2",

	 .pmc = 60,

	 .pmd = 15,

	 .allowed_escrs = { 39, 40, 41, -1, 42, 43, 44, -1 },

	},

	{.name = "IQ_CCCR4",

	 .pmc = 31,

	 .pmd = 8,

	 .allowed_escrs = { 16, 17, 18, 19, 20, 21, 22, -1 },

	},

	{.name = "BPU_CCCR1",

	 .pmc = 24,

	 .pmd = 1,

	 .allowed_escrs = { 0, 1, 2, 3, 4, 5, 6, 7 },

	},

	{.name = "BPU_CCCR3",

	 .pmc = 55,

	 .pmd = 10,

	 .allowed_escrs = { 23, 24, 25, 26, 27, 28, 29, 30 },

	},

	{.name = "MS_CCCR1",

	 .pmc = 26,

	 .pmd = 3,

	 .allowed_escrs = { 8, 9, 10, -1, -1, -1, -1, -1, },

	},

	{.name = "MS_CCCR3",

	 .pmc = 57,

	 .pmd = 12,

	 .allowed_escrs = { 31, 32, 33, -1, -1, -1, -1, -1, },

	},

	{.name = "FLAME_CCCR1",

	 .pmc = 28,

	 .pmd = 5,

	 .allowed_escrs = { 11, 12, 13, 14, -1, 15, -1, -1 },

	},

	{.name = "FLAME_CCCR3",

	 .pmc = 59,

	 .pmd = 14,

	 .allowed_escrs = { 34, 35, 36, 37, -1, 38, -1, -1 },

	},

	{.name = "IQ_CCCR1",

	 .pmc = 30,

	 .pmd = 7,

	 .allowed_escrs = { 16, 17, 18, 19, 20, 21, 22, -1 },

	},

	{.name = "IQ_CCCR3",

	 .pmc = 61,

	 .pmd = 16,

	 .allowed_escrs = { 39, 40, 41, -1, 42, 43, 44, -1 },

	},

	{.name = "IQ_CCCR5",

	 .pmc = 62,

	 .pmd = 17,

	 .allowed_escrs = { 39, 40, 41, -1, 42, 43, 44, -1 },

	},

};

#define PENTIUM4_NUM_CCCRS (sizeof(pentium4_cccrs)/sizeof(pentium4_cccrs[0]))

#define PENTIUM4_NUM_PMCS (PENTIUM4_NUM_CCCRS + PENTIUM4_NUM_ESCRS)

#define PENTIUM4_NUM_PMDS PENTIUM4_NUM_CCCRS

#define PENTIUM4_COUNTER_WIDTH 40

/**

 * pentium4_pmcs

 *

 * Array of PMCs on the Pentium4, showing how they map to the ESCRs and CCCRs.

 **/

pentium4_pmc_t pentium4_pmcs[PENTIUM4_NUM_PMCS] = {

	{.name = "BPU_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 0,

	},

	{.name = "IS_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 1,

	},

	{.name = "MOB_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 2,

	},

	{.name = "ITLB_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 3,

	},

	{.name = "PMH_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 4,

	},

	{.name = "IX_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 5,

	},

	{.name = "FSB_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 6,

	},

	{.name = "BSU_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 7,

	},

	{.name = "MS_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 8,

	},

	{.name = "TC_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 9,

	},

	{.name = "TBPU_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 10,

	},

	{.name = "FLAME_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 11,

	},

	{.name = "FIRM_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 12,

	},

	{.name = "SAAT_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 13,

	},

	{.name = "U2L_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 14,

	},

	{.name = "DAC_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 15,

	},

	{.name = "IQ_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 16,

	},

	{.name = "ALF_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 17,

	},

	{.name = "RAT_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 18,

	},

	{.name = "SSU_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 19,

	},

	{.name = "CRU_ESCR0",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 20,

	},

	{.name = "CRU_ESCR2",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 21,

	},

	{.name = "CRU_ESCR4",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 22,

	},

	{.name = "BPU_CCCR0",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 0,

	},

	{.name = "BPU_CCCR2",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 1,

	},

	{.name = "MS_CCCR0",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 2,

	},

	{.name = "MS_CCCR2",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 3,

	},

	{.name = "FLAME_CCCR0",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 4,

	},

	{.name = "FLAME_CCCR2",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 5,

	},

	{.name = "IQ_CCCR0",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 6,

	},

	{.name = "IQ_CCCR2",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 7,

	},

	{.name = "IQ_CCCR4",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 8,

	},

	{.name = "BPU_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 23,

	},

	{.name = "IS_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 24,

	},

	{.name = "MOB_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 25,

	},

	{.name = "ITLB_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 26,

	},

	{.name = "PMH_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 27,

	},

	{.name = "IX_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 28,

	},

	{.name = "FSB_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 29,

	},

	{.name = "BSU_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 30,

	},

	{.name = "MS_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 31,

	},

	{.name = "TC_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 32,

	},

	{.name = "TBPU_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 33,

	},

	{.name = "FLAME_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 34,

	},

	{.name = "FIRM_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 35,

	},

	{.name = "SAAT_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 36,

	},

	{.name = "U2L_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 37,

	},

	{.name = "DAC_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 38,

	},

	{.name = "IQ_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 39,

	},

	{.name = "ALF_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 40,

	},

	{.name = "RAT_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 41,

	},

	{.name = "CRU_ESCR1",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 42,

	},

	{.name = "CRU_ESCR3",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 43,

	},

	{.name = "CRU_ESCR5",

	 .type = PENTIUM4_PMC_TYPE_ESCR,

	 .index = 44,

	},

	{.name = "BPU_CCCR1",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 9,

	},

	{.name = "BPU_CCCR3",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 10,

	},

	{.name = "MS_CCCR1",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 11,

	},

	{.name = "MS_CCCR3",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 12,

	},

	{.name = "FLAME_CCCR1",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 13,

	},

	{.name = "FLAME_CCCR3",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 14,

	},

	{.name = "IQ_CCCR1",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 15,

	},

	{.name = "IQ_CCCR3",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 16,

	},

	{.name = "IQ_CCCR5",

	 .type = PENTIUM4_PMC_TYPE_CCCR,

	 .index = 17,

	},

};

/**

 * pentium4_events

 *

 * Array of events that can be counted on Pentium4.

 **/

pentium4_event_t pentium4_events[] = {

	/* 0 */

	{.name = "TC_deliver_mode",

	 .desc = "The duration (in clock cycles) of the operating modes of "

		 "the trace cache and decode engine in the processor package.",

	 .event_select = 0x1,

	 .escr_select = 0x1,

	 .allowed_escrs = { 9, 32 },

	 .event_masks = {

		{.name = "DD",

		 .desc = "Both logical CPUs in deliver mode.",

		 .bit = 0,

		},

		{.name = "DB",

		 .desc = "Logical CPU 0 in deliver mode and "

			 "logical CPU 1 in build mode.",

		 .bit = 1,

		},

		{.name = "DI",

		 .desc = "Logical CPU 0 in deliver mode and logical CPU 1 "

			 "either halted, under machine clear condition, or "

			 "transitioning to a long microcode flow.",

		 .bit = 2,

		},

		{.name = "BD",

		 .desc = "Logical CPU 0 in build mode and "

			 "logical CPU 1 is in deliver mode.",

		 .bit = 3,

		},

		{.name = "BB",

		 .desc = "Both logical CPUs in build mode.",

		 .bit = 4,

		},

		{.name = "BI",

		 .desc = "Logical CPU 0 in build mode and logical CPU 1 "

			 "either halted, under machine clear condition, or "

			 "transitioning to a long microcode flow.",

		 .bit = 5,

		},

		{.name = "ID",

		 .desc = "Logical CPU 0 either halted, under machine clear "

			 "condition, or transitioning to a long microcode "

			 "flow, and logical CPU 1 in deliver mode.",

		 .bit = 6,

		},

		{.name = "IB",

		 .desc = "Logical CPU 0 either halted, under machine clear "

			 "condition, or transitioning to a long microcode "

			 "flow, and logical CPU 1 in build mode.",

		 .bit = 7,

		},

	 },

	},

	/* 1 */

	{.name = "BPU_fetch_request",

	 .desc = "Instruction fetch requests by the Branch Prediction Unit.",

	 .event_select = 0x3,

	 .escr_select = 0x0,

	 .allowed_escrs = { 0, 23 },

	 .event_masks = {

		{.name = "TCMISS",

		 .desc = "Trace cache lookup miss.",

		 .bit = 0,

		},

	 },

	},

	/* 2 */

	{.name = "ITLB_reference",

	 .desc = "Translations using the Instruction "

		 "Translation Look-Aside Buffer.",

	 .event_select = 0x18,

	 .escr_select = 0x3,

	 .allowed_escrs = { 3, 26 },

	 .event_masks = {

		{.name = "HIT",

		 .desc = "ITLB hit.",

		 .bit = 0,

		},

		{.name = "MISS",

		 .desc = "ITLB miss.",

		 .bit = 1,

		},

		{.name = "HIT_UC",

		 .desc = "Uncacheable ITLB hit.",

		 .bit = 2,

		},

	 },

	},

	/* 3 */

	{.name = "memory_cancel",

	 .desc = "Canceling of various types of requests in the "

		 "Data cache Address Control unit (DAC).",

	 .event_select = 0x2,

	 .escr_select = 0x5,

	 .allowed_escrs = { 15, 38 },

	 .event_masks = {

		{.name = "ST_RB_FULL",

		 .desc = "Replayed because no store request "

			 "buffer is available.",

		 .bit = 2,

		},

		{.name = "64K_CONF",

		 .desc = "Conflicts due to 64K aliasing.",

		 .bit = 3,

		},

	 },

	},

	/* 4 */

	{.name = "memory_complete",

	 .desc = "Completions of a load split, store split, "

		 "uncacheable (UC) split, or UC load.",

	 .event_select = 0x8,

	 .escr_select = 0x2,

	 .allowed_escrs = { 13, 36 },

	 .event_masks = {

		{.name = "LSC",

		 .desc = "Load split completed, excluding UC/WC loads.",

		 .bit = 0,

		},

		{.name = "SSC",

		 .desc = "Any split stores completed.",

		 .bit = 1,

		},

	 },

	},

	/* 5 */

	{.name = "load_port_replay",

	 .desc = "Replayed events at the load port.",

	 .event_select = 0x4,

	 .escr_select = 0x2,

	 .allowed_escrs = { 13, 36 },

	 .event_masks = {

		{.name = "SPLIT_LD",

		 .desc = "Split load.",

		 .bit = 1,

		},

	 },

	},

	/* 6 */

	{.name = "store_port_replay",

	 .desc = "Replayed events at the store port.",

	 .event_select = 0x5,

	 .escr_select = 0x2,

	 .allowed_escrs = { 13, 36 },

	 .event_masks = {

		{.name = "SPLIT_ST",

		 .desc = "Split store.",

		 .bit = 1,

		},

	 },

	},

	/* 7 */

	{.name = "MOB_load_replay",

	 .desc = "Count of times the memory order buffer (MOB) "

		 "caused a load operation to be replayed.",

	 .event_select = 0x3,

	 .escr_select = 0x2,

	 .allowed_escrs = { 2, 25 },

	 .event_masks = {

		{.name = "NO_STA",

		 .desc = "Replayed because of unknown store address.",

		 .bit = 1,

		},

		{.name = "NO_STD",

		 .desc = "Replayed because of unknown store data.",

		 .bit = 3,

		},

		{.name = "PARTIAL_DATA",

		 .desc = "Replayed because of partially overlapped data "

			 "access between the load and store operations.",

		 .bit = 4,

		},

		{.name = "UNALGN_ADDR",

		 .desc = "Replayed because the lower 4 bits of the "

			 "linear address do not match between the "

			 "load and store operations.",

		 .bit = 5,

		},

	 },

	},

	/* 8 */

	{.name = "page_walk_type",

	 .desc = "Page walks that the page miss handler (PMH) performs.",

	 .event_select = 0x1,

	 .escr_select = 0x4,

	 .allowed_escrs = { 4, 27 },

	 .event_masks = {

		{.name = "DTMISS",

		 .desc = "Page walk for a data TLB miss (load or store)",

		 .bit = 0,

		},

		{.name = "ITMISS",

		 .desc = "Page walk for an instruction TLB miss",

		 .bit = 1,

		},

	 },

	},

	/* 9 */

	{.name = "BSQ_cache_reference",

	 .desc = "Cache references (2nd or 3rd level caches) as seen by the "

		 "bus unit. Read types include both load and RFO, and write "

		 "types include writebacks and evictions.",

	 .event_select = 0xC,

	 .escr_select = 0x7,

	 .allowed_escrs = { 7, 30 },

	 .event_masks = {

		{.name = "RD_2ndL_HITS",

		 .desc = "Read 2nd level cache hit Shared.",

		 .bit = 0,

		},

		{.name = "RD_2ndL_HITE",

		 .desc = "Read 2nd level cache hit Exclusive.",

		 .bit = 1,

		},

		{.name = "RD_2ndL_HITM",

		 .desc = "Read 2nd level cache hit Modified.",

		 .bit = 2,

		},

		{.name = "RD_3rdL_HITS",

		 .desc = "Read 3rd level cache hit Shared.",

		 .bit = 3,

		},

		{.name = "RD_3rdL_HITE",

		 .desc = "Read 3rd level cache hit Exclusive.",

		 .bit = 4,

		},

		{.name = "RD_3rdL_HITM",

		 .desc = "Read 3rd level cache hit Modified.",

		 .bit = 5,

		},

		{.name = "RD_2ndL_MISS",

		 .desc = "Read 2nd level cache miss.",

		 .bit = 8,

		},

		{.name = "RD_3rdL_MISS",

		 .desc = "Read 3rd level cache miss.",

		 .bit = 9,

		},

		{.name = "WR_2ndL_MISS",

		 .desc = "A writeback lookup from DAC misses the 2nd "

			 "level cache (unlikely to happen)",

		 .bit = 10,

		},

	 },

	},

	/* 10 */

	{.name = "IOQ_allocation",

	 .desc = "Count of various types of transactions on the bus. A count "

		 "is generated each time a transaction is allocated into the "

		 "IOQ that matches the specified mask bits. An allocated entry "

		 "can be a sector (64 bytes) or a chunk of 8 bytes. Requests "

		 "are counted once per retry. All 'TYPE_BIT*' event-masks "

		 "together are treated as a single 5-bit value.",

	 .event_select = 0x3,

	 .escr_select = 0x6,

	 .allowed_escrs = { 6, 29 },

	 .event_masks = {

		{.name = "TYPE_BIT0",

		 .desc = "Bus request type (bit 0).",

		 .bit = 0,

		},

		{.name = "TYPE_BIT1",