/*

 * Copyright (c) 2010 Google, Inc

 * Contributed by Stephane Eranian <eranian@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies

 * of the Software, and to permit persons to whom the Software is furnished to do so,

 * subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in all

 * copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,

 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF

 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE

 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 * This file is part of libpfm, a performance monitoring support library for

 * applications on Linux.

 */

static pme_nhm_entry_t wsm_pe[]={

	/*

	 * BEGIN architected events

	 */

	{.pme_name = "UNHALTED_CORE_CYCLES",

		.pme_code = 0x003c,

		.pme_cntmsk = 0x2000f,

		.pme_flags = PFMLIB_NHM_FIXED1,

		.pme_desc =  "count core clock cycles whenever the clock signal on the specific core is running (not halted). Alias to event CPU_CLK_UNHALTED:THREAD"

	},

	{.pme_name = "INSTRUCTION_RETIRED",

		.pme_code = 0x00c0,

		.pme_cntmsk = 0x1000f,

		.pme_flags = PFMLIB_NHM_FIXED0|PFMLIB_NHM_PEBS,

		.pme_desc =  "count the number of instructions at retirement. Alias to event INST_RETIRED:ANY_P",

	},

	{.pme_name = "INSTRUCTIONS_RETIRED",

		.pme_code = 0x00c0,

		.pme_cntmsk = 0x1000f,

		.pme_flags = PFMLIB_NHM_FIXED0|PFMLIB_NHM_PEBS,

		.pme_desc =  "This is an alias for INSTRUCTION_RETIRED",

	},

	{.pme_name = "UNHALTED_REFERENCE_CYCLES",

		.pme_code = 0x013c,

		.pme_cntmsk = 0x40000,

		.pme_flags = PFMLIB_NHM_FIXED2_ONLY,

		.pme_desc =  "Unhalted reference cycles",

	},

	{.pme_name = "LLC_REFERENCES",

		.pme_code = 0x4f2e,

		.pme_cntmsk = 0xf,

		.pme_desc =  "count each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESI",

	},

	{.pme_name = "LAST_LEVEL_CACHE_REFERENCES",

		.pme_code = 0x4f2e,

		.pme_cntmsk = 0xf,

		.pme_desc =  "This is an alias for LLC_REFERENCES",

	},

	{.pme_name = "LLC_MISSES",

		.pme_code = 0x412e,

		.pme_cntmsk = 0xf,

		.pme_desc =  "count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATE",

	},

	{.pme_name = "LAST_LEVEL_CACHE_MISSES",

		.pme_code = 0x412e,

		.pme_cntmsk = 0xf,

		.pme_desc =  "This is an alias for LLC_MISSES",

	},

	{.pme_name = "BRANCH_INSTRUCTIONS_RETIRED",

		.pme_code = 0x00c4,

		.pme_cntmsk = 0xf,

		.pme_desc =  "count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction. Alias to event BR_INST_RETIRED:ANY",

	},

	/*

	 * BEGIN core specific events

	 */

	{ .pme_name   = "UOPS_DECODED",

	  .pme_desc   = "micro-ops decoded",

	  .pme_code   = 0xD1,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "ESP_FOLDING",

		  .pme_udesc  = "Stack pointer instructions decoded",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "ESP_SYNC",

		  .pme_udesc  = "Stack pointer sync operations",

		  .pme_ucode  = 0x8,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "MS_CYCLES_ACTIVE",

		  .pme_udesc  = "cycles in which at least one uop is decoded by Microcode Sequencer",

		  .pme_ucode  = 0x2 | (1<< 16), /* counter-mask = 1 */

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "STALL_CYCLES",

		  .pme_udesc  = "Cycles no Uops are decoded",

		  .pme_ucode  = 0x1 | (1<<16) | (1<<15), /* inv=1, counter-mask=1 */

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 4

	},

	{ .pme_name   = "L1D_CACHE_LOCK_FB_HIT",

	  .pme_desc   = "L1D cacheable load lock speculated or retired accepted into the fill buffer",

	  .pme_code   = 0x0152,

	  .pme_flags  = 0,

	},

	{ .pme_name   = "BPU_CLEARS",

	  .pme_desc   = "Branch Prediciton Unit clears",

	  .pme_code   = 0xE8,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "EARLY",

		  .pme_udesc  = "Early Branch Prediciton Unit clears",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "LATE",

		  .pme_udesc  = "Late Branch Prediction Unit clears",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 2

	},

	{ .pme_name   = "UOPS_RETIRED",

	  .pme_desc   = "Cycles Uops are being retired",

	  .pme_code   = 0xC2,

	  .pme_flags  = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "ANY",

		  .pme_udesc  = "Uops retired (Precise Event)",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "MACRO_FUSED",

		  .pme_udesc  = "Macro-fused Uops retired (Precise Event)",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "RETIRE_SLOTS",

		  .pme_udesc  = "Retirement slots used (Precise Event)",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "STALL_CYCLES",

		  .pme_udesc  = "Cycles Uops are not retiring (Precise Event)",

		  .pme_ucode  = 0x01 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "TOTAL_CYCLES",

		  .pme_udesc  = "Total cycles using precise uop retired event (Precise Event)",

		  .pme_ucode  = 0x01 | (1<< 16), /* counter mask = 1 */

		  .pme_uflags = PFMLIB_NHM_PEBS,

		},

		{ .pme_uname  = "ACTIVE_CYCLES",

		  .pme_udesc  = "Alias for TOTAL_CYCLES",

		  .pme_ucode  = 0x01 | (1<< 16), /* counter mask = 1 */

		  .pme_uflags = PFMLIB_NHM_PEBS,

		},

	  },

	  .pme_numasks = 6

	},

	{ .pme_name   = "BR_MISP_RETIRED",

	  .pme_desc   = "Mispredicted retired branches",

	  .pme_code   = 0xC5,

	  .pme_flags  = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "ALL_BRANCHES",

		  .pme_udesc  = "Mispredicted retired branch instructions",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "NEAR_CALL",

		  .pme_udesc  = "Mispredicted near retired calls",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "CONDITIONAL",

		  .pme_udesc  = "Mispredicted conditional branches retired",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		}

	  },

	  .pme_numasks = 3

	},

	{ .pme_name   = "EPT",

	  .pme_desc   = "Extended Page Table",

	  .pme_code   = 0x4F,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "WALK_CYCLES",

		  .pme_udesc  = "Extended Page Table walk cycles",

		  .pme_ucode  = 0x10,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 1

	},

	{ .pme_name   = "UOPS_EXECUTED",

	  .pme_desc   = "micro-ops executed",

	  .pme_code   = 0xB1,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

			{ .pme_uname  = "PORT0",

				.pme_udesc  = "Uops executed on port 0 (integer arithmetic, SIMD and FP add uops)",

				.pme_ucode  = 0x01,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PORT1",

				.pme_udesc  = "Uops executed on port 1 (integer arithmetic, SIMD, integer shift, FP multiply, FP divide uops)",

				.pme_ucode  = 0x02,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PORT2_CORE",

				.pme_udesc  = "Uops executed on port 2 from any thread (load uops) (core count only)",

				.pme_ucode  = 0x04 | (1<< 13), /* any=1 */

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PORT3_CORE",

				.pme_udesc  = "Uops executed on port 3 from any thread (store uops) (core count only)",

				.pme_ucode  = 0x08 | (1<<13), /* any=1 */

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PORT4_CORE",

				.pme_udesc  = "Uops executed on port 4 from any thread (handle store values for stores on port 3) (core count only)",

				.pme_ucode  = 0x10 | (1<<13), /* any=1 */

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PORT5",

				.pme_udesc  = "Uops executed on port 5",

				.pme_ucode  = 0x20,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PORT015",

				.pme_udesc  = "Uops issued on ports 0, 1 or 5",

				.pme_ucode  = 0x40,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PORT234_CORE",

				.pme_udesc  = "Uops issued on ports 2, 3 or 4 from any thread (core count only)",

				.pme_ucode  = 0x80 | (1<<13), /* any=1 */

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PORT015_STALL_CYCLES",

				.pme_udesc  = "Cycles no Uops issued on ports 0, 1 or 5",

				.pme_ucode  = 0x40 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */

				.pme_uflags = 0,

			},

			{ .pme_uname  = "CORE_ACTIVE_CYCLES_NO_PORT5",

		  		.pme_udesc  = "Cycles in which uops are executed only on port0-4 on any thread (core count only)",

				.pme_ucode  = 0x1f | (1<<13) | (1<<16), /* counter-mask = 1, any=1 */

			},

			{ .pme_uname  = "CORE_ACTIVE_CYCLES",

		  		.pme_udesc  = "Cycles in which uops are executed on any port any thread (core count only)",

		  		.pme_ucode  = 0x3f | (1<<13) | (1<<16), /* counter-mask = 1, any=1 */

			},

			{ .pme_uname  = "CORE_STALL_CYCLES",

		  		.pme_udesc  = "Cycles in which no uops are executed on any port any thread (core count only)",

		  		.pme_ucode  = 0x3f | (1<<13) | (1<<15) | (1<<16), /* counter-mask = 1, inv = 1,any=1 */

			},

			{ .pme_uname  = "CORE_STALL_CYCLES_NO_PORT5",

		  		.pme_udesc  = "Cycles in which no uops are executed on any port0-4 on any thread (core count only)",

		  		.pme_ucode  = 0x1f | (1<<13) | (1<<15) | (1<<16), /* counter-mask = 1, inv = 1,any=1 */

			},

			{ .pme_uname  = "CORE_STALL_COUNT",

		  		.pme_udesc  = "number of transitions from stalled to uops to execute on any port any thread(core count only)",

		  		.pme_ucode  = 0x3f | (1<<13) | (1<<15) | (1<<16) | (1<<10), /* counter-mask = 1, inv = 1, any=1, edge=1 */

			},

			{ .pme_uname  = "CORE_STALL_COUNT_NO_PORT5",

		  		.pme_udesc  = "number of transitions from stalled to uops to execute on port0-4 on any thread (core count only)",

		  		.pme_ucode  = 0x1f | (1<<13) | (1<<15) | (1<<16) | (1<<10), /* counter-mask = 1, inv = 1, any=1, edge=1 */

			},

	  },

	  .pme_numasks = 15

	},

	{ .pme_name   = "IO_TRANSACTIONS",

	  .pme_desc   = "I/O transactions",

	  .pme_code   = 0x016C,

	  .pme_flags  = 0,

	},

	{ .pme_name   = "ES_REG_RENAMES",

	  .pme_desc   = "ES segment renames",

	  .pme_code   = 0x01D5,

	  .pme_flags  = 0,

	},

	{ .pme_name   = "INST_RETIRED",

		.pme_desc   = "Instructions retired",

		.pme_code   = 0xC0,

		.pme_flags  = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

			{ .pme_uname  = "ANY_P",

				.pme_udesc  = "Instructions Retired (Precise Event)",

				.pme_ucode  = 0x00,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "X87",

				.pme_udesc  = "Retired floating-point operations (Precise Event)",

				.pme_ucode  = 0x02,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "MMX",

		  		.pme_udesc  = "Retired MMX instructions (Precise Event)",

		  		.pme_ucode  = 0x4,

		  		.pme_uflags = 0,

			},

			{ .pme_uname  = "TOTAL_CYCLES",

				.pme_udesc  = "Total cycles (Precise Event)",

				.pme_ucode  = 0x1 | (16 << 16) | (1 <<15), /* inv=1, cmask = 16 */

				.pme_uflags = 0,

			},

		},

		.pme_numasks = 4

	},

	{ .pme_name   = "ILD_STALL",

	  .pme_desc   = "Instruction Length Decoder stalls",

	  .pme_code   = 0x87,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "ANY",

		  .pme_udesc  = "Any Instruction Length Decoder stall cycles",

		  .pme_ucode  = 0xF,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "IQ_FULL",

		  .pme_udesc  = "Instruction Queue full stall cycles",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "LCP",

		  .pme_udesc  = "Length Change Prefix stall cycles",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "MRU",

		  .pme_udesc  = "Stall cycles due to BPU MRU bypass",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "REGEN",

		  .pme_udesc  = "Regen stall cycles",

		  .pme_ucode  = 0x8,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 5

	},

	{ .pme_name   = "DTLB_LOAD_MISSES",

	  .pme_desc   = "DTLB load misses",

	  .pme_code   = 0x8,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "ANY",

		  .pme_udesc  = "DTLB load misses",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "PDE_MISS",

		  .pme_udesc  = "DTLB load miss caused by low part of address",

		  .pme_ucode  = 0x20,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "STLB_HIT",

		  .pme_udesc  = "DTLB second level hit",

		  .pme_ucode  = 0x10,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "WALK_COMPLETED",

		  .pme_udesc  = "DTLB load miss page walks complete",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "WALK_CYCLES",

		  .pme_udesc  = "DTLB load miss page walk cycles",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 5

	},

	{ .pme_name   = "L2_LINES_IN",

	  .pme_desc   = "L2 lines alloacated",

	  .pme_code   = 0xF1,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "ANY",

		  .pme_udesc  = "L2 lines alloacated",

		  .pme_ucode  = 0x7,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "E_STATE",

		  .pme_udesc  = "L2 lines allocated in the E state",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "S_STATE",

		  .pme_udesc  = "L2 lines allocated in the S state",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 3

	},

	{ .pme_name   = "SSEX_UOPS_RETIRED",

	  .pme_desc   = "SIMD micro-ops retired (Precise Event)",

	  .pme_code   = 0xC7,

	  .pme_flags  = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "PACKED_DOUBLE",

		  .pme_udesc  = "SIMD Packed-Double Uops retired (Precise Event)",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "PACKED_SINGLE",

		  .pme_udesc  = "SIMD Packed-Single Uops retired (Precise Event)",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "SCALAR_DOUBLE",

		  .pme_udesc  = "SIMD Scalar-Double Uops retired (Precise Event)",

		  .pme_ucode  = 0x8,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "SCALAR_SINGLE",

		  .pme_udesc  = "SIMD Scalar-Single Uops retired (Precise Event)",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "VECTOR_INTEGER",

		  .pme_udesc  = "SIMD Vector Integer Uops retired (Precise Event)",

		  .pme_ucode  = 0x10,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 5

	},

	{ .pme_name   = "STORE_BLOCKS",

	  .pme_desc   = "Load delayed by block code",

	  .pme_code   = 0x6,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "AT_RET",

		  .pme_udesc  = "Loads delayed with at-Retirement block code",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "L1D_BLOCK",

		  .pme_udesc  = "Cacheable loads delayed with L1D block code",

		  .pme_ucode  = 0x8,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 2

	},

	{ .pme_name   = "FP_MMX_TRANS",

	  .pme_desc   = "Floating Point to and from MMX transitions",

	  .pme_code   = 0xCC,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "ANY",

		  .pme_udesc  = "All Floating Point to and from MMX transitions",

		  .pme_ucode  = 0x3,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "TO_FP",

		  .pme_udesc  = "Transitions from MMX to Floating Point instructions",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "TO_MMX",

		  .pme_udesc  = "Transitions from Floating Point to MMX instructions",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 3

	},

	{ .pme_name   = "CACHE_LOCK_CYCLES",

	  .pme_desc   = "Cache locked",

	  .pme_code   = 0x63,

	  .pme_flags  = PFMLIB_NHM_PMC01,

	  .pme_umasks = {

		{ .pme_uname  = "L1D",

		  .pme_udesc  = "Cycles L1D locked",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "L1D_L2",

		  .pme_udesc  = "Cycles L1D and L2 locked",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 2

	},

	{ .pme_name   = "OFFCORE_REQUESTS_SQ_FULL",

	  .pme_desc   = "Offcore requests blocked due to Super Queue full",

	  .pme_code   = 0x01B2,

	  .pme_flags  = 0,

	},

	{ .pme_name   = "L3_LAT_CACHE",

	  .pme_desc   = "Last level cache accesses",

	  .pme_code   = 0x2E,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "MISS",

		  .pme_udesc  = "Last level cache miss",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "REFERENCE",

		  .pme_udesc  = "Last level cache reference",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 2

	},

	{ .pme_name   = "SIMD_INT_64",

	  .pme_desc   = "SIMD 64-bit integer operations",

	  .pme_code   = 0xFD,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "PACK",

		  .pme_udesc  = "SIMD integer 64 bit pack operations",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "PACKED_ARITH",

		  .pme_udesc  = "SIMD integer 64 bit arithmetic operations",

		  .pme_ucode  = 0x20,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "PACKED_LOGICAL",

		  .pme_udesc  = "SIMD integer 64 bit logical operations",

		  .pme_ucode  = 0x10,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "PACKED_MPY",

		  .pme_udesc  = "SIMD integer 64 bit packed multiply operations",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "PACKED_SHIFT",

		  .pme_udesc  = "SIMD integer 64 bit shift operations",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "SHUFFLE_MOVE",

		  .pme_udesc  = "SIMD integer 64 bit shuffle/move operations",

		  .pme_ucode  = 0x40,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "UNPACK",

		  .pme_udesc  = "SIMD integer 64 bit unpack operations",

		  .pme_ucode  = 0x8,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 7

	},

	{ .pme_name   = "BR_INST_DECODED",

	  .pme_desc   = "Branch instructions decoded",

	  .pme_code   = 0x01E0,

	  .pme_flags  = 0,

	},

	{ .pme_name   = "BR_MISP_EXEC",

	  .pme_desc   = "Mispredicted branches executed",

	  .pme_code   = 0x89,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "ANY",

		  .pme_udesc  = "Mispredicted branches executed",

		  .pme_ucode  = 0x7F,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "COND",

		  .pme_udesc  = "Mispredicted conditional branches executed",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "DIRECT",

		  .pme_udesc  = "Mispredicted unconditional branches executed",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "DIRECT_NEAR_CALL",

		  .pme_udesc  = "Mispredicted non call branches executed",

		  .pme_ucode  = 0x10,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "INDIRECT_NEAR_CALL",

		  .pme_udesc  = "Mispredicted indirect call branches executed",

		  .pme_ucode  = 0x20,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "INDIRECT_NON_CALL",

		  .pme_udesc  = "Mispredicted indirect non call branches executed",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "NEAR_CALLS",

		  .pme_udesc  = "Mispredicted call branches executed",

		  .pme_ucode  = 0x30,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "NON_CALLS",

		  .pme_udesc  = "Mispredicted non call branches executed",

		  .pme_ucode  = 0x7,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "RETURN_NEAR",

		  .pme_udesc  = "Mispredicted return branches executed",

		  .pme_ucode  = 0x8,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "TAKEN",

		  .pme_udesc  = "Mispredicted taken branches executed",

		  .pme_ucode  = 0x40,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 10

	},

	{ .pme_name   = "SQ_FULL_STALL_CYCLES",

	  .pme_desc   = "Super Queue full stall cycles",

	  .pme_code   = 0x01F6,

	  .pme_flags  = 0,

	},

	/*

	 * BEGIN OFFCORE_RESPONSE

	 */

	{ .pme_name   = "OFFCORE_RESPONSE_0",

		.pme_desc   = "Offcore response 0",

		.pme_code   = 0x01B7,

		.pme_flags  = PFMLIB_NHM_OFFCORE_RSP0,

	  .pme_umasks = {

			{ .pme_uname  = "DMND_DATA_RD",

				.pme_udesc  = "Request. Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches",

				.pme_ucode  = 0x01,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "DMND_RFO",

				.pme_udesc  = "Request. Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO",

				.pme_ucode  = 0x02,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "DMND_IFETCH",

				.pme_udesc  = "Request. Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches",

				.pme_ucode  = 0x04,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "WB",

				.pme_udesc  = "Request. Counts the number of writeback (modified to exclusive) transactions",

				.pme_ucode  = 0x08,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PF_DATA_RD",

				.pme_udesc  = "Request. Counts the number of data cacheline reads generated by L2 prefetchers",

				.pme_ucode  = 0x10,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PF_RFO",

				.pme_udesc  = "Request. Counts the number of RFO requests generated by L2 prefetchers",

				.pme_ucode  = 0x20,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PF_IFETCH",

				.pme_udesc  = "Request. Counts the number of code reads generated by L2 prefetchers",

				.pme_ucode  = 0x40,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "OTHER",

				.pme_udesc  = "Request. Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock",

				.pme_ucode  = 0x80,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "ANY_REQUEST",

				.pme_udesc  = "Request. Counts any request type",

				.pme_ucode  = 0xff,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "UNCORE_HIT",

				.pme_udesc  = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)",

				.pme_ucode  = 0x100,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "OTHER_CORE_HIT_SNP",

				.pme_udesc  = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)",

				.pme_ucode  = 0x200,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "OTHER_CORE_HITM",

				.pme_udesc  = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)",

				.pme_ucode  = 0x400,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "REMOTE_CACHE_FWD",

				.pme_udesc  = "Response. Counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)",

				.pme_ucode  = 0x1000,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "REMOTE_DRAM",

				.pme_udesc  = "Response. Counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM",

				.pme_ucode  = 0x2000,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "LOCAL_DRAM",

				.pme_udesc  = "Response. Counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM",

				.pme_ucode  = 0x4000,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "NON_DRAM",

				.pme_udesc  = "Response. Non-DRAM requests that were serviced by IOH",

				.pme_ucode  = 0x8000,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "ANY_RESPONSE",

				.pme_udesc  = "Response. Counts any response type",

				.pme_ucode  = 0xf700,

				.pme_uflags = 0,

			},

		},

		.pme_numasks = 17

	},

	{ .pme_name   = "OFFCORE_RESPONSE_1",

		.pme_desc   = "Offcore response 1",

		.pme_code   = 0x01BB,

		.pme_flags  = PFMLIB_NHM_OFFCORE_RSP1,

	  .pme_umasks = {

			{ .pme_uname  = "DMND_DATA_RD",

				.pme_udesc  = "Request. Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches",

				.pme_ucode  = 0x01,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "DMND_RFO",

				.pme_udesc  = "Request. Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO",

				.pme_ucode  = 0x02,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "DMND_IFETCH",

				.pme_udesc  = "Request. Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches",

				.pme_ucode  = 0x04,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "WB",

				.pme_udesc  = "Request. Counts the number of writeback (modified to exclusive) transactions",

				.pme_ucode  = 0x08,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PF_DATA_RD",

				.pme_udesc  = "Request. Counts the number of data cacheline reads generated by L2 prefetchers",

				.pme_ucode  = 0x10,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PF_RFO",

				.pme_udesc  = "Request. Counts the number of RFO requests generated by L2 prefetchers",

				.pme_ucode  = 0x20,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "PF_IFETCH",

				.pme_udesc  = "Request. Counts the number of code reads generated by L2 prefetchers",

				.pme_ucode  = 0x40,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "OTHER",

				.pme_udesc  = "Request. Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock",

				.pme_ucode  = 0x80,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "ANY_REQUEST",

				.pme_udesc  = "Request. Counts any request type",

				.pme_ucode  = 0xff,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "UNCORE_HIT",

				.pme_udesc  = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)",

				.pme_ucode  = 0x100,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "OTHER_CORE_HIT_SNP",

				.pme_udesc  = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)",

				.pme_ucode  = 0x200,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "OTHER_CORE_HITM",

				.pme_udesc  = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)",

				.pme_ucode  = 0x400,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "REMOTE_CACHE_FWD",

				.pme_udesc  = "Response. Counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)",

				.pme_ucode  = 0x1000,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "REMOTE_DRAM",

				.pme_udesc  = "Response. Counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM",

				.pme_ucode  = 0x2000,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "LOCAL_DRAM",

				.pme_udesc  = "Response. Counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM",

				.pme_ucode  = 0x4000,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "NON_DRAM",

				.pme_udesc  = "Response. Non-DRAM requests that were serviced by IOH",

				.pme_ucode  = 0x8000,

				.pme_uflags = 0,

			},

			{ .pme_uname  = "ANY_RESPONSE",

				.pme_udesc  = "Response. Counts any response type",

				.pme_ucode  = 0xf700,

				.pme_uflags = 0,

			},

		},

		.pme_numasks = 17

	},

	/*

	 * END OFFCORE_RESPONSE

	 */

	{ .pme_name   = "BACLEAR",

	  .pme_desc   = "Branch address calculator clears",

	  .pme_code   = 0xE6,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "BAD_TARGET",

		  .pme_udesc  = "BACLEAR asserted with bad target address",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "CLEAR",

		  .pme_udesc  = "BACLEAR asserted, regardless of cause",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 2

	},

	{ .pme_name   = "DTLB_MISSES",

	  .pme_desc   = "Data TLB misses",

	  .pme_code   = 0x49,

	  .pme_flags  = PFMLIB_NHM_UMASK_NCOMBO,

	  .pme_umasks = {

		{ .pme_uname  = "ANY",

		  .pme_udesc  = "DTLB misses",

		  .pme_ucode  = 0x1,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "LARGE_WALK_COMPLETED",

		  .pme_udesc  = "DTLB miss large page walks",

		  .pme_ucode  = 0x80,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "STLB_HIT",

		  .pme_udesc  = "DTLB first level misses but second level hit",

		  .pme_ucode  = 0x10,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "WALK_COMPLETED",

		  .pme_udesc  = "DTLB miss page walks",

		  .pme_ucode  = 0x2,

		  .pme_uflags = 0,

		},

		{ .pme_uname  = "WALK_CYCLES",

		  .pme_udesc  = "DTLB miss page walk cycles",

		  .pme_ucode  = 0x4,

		  .pme_uflags = 0,

		},

	  },

	  .pme_numasks = 5

	},

	{ .pme_name   = "MEM_INST_RETIRED",