{ ****************************

{  THIS IS OPEN SOURCE CODE 

{ ****************************

{ (C) COPYRIGHT International Business Machines Corp. 2005

{ This file is licensed under the University of Tennessee license.

{ See LICENSE.txt.

{

{ File:    events/ppc970/events

{ Author:  Maynard Johnson

{          maynardj@us.ibm.com

{ Mods: 

{

{ counter 1 }

#0,u,g,n,n,PM_BRQ_FULL_CYC,Cycles branch queue full

##10095,60095

The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).

#1,v,g,n,n,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full

##10094,60094

The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#2,v,g,n,n,PM_CYC,Processor cycles

##0000F

Processor cycles

#3,v,g,n,n,PM_DATA_FROM_L2,Data loaded from L2

##C3087

DL1 was reloaded from the local L2 due to a demand load

#4,v,g,n,n,PM_DATA_TABLEWALK_CYC,Cycles doing data tablewalks

##80097

This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.

#5,v,g,n,n,PM_DSLB_MISS,Data SLB misses

##80095

A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve

#6,v,g,n,n,PM_DTLB_MISS,Data TLB misses

##80094

A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.

#7,v,g,n,n,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full

##10091,60091

The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#8,v,g,n,n,PM_FPU0_ALL,FPU0 executed add, mult, sub, cmp or sel instruction

##00093

This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo

#9,v,g,n,n,PM_FPU0_DENORM,FPU0 received denormalized data

##02098

This signal is active for one cycle when one of the operands is denormalized.

#10,v,g,n,n,PM_FPU0_FDIV,FPU0 executed FDIV instruction

##00090

This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.

#11,v,g,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction

##00091

This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#12,v,g,n,n,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction

##00092

This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#13,v,g,n,n,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full

##10093,60093

The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped

#14,v,g,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction

##0209B

This signal is active for one cycle when fp0 is executing single precision instruction.

#15,v,g,n,n,PM_FPU0_STALL3,FPU0 stalled in pipe3

##02099

This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. 

#16,v,g,n,n,PM_FPU0_STF,FPU0 executed store instruction

##0209A

This signal is active for one cycle when fp0 is executing a store instruction.

#17,v,g,n,n,PM_FPU1_ALL,FPU1 executed add, mult, sub, cmp or sel instruction

##00097

This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo

#18,v,g,n,n,PM_FPU1_DENORM,FPU1 received denormalized data

##0209C

This signal is active for one cycle when one of the operands is denormalized.

#19,v,g,n,n,PM_FPU1_FDIV,FPU1 executed FDIV instruction

##00094

This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.

#20,v,g,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction

##00095

This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#21,v,g,n,n,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction

##00096

This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#22,v,g,n,n,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full

##10097,60097

The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped

#23,v,g,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction

##0209F

This signal is active for one cycle when fp1 is executing single precision instruction.

#24,v,g,n,n,PM_FPU1_STALL3,FPU1 stalled in pipe3

##0209D

This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. 

#25,v,g,n,n,PM_FPU1_STF,FPU1 executed store instruction

##0209E

This signal is active for one cycle when fp1 is executing a store instruction.

#26,v,g,n,n,PM_FPU_DENORM,FPU received denormalized data

##02080

This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1

#27,v,g,n,n,PM_FPU_FDIV,FPU executed FDIV instruction

##00080

This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1

#28,v,g,n,n,PM_GCT_EMPTY_CYC,Cycles GCT empty

##00004

The Global Completion Table is completely empty

#29,v,g,n,n,PM_GCT_FULL_CYC,Cycles GCT full

##10090,60090

The ISU sends a signal indicating the gct is full. 

#30,v,g,n,n,PM_GRP_BR_MPRED,Group experienced a branch mispredict

##1209F,6209F

Group experienced a branch mispredict

#31,v,g,n,n,PM_GRP_BR_REDIR,Group experienced branch redirect

##1209E,6209E

Group experienced branch redirect

#32,v,g,n,n,PM_GRP_DISP_REJECT,Group dispatch rejected

##1209C,6209C

A group that previously attempted dispatch was rejected.

#33,v,g,n,n,PM_GRP_DISP_VALID,Group dispatch valid

##1209B,6209B

Dispatch has been attempted for a valid group.  Some groups may be rejected.  The total number of successful dispatches is the number of dispatch valid minus dispatch reject.

#34,v,g,n,n,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch

##2209E

New line coming into the prefetch buffer

#35,v,g,n,n,PM_IC_PREF_REQ,Instruction prefetch requests

##2209D

Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).

#36,v,g,n,n,PM_IERAT_XLATE_WR,Translation written to ierat

##2209F

This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).

#37,c,g,n,n,PM_INST_CMPL,Instructions completed

##00009

Number of Eligible Instructions that completed. 

#38,v,g,n,n,PM_INST_DISP,Instructions dispatched

##12098,12099,1209A,62098,62099,6209A

The ISU sends the number of instructions dispatched.

#39,v,g,n,n,PM_INST_FROM_L1,Instruction fetched from L1

##2208D

An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions

#40,v,g,n,n,PM_INST_FROM_L2,Instructions fetched from L2

##22086

An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions

#41,u,g,n,n,PM_ISLB_MISS,Instruction SLB misses

##80091

A SLB miss for an instruction fetch as occurred

#42,v,g,n,n,PM_ITLB_MISS,Instruction TLB misses

##80090

A TLB miss for an Instruction Fetch has occurred

#43,v,g,n,n,PM_LARX_LSU0,Larx executed on LSU0

##8209F

A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)

#44,u,g,n,n,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full

##10096,60096

The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#45,v,g,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses

##80092

A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.

#46,v,g,n,n,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes

##C0092

A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#47,u,g,n,n,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes

##C0093

A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.

#48,v,g,n,n,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes

##C0090

A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#49,v,g,n,n,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes

##C0091

A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)

#50,v,g,n,n,PM_LSU0_REJECT_ERAT_MISS,LSU0 reject due to ERAT miss

##C609B

LSU0 reject due to ERAT miss

#51,v,g,n,n,PM_LSU0_REJECT_LMQ_FULL,LSU0 reject due to LMQ full or missed data coming

##C6099

LSU0 reject due to LMQ full or missed data coming

#52,v,g,n,n,PM_LSU0_REJECT_RELOAD_CDF,LSU0 reject due to reload CDF or tag update collision

##C609A

LSU0 reject due to reload CDF or tag update collision

#53,v,g,n,n,PM_LSU0_REJECT_SRQ,LSU0 SRQ rejects

##C6098

LSU0 SRQ rejects

#54,u,g,n,n,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded

##C2098

Data from a store instruction was forwarded to a load on unit 0

#55,v,g,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses

##80096

A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.

#56,v,g,n,n,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes

##C0096

A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#57,u,g,n,n,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes

##C0097

A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. 

#58,v,g,n,n,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes

##C0094

A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#59,u,g,n,n,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes

##C0095

A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)

#60,v,g,n,n,PM_LSU1_REJECT_ERAT_MISS,LSU1 reject due to ERAT miss

##C609F

LSU1 reject due to ERAT miss

#61,v,g,n,n,PM_LSU1_REJECT_LMQ_FULL,LSU1 reject due to LMQ full or missed data coming

##C609D

LSU1 reject due to LMQ full or missed data coming

#62,v,g,n,n,PM_LSU1_REJECT_RELOAD_CDF,LSU1 reject due to reload CDF or tag update collision

##C609E

LSU1 reject due to reload CDF or tag update collision

#63,v,g,n,n,PM_LSU1_REJECT_SRQ,LSU1 SRQ rejects

##C609C

LSU1 SRQ rejects

#64,u,g,n,n,PM_LSU1_SRQ_STFWD,LSU1 SRQ store forwarded

##C209C

Data from a store instruction was forwarded to a load on unit 1

#65,v,g,n,n,PM_LSU_FLUSH_ULD,LRQ unaligned load flushes

##C0080

A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#66,v,g,n,n,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated

##C209E

LRQ slot zero was allocated

#67,v,g,n,n,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid

##C209A

This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.

#68,v,g,n,n,PM_LSU_REJECT_SRQ,LSU SRQ rejects

##C6080

LSU SRQ rejects

#69,v,g,n,n,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated

##C209D

SRQ Slot zero was allocated

#70,v,g,n,n,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid

##C2099

This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.

#71,c,g,n,n,PM_LSU_SRQ_STFWD,SRQ store forwarded

##C2080

Data from a store instruction was forwarded to a load

#72,v,g,n,n,PM_MRK_DATA_FROM_L2,Marked data loaded from L2

##C7087

DL1 was reloaded from the local L2 due to a marked demand load

#73,v,g,n,n,PM_MRK_GRP_DISP,Marked group dispatched

##00002

A group containing a sampled instruction was dispatched

#74,v,g,n,n,PM_MRK_IMR_RELOAD,Marked IMR reloaded

##8209A

A DL1 reload occured due to marked load

#75,v,g,n,n,PM_MRK_LD_MISS_L1,Marked L1 D cache load misses

##82080

Marked L1 D cache load misses

#76,v,g,n,n,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses

##82098

A marked load, executing on unit 0, missed the dcache

#77,v,g,n,n,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses

##8209C

A marked load, executing on unit 1, missed the dcache

#78,v,g,n,n,PM_MRK_STCX_FAIL,Marked STCX failed

##8209E

A marked stcx (stwcx or stdcx) failed

#79,v,g,n,n,PM_MRK_ST_CMPL,Marked store instruction completed

##00003

A sampled store has completed (data home)

#80,v,g,n,n,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses

##8209B

A marked store missed the dcache

#81,v,g,n,n,PM_PMC8_OVERFLOW,PMC8 Overflow

##0000A

PMC8 Overflow

#82,v,g,n,n,PM_RUN_CYC,Run cycles

##00005

Processor Cycles gated by the run latch

#83,u,g,n,n,PM_SNOOP_TLBIE,Snoop TLBIE

##80093

A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.

#84,v,g,n,n,PM_STCX_FAIL,STCX failed

##82099

A stcx (stwcx or stdcx) failed

#85,v,g,n,n,PM_STCX_PASS,Stcx passes

##8209D

A stcx (stwcx or stdcx) instruction was successful

#86,v,g,n,n,PM_ST_MISS_L1,L1 D cache store misses

##C209B

A store missed the dcache

#87,v,g,n,n,PM_SUSPENDED,Suspended

##00008

Suspended

#88,v,g,n,n,PM_XER_MAP_FULL_CYC,Cycles XER mapper full

##10092,60092

The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

$$$$$$$$

{ counter 2 }

#0,u,g,n,n,PM_BRQ_FULL_CYC,Cycles branch queue full

##10095,60095

The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).

#1,v,g,n,n,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full

##10094,60094

The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#2,v,g,n,n,PM_CYC,Processor cycles

##0000F

Processor cycles

#3,v,g,n,n,PM_DATA_TABLEWALK_CYC,Cycles doing data tablewalks

##80097

This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.

#4,v,g,n,n,PM_DSLB_MISS,Data SLB misses

##80095

A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve

#5,v,g,n,n,PM_DTLB_MISS,Data TLB misses

##80094

A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.

#6,v,g,n,n,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full

##10091,60091

The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#7,v,g,n,n,PM_FPU0_ALL,FPU0 executed add, mult, sub, cmp or sel instruction

##00093

This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo

#8,v,g,n,n,PM_FPU0_DENORM,FPU0 received denormalized data

##02098

This signal is active for one cycle when one of the operands is denormalized.

#9,v,g,n,n,PM_FPU0_FDIV,FPU0 executed FDIV instruction

##00090

This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.

#10,v,g,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction

##00091

This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#11,v,g,n,n,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction

##00092

This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#12,v,g,n,n,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full

##10093,60093

The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped

#13,v,g,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction

##0209B

This signal is active for one cycle when fp0 is executing single precision instruction.

#14,v,g,n,n,PM_FPU0_STALL3,FPU0 stalled in pipe3

##02099

This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. 

#15,v,g,n,n,PM_FPU0_STF,FPU0 executed store instruction

##0209A

This signal is active for one cycle when fp0 is executing a store instruction.

#16,v,g,n,n,PM_FPU1_ALL,FPU1 executed add, mult, sub, cmp or sel instruction

##00097

This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo

#17,v,g,n,n,PM_FPU1_DENORM,FPU1 received denormalized data

##0209C

This signal is active for one cycle when one of the operands is denormalized.

#18,v,g,n,n,PM_FPU1_FDIV,FPU1 executed FDIV instruction

##00094

This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.

#19,v,g,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction

##00095

This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#20,v,g,n,n,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction

##00096

This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#21,v,g,n,n,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full

##10097,60097

The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped

#22,v,g,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction

##0209F

This signal is active for one cycle when fp1 is executing single precision instruction.

#23,v,g,n,n,PM_FPU1_STALL3,FPU1 stalled in pipe3

##0209D

This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. 

#24,v,g,n,n,PM_FPU1_STF,FPU1 executed store instruction

##0209E

This signal is active for one cycle when fp1 is executing a store instruction.

#25,v,g,n,n,PM_FPU_FMA,FPU executed multiply-add instruction

##00080

This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1

#26,v,g,n,n,PM_FPU_STALL3,FPU stalled in pipe3

##02080

FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1

#27,v,g,n,n,PM_GCT_EMPTY_SRQ_FULL,GCT empty caused by SRQ full

##0000B

GCT empty caused by SRQ full

#28,v,g,n,n,PM_GCT_FULL_CYC,Cycles GCT full

##10090,60090

The ISU sends a signal indicating the gct is full. 

#29,v,g,n,n,PM_GRP_BR_MPRED,Group experienced a branch mispredict

##1209F,6209F

Group experienced a branch mispredict

#30,v,g,n,n,PM_GRP_BR_REDIR,Group experienced branch redirect

##1209E,6209E

Group experienced branch redirect

#31,v,g,n,n,PM_GRP_DISP,Group dispatches

##00004

A group was dispatched

#32,v,g,n,n,PM_GRP_DISP_REJECT,Group dispatch rejected

##1209C,6209C

A group that previously attempted dispatch was rejected.

#33,v,g,n,n,PM_GRP_DISP_VALID,Group dispatch valid

##1209B,6209B

Dispatch has been attempted for a valid group.  Some groups may be rejected.  The total number of successful dispatches is the number of dispatch valid minus dispatch reject.

#34,v,g,n,n,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch

##2209E

New line coming into the prefetch buffer

#35,v,g,n,n,PM_IC_PREF_REQ,Instruction prefetch requests

##2209D

Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).

#36,v,g,n,n,PM_IERAT_XLATE_WR,Translation written to ierat

##2209F

This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).

#37,c,g,n,n,PM_INST_CMPL,Instructions completed

##00009

Number of Eligible Instructions that completed. 

#38,v,g,n,n,PM_INST_DISP,Instructions dispatched

##12098,12099,1209A,62098,62099,6209A

The ISU sends the number of instructions dispatched.

#39,v,g,n,n,PM_INST_FROM_MEM,Instruction fetched from memory

##22086

Instruction fetched from memory

#40,u,g,n,n,PM_ISLB_MISS,Instruction SLB misses

##80091

A SLB miss for an instruction fetch as occurred

#41,v,g,n,n,PM_ITLB_MISS,Instruction TLB misses

##80090

A TLB miss for an Instruction Fetch has occurred

#42,v,g,n,n,PM_LARX_LSU0,Larx executed on LSU0

##8209F

A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)

#43,u,g,n,n,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full

##10096,60096

The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#44,v,g,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses

##80092

A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.

#45,v,g,n,n,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes

##C0092

A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#46,u,g,n,n,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes

##C0093

A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.

#47,v,g,n,n,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes

##C0090

A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#48,v,g,n,n,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes

##C0091

A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)

#49,v,g,n,n,PM_LSU0_REJECT_ERAT_MISS,LSU0 reject due to ERAT miss

##C609B

LSU0 reject due to ERAT miss

#50,v,g,n,n,PM_LSU0_REJECT_LMQ_FULL,LSU0 reject due to LMQ full or missed data coming

##C6099

LSU0 reject due to LMQ full or missed data coming

#51,v,g,n,n,PM_LSU0_REJECT_RELOAD_CDF,LSU0 reject due to reload CDF or tag update collision

##C609A

LSU0 reject due to reload CDF or tag update collision

#52,v,g,n,n,PM_LSU0_REJECT_SRQ,LSU0 SRQ rejects

##C6098

LSU0 SRQ rejects

#53,u,g,n,n,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded

##C2098

Data from a store instruction was forwarded to a load on unit 0

#54,v,g,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses

##80096

A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.

#55,v,g,n,n,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes

##C0096

A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#56,u,g,n,n,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes

##C0097

A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. 

#57,v,g,n,n,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes

##C0094

A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#58,u,g,n,n,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes

##C0095

A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)

#59,v,g,n,n,PM_LSU1_REJECT_ERAT_MISS,LSU1 reject due to ERAT miss

##C609F

LSU1 reject due to ERAT miss

#60,v,g,n,n,PM_LSU1_REJECT_LMQ_FULL,LSU1 reject due to LMQ full or missed data coming

##C609D

LSU1 reject due to LMQ full or missed data coming

#61,v,g,n,n,PM_LSU1_REJECT_RELOAD_CDF,LSU1 reject due to reload CDF or tag update collision

##C609E

LSU1 reject due to reload CDF or tag update collision

#62,v,g,n,n,PM_LSU1_REJECT_SRQ,LSU1 SRQ rejects

##C609C

LSU1 SRQ rejects

#63,u,g,n,n,PM_LSU1_SRQ_STFWD,LSU1 SRQ store forwarded

##C209C

Data from a store instruction was forwarded to a load on unit 1

#64,v,g,n,n,PM_LSU_FLUSH_UST,SRQ unaligned store flushes

##C0080

A store was flushed because it was unaligned

#65,u,g,n,n,PM_LSU_LMQ_SRQ_EMPTY_CYC,Cycles LMQ and SRQ empty

##00002

Cycles when both the LMQ and SRQ are empty (LSU is idle)

#66,v,g,n,n,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated

##C209E

LRQ slot zero was allocated

#67,v,g,n,n,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid

##C209A

This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.

#68,v,g,n,n,PM_LSU_REJECT_LMQ_FULL,LSU reject due to LMQ full or missed data coming

##C6080

LSU reject due to LMQ full or missed data coming

#69,v,g,n,n,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated

##C209D

SRQ Slot zero was allocated

#70,v,g,n,n,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid

##C2099

This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.

#71,v,g,n,n,PM_MRK_BRU_FIN,Marked instruction BRU processing finished

##00005

The branch unit finished a marked instruction. Instructions that finish may not necessary complete

#72,v,g,n,n,PM_MRK_IMR_RELOAD,Marked IMR reloaded

##8209A

A DL1 reload occured due to marked load

#73,v,g,n,n,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses

##82098

A marked load, executing on unit 0, missed the dcache

#74,v,g,n,n,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses

##8209C

A marked load, executing on unit 1, missed the dcache

#75,v,g,n,n,PM_MRK_STCX_FAIL,Marked STCX failed

##8209E

A marked stcx (stwcx or stdcx) failed

#76,v,g,n,n,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses

##8209B

A marked store missed the dcache

#77,v,g,n,n,PM_PMC1_OVERFLOW,PMC1 Overflow

##0000A

PMC1 Overflow

#78,u,g,n,n,PM_SNOOP_TLBIE,Snoop TLBIE

##80093

A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.

#79,v,g,n,n,PM_STCX_FAIL,STCX failed

##82099

A stcx (stwcx or stdcx) failed

#80,v,g,n,n,PM_STCX_PASS,Stcx passes

##8209D

A stcx (stwcx or stdcx) instruction was successful

#81,v,g,n,n,PM_ST_MISS_L1,L1 D cache store misses

##C209B

A store missed the dcache

#82,v,g,n,n,PM_SUSPENDED,Suspended

##00008

Suspended

#83,v,g,t,n,PM_THRESH_TIMEO,Threshold timeout

##00003

The threshold timer expired

#84,v,g,n,n,PM_WORK_HELD,Work held

##00001

RAS Unit has signaled completion to stop and there are groups waiting to complete

#85,v,g,n,n,PM_XER_MAP_FULL_CYC,Cycles XER mapper full

##10092,60092

The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

$$$$$$$$

{ counter 3 }

#0,v,g,n,n,PM_BR_ISSUED,Branches issued

##23098

This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.

#1,v,g,n,n,PM_BR_MPRED_CR,Branch mispredictions due to CR bit setting

##23099

This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.

#2,v,g,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address

##2309A

branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.

#3,u,g,n,n,PM_CRQ_FULL_CYC,Cycles CR issue queue full

##11091,61091

The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).

#4,v,g,n,n,PM_CYC,Processor cycles

##0000F

Processor cycles

#5,v,g,n,n,PM_DATA_FROM_MEM,Data loaded from memory

##C3087

Data loaded from memory

#6,u,g,n,n,PM_DC_INV_L2,L1 D cache entries invalidated from L2

##C1097

A dcache invalidated was received from the L2 because a line in L2 was castout.

#7,u,g,n,n,PM_DC_PREF_OUT_OF_STREAMS,D cache out of streams

##8309A

out of streams

#8,v,g,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated

##8309F

A new Prefetch Stream was allocated

#9,v,g,n,n,PM_EE_OFF,Cycles MSR(EE) bit off

##1309B,6309B

The number of Cycles MSR(EE) bit was off.

#10,u,g,n,n,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending

##1309F,6309F

Cycles MSR(EE) bit off and external interrupt pending

#11,v,g,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict

##11096,61096

Flush caused by branch mispredict

#12,v,g,n,n,PM_FLUSH_LSU_BR_MPRED,Flush caused by LSU or branch mispredict

##11097,61097

Flush caused by LSU or branch mispredict

#13,v,g,n,n,PM_FPU0_FEST,FPU0 executed FEST instruction

##01092

This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 

#14,v,g,n,n,PM_FPU0_FIN,FPU0 produced a result

##01093

fp0 finished, produced a result This only indicates finish, not completion. 

#15,v,g,n,n,PM_FPU0_FMOV_FEST,FPU0 executed FMOV or FEST instructions

##01090

This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ

#16,v,g,n,n,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction

##03098

This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs

#17,v,g,n,n,PM_FPU0_FRSP_FCONV,FPU0 executed FRSP or FCONV instructions

##01091

This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#18,v,g,n,n,PM_FPU1_FEST,FPU1 executed FEST instruction

##01096

This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 

#19,v,g,n,n,PM_FPU1_FIN,FPU1 produced a result

##01097

fp1 finished, produced a result. This only indicates finish, not completion. 

#20,v,g,n,n,PM_FPU1_FMOV_FEST,FPU1 executing FMOV or FEST instructions

##01094

This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ

#21,v,g,n,n,PM_FPU1_FRSP_FCONV,FPU1 executed FRSP or FCONV instructions

##01095

This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#22,v,g,n,n,PM_FPU_FEST,FPU executed FEST instruction

##01080

This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.

#23,v,g,n,n,PM_FXLS0_FULL_CYC,Cycles FXU0/LS0 queue full

##11090,61090

The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped

#24,v,g,n,n,PM_FXLS1_FULL_CYC,Cycles FXU1/LS1 queue full

##11094,61094

The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped

#25,v,g,n,n,PM_FXU0_FIN,FXU0 produced a result

##1309A,6309A

The Fixed Point unit 0 finished an instruction and produced a result

#26,v,g,n,n,PM_FXU1_FIN,FXU1 produced a result

##1309E,6309E

The Fixed Point unit 1 finished an instruction and produced a result

#27,v,g,n,n,PM_FXU_FIN,FXU produced a result

##63080

The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.

#28,v,g,n,n,PM_GPR_MAP_FULL_CYC,Cycles GPR mapper full

##1309D,6309D

The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#29,v,g,n,n,PM_GRP_DISP_BLK_SB_CYC,Cycles group dispatch blocked by scoreboard

##13099,63099

The ISU sends a signal indicating that dispatch is blocked by scoreboard.

#30,v,g,n,n,PM_HV_CYC,Hypervisor Cycles

##00004

Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)

#31,c,g,n,n,PM_INST_CMPL,Instructions completed

##00009

Number of Eligible Instructions that completed. 

#32,v,g,n,n,PM_INST_FROM_PREF,Instructions fetched from prefetch

##2208D

An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions

#33,v,g,n,n,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid

##C309C

The data source information is valid

#34,v,g,n,n,PM_L1_PREF,L1 cache data prefetches

##83099

A request to prefetch data into the L1 was made

#35,v,g,n,n,PM_L1_WRITE_CYC,Cycles writing to instruction L1

##2309B

This signal is asserted each cycle a cache write is active.

#36,v,g,n,n,PM_L2_PREF,L2 cache prefetches

##8309B

A request to prefetch data into L2 was made

#37,v,g,n,n,PM_LD_MISS_L1,L1 D cache load misses

##C1080

Total DL1 Load references that miss the DL1

#38,v,g,n,n,PM_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses

##C1092

A load, executing on unit 0, missed the dcache

#39,v,g,n,n,PM_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses

##C1096

A load, executing on unit 1, missed the dcache

#40,v,g,n,n,PM_LD_REF_L1_LSU0,LSU0 L1 D cache load references

##C1090

A load executed on unit 0

#41,v,g,n,n,PM_LD_REF_L1_LSU1,LSU1 L1 D cache load references

##C1094

A load executed on unit 1

#42,v,g,n,n,PM_LSU0_LDF,LSU0 executed Floating Point load instruction

##83098

A floating point load was executed from LSU unit 0

#43,v,g,n,n,PM_LSU1_LDF,LSU1 executed Floating Point load instruction

##8309C

A floating point load was executed from LSU unit 1

#44,v,g,n,n,PM_LSU_FLUSH,Flush initiated by LSU

##11095,61095

Flush initiated by LSU

#45,u,g,n,n,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full

##C309F

The LMQ was full

#46,v,g,n,n,PM_LSU_LMQ_LHR_MERGE,LMQ LHR merges

##C709D

A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.

#47,v,g,n,n,PM_LSU_LMQ_S0_ALLOC,LMQ slot 0 allocated

##C309E

The first entry in the LMQ was allocated.

#48,v,g,n,n,PM_LSU_LMQ_S0_VALID,LMQ slot 0 valid

##C309D

This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO

#49,u,g,n,n,PM_LSU_LMQ_SRQ_EMPTY_CYC,Cycles LMQ and SRQ empty

##00002

Cycles when both the LMQ and SRQ are empty (LSU is idle)

#50,v,g,n,n,PM_LSU_LRQ_FULL_CYC,Cycles LRQ full

##11092,61092

The ISU sends this signal when the LRQ is full.

#51,v,g,n,n,PM_LSU_SRQ_FULL_CYC,Cycles SRQ full

##11093,61093

The ISU sends this signal when the srq is full.

#52,u,g,n,n,PM_LSU_SRQ_SYNC_CYC,SRQ sync duration

##8309D

This signal is asserted every cycle when a sync is in the SRQ.

#53,v,g,n,n,PM_MRK_DATA_FROM_MEM,Marked data loaded from memory

##C7087

Marked data loaded from memory

#54,v,g,n,n,PM_MRK_L1_RELOAD_VALID,Marked L1 reload data source valid

##C709C

The source information is valid and is for a marked load

#55,v,g,n,n,PM_MRK_LSU0_FLUSH_LRQ,LSU0 marked LRQ flushes

##81092

A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#56,u,g,n,n,PM_MRK_LSU0_FLUSH_SRQ,LSU0 marked SRQ flushes

##81093

A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.

#57,v,g,n,n,PM_MRK_LSU0_FLUSH_ULD,LSU0 marked unaligned load flushes

##81090

A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#58,v,g,n,n,PM_MRK_LSU0_FLUSH_UST,LSU0 marked unaligned store flushes

##81091

A marked store was flushed from unit 0 because it was unaligned

#59,v,g,n,n,PM_MRK_LSU1_FLUSH_LRQ,LSU1 marked LRQ flushes

##81096

A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#60,u,g,n,n,PM_MRK_LSU1_FLUSH_SRQ,LSU1 marked SRQ flushes

##81097

A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.

#61,v,g,n,n,PM_MRK_LSU1_FLUSH_ULD,LSU1 marked unaligned load flushes

##81094

A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#62,u,g,n,n,PM_MRK_LSU1_FLUSH_UST,LSU1 marked unaligned store flushes

##81095

A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)

#63,u,g,n,n,PM_MRK_LSU_SRQ_INST_VALID,Marked instruction valid in SRQ

##C709E

This signal is asserted every cycle when a marked request is resident in the Store Request Queue

#64,v,g,n,n,PM_MRK_ST_CMPL_INT,Marked store completed with intervention

##00003

A marked store previously sent to the memory subsystem completed (data home) after requiring intervention

#65,v,g,n,n,PM_MRK_VMX_FIN,Marked instruction VMX processing finished

##00005

Marked instruction VMX processing finished

#66,v,g,n,n,PM_PMC2_OVERFLOW,PMC2 Overflow

##0000A

PMC2 Overflow

#67,v,g,n,n,PM_STOP_COMPLETION,Completion stopped

##00001

RAS Unit has signaled completion to stop

#68,v,g,n,n,PM_ST_MISS_L1,L1 D cache store misses

##C1093

A store missed the dcache

#69,v,g,n,n,PM_ST_REF_L1_LSU0,LSU0 L1 D cache store references

##C1091

A store executed on unit 0

#70,v,g,n,n,PM_ST_REF_L1_LSU1,LSU1 L1 D cache store references

##C1095

A store executed on unit 1

#71,v,g,n,n,PM_SUSPENDED,Suspended

##00008

Suspended

$$$$$$$$

{ counter 4 }

#0,v,g,n,n,PM_0INST_FETCH,No instructions fetched

##2208D

No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)

#1,v,g,n,n,PM_BR_ISSUED,Branches issued

##23098

This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.

#2,v,g,n,n,PM_BR_MPRED_CR,Branch mispredictions due to CR bit setting

##23099

This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.

#3,v,g,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address

##2309A

branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.

#4,u,g,n,n,PM_CRQ_FULL_CYC,Cycles CR issue queue full

##11091,61091

The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).

#5,v,g,n,n,PM_CYC,Processor cycles

##0000F

Processor cycles

#6,u,g,n,n,PM_DC_INV_L2,L1 D cache entries invalidated from L2

##C1097

A dcache invalidated was received from the L2 because a line in L2 was castout.

#7,u,g,n,n,PM_DC_PREF_OUT_OF_STREAMS,D cache out of streams

##8309A

out of streams

#8,v,g,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated

##8309F

A new Prefetch Stream was allocated

#9,v,g,n,n,PM_EE_OFF,Cycles MSR(EE) bit off

##1309B,6309B

The number of Cycles MSR(EE) bit was off.

#10,u,g,n,n,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending

##1309F,6309F

Cycles MSR(EE) bit off and external interrupt pending

#11,v,g,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict

##11096,61096

Flush caused by branch mispredict

#12,v,g,n,n,PM_FLUSH_LSU_BR_MPRED,Flush caused by LSU or branch mispredict

##11097,61097

Flush caused by LSU or branch mispredict

#13,v,g,n,n,PM_FPU0_FEST,FPU0 executed FEST instruction

##01092

This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 

#14,v,g,n,n,PM_FPU0_FIN,FPU0 produced a result

##01093

fp0 finished, produced a result This only indicates finish, not completion. 

#15,v,g,n,n,PM_FPU0_FMOV_FEST,FPU0 executed FMOV or FEST instructions

##01090

This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ

#16,v,g,n,n,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction

##03098

This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs

#17,v,g,n,n,PM_FPU0_FRSP_FCONV,FPU0 executed FRSP or FCONV instructions

##01091

This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#18,v,g,n,n,PM_FPU1_FEST,FPU1 executed FEST instruction

##01096

This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 

#19,v,g,n,n,PM_FPU1_FIN,FPU1 produced a result

##01097

fp1 finished, produced a result. This only indicates finish, not completion. 

#20,v,g,n,n,PM_FPU1_FMOV_FEST,FPU1 executing FMOV or FEST instructions

##01094

This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ

#21,v,g,n,n,PM_FPU1_FRSP_FCONV,FPU1 executed FRSP or FCONV instructions

##01095

This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#22,v,g,n,n,PM_FPU_FIN,FPU produced a result

##01080

FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1

#23,v,g,n,n,PM_FXLS0_FULL_CYC,Cycles FXU0/LS0 queue full

##11090,61090

The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped

#24,v,g,n,n,PM_FXLS1_FULL_CYC,Cycles FXU1/LS1 queue full

##11094,61094

The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped

#25,v,g,n,n,PM_FXU0_FIN,FXU0 produced a result

##1309A,6309A

The Fixed Point unit 0 finished an instruction and produced a result

#26,u,g,n,n,PM_FXU1_BUSY_FXU0_IDLE,FXU1 busy FXU0 idle

##00002

FXU0 was idle while FXU1 was busy

#27,v,g,n,n,PM_FXU1_FIN,FXU1 produced a result

##1309E,6309E

The Fixed Point unit 1 finished an instruction and produced a result

#28,v,g,n,n,PM_GPR_MAP_FULL_CYC,Cycles GPR mapper full

##1309D,6309D

The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#29,v,g,n,n,PM_GRP_DISP_BLK_SB_CYC,Cycles group dispatch blocked by scoreboard

##13099,63099

The ISU sends a signal indicating that dispatch is blocked by scoreboard.

#30,c,g,n,n,PM_INST_CMPL,Instructions completed

##00009

Number of Eligible Instructions that completed. 

#31,v,g,n,n,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid

##C309C

The data source information is valid

#32,v,g,n,n,PM_L1_PREF,L1 cache data prefetches

##83099

A request to prefetch data into the L1 was made

#33,v,g,n,n,PM_L1_WRITE_CYC,Cycles writing to instruction L1

##2309B

This signal is asserted each cycle a cache write is active.

#34,v,g,n,n,PM_L2_PREF,L2 cache prefetches

##8309B

A request to prefetch data into L2 was made

#35,v,g,n,n,PM_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses

##C1092

A load, executing on unit 0, missed the dcache

#36,v,g,n,n,PM_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses

##C1096

A load, executing on unit 1, missed the dcache

#37,v,g,n,n,PM_LD_REF_L1_LSU0,LSU0 L1 D cache load references