{ ****************************

{  THIS IS OPEN SOURCE CODE 

{ ****************************

{ (C) COPYRIGHT International Business Machines Corp. 2005

{ This file is licensed under the University of Tennessee license.

{ See LICENSE.txt.

{

{ File:    events/power4/events

{ Author:  Maynard Johnson

{          maynardj@us.ibm.com

{ Mods: 

{

{ counter 1 }

#0,v,g,n,n,PM_BIQ_IDU_FULL_CYC,Cycles BIQ or IDU full

##0224,0824

This signal will be asserted each time either the IDU is full or the BIQ is full.

#1,u,g,n,n,PM_BRQ_FULL_CYC,Cycles branch queue full

##0105,0605

The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).

#2,v,g,n,n,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full

##0104,0604

The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#3,u,g,n,n,PM_DC_PREF_L2_CLONE_L3,L2 prefetch cloned with L3

##0C27

A prefetch request was made to the L2 with a cloned request sent to the L3

#4,v,g,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated

##0907

A new Prefetch Stream was allocated

#5,v,g,n,n,PM_DSLB_MISS,Data SLB misses

##0905

A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve

#6,v,g,n,n,PM_DTLB_MISS,Data TLB misses

##0904

A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.

#7,v,g,n,n,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full

##0101,0601

The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#8,v,g,n,n,PM_FPU0_ALL,FPU0 executed add, mult, sub, cmp or sel instruction

##0003

This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo

#9,v,g,n,n,PM_FPU0_DENORM,FPU0 received denormalized data

##0020

This signal is active for one cycle when one of the operands is denormalized.

#10,v,g,n,n,PM_FPU0_FDIV,FPU0 executed FDIV instruction

##0000

This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.

#11,v,g,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction

##0001

This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#12,v,g,n,n,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction

##0002

This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#13,v,g,n,n,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full

##0103,0603

The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped

#14,v,g,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction

##0023

This signal is active for one cycle when fp0 is executing single precision instruction.

#15,v,g,n,n,PM_FPU0_STALL3,FPU0 stalled in pipe3

##0021

This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. 

#16,v,g,n,n,PM_FPU0_STF,FPU0 executed store instruction

##0022

This signal is active for one cycle when fp0 is executing a store instruction.

#17,v,g,n,n,PM_FPU1_ALL,FPU1 executed add, mult, sub, cmp or sel instruction

##0007

This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo

#18,v,g,n,n,PM_FPU1_DENORM,FPU1 received denormalized data

##0024

This signal is active for one cycle when one of the operands is denormalized.

#19,v,g,n,n,PM_FPU1_FDIV,FPU1 executed FDIV instruction

##0004

This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.

#20,v,g,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction

##0005

This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#21,v,g,n,n,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction

##0006

This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#22,v,g,n,n,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full

##0107,0607

The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped

#23,v,g,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction

##0027

This signal is active for one cycle when fp1 is executing single precision instruction.

#24,v,g,n,n,PM_FPU1_STALL3,FPU1 stalled in pipe3

##0025

This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. 

#25,v,g,n,n,PM_FPU1_STF,FPU1 executed store instruction

##0026

This signal is active for one cycle when fp1 is executing a store instruction.

#26,v,g,n,n,PM_GCT_FULL_CYC,Cycles GCT full

##0100,0600

The ISU sends a signal indicating the gct is full. 

#27,v,g,n,n,PM_GRP_DISP_REJECT,Group dispatch rejected

##0124,0624

A group that previously attempted dispatch was rejected.

#28,v,g,n,n,PM_GRP_DISP_VALID,Group dispatch valid

##0123,0623

Dispatch has been attempted for a valid group.  Some groups may be rejected.  The total number of successful dispatches is the number of dispatch valid minus dispatch reject.

#29,v,g,n,n,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch buffer

##0225,0825

This signal is asserted when a prefetch buffer entry (line) is allocated but the request is not a demand fetch.

#30,v,g,n,n,PM_IC_PREF_REQ,Instruction prefetch requests

##0226,0826

Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).

#31,v,g,n,n,PM_IERAT_XLATE_WR,Translation written to ierat

##0227,0827

This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).

#32,v,g,n,n,PM_INST_DISP,Instructions dispatched

##0121,0621

The ISU sends the number of instructions dispatched.

#33,v,g,n,n,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched

##0223,0823

Asserted each cycle when the IFU sends at least one instruction to the IDU. 

#34,u,g,n,n,PM_ISLB_MISS,Instruction SLB misses

##0901

A SLB miss for an instruction fetch as occurred

#35,v,g,n,n,PM_ITLB_MISS,Instruction TLB misses

##0900

A TLB miss for an Instruction Fetch has occurred

#36,v,g,n,n,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid

##0C64

The data source information is valid

#37,v,g,n,n,PM_L2SA_MOD_INV,L2 slice A transition from modified to invalid

##4007

A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#38,v,g,n,n,PM_L2SA_MOD_TAG,L2 slice A transition from modified to tagged

##4006

A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#39,v,g,n,n,PM_L2SA_SHR_INV,L2 slice A transition from shared to invalid

##4005

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.

#40,v,g,n,n,PM_L2SA_SHR_MOD,L2 slice A transition from shared to modified

##4004

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. 

#41,v,g,n,n,PM_L2SB_MOD_INV,L2 slice B transition from modified to invalid

##4023

A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#42,v,g,n,n,PM_L2SB_MOD_TAG,L2 slice B transition from modified to tagged

##4022

A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#43,v,g,n,n,PM_L2SB_SHR_INV,L2 slice B transition from shared to invalid

##4021

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.

#44,v,g,n,n,PM_L2SB_SHR_MOD,L2 slice B transition from shared to modified

##4020

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. 

#45,v,g,n,n,PM_L2SC_MOD_INV,L2 slice C transition from modified to invalid

##4027

A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#46,v,g,n,n,PM_L2SC_MOD_TAG,L2 slice C transition from modified to tagged

##4026

A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#47,v,g,n,n,PM_L2SC_SHR_INV,L2 slice C transition from shared to invalid

##4025

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.

#48,v,g,n,n,PM_L2SC_SHR_MOD,L2 slice C transition from shared to modified

##4024

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. 

#49,v,g,n,n,PM_L3B0_DIR_MIS,L3 bank 0 directory misses

##4001

A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3

#50,v,g,n,n,PM_L3B0_DIR_REF,L3 bank 0 directory references

##4000

A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3

#51,v,g,n,n,PM_L3B1_DIR_MIS,L3 bank 1 directory misses

##4003

A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3

#52,v,g,n,n,PM_L3B1_DIR_REF,L3 bank 1 directory references

##4002

A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3

#53,u,g,n,n,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full

##0106,0606

The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#54,v,g,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses

##0902

A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.

#55,v,g,n,n,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes

##0C02

A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#56,u,g,n,n,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes

##0C03

A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.

#57,v,g,n,n,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes

##0C00

A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#58,v,g,n,n,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes

##0C01

A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)

#59,u,g,n,n,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded

##0C20

Data from a store instruction was forwarded to a load on unit 0

#60,v,g,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses

##0906

A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.

#61,v,g,n,n,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes

##0C06

A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#62,u,g,n,n,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes

##0C07

A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. 

#63,v,g,n,n,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes

##0C04

A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#64,u,g,n,n,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes

##0C05

A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)

#65,u,g,n,n,PM_LSU1_SRQ_STFWD,LSU1 SRQ store forwarded

##0C24

Data from a store instruction was forwarded to a load on unit 1

#66,u,g,n,n,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full

##0927

The LMQ was full

#67,v,g,n,n,PM_LSU_LMQ_LHR_MERGE,LMQ LHR merges

##0926

A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.

#68,v,g,n,n,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated

##0C26

LRQ slot zero was allocated

#69,v,g,n,n,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid

##0C22

This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.

#70,v,g,n,n,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated

##0C25

SRQ Slot zero was allocated

#71,v,g,n,n,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid

##0C21

This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.

#72,v,g,n,n,PM_MRK_IMR_RELOAD,Marked IMR reloaded

##0922

A DL1 reload occured due to marked load

#73,v,g,n,n,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses

##0920

A marked load, executing on unit 0, missed the dcache

#74,v,g,n,n,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses

##0924

A marked load, executing on unit 1, missed the dcache

#75,v,g,n,n,PM_MRK_STCX_FAIL,Marked STCX failed

##0925

A marked stcx (stwcx or stdcx) failed

#76,v,g,n,n,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses

##0923

A marked store missed the dcache

#77,u,g,n,n,PM_SNOOP_TLBIE,Snoop TLBIE

##0903

A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.

#78,v,g,n,n,PM_STCX_FAIL,STCX failed

##0921

A stcx (stwcx or stdcx) failed

#79,v,g,n,n,PM_ST_MISS_L1,L1 D cache store misses

##0C23

A store missed the dcache

#80,v,g,n,n,PM_XER_MAP_FULL_CYC,Cycles XER mapper full

##0102,0602

The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#81,v,g,n,n,PM_CYC,Processor cycles

##800F

Processor cycles

#82,v,g,n,n,PM_DATA_FROM_L3,Data loaded from L3

##8C66

DL1 was reloaded from the local L3 due to a demand load

#83,v,g,n,n,PM_FPU_DENORM,FPU received denormalized data

##8020

This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1

#84,v,g,n,n,PM_FPU_FDIV,FPU executed FDIV instruction

##8000

This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1

#85,u,g,n,n,PM_GCT_EMPTY_CYC,Cycles GCT empty

##8004

The Global Completion Table is completely empty

#86,c,g,n,n,PM_INST_CMPL,Instructions completed

##8001

Number of Eligible Instructions that completed. 

#87,v,g,n,n,PM_INST_FROM_MEM,Instruction fetched from memory

##8227

An instruction fetch group was fetched from memory. Fetch Groups can contain up to 8 instructions

#88,v,g,n,n,PM_LSU_FLUSH_ULD,LRQ unaligned load flushes

##8C00

A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#89,c,g,n,n,PM_LSU_SRQ_STFWD,SRQ store forwarded

##8C20

Data from a store instruction was forwarded to a load

#90,v,g,n,n,PM_MRK_DATA_FROM_L3,Marked data loaded from L3

##8C76

DL1 was reloaded from the local L3 due to a marked demand load

#91,v,g,n,n,PM_MRK_GRP_DISP,Marked group dispatched

##8002

A group containing a sampled instruction was dispatched

#92,v,g,n,n,PM_MRK_LD_MISS_L1,Marked L1 D cache load misses

##8920

Marked L1 D cache load misses

#93,v,g,n,n,PM_MRK_ST_CMPL,Marked store instruction completed

##8003

A sampled store has completed (data home)

#94,v,g,n,n,PM_RUN_CYC,Run cycles

##8005

Processor Cycles gated by the run latch

$$$$

{ counter 2 }

#0,v,g,n,n,PM_BIQ_IDU_FULL_CYC,Cycles BIQ or IDU full

##0224,0824

This signal will be asserted each time either the IDU is full or the BIQ is full.

#1,u,g,n,n,PM_BRQ_FULL_CYC,Cycles branch queue full

##0105,0605

The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).

#2,v,g,n,n,PM_CR_MAP_FULL_CYC,Cycles CR logical operation mapper full

##0104,0604

The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#3,u,g,n,n,PM_DC_PREF_L2_CLONE_L3,L2 prefetch cloned with L3

##0C27

A prefetch request was made to the L2 with a cloned request sent to the L3

#4,v,g,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated

##0907

A new Prefetch Stream was allocated

#5,v,g,n,n,PM_DSLB_MISS,Data SLB misses

##0905

A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve

#6,v,g,n,n,PM_DTLB_MISS,Data TLB misses

##0904

A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.

#7,v,g,n,n,PM_FPR_MAP_FULL_CYC,Cycles FPR mapper full

##0101,0601

The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#8,v,g,n,n,PM_FPU0_ALL,FPU0 executed add, mult, sub, cmp or sel instruction

##0003

This signal is active for one cycle when fp0 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo

#9,v,g,n,n,PM_FPU0_DENORM,FPU0 received denormalized data

##0020

This signal is active for one cycle when one of the operands is denormalized.

#10,v,g,n,n,PM_FPU0_FDIV,FPU0 executed FDIV instruction

##0000

This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.

#11,v,g,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction

##0001

This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#12,v,g,n,n,PM_FPU0_FSQRT,FPU0 executed FSQRT instruction

##0002

This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#13,v,g,n,n,PM_FPU0_FULL_CYC,Cycles FPU0 issue queue full

##0103,0603

The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped

#14,v,g,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction

##0023

This signal is active for one cycle when fp0 is executing single precision instruction.

#15,v,g,n,n,PM_FPU0_STALL3,FPU0 stalled in pipe3

##0021

This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. 

#16,v,g,n,n,PM_FPU0_STF,FPU0 executed store instruction

##0022

This signal is active for one cycle when fp0 is executing a store instruction.

#17,v,g,n,n,PM_FPU1_ALL,FPU1 executed add, mult, sub, cmp or sel instruction

##0007

This signal is active for one cycle when fp1 is executing an add, mult, sub, compare, or fsel kind of instruction. This could be fadd*, fmul*, fsub*, fcmp**, fsel where XYZ* means XYZ, XYZs, XYZ., XYZs. and XYZ** means XYZu, XYZo

#18,v,g,n,n,PM_FPU1_DENORM,FPU1 received denormalized data

##0024

This signal is active for one cycle when one of the operands is denormalized.

#19,v,g,n,n,PM_FPU1_FDIV,FPU1 executed FDIV instruction

##0004

This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.

#20,v,g,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction

##0005

This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#21,v,g,n,n,PM_FPU1_FSQRT,FPU1 executed FSQRT instruction

##0006

This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#22,v,g,n,n,PM_FPU1_FULL_CYC,Cycles FPU1 issue queue full

##0107,0607

The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped

#23,v,g,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction

##0027

This signal is active for one cycle when fp1 is executing single precision instruction.

#24,v,g,n,n,PM_FPU1_STALL3,FPU1 stalled in pipe3

##0025

This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. 

#25,v,g,n,n,PM_FPU1_STF,FPU1 executed store instruction

##0026

This signal is active for one cycle when fp1 is executing a store instruction.

#26,v,g,n,n,PM_GCT_FULL_CYC,Cycles GCT full

##0100,0600

The ISU sends a signal indicating the gct is full. 

#27,v,g,n,n,PM_GRP_DISP_REJECT,Group dispatch rejected

##0124,0624

A group that previously attempted dispatch was rejected.

#28,v,g,n,n,PM_GRP_DISP_VALID,Group dispatch valid

##0123,0623

Dispatch has been attempted for a valid group.  Some groups may be rejected.  The total number of successful dispatches is the number of dispatch valid minus dispatch reject.

#29,v,g,n,n,PM_IC_PREF_INSTALL,Instruction prefetched installed in prefetch buffer

##0225,0825

This signal is asserted when a prefetch buffer entry (line) is allocated but the request is not a demand fetch.

#30,v,g,n,n,PM_IC_PREF_REQ,Instruction prefetch requests

##0226,0826

Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).

#31,v,g,n,n,PM_IERAT_XLATE_WR,Translation written to ierat

##0227,0827

This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).

#32,v,g,n,n,PM_INST_DISP,Instructions dispatched

##0121,0621

The ISU sends the number of instructions dispatched.

#33,v,g,n,n,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched

##0223,0823

Asserted each cycle when the IFU sends at least one instruction to the IDU. 

#34,u,g,n,n,PM_ISLB_MISS,Instruction SLB misses

##0901

A SLB miss for an instruction fetch as occurred

#35,v,g,n,n,PM_ITLB_MISS,Instruction TLB misses

##0900

A TLB miss for an Instruction Fetch has occurred

#36,v,g,n,n,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid

##0C64

The data source information is valid

#37,v,g,n,n,PM_L2SA_MOD_INV,L2 slice A transition from modified to invalid

##4007

A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#38,v,g,n,n,PM_L2SA_MOD_TAG,L2 slice A transition from modified to tagged

##4006

A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#39,v,g,n,n,PM_L2SA_SHR_INV,L2 slice A transition from shared to invalid

##4005

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.

#40,v,g,n,n,PM_L2SA_SHR_MOD,L2 slice A transition from shared to modified

##4004

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. 

#41,v,g,n,n,PM_L2SB_MOD_INV,L2 slice B transition from modified to invalid

##4023

A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#42,v,g,n,n,PM_L2SB_MOD_TAG,L2 slice B transition from modified to tagged

##4022

A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#43,v,g,n,n,PM_L2SB_SHR_INV,L2 slice B transition from shared to invalid

##4021

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.

#44,v,g,n,n,PM_L2SB_SHR_MOD,L2 slice B transition from shared to modified

##4020

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. 

#45,v,g,n,n,PM_L2SC_MOD_INV,L2 slice C transition from modified to invalid

##4027

A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#46,v,g,n,n,PM_L2SC_MOD_TAG,L2 slice C transition from modified to tagged

##4026

A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.

#47,v,g,n,n,PM_L2SC_SHR_INV,L2 slice C transition from shared to invalid

##4025

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.

#48,v,g,n,n,PM_L2SC_SHR_MOD,L2 slice C transition from shared to modified

##4024

A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. 

#49,v,g,n,n,PM_L3B0_DIR_MIS,L3 bank 0 directory misses

##4001

A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3

#50,v,g,n,n,PM_L3B0_DIR_REF,L3 bank 0 directory references

##4000

A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3

#51,v,g,n,n,PM_L3B1_DIR_MIS,L3 bank 1 directory misses

##4003

A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3

#52,v,g,n,n,PM_L3B1_DIR_REF,L3 bank 1 directory references

##4002

A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3

#53,u,g,n,n,PM_LR_CTR_MAP_FULL_CYC,Cycles LR/CTR mapper full

##0106,0606

The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#54,v,g,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses

##0902

A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.

#55,v,g,n,n,PM_LSU0_FLUSH_LRQ,LSU0 LRQ flushes

##0C02

A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#56,u,g,n,n,PM_LSU0_FLUSH_SRQ,LSU0 SRQ flushes

##0C03

A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.

#57,v,g,n,n,PM_LSU0_FLUSH_ULD,LSU0 unaligned load flushes

##0C00

A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#58,v,g,n,n,PM_LSU0_FLUSH_UST,LSU0 unaligned store flushes

##0C01

A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)

#59,u,g,n,n,PM_LSU0_SRQ_STFWD,LSU0 SRQ store forwarded

##0C20

Data from a store instruction was forwarded to a load on unit 0

#60,v,g,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses

##0906

A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.

#61,v,g,n,n,PM_LSU1_FLUSH_LRQ,LSU1 LRQ flushes

##0C06

A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#62,u,g,n,n,PM_LSU1_FLUSH_SRQ,LSU1 SRQ flushes

##0C07

A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. 

#63,v,g,n,n,PM_LSU1_FLUSH_ULD,LSU1 unaligned load flushes

##0C04

A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#64,u,g,n,n,PM_LSU1_FLUSH_UST,LSU1 unaligned store flushes

##0C05

A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)

#65,u,g,n,n,PM_LSU1_SRQ_STFWD,LSU1 SRQ store forwarded

##0C24

Data from a store instruction was forwarded to a load on unit 1

#66,u,g,n,n,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full

##0927

The LMQ was full

#67,v,g,n,n,PM_LSU_LMQ_LHR_MERGE,LMQ LHR merges

##0926

A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.

#68,v,g,n,n,PM_LSU_LRQ_S0_ALLOC,LRQ slot 0 allocated

##0C26

LRQ slot zero was allocated

#69,v,g,n,n,PM_LSU_LRQ_S0_VALID,LRQ slot 0 valid

##0C22

This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.

#70,v,g,n,n,PM_LSU_SRQ_S0_ALLOC,SRQ slot 0 allocated

##0C25

SRQ Slot zero was allocated

#71,v,g,n,n,PM_LSU_SRQ_S0_VALID,SRQ slot 0 valid

##0C21

This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.

#72,v,g,n,n,PM_MRK_IMR_RELOAD,Marked IMR reloaded

##0922

A DL1 reload occured due to marked load

#73,v,g,n,n,PM_MRK_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses

##0920

A marked load, executing on unit 0, missed the dcache

#74,v,g,n,n,PM_MRK_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses

##0924

A marked load, executing on unit 1, missed the dcache

#75,v,g,n,n,PM_MRK_STCX_FAIL,Marked STCX failed

##0925

A marked stcx (stwcx or stdcx) failed

#76,v,g,n,n,PM_MRK_ST_MISS_L1,Marked L1 D cache store misses

##0923

A marked store missed the dcache

#77,u,g,n,n,PM_SNOOP_TLBIE,Snoop TLBIE

##0903

A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.

#78,v,g,n,n,PM_STCX_FAIL,STCX failed

##0921

A stcx (stwcx or stdcx) failed

#79,v,g,n,n,PM_ST_MISS_L1,L1 D cache store misses

##0C23

A store missed the dcache

#80,v,g,n,n,PM_XER_MAP_FULL_CYC,Cycles XER mapper full

##0102,0602

The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#81,v,g,n,n,PM_CYC,Processor cycles

##800F

Processor cycles

#82,v,g,n,n,PM_DATA_FROM_MEM,Data loaded from memory

##8C66

DL1 was reloaded from memory due to a demand load

#83,v,g,n,n,PM_FPU_FMA,FPU executed multiply-add instruction

##8000

This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1

#84,v,g,n,n,PM_FPU_STALL3,FPU stalled in pipe3

##8020

FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1

#85,v,g,n,n,PM_GRP_DISP,Group dispatches

##8004

A group was dispatched

#86,c,g,n,n,PM_INST_FROM_L25_L275,Instruction fetched from L2.5/L2.75

##8227

An instruction fetch group was fetched from the L2 of another chip. Fetch Groups can contain up to 8 instructions

#87,v,g,n,n,PM_LSU_FLUSH_UST,SRQ unaligned store flushes

##8C00

A store was flushed because it was unaligned

#88,u,g,n,n,PM_LSU_LMQ_SRQ_EMPTY_CYC,Cycles LMQ and SRQ empty

##8002

Cycles when both the LMQ and SRQ are empty (LSU is idle)

#89,v,g,n,n,PM_MRK_BRU_FIN,Marked instruction BRU processing finished

##8005

The branch unit finished a marked instruction. Instructions that finish may not necessary complete

#90,v,g,n,n,PM_MRK_DATA_FROM_MEM,Marked data loaded from memory

##8C76

DL1 was reloaded from memory due to a marked demand load

#91,v,g,t,n,PM_THRESH_TIMEO,Threshold timeout

##8003

The threshold timer expired

#92,v,g,n,n,PM_WORK_HELD,Work held

##8001

RAS Unit has signaled completion to stop and there are groups waiting to complete

$$$$

{ counter 3 }

#0,v,g,n,n,PM_1INST_CLB_CYC,Cycles 1 instruction in CLB

##0450

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#1,v,g,n,n,PM_2INST_CLB_CYC,Cycles 2 instructions in CLB

##0451

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#2,v,g,n,n,PM_3INST_CLB_CYC,Cycles 3 instructions in CLB

##0452

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#3,v,g,n,n,PM_4INST_CLB_CYC,Cycles 4 instructions in CLB

##0453

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#4,v,g,n,n,PM_5INST_CLB_CYC,Cycles 5 instructions in CLB

##0454

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#5,v,g,n,n,PM_6INST_CLB_CYC,Cycles 6 instructions in CLB

##0455

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#6,v,g,n,n,PM_7INST_CLB_CYC,Cycles 7 instructions in CLB

##0456

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#7,v,g,n,n,PM_8INST_CLB_CYC,Cycles 8 instructions in CLB

##0457

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#8,v,g,n,n,PM_BR_ISSUED,Branches issued

##0230,0830

This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.

#9,v,g,n,n,PM_BR_MPRED_CR,Branch mispredictions due CR bit setting

##0231,0831

This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.

#10,v,g,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address

##0232,0832

branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.

#11,u,g,n,n,PM_CRQ_FULL_CYC,Cycles CR issue queue full

##0111,0611

The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).

#12,v,g,n,n,PM_DATA_TABLEWALK_CYC,Cycles doing data tablewalks

##0936

This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.

#13,u,g,n,n,PM_DC_INV_L2,L1 D cache entries invalidated from L2

##0C17

A dcache invalidated was received from the L2 because a line in L2 was castout.

#14,v,g,n,n,PM_DC_PREF_OUT_STREAMS,Out of prefetch streams

##0C36

A new prefetch stream was detected, but no more stream entries were available

#15,v,g,n,n,PM_EE_OFF,Cycles MSR(EE) bit off

##0133,0633

The number of Cycles MSR(EE) bit was off.

#16,u,g,n,n,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending

##0137,0637

Cycles MSR(EE) bit off and external interrupt pending

#17,v,g,n,n,PM_FAB_CMD_ISSUED,Fabric command issued

##4016

A bus command was issued on the MCM to MCM fabric from the local (this chip's) Fabric Bus Controller.  This event is scaled to the fabric frequency and must be adjusted for a true count.  i.e. if the fabric is running 2:1, divide the count by 2.

#18,v,g,n,n,PM_FAB_CMD_RETRIED,Fabric command retried

##4017

A bus command on the MCM to MCM fabric was retried.  This event is the total count of all retried fabric commands for the local MCM (all four chips report the same value).  This event is scaled to the fabric frequency and must be adjusted for a true count.  i.e. if the fabric is running 2:1, divide the count by 2.

#19,v,g,n,n,PM_LSU0_LDF,LSU0 executed Floating Point load instruction

##0930

A floating point load was executed from LSU unit 0

#20,v,g,n,n,PM_LSU1_LDF,LSU1 executed Floating Point load instruction

##0934

A floating point load was executed from LSU unit 1

#21,v,g,n,n,PM_FPU0_FEST,FPU0 executed FEST instruction

##0012

This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 

#22,v,g,n,n,PM_FPU0_FIN,FPU0 produced a result

##0013

fp0 finished, produced a result This only indicates finish, not completion. 

#23,v,g,n,n,PM_FPU0_FMOV_FEST,FPU0 executed FMOV or FEST instructions

##0010

This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ

#24,v,g,n,n,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction

##0030

This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs

#25,v,g,n,n,PM_FPU0_FRSP_FCONV,FPU0 executed FRSP or FCONV instructions

##0011

fThis signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#26,v,g,n,n,PM_FPU1_FEST,FPU1 executed FEST instruction

##0016

This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 

#27,v,g,n,n,PM_FPU1_FIN,FPU1 produced a result

##0017

fp1 finished, produced a result. This only indicates finish, not completion. 

#28,v,g,n,n,PM_FPU1_FMOV_FEST,FPU1 executing FMOV or FEST instructions

##0014

This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ

#29,v,g,n,n,PM_FPU1_FRSP_FCONV,FPU1 executed FRSP or FCONV instructions

##0015

fThis signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.

#30,v,g,n,n,PM_FXLS0_FULL_CYC,Cycles FXU0/LS0 queue full

##0110,0610

The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped

#31,v,g,n,n,PM_FXU0_FIN,FXU0 produced a result

##0132,0632

The Fixed Point unit 0 finished an instruction and produced a result

#32,v,g,n,n,PM_FXU1_FIN,FXU1 produced a result

##0136,0636

The Fixed Point unit 1 finished an instruction and produced a result

#33,v,g,n,n,PM_GPR_MAP_FULL_CYC,Cycles GPR mapper full

##0135,0635

The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.

#34,v,g,n,n,PM_GRP_DISP_BLK_SB_CYC,Cycles group dispatch blocked by scoreboard

##0131,0631

The ISU sends a signal indicating that dispatch is blocked by scoreboard.

#35,v,g,n,n,PM_L1_PREF,L1 cache data prefetches

##0C35

A request to prefetch data into the L1 was made

#36,v,g,n,n,PM_L1_WRITE_CYC,Cycles writing to instruction L1

##0233,0833

This signal is asserted each cycle a cache write is active.

#37,v,g,n,n,PM_L2SA_ST_HIT,L2 slice A store hits

##4011

A store request made from the core hit in the L2 directory.  This event is provided on each of the three L2 slices A,B, and C.

#38,v,g,n,n,PM_L2SA_ST_REQ,L2 slice A store requests

##4010

A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.

#39,v,g,n,n,PM_L2SB_ST_HIT,L2 slice B store hits

##4013

A store request made from the core hit in the L2 directory.  This event is provided on each of the three L2 slices A,B, and C.

#40,v,g,n,n,PM_L2SB_ST_REQ,L2 slice B store requests

##4012

A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.

#41,v,g,n,n,PM_L2SC_ST_HIT,L2 slice C store hits

##4015

A store request made from the core hit in the L2 directory.  This event is provided on each of the three L2 slices A,B, and C.

#42,v,g,n,n,PM_L2SC_ST_REQ,L2 slice C store requests

##4014

A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.

#43,v,g,n,n,PM_L2_PREF,L2 cache prefetches

##0C34

A request to prefetch data into L2 was made

#44,v,g,n,n,PM_LARX_LSU0,Larx executed on LSU0

##0C73

A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)

#45,c,g,n,n,PM_LARX_LSU1,Larx executed on LSU1

##0C77

Invalid event, larx instructions are never executed on unit 1

#46,v,g,n,n,PM_LD_MISS_L1_LSU0,LSU0 L1 D cache load misses

##0C12

A load, executing on unit 0, missed the dcache

#47,v,g,n,n,PM_LD_MISS_L1_LSU1,LSU1 L1 D cache load misses

##0C16

A load, executing on unit 1, missed the dcache

#48,v,g,n,n,PM_LD_REF_L1_LSU0,LSU0 L1 D cache load references

##0C10

A load executed on unit 0

#49,v,g,n,n,PM_LD_REF_L1_LSU1,LSU1 L1 D cache load references

##0C14

A load executed on unit 1

#50,v,g,n,n,PM_LSU0_BUSY,LSU0 busy

##0C33

LSU unit 0 is busy rejecting instructions

#51,v,g,n,n,PM_LSU1_BUSY,LSU1 busy

##0C37

LSU unit 1 is busy rejecting instructions 

#52,v,g,n,n,PM_LSU_LMQ_S0_ALLOC,LMQ slot 0 allocated

##0935

The first entry in the LMQ was allocated.

#53,v,g,n,n,PM_LSU_LMQ_S0_VALID,LMQ slot 0 valid

##0931

This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO

#54,v,g,n,n,PM_LSU_LRQ_FULL_CYC,Cycles LRQ full

##0112,0612

The isu sends this signal when the lrq is full.

#55,v,g,n,n,PM_LSU_SRQ_FULL_CYC,Cycles SRQ full

##0113,0613

The isu sends this signal when the srq is full.

#56,u,g,n,n,PM_LSU_SRQ_SYNC_CYC,SRQ sync duration

##0932

This signal is asserted every cycle when a sync is in the SRQ.

#57,v,g,n,n,PM_MRK_L1_RELOAD_VALID,Marked L1 reload data source valid

##0C74

The source information is valid and is for a marked load

#58,v,g,n,n,PM_MRK_LSU0_FLUSH_LRQ,LSU0 marked LRQ flushes

##0912

A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#59,u,g,n,n,PM_MRK_LSU0_FLUSH_SRQ,LSU0 marked SRQ flushes

##0913

A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.

#60,v,g,n,n,PM_MRK_LSU0_FLUSH_ULD,LSU0 marked unaligned load flushes

##0910

A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#61,v,g,n,n,PM_MRK_LSU0_FLUSH_UST,LSU0 marked unaligned store flushes

##0911

A marked store was flushed from unit 0 because it was unaligned

#62,c,g,n,n,PM_MRK_LSU0_INST_FIN,LSU0 finished a marked instruction

##0C31

LSU unit 0 finished a marked instruction

#63,v,g,n,n,PM_MRK_LSU1_FLUSH_LRQ,LSU1 marked LRQ flushes

##0916

A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#64,u,g,n,n,PM_MRK_LSU1_FLUSH_SRQ,LSU1 marked SRQ flushes

##0917

A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.

#65,v,g,n,n,PM_MRK_LSU1_FLUSH_ULD,LSU1 marked unaligned load flushes

##0914

A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)

#66,u,g,n,n,PM_MRK_LSU1_FLUSH_UST,LSU1 marked unaligned store flushes

##0915

A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)

#67,c,g,n,n,PM_MRK_LSU1_INST_FIN,LSU1 finished a marked instruction

##0C32

LSU unit 1 finished a marked instruction

#68,u,g,n,n,PM_MRK_LSU_SRQ_INST_VALID,Marked instruction valid in SRQ

##0933

This signal is asserted every cycle when a marked request is resident in the Store Request Queue

#69,v,g,n,n,PM_STCX_PASS,Stcx passes

##0C75

A stcx (stwcx or stdcx) instruction was successful

#70,v,g,n,n,PM_ST_MISS_L1,L1 D cache store misses

##0C13

A store missed the dcache

#71,v,g,n,n,PM_ST_REF_L1_LSU0,LSU0 L1 D cache store references

##0C11

A store executed on unit 0

#72,v,g,n,n,PM_ST_REF_L1_LSU1,LSU1 L1 D cache store references

##0C15

A store executed on unit 1

#73,v,g,n,n,PM_CYC,Processor cycles

##800F

Processor cycles

#74,v,g,n,n,PM_DATA_FROM_L35,Data loaded from L3.5

##8C66

DL1 was reloaded from the L3 of another MCM due to a demand load

#75,v,g,n,n,PM_FPU_FEST,FPU executed FEST instruction

##8010

This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.

#76,v,g,n,n,PM_FXU_FIN,FXU produced a result

##8130

The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.

#77,v,g,n,n,PM_FXU_FIN,FXU produced a result

##8630

The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.

#78,v,g,n,n,PM_INST_FROM_L2,Instructions fetched from L2

##8227

An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions

#79,v,g,n,n,PM_LD_MISS_L1,L1 D cache load misses

##8C10

Total DL1 Load references that miss the DL1

#80,v,g,n,n,PM_MRK_DATA_FROM_L35,Marked data loaded from L3.5

##8C76

DL1 was reloaded from the L3 of another MCM due to a marked demand load

#81,v,g,n,n,PM_MRK_LSU_FLUSH_LRQ,Marked LRQ flushes

##8910

A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.

#82,v,g,n,n,PM_MRK_ST_CMPL_INT,Marked store completed with intervention

##8003

A marked store previously sent to the memory subsystem completed (data home) after requiring intervention

#83,v,g,n,n,PM_STOP_COMPLETION,Completion stopped

##8001

RAS Unit has signaled completion to stop

#84,v,g,n,n,PM_HV_CYC,Hypervisor Cycles

##8004

Cycles when the processor is executing in Hypervisor (MSR[HV] = 0 and MSR[PR]=0)

#85,v,g,n,n,PM_FXLS1_FULL_CYC,Cycles FXU1/LS1 queue full

##0114,0614

The issue queue for FXU/LSU unit 1 cannot accept any more instructions. Issue is stopped

$$$$

{ counter 4 }

#0,v,g,n,n,PM_1INST_CLB_CYC,Cycles 1 instruction in CLB

##0450

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#1,v,g,n,n,PM_2INST_CLB_CYC,Cycles 2 instructions in CLB

##0451

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#2,v,g,n,n,PM_3INST_CLB_CYC,Cycles 3 instructions in CLB

##0452

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#3,v,g,n,n,PM_4INST_CLB_CYC,Cycles 4 instructions in CLB

##0453

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#4,v,g,n,n,PM_5INST_CLB_CYC,Cycles 5 instructions in CLB

##0454

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#5,v,g,n,n,PM_6INST_CLB_CYC,Cycles 6 instructions in CLB

##0455

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#6,v,g,n,n,PM_7INST_CLB_CYC,Cycles 7 instructions in CLB

##0456

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#7,v,g,n,n,PM_8INST_CLB_CYC,Cycles 8 instructions in CLB

##0457

The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.

#8,v,g,n,n,PM_BR_ISSUED,Branches issued

##0230,0830

This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.

#9,v,g,n,n,PM_BR_MPRED_CR,Branch mispredictions due CR bit setting

##0231,0831

This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.

#10,v,g,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address

##0232,0832

branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.

#11,u,g,n,n,PM_CRQ_FULL_CYC,Cycles CR issue queue full