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/****************************/
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/* THIS IS OPEN SOURCE CODE */
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/****************************/
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/*
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* File: perfctr-ppc64.c
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* Author: Maynard Johnson
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* maynardj@us.ibm.com
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* Mods: <your name here>
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* <your email address>
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*/
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/* PAPI stuff */
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#include "papi.h"
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#include "papi_internal.h"
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#include "papi_vector.h"
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#include SUBSTRATE
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#ifdef PERFCTR26
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#define PERFCTR_CPU_NAME perfctr_info_cpu_name
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#define PERFCTR_CPU_NRCTRS perfctr_info_nrctrs
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#else
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#define PERFCTR_CPU_NAME perfctr_cpu_name
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#define PERFCTR_CPU_NRCTRS perfctr_cpu_nrctrs
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#endif
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static hwi_search_t preset_name_map_PPC64[PAPI_MAX_PRESET_EVENTS] = {
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#if defined(_POWER5) || defined(_POWER5p)
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{PAPI_L1_DCM, {DERIVED_ADD, {PNE_PM_LD_MISS_L1, PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 data cache misses */
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{PAPI_L1_DCA, {DERIVED_ADD, {PNE_PM_LD_REF_L1, PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 data cache access */
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/* can't count level 1 data cache hits due to hardware limitations. */
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{PAPI_L1_LDM, {0, {PNE_PM_LD_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 load misses */
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{PAPI_L1_STM, {0, {PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 store misses */
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{PAPI_L1_DCW, {0, {PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 D cache write */
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{PAPI_L1_DCR, {0, {PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 D cache read */
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/* can't count level 2 data cache reads due to hardware limitations. */
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/* can't count level 2 data cache hits due to hardware limitations. */
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{PAPI_L2_DCM, {0, {PNE_PM_DATA_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 2 data cache misses */
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{PAPI_L2_LDM, {0, {PNE_PM_DATA_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 2 cache read misses */
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{PAPI_L3_DCR, {0, {PNE_PM_DATA_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 3 data cache reads */
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/* can't count level 3 data cache hits due to hardware limitations. */
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{PAPI_L3_DCM, {DERIVED_ADD, {PNE_PM_DATA_FROM_LMEM, PNE_PM_DATA_FROM_RMEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 data cache misses (reads & writes) */
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{PAPI_L3_LDM, {DERIVED_ADD, {PNE_PM_DATA_FROM_LMEM, PNE_PM_DATA_FROM_RMEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 data cache read misses */
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/* can't count level 1 instruction cache accesses due to hardware limitations. */
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{PAPI_L1_ICH, {0, {PNE_PM_INST_FROM_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 1 inst cache hits */
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/* can't count level 1 instruction cache misses due to hardware limitations. */
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/* can't count level 2 instruction cache accesses due to hardware limitations. */
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/* can't count level 2 instruction cache hits due to hardware limitations. */
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{PAPI_L2_ICM, {0, {PNE_PM_INST_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 inst cache misses */
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{PAPI_L3_ICA, {0, {PNE_PM_INST_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 inst cache accesses */
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/* can't count level 3 instruction cache hits due to hardware limitations. */
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{PAPI_L3_ICM, {DERIVED_ADD, {PNE_PM_DATA_FROM_LMEM, PNE_PM_DATA_FROM_RMEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 instruction cache misses (reads & writes) */
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{PAPI_FMA_INS, {0, {PNE_PM_FPU_FMA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FMA instructions completed */
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{PAPI_TOT_IIS, {0, {PNE_PM_INST_DISP, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total instructions issued */
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{PAPI_TOT_INS, {0, {PNE_PM_INST_CMPL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total instructions executed */
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{PAPI_INT_INS, {0, {PNE_PM_FXU_FIN, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Integer instructions executed */
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{PAPI_FP_OPS, {DERIVED_ADD, {PNE_PM_FPU_1FLOP, PNE_PM_FPU_FMA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Floating point instructions executed */
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{PAPI_FP_INS, {0, {PNE_PM_FPU_FIN, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Floating point instructions executed */
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{PAPI_TOT_CYC, {0, {PNE_PM_RUN_CYC, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Processor cycles gated by the run latch */
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{PAPI_FDV_INS, {0, {PNE_PM_FPU_FDIV, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FD ins */
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{PAPI_FSQ_INS, {0, {PNE_PM_FPU_FSQRT, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FSq ins */
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{PAPI_TLB_DM, {0, {PNE_PM_DTLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Data translation lookaside buffer misses */
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{PAPI_TLB_IM, {0, {PNE_PM_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Instr translation lookaside buffer misses */
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{PAPI_TLB_TL, {DERIVED_ADD, {PNE_PM_DTLB_MISS, PNE_PM_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total translation lookaside buffer misses */
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{PAPI_HW_INT, {0, {PNE_PM_EXT_INT, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Hardware interrupts */
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{PAPI_STL_ICY, {0, {PNE_PM_0INST_FETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Cycles with No Instruction Issue */
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{PAPI_LD_INS, {0, {PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Load instructions */
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{PAPI_SR_INS, {0, {PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Store instructions */
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{PAPI_LST_INS, {DERIVED_ADD, {PNE_PM_ST_REF_L1, PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Load and Store instructions */
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{PAPI_BR_INS, {0, {PNE_PM_BR_ISSUED, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Branch instructions */
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{PAPI_BR_MSP, {DERIVED_ADD, {PNE_PM_BR_MPRED_CR, PNE_PM_BR_MPRED_TA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Branch mispredictions */
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{PAPI_FXU_IDL, {0, {PNE_PM_FXU_IDLE, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Cycles integer units are idle */
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{0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}} /* end of list */
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#else
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#ifdef _PPC970
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{PAPI_L2_DCM, {0, {PNE_PM_DATA_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 2 data cache misses */
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{PAPI_L2_DCR, {DERIVED_ADD, {PNE_PM_DATA_FROM_L2, PNE_PM_DATA_FROM_L25_MOD, PNE_PM_DATA_FROM_L25_SHR, PNE_PM_DATA_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 data cache read attempts */
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{PAPI_L2_DCH, {DERIVED_ADD, {PNE_PM_DATA_FROM_L2, PNE_PM_DATA_FROM_L25_MOD, PNE_PM_DATA_FROM_L25_SHR, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 data cache hits */
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{PAPI_L2_LDM, {0, {PNE_PM_DATA_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 data cache read misses */
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/* no PAPI_L1_ICA since PM_INST_FROM_L1 and PM_INST_FROM_L2 cannot be counted simultaneously. */
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{PAPI_L1_ICM, {DERIVED_ADD, {PNE_PM_INST_FROM_L2, PNE_PM_INST_FROM_L25_SHR, PNE_PM_INST_FROM_L25_MOD, PNE_PM_INST_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 1 inst cache misses */
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{PAPI_L2_ICA, {DERIVED_ADD, {PNE_PM_INST_FROM_L2, PNE_PM_INST_FROM_L25_SHR, PNE_PM_INST_FROM_L25_MOD, PNE_PM_INST_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 inst cache accesses */
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{PAPI_L2_ICH, {DERIVED_ADD, {PNE_PM_INST_FROM_L2, PNE_PM_INST_FROM_L25_SHR, PNE_PM_INST_FROM_L25_MOD, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 inst cache hits */
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{PAPI_L2_ICM, {0, {PNE_PM_INST_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 inst cache misses */
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#endif
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/* Common preset events for PPC970 */
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{PAPI_L1_DCM, {DERIVED_ADD, {PNE_PM_LD_MISS_L1, PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 data cache misses */
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{PAPI_L1_DCA, {DERIVED_ADD, {PNE_PM_LD_REF_L1, PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 data cache access */
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{PAPI_FXU_IDL, {0, {PNE_PM_FXU_IDLE, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Cycles integer units are idle */
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{PAPI_L1_LDM, {0, {PNE_PM_LD_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 load misses */
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{PAPI_L1_STM, {0, {PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 store misses */
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{PAPI_L1_DCW, {0, {PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 D cache write */
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{PAPI_L1_DCR, {0, {PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 D cache read */
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{PAPI_FMA_INS, {0, {PNE_PM_FPU_FMA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FMA instructions completed */
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{PAPI_TOT_IIS, {0, {PNE_PM_INST_DISP, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total instructions issued */
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{PAPI_TOT_INS, {0, {PNE_PM_INST_CMPL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total instructions executed */
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{PAPI_INT_INS, {0, {PNE_PM_FXU_FIN, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Integer instructions executed */
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{PAPI_FP_OPS, {DERIVED_POSTFIX, {PNE_PM_FPU0_FIN, PNE_PM_FPU1_FIN, PNE_PM_FPU_FMA, PNE_PM_FPU_STF, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, "N0|N1|+|N2|+|N3|-|"}}, /*Floating point instructions executed */
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{PAPI_FP_INS, {0, {PNE_PM_FPU_FIN, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Floating point instructions executed */
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{PAPI_TOT_CYC, {0, {PNE_PM_CYC, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total cycles */
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{PAPI_FDV_INS, {0, {PNE_PM_FPU_FDIV, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FD ins */
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{PAPI_FSQ_INS, {0, {PNE_PM_FPU_FSQRT, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FSq ins */
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{PAPI_TLB_DM, {0, {PNE_PM_DTLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Data translation lookaside buffer misses */
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{PAPI_TLB_IM, {0, {PNE_PM_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Instr translation lookaside buffer misses */
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{PAPI_TLB_TL, {DERIVED_ADD, {PNE_PM_DTLB_MISS, PNE_PM_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total translation lookaside buffer misses */
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{PAPI_HW_INT, {0, {PNE_PM_EXT_INT, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Hardware interrupts */
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{PAPI_STL_ICY, {0, {PNE_PM_0INST_FETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Cycles with No Instruction Issue */
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{PAPI_LD_INS, {0, {PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Load instructions */
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{PAPI_SR_INS, {0, {PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Store instructions */
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{PAPI_LST_INS, {DERIVED_ADD, {PNE_PM_ST_REF_L1, PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Load and Store instructions */
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{PAPI_BR_INS, {0, {PNE_PM_BR_ISSUED, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Branch instructions */
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{PAPI_BR_MSP, {DERIVED_ADD, {PNE_PM_BR_MPRED_CR, PNE_PM_BR_MPRED_TA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Branch mispredictions */
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{PAPI_L1_DCH, {DERIVED_POSTFIX, {PNE_PM_LD_REF_L1, PNE_PM_LD_MISS_L1, PNE_PM_ST_REF_L1, PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, "N0|N1|-|N2|+|N3|-|"}}, /* Level 1 data cache hits */
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/* no PAPI_L2_STM, PAPI_L2_DCW nor PAPI_L2_DCA since stores/writes to L2 aren't countable */
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{PAPI_L3_DCM, {0, {PNE_PM_DATA_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 data cache misses (reads & writes) */
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{PAPI_L3_LDM, {0, {PNE_PM_DATA_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 data cache read misses */
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{PAPI_L1_ICH, {0, {PNE_PM_INST_FROM_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 1 inst cache hits */
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{PAPI_L3_ICM, {0, {PNE_PM_INST_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 inst cache misses */
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{0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}} /* end of list */
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#endif
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};
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hwi_search_t *preset_search_map;
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#if defined(_POWER5) || defined(_POWER5p)
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unsigned long long pmc_sel_mask[NUM_COUNTER_MASKS] = {
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PMC1_SEL_MASK,
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577717 |
PMC2_SEL_MASK,
|
|
Packit |
577717 |
PMC3_SEL_MASK,
|
|
Packit |
577717 |
PMC4_SEL_MASK
|
|
Packit |
577717 |
};
|
|
Packit |
577717 |
#else
|
|
Packit |
577717 |
unsigned long long pmc_sel_mask[NUM_COUNTER_MASKS] = {
|
|
Packit |
577717 |
PMC1_SEL_MASK,
|
|
Packit |
577717 |
PMC2_SEL_MASK,
|
|
Packit |
577717 |
PMC3_SEL_MASK,
|
|
Packit |
577717 |
PMC4_SEL_MASK,
|
|
Packit |
577717 |
PMC5_SEL_MASK,
|
|
Packit |
577717 |
PMC6_SEL_MASK,
|
|
Packit |
577717 |
PMC7_SEL_MASK,
|
|
Packit |
577717 |
PMC8_SEL_MASK,
|
|
Packit |
577717 |
PMC8a_SEL_MASK
|
|
Packit |
577717 |
};
|
|
Packit |
577717 |
#endif
|
|
Packit |
577717 |
|
|
Packit |
577717 |
static void
|
|
Packit |
577717 |
clear_unused_pmcsel_bits( hwd_control_state_t * cntrl )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
struct perfctr_cpu_control *cpu_ctl = &cntrl->control.cpu_control;
|
|
Packit |
577717 |
int i;
|
|
Packit |
577717 |
int num_used_counters = cpu_ctl->nractrs + cpu_ctl->nrictrs;
|
|
Packit |
577717 |
unsigned int used_counters = 0x0;
|
|
Packit |
577717 |
for ( i = 0; i < num_used_counters; i++ ) {
|
|
Packit |
577717 |
used_counters |= 1 << cpu_ctl->pmc_map[i];
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
#if defined(_POWER5) || defined(_POWER5p)
|
|
Packit |
577717 |
int freeze_pmc5_pmc6 = 0; /* for Power5 use only */
|
|
Packit |
577717 |
#endif
|
|
Packit |
577717 |
|
|
Packit |
577717 |
for ( i = 0; i < MAX_COUNTERS; i++ ) {
|
|
Packit |
577717 |
unsigned int active_counter = ( ( 1 << i ) & used_counters );
|
|
Packit |
577717 |
if ( !active_counter ) {
|
|
Packit |
577717 |
#if defined(_POWER5) || defined(_POWER5p)
|
|
Packit |
577717 |
if ( i > 3 )
|
|
Packit |
577717 |
freeze_pmc5_pmc6++;
|
|
Packit |
577717 |
else
|
|
Packit |
577717 |
cpu_ctl->ppc64.mmcr1 &= pmc_sel_mask[i];
|
|
Packit |
577717 |
#else
|
|
Packit |
577717 |
if ( i < 2 ) {
|
|
Packit |
577717 |
cpu_ctl->ppc64.mmcr0 &= pmc_sel_mask[i];
|
|
Packit |
577717 |
} else {
|
|
Packit |
577717 |
cpu_ctl->ppc64.mmcr1 &= pmc_sel_mask[i];
|
|
Packit |
577717 |
if ( i == ( MAX_COUNTERS - 1 ) )
|
|
Packit |
577717 |
cpu_ctl->ppc64.mmcra &= pmc_sel_mask[NUM_COUNTER_MASKS - 1];
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
#endif
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
#if defined(_POWER5) || defined(_POWER5p)
|
|
Packit |
577717 |
if ( freeze_pmc5_pmc6 == 2 )
|
|
Packit |
577717 |
cpu_ctl->ppc64.mmcr0 |= PMC5_PMC6_FREEZE;
|
|
Packit |
577717 |
#endif
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
static int
|
|
Packit |
577717 |
set_domain( hwd_control_state_t * cntrl, unsigned int domain )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
int did = 0;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* A bit setting of '0' indicates "count this context".
|
|
Packit |
577717 |
* Start off by turning off counting for all contexts;
|
|
Packit |
577717 |
* then, selectively re-enable.
|
|
Packit |
577717 |
*/
|
|
Packit |
577717 |
cntrl->control.cpu_control.ppc64.mmcr0 |=
|
|
Packit |
577717 |
PERF_USER | PERF_KERNEL | PERF_HYPERVISOR;
|
|
Packit |
577717 |
if ( domain & PAPI_DOM_USER ) {
|
|
Packit |
577717 |
cntrl->control.cpu_control.ppc64.mmcr0 |= PERF_USER;
|
|
Packit |
577717 |
cntrl->control.cpu_control.ppc64.mmcr0 ^= PERF_USER;
|
|
Packit |
577717 |
did = 1;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
if ( domain & PAPI_DOM_KERNEL ) {
|
|
Packit |
577717 |
cntrl->control.cpu_control.ppc64.mmcr0 |= PERF_KERNEL;
|
|
Packit |
577717 |
cntrl->control.cpu_control.ppc64.mmcr0 ^= PERF_KERNEL;
|
|
Packit |
577717 |
did = 1;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
if ( domain & PAPI_DOM_SUPERVISOR ) {
|
|
Packit |
577717 |
cntrl->control.cpu_control.ppc64.mmcr0 |= PERF_HYPERVISOR;
|
|
Packit |
577717 |
cntrl->control.cpu_control.ppc64.mmcr0 ^= PERF_HYPERVISOR;
|
|
Packit |
577717 |
did = 1;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
if ( did ) {
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
} else {
|
|
Packit |
577717 |
return ( PAPI_EINVAL );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
//extern native_event_entry_t *native_table;
|
|
Packit |
577717 |
//extern hwi_search_t _papi_hwd_preset_map[];
|
|
Packit |
577717 |
extern papi_mdi_t _papi_hwi_system_info;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
#ifdef DEBUG
|
|
Packit |
577717 |
void
|
|
Packit |
577717 |
print_control( const struct perfctr_cpu_control *control )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
unsigned int i;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
SUBDBG( "Control used:\n" );
|
|
Packit |
577717 |
SUBDBG( "tsc_on\t\t\t%u\n", control->tsc_on );
|
|
Packit |
577717 |
SUBDBG( "nractrs\t\t\t%u\n", control->nractrs );
|
|
Packit |
577717 |
SUBDBG( "nrictrs\t\t\t%u\n", control->nrictrs );
|
|
Packit |
577717 |
SUBDBG( "mmcr0\t\t\t0x%X\n", control->ppc64.mmcr0 );
|
|
Packit |
577717 |
SUBDBG( "mmcr1\t\t\t0x%llX\n",
|
|
Packit |
577717 |
( unsigned long long ) control->ppc64.mmcr1 );
|
|
Packit |
577717 |
SUBDBG( "mmcra\t\t\t0x%X\n", control->ppc64.mmcra );
|
|
Packit |
577717 |
|
|
Packit |
577717 |
for ( i = 0; i < ( control->nractrs + control->nrictrs ); ++i ) {
|
|
Packit |
577717 |
SUBDBG( "pmc_map[%u]\t\t%u\n", i, control->pmc_map[i] );
|
|
Packit |
577717 |
if ( control->ireset[i] ) {
|
|
Packit |
577717 |
SUBDBG( "ireset[%d]\t%X\n", i, control->ireset[i] );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
#endif
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* Assign the global native and preset table pointers, find the native
|
|
Packit |
577717 |
table's size in memory and then call the preset setup routine. */
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
setup_ppc64_presets( int cputype )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
preset_search_map = preset_name_map_PPC64;
|
|
Packit |
577717 |
return ( _papi_hwi_setup_all_presets( preset_search_map, NULL ) );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/*called when an EventSet is allocated */
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_init_control_state( hwd_control_state_t * ptr )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
int i = 0;
|
|
Packit |
577717 |
for ( i = 0; i < _papi_hwi_system_info.sub_info.num_cntrs; i++ ) {
|
|
Packit |
577717 |
ptr->control.cpu_control.pmc_map[i] = i;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
ptr->control.cpu_control.tsc_on = 1;
|
|
Packit |
577717 |
set_domain( ptr, _papi_hwi_system_info.sub_info.default_domain );
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* At init time, the higher level library should always allocate and
|
|
Packit |
577717 |
reserve EventSet zero. */
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* Called once per process. */
|
|
Packit |
577717 |
/* No longer needed if not implemented
|
|
Packit |
577717 |
int _papi_hwd_shutdown_global(void) {
|
|
Packit |
577717 |
return (PAPI_OK);
|
|
Packit |
577717 |
} */
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* this function recusively does Modified Bipartite Graph counter allocation
|
|
Packit |
577717 |
success return 1
|
|
Packit |
577717 |
fail return 0
|
|
Packit |
577717 |
*/
|
|
Packit |
577717 |
static int
|
|
Packit |
577717 |
do_counter_allocation( ppc64_reg_alloc_t * event_list, int size )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
int i, j, group = -1;
|
|
Packit |
577717 |
unsigned int map[GROUP_INTS];
|
|
Packit |
577717 |
|
|
Packit |
577717 |
for ( i = 0; i < GROUP_INTS; i++ ) {
|
|
Packit |
577717 |
map[i] = event_list[0].ra_group[i];
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
for ( i = 1; i < size; i++ ) {
|
|
Packit |
577717 |
for ( j = 0; j < GROUP_INTS; j++ )
|
|
Packit |
577717 |
map[j] &= event_list[i].ra_group[j];
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
for ( i = 0; i < GROUP_INTS; i++ ) {
|
|
Packit |
577717 |
if ( map[i] ) {
|
|
Packit |
577717 |
group = ffs( map[i] ) - 1 + i * 32;
|
|
Packit |
577717 |
break;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
if ( group < 0 )
|
|
Packit |
577717 |
return group; /* allocation fail */
|
|
Packit |
577717 |
else {
|
|
Packit |
577717 |
for ( i = 0; i < size; i++ ) {
|
|
Packit |
577717 |
for ( j = 0; j < MAX_COUNTERS; j++ ) {
|
|
Packit |
577717 |
if ( event_list[i].ra_counter_cmd[j] >= 0
|
|
Packit |
577717 |
&& event_list[i].ra_counter_cmd[j] ==
|
|
Packit |
577717 |
group_map[group].counter_cmd[j] )
|
|
Packit |
577717 |
event_list[i].ra_position = j;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
return group;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* Register allocation */
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_allocate_registers( EventSetInfo_t * ESI )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
hwd_control_state_t *this_state = &ESI->machdep;
|
|
Packit |
577717 |
int i, j, natNum, index;
|
|
Packit |
577717 |
ppc64_reg_alloc_t event_list[MAX_COUNTERS];
|
|
Packit |
577717 |
int group;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* not yet successfully mapped, but have enough slots for events */
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* Initialize the local structure needed
|
|
Packit |
577717 |
for counter allocation and optimization. */
|
|
Packit |
577717 |
natNum = ESI->NativeCount;
|
|
Packit |
577717 |
for ( i = 0; i < natNum; i++ ) {
|
|
Packit |
577717 |
event_list[i].ra_position = -1;
|
|
Packit |
577717 |
for ( j = 0; j < MAX_COUNTERS; j++ ) {
|
|
Packit |
577717 |
if ( ( index =
|
|
Packit |
577717 |
native_name_map[ESI->NativeInfoArray[i].
|
|
Packit |
577717 |
ni_event & PAPI_NATIVE_AND_MASK].index ) <
|
|
Packit |
577717 |
0 )
|
|
Packit |
577717 |
return PAPI_ECNFLCT;
|
|
Packit |
577717 |
event_list[i].ra_counter_cmd[j] =
|
|
Packit |
577717 |
native_table[index].resources.counter_cmd[j];
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
for ( j = 0; j < GROUP_INTS; j++ ) {
|
|
Packit |
577717 |
if ( ( index =
|
|
Packit |
577717 |
native_name_map[ESI->NativeInfoArray[i].
|
|
Packit |
577717 |
ni_event & PAPI_NATIVE_AND_MASK].index ) <
|
|
Packit |
577717 |
0 )
|
|
Packit |
577717 |
return PAPI_ECNFLCT;
|
|
Packit |
577717 |
event_list[i].ra_group[j] = native_table[index].resources.group[j];
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
if ( ( group = do_counter_allocation( event_list, natNum ) ) >= 0 ) { /* successfully mapped */
|
|
Packit |
577717 |
/* copy counter allocations info back into NativeInfoArray */
|
|
Packit |
577717 |
this_state->group_id = group;
|
|
Packit |
577717 |
for ( i = 0; i < natNum; i++ ) {
|
|
Packit |
577717 |
// ESI->NativeInfoArray[i].ni_position = event_list[i].ra_position;
|
|
Packit |
577717 |
this_state->control.cpu_control.pmc_map[i] =
|
|
Packit |
577717 |
event_list[i].ra_position;
|
|
Packit |
577717 |
ESI->NativeInfoArray[i].ni_position = i;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
/* update the control structure based on the NativeInfoArray */
|
|
Packit |
577717 |
SUBDBG( "Group ID: %d\n", group );
|
|
Packit |
577717 |
|
|
Packit |
577717 |
return PAPI_OK;
|
|
Packit |
577717 |
} else {
|
|
Packit |
577717 |
return PAPI_ECNFLCT;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* This function clears the current contents of the control structure and
|
|
Packit |
577717 |
updates it with whatever resources are allocated for all the native events
|
|
Packit |
577717 |
in the native info structure array. */
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_update_control_state( hwd_control_state_t * this_state,
|
|
Packit |
577717 |
NativeInfo_t * native, int count,
|
|
Packit |
577717 |
hwd_context_t * context )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
this_state->control.cpu_control.nractrs =
|
|
Packit |
577717 |
count - this_state->control.cpu_control.nrictrs;
|
|
Packit |
577717 |
// save control state
|
|
Packit |
577717 |
unsigned int save_mmcr0_ctlbits =
|
|
Packit |
577717 |
PERF_CONTROL_MASK & this_state->control.cpu_control.ppc64.mmcr0;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
this_state->control.cpu_control.ppc64.mmcr0 =
|
|
Packit |
577717 |
group_map[this_state->group_id].mmcr0 | save_mmcr0_ctlbits;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
unsigned long long mmcr1 =
|
|
Packit |
577717 |
( ( unsigned long long ) group_map[this_state->group_id].mmcr1U ) << 32;
|
|
Packit |
577717 |
mmcr1 += group_map[this_state->group_id].mmcr1L;
|
|
Packit |
577717 |
this_state->control.cpu_control.ppc64.mmcr1 = mmcr1;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
this_state->control.cpu_control.ppc64.mmcra =
|
|
Packit |
577717 |
group_map[this_state->group_id].mmcra;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
clear_unused_pmcsel_bits( this_state );
|
|
Packit |
577717 |
return PAPI_OK;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_start( hwd_context_t * ctx, hwd_control_state_t * state )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
int error;
|
|
Packit |
577717 |
/* clear_unused_pmcsel_bits(this_state); moved to update_control_state */
|
|
Packit |
577717 |
#ifdef DEBUG
|
|
Packit |
577717 |
print_control( &state->control.cpu_control );
|
|
Packit |
577717 |
#endif
|
|
Packit |
577717 |
if ( state->rvperfctr != NULL ) {
|
|
Packit |
577717 |
if ( ( error =
|
|
Packit |
577717 |
rvperfctr_control( state->rvperfctr, &state->control ) ) < 0 ) {
|
|
Packit |
577717 |
SUBDBG( "rvperfctr_control returns: %d\n", error );
|
|
Packit |
577717 |
PAPIERROR( RCNTRL_ERROR );
|
|
Packit |
577717 |
return ( PAPI_ESYS );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
if ( ( error = vperfctr_control( ctx->perfctr, &state->control ) ) < 0 ) {
|
|
Packit |
577717 |
SUBDBG( "vperfctr_control returns: %d\n", error );
|
|
Packit |
577717 |
PAPIERROR( VCNTRL_ERROR );
|
|
Packit |
577717 |
return ( PAPI_ESYS );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_stop( hwd_context_t * ctx, hwd_control_state_t * state )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
if ( state->rvperfctr != NULL ) {
|
|
Packit |
577717 |
if ( rvperfctr_stop( ( struct rvperfctr * ) ctx->perfctr ) < 0 ) {
|
|
Packit |
577717 |
PAPIERROR( RCNTRL_ERROR );
|
|
Packit |
577717 |
return ( PAPI_ESYS );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
if ( vperfctr_stop( ctx->perfctr ) < 0 ) {
|
|
Packit |
577717 |
PAPIERROR( VCNTRL_ERROR );
|
|
Packit |
577717 |
return ( PAPI_ESYS );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_read( hwd_context_t * ctx, hwd_control_state_t * spc, long long **dp,
|
|
Packit |
577717 |
int flags )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
if ( flags & PAPI_PAUSED ) {
|
|
Packit |
577717 |
vperfctr_read_state( ctx->perfctr, &spc->state, NULL );
|
|
Packit |
577717 |
} else {
|
|
Packit |
577717 |
SUBDBG( "vperfctr_read_ctrs\n" );
|
|
Packit |
577717 |
if ( spc->rvperfctr != NULL ) {
|
|
Packit |
577717 |
rvperfctr_read_ctrs( spc->rvperfctr, &spc->state );
|
|
Packit |
577717 |
} else {
|
|
Packit |
577717 |
vperfctr_read_ctrs( ctx->perfctr, &spc->state );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
*dp = ( long long * ) spc->state.pmc;
|
|
Packit |
577717 |
#ifdef DEBUG
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
if ( ISLEVEL( DEBUG_SUBSTRATE ) ) {
|
|
Packit |
577717 |
int i;
|
|
Packit |
577717 |
for ( i = 0;
|
|
Packit |
577717 |
i <
|
|
Packit |
577717 |
spc->control.cpu_control.nractrs +
|
|
Packit |
577717 |
spc->control.cpu_control.nrictrs; i++ ) {
|
|
Packit |
577717 |
SUBDBG( "raw val hardware index %d is %lld\n", i,
|
|
Packit |
577717 |
( long long ) spc->state.pmc[i] );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
#endif
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_reset( hwd_context_t * ctx, hwd_control_state_t * cntrl )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
return ( _papi_hwd_start( ctx, cntrl ) );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* This routine is for shutting down threads, including the
|
|
Packit |
577717 |
master thread. */
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_shutdown( hwd_context_t * ctx )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
int retval = vperfctr_unlink( ctx->perfctr );
|
|
Packit |
577717 |
SUBDBG( "_papi_hwd_shutdown vperfctr_unlink(%p) = %d\n", ctx->perfctr,
|
|
Packit |
577717 |
retval );
|
|
Packit |
577717 |
vperfctr_close( ctx->perfctr );
|
|
Packit |
577717 |
SUBDBG( "_papi_hwd_shutdown vperfctr_close(%p)\n", ctx->perfctr );
|
|
Packit |
577717 |
memset( ctx, 0x0, sizeof ( hwd_context_t ) );
|
|
Packit |
577717 |
|
|
Packit |
577717 |
if ( retval )
|
|
Packit |
577717 |
return ( PAPI_ESYS );
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* Perfctr requires that interrupting counters appear at the end of the pmc list
|
|
Packit |
577717 |
In the case a user wants to interrupt on a counter in an evntset that is not
|
|
Packit |
577717 |
among the last events, we need to move the perfctr virtual events around to
|
|
Packit |
577717 |
make it last. This function swaps two perfctr events, and then adjust the
|
|
Packit |
577717 |
position entries in both the NativeInfoArray and the EventInfoArray to keep
|
|
Packit |
577717 |
everything consistent.
|
|
Packit |
577717 |
*/
|
|
Packit |
577717 |
static void
|
|
Packit |
577717 |
swap_events( EventSetInfo_t * ESI, struct hwd_pmc_control *contr, int cntr1,
|
|
Packit |
577717 |
int cntr2 )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
unsigned int ui;
|
|
Packit |
577717 |
int si, i, j;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
for ( i = 0; i < ESI->NativeCount; i++ ) {
|
|
Packit |
577717 |
if ( ESI->NativeInfoArray[i].ni_position == cntr1 )
|
|
Packit |
577717 |
ESI->NativeInfoArray[i].ni_position = cntr2;
|
|
Packit |
577717 |
else if ( ESI->NativeInfoArray[i].ni_position == cntr2 )
|
|
Packit |
577717 |
ESI->NativeInfoArray[i].ni_position = cntr1;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
for ( i = 0; i < ESI->NumberOfEvents; i++ ) {
|
|
Packit |
577717 |
for ( j = 0; ESI->EventInfoArray[i].pos[j] >= 0; j++ ) {
|
|
Packit |
577717 |
if ( ESI->EventInfoArray[i].pos[j] == cntr1 )
|
|
Packit |
577717 |
ESI->EventInfoArray[i].pos[j] = cntr2;
|
|
Packit |
577717 |
else if ( ESI->EventInfoArray[i].pos[j] == cntr2 )
|
|
Packit |
577717 |
ESI->EventInfoArray[i].pos[j] = cntr1;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
ui = contr->cpu_control.pmc_map[cntr1];
|
|
Packit |
577717 |
contr->cpu_control.pmc_map[cntr1] = contr->cpu_control.pmc_map[cntr2];
|
|
Packit |
577717 |
contr->cpu_control.pmc_map[cntr2] = ui;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
si = contr->cpu_control.ireset[cntr1];
|
|
Packit |
577717 |
contr->cpu_control.ireset[cntr1] = contr->cpu_control.ireset[cntr2];
|
|
Packit |
577717 |
contr->cpu_control.ireset[cntr2] = si;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_set_overflow( EventSetInfo_t * ESI, int EventIndex, int threshold )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
hwd_control_state_t *this_state = &ESI->machdep;
|
|
Packit |
577717 |
struct hwd_pmc_control *contr = &this_state->control;
|
|
Packit |
577717 |
int i, ncntrs, nricntrs = 0, nracntrs = 0, retval = 0;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
OVFDBG( "EventIndex=%d, threshold = %d\n", EventIndex, threshold );
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* The correct event to overflow is EventIndex */
|
|
Packit |
577717 |
ncntrs = _papi_hwi_system_info.sub_info.num_cntrs;
|
|
Packit |
577717 |
i = ESI->EventInfoArray[EventIndex].pos[0];
|
|
Packit |
577717 |
if ( i >= ncntrs ) {
|
|
Packit |
577717 |
OVFDBG( "Selector id (%d) larger than ncntrs (%d)\n", i, ncntrs );
|
|
Packit |
577717 |
return PAPI_EINVAL;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
if ( threshold != 0 ) { /* Set an overflow threshold */
|
|
Packit |
577717 |
if ( ESI->EventInfoArray[EventIndex].derived ) {
|
|
Packit |
577717 |
OVFDBG( "Can't overflow on a derived event.\n" );
|
|
Packit |
577717 |
return PAPI_EINVAL;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
if ( ( retval =
|
|
Packit |
577717 |
_papi_hwi_start_signal( _papi_hwi_system_info.sub_info.
|
|
Packit |
577717 |
hardware_intr_sig,
|
|
Packit |
577717 |
NEED_CONTEXT ) ) != PAPI_OK )
|
|
Packit |
577717 |
return ( retval );
|
|
Packit |
577717 |
|
|
Packit |
577717 |
contr->cpu_control.ireset[i] = PMC_OVFL - threshold;
|
|
Packit |
577717 |
nricntrs = ++contr->cpu_control.nrictrs;
|
|
Packit |
577717 |
nracntrs = --contr->cpu_control.nractrs;
|
|
Packit |
577717 |
contr->si_signo = _papi_hwi_system_info.sub_info.hardware_intr_sig;
|
|
Packit |
577717 |
contr->cpu_control.ppc64.mmcr0 |= PERF_INT_ENABLE;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* move this event to the bottom part of the list if needed */
|
|
Packit |
577717 |
if ( i < nracntrs )
|
|
Packit |
577717 |
swap_events( ESI, contr, i, nracntrs );
|
|
Packit |
577717 |
|
|
Packit |
577717 |
OVFDBG( "Modified event set\n" );
|
|
Packit |
577717 |
} else {
|
|
Packit |
577717 |
if ( contr->cpu_control.ppc64.mmcr0 & PERF_INT_ENABLE ) {
|
|
Packit |
577717 |
contr->cpu_control.ireset[i] = 0;
|
|
Packit |
577717 |
nricntrs = --contr->cpu_control.nrictrs;
|
|
Packit |
577717 |
nracntrs = ++contr->cpu_control.nractrs;
|
|
Packit |
577717 |
if ( !nricntrs )
|
|
Packit |
577717 |
contr->cpu_control.ppc64.mmcr0 &= ( ~PERF_INT_ENABLE );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
/* move this event to the top part of the list if needed */
|
|
Packit |
577717 |
if ( i >= nracntrs )
|
|
Packit |
577717 |
swap_events( ESI, contr, i, nracntrs - 1 );
|
|
Packit |
577717 |
if ( !nricntrs )
|
|
Packit |
577717 |
contr->si_signo = 0;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
OVFDBG( "Modified event set\n" );
|
|
Packit |
577717 |
|
|
Packit |
577717 |
retval =
|
|
Packit |
577717 |
_papi_hwi_stop_signal( _papi_hwi_system_info.sub_info.
|
|
Packit |
577717 |
hardware_intr_sig );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
#ifdef DEBUG
|
|
Packit |
577717 |
print_control( &contr->cpu_control );
|
|
Packit |
577717 |
#endif
|
|
Packit |
577717 |
OVFDBG( "%s:%d: Hardware overflow is still experimental.\n", __FILE__,
|
|
Packit |
577717 |
__LINE__ );
|
|
Packit |
577717 |
OVFDBG( "End of call. Exit code: %d\n", retval );
|
|
Packit |
577717 |
|
|
Packit |
577717 |
return ( retval );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_set_profile( EventSetInfo_t * ESI, int EventIndex, int threshold )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
/* This function is not used and shouldn't be called. */
|
|
Packit |
577717 |
return PAPI_ECMP;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_stop_profiling( ThreadInfo_t * master, EventSetInfo_t * ESI )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
ESI->profile.overflowcount = 0;
|
|
Packit |
577717 |
return PAPI_OK;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_set_domain( hwd_control_state_t * cntrl, int domain )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
return set_domain( cntrl, domain );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
/* Routines to support an opaque native event table */
|
|
Packit |
577717 |
char *
|
|
Packit |
577717 |
_papi_hwd_ntv_code_to_name( unsigned int EventCode )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
if ( ( EventCode & PAPI_NATIVE_AND_MASK ) >=
|
|
Packit |
577717 |
_papi_hwi_system_info.sub_info.num_native_events )
|
|
Packit |
577717 |
return ( '\0' ); // return a null string for invalid events
|
|
Packit |
577717 |
return ( native_name_map[EventCode & PAPI_NATIVE_AND_MASK].name );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_ntv_code_to_bits( unsigned int EventCode, hwd_register_t * bits )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
if ( ( EventCode & PAPI_NATIVE_AND_MASK ) >=
|
|
Packit |
577717 |
_papi_hwi_system_info.sub_info.num_native_events ) {
|
|
Packit |
577717 |
return ( PAPI_ENOEVNT );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
memcpy( bits,
|
|
Packit |
577717 |
&native_table[native_name_map[EventCode & PAPI_NATIVE_AND_MASK].
|
|
Packit |
577717 |
index].resources, sizeof ( hwd_register_t ) );
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
static void
|
|
Packit |
577717 |
copy_value( unsigned int val, char *nam, char *names, unsigned int *values,
|
|
Packit |
577717 |
int len )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
*values = val;
|
|
Packit |
577717 |
strncpy( names, nam, len );
|
|
Packit |
577717 |
names[len - 1] = 0;
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
|
|
Packit |
577717 |
char *
|
|
Packit |
577717 |
_papi_hwd_ntv_code_to_descr( unsigned int EventCode )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
if ( ( EventCode & PAPI_NATIVE_AND_MASK ) >=
|
|
Packit |
577717 |
_papi_hwi_system_info.sub_info.num_native_events ) {
|
|
Packit |
577717 |
return "\0";
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
return ( native_table
|
|
Packit |
577717 |
[native_name_map[EventCode & PAPI_NATIVE_AND_MASK].index].
|
|
Packit |
577717 |
description );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
_papi_hwd_ntv_enum_events( unsigned int *EventCode, int modifier )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
if ( modifier == PAPI_ENUM_EVENTS ) {
|
|
Packit |
577717 |
int index = *EventCode & PAPI_NATIVE_AND_MASK;
|
|
Packit |
577717 |
if ( index + 1 == MAX_NATNAME_MAP_INDEX ) {
|
|
Packit |
577717 |
return ( PAPI_ENOEVNT );
|
|
Packit |
577717 |
} else {
|
|
Packit |
577717 |
*EventCode = *EventCode + 1;
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
} else if ( modifier == PAPI_PWR4_ENUM_GROUPS ) {
|
|
Packit |
577717 |
/* Use this modifier for all supported PPC64 processors. */
|
|
Packit |
577717 |
unsigned int group = ( *EventCode & 0x00FF0000 ) >> 16;
|
|
Packit |
577717 |
int index = *EventCode & 0x000001FF;
|
|
Packit |
577717 |
int i;
|
|
Packit |
577717 |
unsigned int tmpg;
|
|
Packit |
577717 |
|
|
Packit |
577717 |
*EventCode = *EventCode & 0xFF00FFFF;
|
|
Packit |
577717 |
for ( i = 0; i < GROUP_INTS; i++ ) {
|
|
Packit |
577717 |
tmpg = native_table[index].resources.group[i];
|
|
Packit |
577717 |
if ( group != 0 ) {
|
|
Packit |
577717 |
while ( ( ffs( tmpg ) + i * 32 ) <= group && tmpg != 0 )
|
|
Packit |
577717 |
tmpg = tmpg ^ ( 1 << ( ffs( tmpg ) - 1 ) );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
if ( tmpg != 0 ) {
|
|
Packit |
577717 |
group = ffs( tmpg ) + i * 32;
|
|
Packit |
577717 |
*EventCode = *EventCode | ( group << 16 );
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
if ( index + 1 == MAX_NATNAME_MAP_INDEX ) {
|
|
Packit |
577717 |
return ( PAPI_ENOEVNT );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
*EventCode = *EventCode + 1;
|
|
Packit |
577717 |
return ( PAPI_OK );
|
|
Packit |
577717 |
} else
|
|
Packit |
577717 |
return ( PAPI_EINVAL );
|
|
Packit |
577717 |
}
|
|
Packit |
577717 |
|
|
Packit |
577717 |
papi_svector_t _ppc64_vector_table[] = {
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_init_control_state,
|
|
Packit |
577717 |
VEC_PAPI_HWD_INIT_CONTROL_STATE},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_allocate_registers,
|
|
Packit |
577717 |
VEC_PAPI_HWD_ALLOCATE_REGISTERS},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_update_control_state,
|
|
Packit |
577717 |
VEC_PAPI_HWD_UPDATE_CONTROL_STATE},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_start, VEC_PAPI_HWD_START},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_stop, VEC_PAPI_HWD_STOP},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_read, VEC_PAPI_HWD_READ},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_reset, VEC_PAPI_HWD_RESET},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_shutdown, VEC_PAPI_HWD_SHUTDOWN},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_set_overflow, VEC_PAPI_HWD_SET_OVERFLOW},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_set_profile, VEC_PAPI_HWD_SET_PROFILE},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_stop_profiling, VEC_PAPI_HWD_STOP_PROFILING},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_set_domain, VEC_PAPI_HWD_SET_DOMAIN},
|
|
Packit |
577717 |
{( void ( * )( ) ) *_papi_hwd_ntv_code_to_name,
|
|
Packit |
577717 |
VEC_PAPI_HWD_NTV_CODE_TO_NAME},
|
|
Packit |
577717 |
{( void ( * )( ) ) _papi_hwd_ntv_code_to_bits,
|
|
Packit |
577717 |
VEC_PAPI_HWD_NTV_CODE_TO_BITS},
|
|
Packit |
577717 |
{( void ( * )( ) ) *_papi_hwd_ntv_code_to_descr,
|
|
Packit |
577717 |
VEC_PAPI_HWD_NTV_CODE_TO_DESCR},
|
|
Packit |
577717 |
{( void ( * )( ) ) *_papi_hwd_ntv_enum_events,
|
|
Packit |
577717 |
VEC_PAPI_HWD_NTV_ENUM_EVENTS},
|
|
Packit |
577717 |
{NULL, VEC_PAPI_END}
|
|
Packit |
577717 |
};
|
|
Packit |
577717 |
|
|
Packit |
577717 |
int
|
|
Packit |
577717 |
ppc64_setup_vector_table( papi_vectors_t * vtable )
|
|
Packit |
577717 |
{
|
|
Packit |
577717 |
int retval = PAPI_OK;
|
|
Packit |
577717 |
retval = _papi_hwi_setup_vector_table( vtable, _ppc64_vector_table );
|
|
Packit |
577717 |
}
|