#! /usr/bin/env perl

# Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.

#

# Licensed under the OpenSSL license (the "License").  You may not use

# this file except in compliance with the License.  You can obtain a copy

# in the file LICENSE in the source distribution or at

# https://www.openssl.org/source/license.html

# ====================================================================

# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL

# project. The module is, however, dual licensed under OpenSSL and

# CRYPTOGAMS licenses depending on where you obtain it. For further

# details see http://www.openssl.org/~appro/cryptogams/.

# ====================================================================

# AES for MIPS

# October 2010

#

# Code uses 1K[+256B] S-box and on single-issue core [such as R5000]

# spends ~68 cycles per byte processed with 128-bit key. This is ~16%

# faster than gcc-generated code, which is not very impressive. But

# recall that compressed S-box requires extra processing, namely

# additional rotations. Rotations are implemented with lwl/lwr pairs,

# which is normally used for loading unaligned data. Another cool

# thing about this module is its endian neutrality, which means that

# it processes data without ever changing byte order...

# September 2012

#

# Add MIPS32R2 (~10% less instructions) and SmartMIPS ASE (further

# ~25% less instructions) code. Note that there is no run-time switch,

# instead, code path is chosen upon pre-process time, pass -mips32r2

# or/and -msmartmips.

######################################################################

# There is a number of MIPS ABI in use, O32 and N32/64 are most

# widely used. Then there is a new contender: NUBI. It appears that if

# one picks the latter, it's possible to arrange code in ABI neutral

# manner. Therefore let's stick to NUBI register layout:

#

($zero,$at,$t0,$t1,$t2)=map("\$$_",(0..2,24,25));

($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));

($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23));

($gp,$tp,$sp,$fp,$ra)=map("\$$_",(3,28..31));

#

# The return value is placed in $a0. Following coding rules facilitate

# interoperability:

#

# - never ever touch $tp, "thread pointer", former $gp;

# - copy return value to $t0, former $v0 [or to $a0 if you're adapting

#   old code];

# - on O32 populate $a4-$a7 with 'lw $aN,4*N($sp)' if necessary;

#

# For reference here is register layout for N32/64 MIPS ABIs:

#

# ($zero,$at,$v0,$v1)=map("\$$_",(0..3));

# ($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));

# ($t0,$t1,$t2,$t3,$t8,$t9)=map("\$$_",(12..15,24,25));

# ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23));

# ($gp,$sp,$fp,$ra)=map("\$$_",(28..31));

#

$flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64

if ($flavour =~ /64|n32/i) {

	$PTR_LA="dla";

	$PTR_ADD="daddu";	# incidentally works even on n32

	$PTR_SUB="dsubu";	# incidentally works even on n32

	$PTR_INS="dins";

	$REG_S="sd";

	$REG_L="ld";

	$PTR_SLL="dsll";	# incidentally works even on n32

	$SZREG=8;

} else {

	$PTR_LA="la";

	$PTR_ADD="addu";

	$PTR_SUB="subu";

	$PTR_INS="ins";

	$REG_S="sw";

	$REG_L="lw";

	$PTR_SLL="sll";

	$SZREG=4;

}

$pf = ($flavour =~ /nubi/i) ? $t0 : $t2;

#

# <appro@openssl.org>

#

######################################################################

$big_endian=(`echo MIPSEB | $ENV{CC} -E -`=~/MIPSEB/)?0:1 if ($ENV{CC});

for (@ARGV) {	$output=$_ if (/\w[\w\-]*\.\w+$/);	}

open STDOUT,">$output";

if (!defined($big_endian))

{    $big_endian=(unpack('L',pack('N',1))==1);   }

while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {}

open STDOUT,">$output";

my ($MSB,$LSB)=(0,3);	# automatically converted to little-endian

$code.=<<___;

#include "mips_arch.h"

.text

#if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))

.option	pic2

#endif

.set	noat

___

{{{

my $FRAMESIZE=16*$SZREG;

my $SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? "0xc0fff008" : "0xc0ff0000";

my ($inp,$out,$key,$Tbl,$s0,$s1,$s2,$s3)=($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7);

my ($i0,$i1,$i2,$i3)=($at,$t0,$t1,$t2);

my ($t0,$t1,$t2,$t3,$t4,$t5,$t6,$t7,$t8,$t9,$t10,$t11) = map("\$$_",(12..23));

my ($key0,$cnt)=($gp,$fp);

# instruction ordering is "stolen" from output from MIPSpro assembler

# invoked with -mips3 -O3 arguments...

$code.=<<___;

.align	5

.ent	_mips_AES_encrypt

_mips_AES_encrypt:

	.frame	$sp,0,$ra

	.set	reorder

	lw	$t0,0($key)

	lw	$t1,4($key)

	lw	$t2,8($key)

	lw	$t3,12($key)

	lw	$cnt,240($key)

	$PTR_ADD $key0,$key,16

	xor	$s0,$t0

	xor	$s1,$t1

	xor	$s2,$t2

	xor	$s3,$t3

	subu	$cnt,1

#if defined(__mips_smartmips)

	ext	$i0,$s1,16,8

.Loop_enc:

	ext	$i1,$s2,16,8

	ext	$i2,$s3,16,8

	ext	$i3,$s0,16,8

	lwxs	$t0,$i0($Tbl)		# Te1[s1>>16]

	ext	$i0,$s2,8,8

	lwxs	$t1,$i1($Tbl)		# Te1[s2>>16]

	ext	$i1,$s3,8,8

	lwxs	$t2,$i2($Tbl)		# Te1[s3>>16]

	ext	$i2,$s0,8,8

	lwxs	$t3,$i3($Tbl)		# Te1[s0>>16]

	ext	$i3,$s1,8,8

	lwxs	$t4,$i0($Tbl)		# Te2[s2>>8]

	ext	$i0,$s3,0,8

	lwxs	$t5,$i1($Tbl)		# Te2[s3>>8]

	ext	$i1,$s0,0,8

	lwxs	$t6,$i2($Tbl)		# Te2[s0>>8]

	ext	$i2,$s1,0,8

	lwxs	$t7,$i3($Tbl)		# Te2[s1>>8]

	ext	$i3,$s2,0,8

	lwxs	$t8,$i0($Tbl)		# Te3[s3]

	ext	$i0,$s0,24,8

	lwxs	$t9,$i1($Tbl)		# Te3[s0]

	ext	$i1,$s1,24,8

	lwxs	$t10,$i2($Tbl)		# Te3[s1]

	ext	$i2,$s2,24,8

	lwxs	$t11,$i3($Tbl)		# Te3[s2]

	ext	$i3,$s3,24,8

	rotr	$t0,$t0,8

	rotr	$t1,$t1,8

	rotr	$t2,$t2,8

	rotr	$t3,$t3,8

	rotr	$t4,$t4,16

	rotr	$t5,$t5,16

	rotr	$t6,$t6,16

	rotr	$t7,$t7,16

	xor	$t0,$t4

	lwxs	$t4,$i0($Tbl)		# Te0[s0>>24]

	xor	$t1,$t5

	lwxs	$t5,$i1($Tbl)		# Te0[s1>>24]

	xor	$t2,$t6

	lwxs	$t6,$i2($Tbl)		# Te0[s2>>24]

	xor	$t3,$t7

	lwxs	$t7,$i3($Tbl)		# Te0[s3>>24]

	rotr	$t8,$t8,24

	lw	$s0,0($key0)

	rotr	$t9,$t9,24

	lw	$s1,4($key0)

	rotr	$t10,$t10,24

	lw	$s2,8($key0)

	rotr	$t11,$t11,24

	lw	$s3,12($key0)

	xor	$t0,$t8

	xor	$t1,$t9

	xor	$t2,$t10

	xor	$t3,$t11

	xor	$t0,$t4

	xor	$t1,$t5

	xor	$t2,$t6

	xor	$t3,$t7

	subu	$cnt,1

	$PTR_ADD $key0,16

	xor	$s0,$t0

	xor	$s1,$t1

	xor	$s2,$t2

	xor	$s3,$t3

	.set	noreorder

	bnez	$cnt,.Loop_enc

	ext	$i0,$s1,16,8

	_xtr	$i0,$s1,16-2

#else

	_xtr	$i0,$s1,16-2

.Loop_enc:

	_xtr	$i1,$s2,16-2

	_xtr	$i2,$s3,16-2

	_xtr	$i3,$s0,16-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)

	lw	$t0,0($i0)		# Te1[s1>>16]

	_xtr	$i0,$s2,8-2

	lw	$t1,0($i1)		# Te1[s2>>16]

	_xtr	$i1,$s3,8-2

	lw	$t2,0($i2)		# Te1[s3>>16]

	_xtr	$i2,$s0,8-2

	lw	$t3,0($i3)		# Te1[s0>>16]

	_xtr	$i3,$s1,8-2

#else

	lwl	$t0,3($i0)		# Te1[s1>>16]

	lwl	$t1,3($i1)		# Te1[s2>>16]

	lwl	$t2,3($i2)		# Te1[s3>>16]

	lwl	$t3,3($i3)		# Te1[s0>>16]

	lwr	$t0,2($i0)		# Te1[s1>>16]

	_xtr	$i0,$s2,8-2

	lwr	$t1,2($i1)		# Te1[s2>>16]

	_xtr	$i1,$s3,8-2

	lwr	$t2,2($i2)		# Te1[s3>>16]

	_xtr	$i2,$s0,8-2

	lwr	$t3,2($i3)		# Te1[s0>>16]

	_xtr	$i3,$s1,8-2

#endif

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)

	rotr	$t0,$t0,8

	rotr	$t1,$t1,8

	rotr	$t2,$t2,8

	rotr	$t3,$t3,8

# if defined(_MIPSEL)

	lw	$t4,0($i0)		# Te2[s2>>8]

	_xtr	$i0,$s3,0-2

	lw	$t5,0($i1)		# Te2[s3>>8]

	_xtr	$i1,$s0,0-2

	lw	$t6,0($i2)		# Te2[s0>>8]

	_xtr	$i2,$s1,0-2

	lw	$t7,0($i3)		# Te2[s1>>8]

	_xtr	$i3,$s2,0-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

	lw	$t8,0($i0)		# Te3[s3]

	$PTR_INS $i0,$s0,2,8

	lw	$t9,0($i1)		# Te3[s0]

	$PTR_INS $i1,$s1,2,8

	lw	$t10,0($i2)		# Te3[s1]

	$PTR_INS $i2,$s2,2,8

	lw	$t11,0($i3)		# Te3[s2]

	$PTR_INS $i3,$s3,2,8

# else

	lw	$t4,0($i0)		# Te2[s2>>8]

	$PTR_INS $i0,$s3,2,8

	lw	$t5,0($i1)		# Te2[s3>>8]

	$PTR_INS $i1,$s0,2,8

	lw	$t6,0($i2)		# Te2[s0>>8]

	$PTR_INS $i2,$s1,2,8

	lw	$t7,0($i3)		# Te2[s1>>8]

	$PTR_INS $i3,$s2,2,8

	lw	$t8,0($i0)		# Te3[s3]

	_xtr	$i0,$s0,24-2

	lw	$t9,0($i1)		# Te3[s0]

	_xtr	$i1,$s1,24-2

	lw	$t10,0($i2)		# Te3[s1]

	_xtr	$i2,$s2,24-2

	lw	$t11,0($i3)		# Te3[s2]

	_xtr	$i3,$s3,24-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

# endif

	rotr	$t4,$t4,16

	rotr	$t5,$t5,16

	rotr	$t6,$t6,16

	rotr	$t7,$t7,16

	rotr	$t8,$t8,24

	rotr	$t9,$t9,24

	rotr	$t10,$t10,24

	rotr	$t11,$t11,24

#else

	lwl	$t4,2($i0)		# Te2[s2>>8]

	lwl	$t5,2($i1)		# Te2[s3>>8]

	lwl	$t6,2($i2)		# Te2[s0>>8]

	lwl	$t7,2($i3)		# Te2[s1>>8]

	lwr	$t4,1($i0)		# Te2[s2>>8]

	_xtr	$i0,$s3,0-2

	lwr	$t5,1($i1)		# Te2[s3>>8]

	_xtr	$i1,$s0,0-2

	lwr	$t6,1($i2)		# Te2[s0>>8]

	_xtr	$i2,$s1,0-2

	lwr	$t7,1($i3)		# Te2[s1>>8]

	_xtr	$i3,$s2,0-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

	lwl	$t8,1($i0)		# Te3[s3]

	lwl	$t9,1($i1)		# Te3[s0]

	lwl	$t10,1($i2)		# Te3[s1]

	lwl	$t11,1($i3)		# Te3[s2]

	lwr	$t8,0($i0)		# Te3[s3]

	_xtr	$i0,$s0,24-2

	lwr	$t9,0($i1)		# Te3[s0]

	_xtr	$i1,$s1,24-2

	lwr	$t10,0($i2)		# Te3[s1]

	_xtr	$i2,$s2,24-2

	lwr	$t11,0($i3)		# Te3[s2]

	_xtr	$i3,$s3,24-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

#endif

	xor	$t0,$t4

	lw	$t4,0($i0)		# Te0[s0>>24]

	xor	$t1,$t5

	lw	$t5,0($i1)		# Te0[s1>>24]

	xor	$t2,$t6

	lw	$t6,0($i2)		# Te0[s2>>24]

	xor	$t3,$t7

	lw	$t7,0($i3)		# Te0[s3>>24]

	xor	$t0,$t8

	lw	$s0,0($key0)

	xor	$t1,$t9

	lw	$s1,4($key0)

	xor	$t2,$t10

	lw	$s2,8($key0)

	xor	$t3,$t11

	lw	$s3,12($key0)

	xor	$t0,$t4

	xor	$t1,$t5

	xor	$t2,$t6

	xor	$t3,$t7

	subu	$cnt,1

	$PTR_ADD $key0,16

	xor	$s0,$t0

	xor	$s1,$t1

	xor	$s2,$t2

	xor	$s3,$t3

	.set	noreorder

	bnez	$cnt,.Loop_enc

	_xtr	$i0,$s1,16-2

#endif

	.set	reorder

	_xtr	$i1,$s2,16-2

	_xtr	$i2,$s3,16-2

	_xtr	$i3,$s0,16-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

	lbu	$t0,2($i0)		# Te4[s1>>16]

	_xtr	$i0,$s2,8-2

	lbu	$t1,2($i1)		# Te4[s2>>16]

	_xtr	$i1,$s3,8-2

	lbu	$t2,2($i2)		# Te4[s3>>16]

	_xtr	$i2,$s0,8-2

	lbu	$t3,2($i3)		# Te4[s0>>16]

	_xtr	$i3,$s1,8-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)

# if defined(_MIPSEL)

	lbu	$t4,2($i0)		# Te4[s2>>8]

	$PTR_INS $i0,$s0,2,8

	lbu	$t5,2($i1)		# Te4[s3>>8]

	$PTR_INS $i1,$s1,2,8

	lbu	$t6,2($i2)		# Te4[s0>>8]

	$PTR_INS $i2,$s2,2,8

	lbu	$t7,2($i3)		# Te4[s1>>8]

	$PTR_INS $i3,$s3,2,8

	lbu	$t8,2($i0)		# Te4[s0>>24]

	_xtr	$i0,$s3,0-2

	lbu	$t9,2($i1)		# Te4[s1>>24]

	_xtr	$i1,$s0,0-2

	lbu	$t10,2($i2)		# Te4[s2>>24]

	_xtr	$i2,$s1,0-2

	lbu	$t11,2($i3)		# Te4[s3>>24]

	_xtr	$i3,$s2,0-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

# else

	lbu	$t4,2($i0)		# Te4[s2>>8]

	_xtr	$i0,$s0,24-2

	lbu	$t5,2($i1)		# Te4[s3>>8]

	_xtr	$i1,$s1,24-2

	lbu	$t6,2($i2)		# Te4[s0>>8]

	_xtr	$i2,$s2,24-2

	lbu	$t7,2($i3)		# Te4[s1>>8]

	_xtr	$i3,$s3,24-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

	lbu	$t8,2($i0)		# Te4[s0>>24]

	$PTR_INS $i0,$s3,2,8

	lbu	$t9,2($i1)		# Te4[s1>>24]

	$PTR_INS $i1,$s0,2,8

	lbu	$t10,2($i2)		# Te4[s2>>24]

	$PTR_INS $i2,$s1,2,8

	lbu	$t11,2($i3)		# Te4[s3>>24]

	$PTR_INS $i3,$s2,2,8

# endif

	_ins	$t0,16

	_ins	$t1,16

	_ins	$t2,16

	_ins	$t3,16

	_ins2	$t0,$t4,8

	lbu	$t4,2($i0)		# Te4[s3]

	_ins2	$t1,$t5,8

	lbu	$t5,2($i1)		# Te4[s0]

	_ins2	$t2,$t6,8

	lbu	$t6,2($i2)		# Te4[s1]

	_ins2	$t3,$t7,8

	lbu	$t7,2($i3)		# Te4[s2]

	_ins2	$t0,$t8,24

	lw	$s0,0($key0)

	_ins2	$t1,$t9,24

	lw	$s1,4($key0)

	_ins2	$t2,$t10,24

	lw	$s2,8($key0)

	_ins2	$t3,$t11,24

	lw	$s3,12($key0)

	_ins2	$t0,$t4,0

	_ins2	$t1,$t5,0

	_ins2	$t2,$t6,0

	_ins2	$t3,$t7,0

#else

	lbu	$t4,2($i0)		# Te4[s2>>8]

	_xtr	$i0,$s0,24-2

	lbu	$t5,2($i1)		# Te4[s3>>8]

	_xtr	$i1,$s1,24-2

	lbu	$t6,2($i2)		# Te4[s0>>8]

	_xtr	$i2,$s2,24-2

	lbu	$t7,2($i3)		# Te4[s1>>8]

	_xtr	$i3,$s3,24-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

	lbu	$t8,2($i0)		# Te4[s0>>24]

	_xtr	$i0,$s3,0-2

	lbu	$t9,2($i1)		# Te4[s1>>24]

	_xtr	$i1,$s0,0-2

	lbu	$t10,2($i2)		# Te4[s2>>24]

	_xtr	$i2,$s1,0-2

	lbu	$t11,2($i3)		# Te4[s3>>24]

	_xtr	$i3,$s2,0-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

	_ins	$t0,16

	_ins	$t1,16

	_ins	$t2,16

	_ins	$t3,16

	_ins	$t4,8

	_ins	$t5,8

	_ins	$t6,8

	_ins	$t7,8

	xor	$t0,$t4

	lbu	$t4,2($i0)		# Te4[s3]

	xor	$t1,$t5

	lbu	$t5,2($i1)		# Te4[s0]

	xor	$t2,$t6

	lbu	$t6,2($i2)		# Te4[s1]

	xor	$t3,$t7

	lbu	$t7,2($i3)		# Te4[s2]

	_ins	$t8,24

	lw	$s0,0($key0)

	_ins	$t9,24

	lw	$s1,4($key0)

	_ins	$t10,24

	lw	$s2,8($key0)

	_ins	$t11,24

	lw	$s3,12($key0)

	xor	$t0,$t8

	xor	$t1,$t9

	xor	$t2,$t10

	xor	$t3,$t11

	_ins	$t4,0

	_ins	$t5,0

	_ins	$t6,0

	_ins	$t7,0

	xor	$t0,$t4

	xor	$t1,$t5

	xor	$t2,$t6

	xor	$t3,$t7

#endif

	xor	$s0,$t0

	xor	$s1,$t1

	xor	$s2,$t2

	xor	$s3,$t3

	jr	$ra

.end	_mips_AES_encrypt

.align	5

.globl	AES_encrypt

.ent	AES_encrypt

AES_encrypt:

	.frame	$sp,$FRAMESIZE,$ra

	.mask	$SAVED_REGS_MASK,-$SZREG

	.set	noreorder

___

$code.=<<___ if ($flavour =~ /o32/i);	# o32 PIC-ification

	.cpload	$pf

___

$code.=<<___;

	$PTR_SUB $sp,$FRAMESIZE

	$REG_S	$ra,$FRAMESIZE-1*$SZREG($sp)

	$REG_S	$fp,$FRAMESIZE-2*$SZREG($sp)

	$REG_S	$s11,$FRAMESIZE-3*$SZREG($sp)

	$REG_S	$s10,$FRAMESIZE-4*$SZREG($sp)

	$REG_S	$s9,$FRAMESIZE-5*$SZREG($sp)

	$REG_S	$s8,$FRAMESIZE-6*$SZREG($sp)

	$REG_S	$s7,$FRAMESIZE-7*$SZREG($sp)

	$REG_S	$s6,$FRAMESIZE-8*$SZREG($sp)

	$REG_S	$s5,$FRAMESIZE-9*$SZREG($sp)

	$REG_S	$s4,$FRAMESIZE-10*$SZREG($sp)

___

$code.=<<___ if ($flavour =~ /nubi/i);	# optimize non-nubi prologue

	$REG_S	\$15,$FRAMESIZE-11*$SZREG($sp)

	$REG_S	\$14,$FRAMESIZE-12*$SZREG($sp)

	$REG_S	\$13,$FRAMESIZE-13*$SZREG($sp)

	$REG_S	\$12,$FRAMESIZE-14*$SZREG($sp)

	$REG_S	$gp,$FRAMESIZE-15*$SZREG($sp)

___

$code.=<<___ if ($flavour !~ /o32/i);	# non-o32 PIC-ification

	.cplocal	$Tbl

	.cpsetup	$pf,$zero,AES_encrypt

___

$code.=<<___;

	.set	reorder

	$PTR_LA	$Tbl,AES_Te		# PIC-ified 'load address'

#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)

	lw	$s0,0($inp)

	lw	$s1,4($inp)

	lw	$s2,8($inp)

	lw	$s3,12($inp)

#else

	lwl	$s0,0+$MSB($inp)

	lwl	$s1,4+$MSB($inp)

	lwl	$s2,8+$MSB($inp)

	lwl	$s3,12+$MSB($inp)

	lwr	$s0,0+$LSB($inp)

	lwr	$s1,4+$LSB($inp)

	lwr	$s2,8+$LSB($inp)

	lwr	$s3,12+$LSB($inp)

#endif

	bal	_mips_AES_encrypt

#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)

	sw	$s0,0($out)

	sw	$s1,4($out)

	sw	$s2,8($out)

	sw	$s3,12($out)

#else

	swr	$s0,0+$LSB($out)

	swr	$s1,4+$LSB($out)

	swr	$s2,8+$LSB($out)

	swr	$s3,12+$LSB($out)

	swl	$s0,0+$MSB($out)

	swl	$s1,4+$MSB($out)

	swl	$s2,8+$MSB($out)

	swl	$s3,12+$MSB($out)

#endif

	.set	noreorder

	$REG_L	$ra,$FRAMESIZE-1*$SZREG($sp)

	$REG_L	$fp,$FRAMESIZE-2*$SZREG($sp)

	$REG_L	$s11,$FRAMESIZE-3*$SZREG($sp)

	$REG_L	$s10,$FRAMESIZE-4*$SZREG($sp)

	$REG_L	$s9,$FRAMESIZE-5*$SZREG($sp)

	$REG_L	$s8,$FRAMESIZE-6*$SZREG($sp)

	$REG_L	$s7,$FRAMESIZE-7*$SZREG($sp)

	$REG_L	$s6,$FRAMESIZE-8*$SZREG($sp)

	$REG_L	$s5,$FRAMESIZE-9*$SZREG($sp)

	$REG_L	$s4,$FRAMESIZE-10*$SZREG($sp)

___

$code.=<<___ if ($flavour =~ /nubi/i);

	$REG_L	\$15,$FRAMESIZE-11*$SZREG($sp)

	$REG_L	\$14,$FRAMESIZE-12*$SZREG($sp)

	$REG_L	\$13,$FRAMESIZE-13*$SZREG($sp)

	$REG_L	\$12,$FRAMESIZE-14*$SZREG($sp)

	$REG_L	$gp,$FRAMESIZE-15*$SZREG($sp)

___

$code.=<<___;

	jr	$ra

	$PTR_ADD $sp,$FRAMESIZE

.end	AES_encrypt

___

$code.=<<___;

.align	5

.ent	_mips_AES_decrypt

_mips_AES_decrypt:

	.frame	$sp,0,$ra

	.set	reorder

	lw	$t0,0($key)

	lw	$t1,4($key)

	lw	$t2,8($key)

	lw	$t3,12($key)

	lw	$cnt,240($key)

	$PTR_ADD $key0,$key,16

	xor	$s0,$t0

	xor	$s1,$t1

	xor	$s2,$t2

	xor	$s3,$t3

	subu	$cnt,1

#if defined(__mips_smartmips)

	ext	$i0,$s3,16,8

.Loop_dec:

	ext	$i1,$s0,16,8

	ext	$i2,$s1,16,8

	ext	$i3,$s2,16,8

	lwxs	$t0,$i0($Tbl)		# Td1[s3>>16]

	ext	$i0,$s2,8,8

	lwxs	$t1,$i1($Tbl)		# Td1[s0>>16]

	ext	$i1,$s3,8,8

	lwxs	$t2,$i2($Tbl)		# Td1[s1>>16]

	ext	$i2,$s0,8,8

	lwxs	$t3,$i3($Tbl)		# Td1[s2>>16]

	ext	$i3,$s1,8,8

	lwxs	$t4,$i0($Tbl)		# Td2[s2>>8]

	ext	$i0,$s1,0,8

	lwxs	$t5,$i1($Tbl)		# Td2[s3>>8]

	ext	$i1,$s2,0,8

	lwxs	$t6,$i2($Tbl)		# Td2[s0>>8]

	ext	$i2,$s3,0,8

	lwxs	$t7,$i3($Tbl)		# Td2[s1>>8]

	ext	$i3,$s0,0,8

	lwxs	$t8,$i0($Tbl)		# Td3[s1]

	ext	$i0,$s0,24,8

	lwxs	$t9,$i1($Tbl)		# Td3[s2]

	ext	$i1,$s1,24,8

	lwxs	$t10,$i2($Tbl)		# Td3[s3]

	ext	$i2,$s2,24,8

	lwxs	$t11,$i3($Tbl)		# Td3[s0]

	ext	$i3,$s3,24,8

	rotr	$t0,$t0,8

	rotr	$t1,$t1,8

	rotr	$t2,$t2,8

	rotr	$t3,$t3,8

	rotr	$t4,$t4,16

	rotr	$t5,$t5,16

	rotr	$t6,$t6,16

	rotr	$t7,$t7,16

	xor	$t0,$t4

	lwxs	$t4,$i0($Tbl)		# Td0[s0>>24]

	xor	$t1,$t5

	lwxs	$t5,$i1($Tbl)		# Td0[s1>>24]

	xor	$t2,$t6

	lwxs	$t6,$i2($Tbl)		# Td0[s2>>24]

	xor	$t3,$t7

	lwxs	$t7,$i3($Tbl)		# Td0[s3>>24]

	rotr	$t8,$t8,24

	lw	$s0,0($key0)

	rotr	$t9,$t9,24

	lw	$s1,4($key0)

	rotr	$t10,$t10,24

	lw	$s2,8($key0)

	rotr	$t11,$t11,24

	lw	$s3,12($key0)

	xor	$t0,$t8

	xor	$t1,$t9

	xor	$t2,$t10

	xor	$t3,$t11

	xor	$t0,$t4

	xor	$t1,$t5

	xor	$t2,$t6

	xor	$t3,$t7

	subu	$cnt,1

	$PTR_ADD $key0,16

	xor	$s0,$t0

	xor	$s1,$t1

	xor	$s2,$t2

	xor	$s3,$t3

	.set	noreorder

	bnez	$cnt,.Loop_dec

	ext	$i0,$s3,16,8

	_xtr	$i0,$s3,16-2

#else

	_xtr	$i0,$s3,16-2

.Loop_dec:

	_xtr	$i1,$s0,16-2

	_xtr	$i2,$s1,16-2

	_xtr	$i3,$s2,16-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)

	lw	$t0,0($i0)		# Td1[s3>>16]

	_xtr	$i0,$s2,8-2

	lw	$t1,0($i1)		# Td1[s0>>16]

	_xtr	$i1,$s3,8-2

	lw	$t2,0($i2)		# Td1[s1>>16]

	_xtr	$i2,$s0,8-2

	lw	$t3,0($i3)		# Td1[s2>>16]

	_xtr	$i3,$s1,8-2

#else

	lwl	$t0,3($i0)		# Td1[s3>>16]

	lwl	$t1,3($i1)		# Td1[s0>>16]

	lwl	$t2,3($i2)		# Td1[s1>>16]

	lwl	$t3,3($i3)		# Td1[s2>>16]

	lwr	$t0,2($i0)		# Td1[s3>>16]

	_xtr	$i0,$s2,8-2

	lwr	$t1,2($i1)		# Td1[s0>>16]

	_xtr	$i1,$s3,8-2

	lwr	$t2,2($i2)		# Td1[s1>>16]

	_xtr	$i2,$s0,8-2

	lwr	$t3,2($i3)		# Td1[s2>>16]

	_xtr	$i3,$s1,8-2

#endif

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl

	$PTR_ADD $i1,$Tbl

	$PTR_ADD $i2,$Tbl

	$PTR_ADD $i3,$Tbl

#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)

	rotr	$t0,$t0,8

	rotr	$t1,$t1,8

	rotr	$t2,$t2,8

	rotr	$t3,$t3,8

# if defined(_MIPSEL)

	lw	$t4,0($i0)		# Td2[s2>>8]

	_xtr	$i0,$s1,0-2

	lw	$t5,0($i1)		# Td2[s3>>8]

	_xtr	$i1,$s2,0-2

	lw	$t6,0($i2)		# Td2[s0>>8]

	_xtr	$i2,$s3,0-2

	lw	$t7,0($i3)		# Td2[s1>>8]

	_xtr	$i3,$s0,0-2

	and	$i0,0x3fc

	and	$i1,0x3fc

	and	$i2,0x3fc

	and	$i3,0x3fc

	$PTR_ADD $i0,$Tbl