// Copyright(c) 2017-2020, Intel Corporation

//

// Redistribution  and  use  in source  and  binary  forms,  with  or  without

// modification, are permitted provided that the following conditions are met:

//

// * Redistributions of  source code  must retain the  above copyright notice,

//   this list of conditions and the following disclaimer.

// * Redistributions in binary form must reproduce the above copyright notice,

//   this list of conditions and the following disclaimer in the documentation

//   and/or other materials provided with the distribution.

// * Neither the name  of Intel Corporation  nor the names of its contributors

//   may be used to  endorse or promote  products derived  from this  software

//   without specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE

// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE

// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR

// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF

// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS

// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN

// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)

// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE

// POSSIBILITY OF SUCH DAMAGE.

#ifdef HAVE_CONFIG_H

#include <config.h>

#endif // HAVE_CONFIG_H

#define _GNU_SOURCE

#include <pthread.h>

#include <glob.h>

#include <dirent.h>

#include <unistd.h>

#include <string.h>

#include <stdlib.h>

#include <stdio.h>

#include <fcntl.h>

#include <errno.h>

#include <sys/stat.h>

#include <regex.h>

#undef _GNU_SOURCE

#include <opae/types.h>

#include <opae/log.h>

#include <opae/types_enum.h>

#include "types_int.h"

#include "sysfs_int.h"

#include "common_int.h"

// substring that identifies a sysfs directory as the FME device.

#define FPGA_SYSFS_FME "fme"

#define FPGA_SYSFS_FME_LEN 3

// substring that identifies a sysfs directory as the AFU device.

#define FPGA_SYSFS_PORT "port"

#define FPGA_SYSFS_PORT_LEN 4

#define OPAE_KERNEL_DRIVERS 2

typedef struct _sysfs_formats {

	const char *sysfs_class_path;

	const char *sysfs_pcidrv_fpga;

	const char *sysfs_device_fmt;

	const char *sysfs_region_fmt;

	const char *sysfs_device_glob;

	const char *sysfs_fme_glob;

	const char *sysfs_port_glob;

	const char *sysfs_compat_id;

	const char *sysfs_fme_pwr_glob;

	const char *sysfs_fme_temp_glob;

	const char *sysfs_fme_perf_glob;

	const char *sysfs_port_err;

	const char *sysfs_port_err_clear;

	const char *sysfs_bmc_glob;

	const char *sysfs_max10_glob;

} sysfs_formats;

static sysfs_formats sysfs_path_table[OPAE_KERNEL_DRIVERS] = {

	// upstream driver sysfs formats

	{.sysfs_class_path = "/sys/class/fpga_region",

	 .sysfs_pcidrv_fpga = "fpga_region",

	 .sysfs_device_fmt = "(region)([0-9])+",

	 .sysfs_region_fmt = "dfl-(fme|port)\\.([0-9]+)",

	 .sysfs_device_glob = "region*",

	 .sysfs_fme_glob = "dfl-fme.*",

	 .sysfs_port_glob = "dfl-port.*",

	 .sysfs_compat_id = "/dfl-fme-region.*/fpga_region/region*/compat_id",

	 .sysfs_fme_temp_glob = "hwmon/hwmon*/temp*_*",

	 .sysfs_fme_pwr_glob = "hwmon/hwmon*/power*_*",

	 .sysfs_fme_perf_glob = "*perf",

	 .sysfs_port_err = "errors/errors",

	 .sysfs_port_err_clear = "errors/errors",

	 .sysfs_bmc_glob = "avmmi-bmc.*/bmc_info",

	 .sysfs_max10_glob = "spi-*/spi_master/spi*/spi*.*"

	},

	// intel driver sysfs formats

	{.sysfs_class_path = "/sys/class/fpga",

	 .sysfs_pcidrv_fpga = "fpga",

	 .sysfs_device_fmt = "(intel-fpga-dev\\.)([0-9]+)",

	 .sysfs_region_fmt = "intel-fpga-(fme|port)\\.([0-9]+)",

	 .sysfs_device_glob = "intel-fpga-dev.*",

	 .sysfs_fme_glob = "intel-fpga-fme.*",

	 .sysfs_port_glob = "intel-fpga-port.*",

	 .sysfs_compat_id = "pr/interface_id",

	 .sysfs_fme_temp_glob = "thermal_mgmt/*",

	 .sysfs_fme_pwr_glob = "power_mgmt/*",

	 .sysfs_fme_perf_glob = "*perf",

	 .sysfs_port_err = "errors/errors",

	 .sysfs_port_err_clear = "errors/clear",

	 .sysfs_bmc_glob = "avmmi-bmc.*/bmc_info",

	 .sysfs_max10_glob = "spi-*/spi_master/spi*/spi*.*"

	} };

// RE_MATCH_STRING is index 0 in a regex match array

#define RE_MATCH_STRING 0

// RE_DEVICE_GROUPS is the matching groups for the device regex in the

// sysfs_path_table above.

// Currently this only has three groups:

// * The matching string itself - group 0

// * The prefix (either 'region' or 'intel-fpga-dev.') - group 1

// * The number - group 2

// These indices are used when indexing a regex match object

#define RE_DEVICE_GROUPS 3

#define RE_DEVICE_GROUP_PREFIX 1

#define RE_DEVICE_GROUP_NUM 2

// RE_REGION_GROUPS is the matching groups for the region regex in the

// sysfs_path_table above.

// Currently this only has three groups:

// * The matching string itself - group 0

// * The type ('fme' or 'port') - group 1

// * The number - group 2

// These indices are used when indexing a regex match object

#define RE_REGION_GROUPS 3

#define RE_REGION_GROUP_TYPE 1

#define RE_REGION_GROUP_NUM 2

static sysfs_formats *_sysfs_format_ptr;

static uint32_t _sysfs_device_count;

/* mutex to protect sysfs device data structures */

pthread_mutex_t _sysfs_device_lock = PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP;

#define SYSFS_FORMAT(s) (_sysfs_format_ptr ? _sysfs_format_ptr->s : NULL)

#define SYSFS_MAX_DEVICES 128

static sysfs_fpga_device _devices[SYSFS_MAX_DEVICES];

#define PCIE_PATH_PATTERN "([0-9a-fA-F]{4}):([0-9a-fA-F]{2}):([0-9]{2})\\.([0-9])/fpga"

#define PCIE_PATH_PATTERN_GROUPS 5

#define PARSE_MATCH_INT(_p, _m, _v, _b, _l)                                    \

	do {                                                                   \

		errno = 0;                                                     \

		_v = strtoul(_p + _m.rm_so, NULL, _b);                         \

		if (errno) {                                                   \

			OPAE_MSG("error parsing int");                         \

			goto _l;                                               \

		}                                                              \

	} while (0)

#define FREE_IF(var)                                                           \

	do {                                                                   \

		if (var) {                                                     \

			free(var);                                             \

			var = NULL;                                            \

		}                                                              \

	} while (0)

STATIC int parse_pcie_info(sysfs_fpga_device *device, char *buffer)

{

	char err[128] = {0};

	regex_t re;

	regmatch_t matches[PCIE_PATH_PATTERN_GROUPS] = { {0} };

	int res = FPGA_EXCEPTION;

	int reg_res = regcomp(&re, PCIE_PATH_PATTERN, REG_EXTENDED | REG_ICASE);

	if (reg_res) {

		OPAE_ERR("Error compling regex");

		return FPGA_EXCEPTION;

	}

	reg_res = regexec(&re, buffer, PCIE_PATH_PATTERN_GROUPS, matches, 0);

	if (reg_res) {

		regerror(reg_res, &re, err, 128);

		OPAE_ERR("Error executing regex: %s", err);

		res = FPGA_EXCEPTION;

		goto out;

	} else {

		PARSE_MATCH_INT(buffer, matches[1], device->segment, 16, out);

		PARSE_MATCH_INT(buffer, matches[2], device->bus, 16, out);

		PARSE_MATCH_INT(buffer, matches[3], device->device, 16, out);

		PARSE_MATCH_INT(buffer, matches[4], device->function, 10, out);

	}

	res = FPGA_OK;

out:

	regfree(&re);

	return res;

}

int sysfs_parse_attribute64(const char *root, const char *attr_path, uint64_t *value)

{

	uint64_t pg_size = (uint64_t)sysconf(_SC_PAGE_SIZE);

	char path[SYSFS_PATH_MAX] = { 0, };

	char buffer[pg_size];

	int fd = -1;

	ssize_t bytes_read = 0;

	snprintf(path, sizeof(path),

		 "%s/%s", root, attr_path);

	fd = open(path, O_RDONLY);

	if (fd < 0) {

		OPAE_MSG("Error opening %s: %s", path, strerror(errno));

		return FPGA_EXCEPTION;

	}

	bytes_read = eintr_read(fd, buffer, pg_size);

	if (bytes_read < 0) {

		OPAE_ERR("Error reading from %s: %s", path,

			 strerror(errno));

		close(fd);

		return FPGA_EXCEPTION;

	}

	*value = strtoull(buffer, NULL, 0);

	close(fd);

	return FPGA_OK;

}

STATIC int parse_device_vendor_id(sysfs_fpga_device *device)

{

	uint64_t value = 0;

	int res = sysfs_parse_attribute64(device->sysfs_path, "device/device", &value);

	if (res) {

		OPAE_MSG("Error parsing device_id for device: %s",

			 device->sysfs_path);

		return res;

	}

	device->device_id = value;

	res = sysfs_parse_attribute64(device->sysfs_path, "device/vendor", &value);

	if (res) {

		OPAE_ERR("Error parsing vendor_id for device: %s",

			 device->sysfs_path);

		return res;

	}

	device->vendor_id = value;

	return FPGA_OK;

}

STATIC sysfs_fpga_region *make_region(sysfs_fpga_device *device, char *name,

				      int num, fpga_objtype type)

{

	size_t len;

	sysfs_fpga_region *region = malloc(sizeof(sysfs_fpga_region));

	if (region == NULL) {

		OPAE_ERR("error creating region");

		return NULL;

	}

	region->device = device;

	region->type = type;

	region->number = num;

	// sysfs path of region is sysfs path of device + / + name

	if (snprintf(region->sysfs_path, SYSFS_PATH_MAX,

		     "%s/%s", device->sysfs_path, name) < 0) {

		free(region);

		OPAE_ERR("snprintf buffer overflow");

		return NULL;

	}

	len = strnlen(name, SYSFS_PATH_MAX - 1);

	memcpy(region->sysfs_name, name, len);

	region->sysfs_name[len] = '\0';

	return region;

}

/**

 * @brief Match a device node given a format pattern

 *

 * @param fmt A regex pattern for the device node

 * @param inpstr A sysfs path to a potential device node

 * @param(out) prefix[] A prefix string for the device node

 * @param prefix_len capacity of prefix (max length)

 * @param(out) num The sysfs number encoded in the name

 *

 * @note fmt is expected to be a regex pattern in our sysfs_format_table

 *       Matching input strings could could look like:

 *       * region0 where 'region' is the prefix and 0 is the num

 *       * intel-fpga-dev.0 where 'intel-fpga-dev.' is the prefix and 0 is the

 *       num

 *

 *

 * @return FPGA_OK if a match is found, FPGA_NOT_FOUND it no match is found,

 *         FPGA_EXCEPTION if an error is encountered

 */

STATIC fpga_result re_match_device(const char *fmt, char *inpstr, char prefix[],

				   size_t prefix_len, int *num)

{

	int reg_res = 0;

	fpga_result res = FPGA_EXCEPTION;

	regmatch_t matches[RE_DEVICE_GROUPS];

	char err[128];

	char *ptr = NULL;

	char *end = NULL;

	regex_t re;

	ASSERT_NOT_NULL(fmt);

	ASSERT_NOT_NULL(inpstr);

	ASSERT_NOT_NULL(prefix);

	ASSERT_NOT_NULL(num);

	reg_res = regcomp(&re, fmt, REG_EXTENDED);

	if (reg_res) {

		regerror(reg_res, &re, err, sizeof(err));

		OPAE_ERR("Error compiling regex: %s", err);

		return FPGA_EXCEPTION;

	}

	reg_res = regexec(&re, inpstr, RE_DEVICE_GROUPS, matches, 0);

	if (reg_res) {

		return FPGA_NOT_FOUND;

	}

	ptr = inpstr + matches[RE_DEVICE_GROUP_PREFIX].rm_so;

	end = inpstr + matches[RE_DEVICE_GROUP_PREFIX].rm_eo;

	if ((size_t)(end - ptr) >= prefix_len) {

		OPAE_ERR("Regex result too long");

		res = FPGA_EXCEPTION;

		goto out_free;

	}

	strncpy(prefix, ptr, end - ptr);

	*(prefix + (end - ptr)) = '\0';

	ptr = inpstr + matches[RE_DEVICE_GROUP_NUM].rm_so;

	errno = 0;

	*num = strtoul(ptr, NULL, 10);

	if (errno) {

		OPAE_ERR("Error parsing number: %s", inpstr);

		goto out_free;

	}

	res = FPGA_OK;

out_free:

	regfree(&re);

	return res;

}

/**

 * @brief Match a device node given a format pattern

 *

 * @param fmt A regex pattern for the device node

 * @param inpstr A sysfs path to a potential device node

 * @param(out) type[] A type string for the device node

 * @param type_len capacity of type (max length)

 * @param(out) num The sysfs number encoded in the name

 *

 * @note fmt is expected to be a regex pattern in our sysfs_format_table

 *       Matching input strings could could look like:

 *       * dfl-fme.0 where 'fme' is the type and 0 is the num

 *       * dfl-port.1 where 'port' is the type and 1 is the num

 *       * intel-fpga-fme.0 where 'fme' is the type and 0 is the num

 *       * intel-fpga-port.1 where 'port' is the type and 1 is the num

 *

 *

 * @return FPGA_OK if a match is found, FPGA_NOT_FOUND it no match is found,

 *         FPGA_EXCEPTION if an error is encountered

 */

STATIC fpga_result re_match_region(const char *fmt, char *inpstr, char type[],

				   size_t type_len, int *num)

{

	int reg_res = 0;

	fpga_result res = FPGA_EXCEPTION;

	regmatch_t matches[RE_REGION_GROUPS];

	char err[128];

	char *ptr = NULL;

	char *end = NULL;

	regex_t re;

	ASSERT_NOT_NULL(fmt);

	ASSERT_NOT_NULL(inpstr);

	ASSERT_NOT_NULL(type);

	ASSERT_NOT_NULL(num);

	reg_res = regcomp(&re, fmt, REG_EXTENDED);

	if (reg_res) {

		regerror(reg_res, &re, err, sizeof(err));

		OPAE_ERR("Error compiling regex: %s", err);

		return FPGA_EXCEPTION;

	}

	reg_res = regexec(&re, inpstr, RE_REGION_GROUPS, matches, 0);

	if (reg_res) {

		res = FPGA_NOT_FOUND;

		goto out_free;

	}

	ptr = inpstr + matches[RE_REGION_GROUP_TYPE].rm_so;

	end = inpstr + matches[RE_REGION_GROUP_TYPE].rm_eo;

	if ((size_t)(end - ptr) >= type_len) {

		OPAE_ERR("Error copying type from string: %s", inpstr);

		goto out_free;

	}

	strncpy(type, ptr, end - ptr);

	*(type + (end - ptr)) = '\0';

	ptr = inpstr + matches[RE_REGION_GROUP_NUM].rm_so;

	errno = 0;

	*num = strtoul(ptr, NULL, 10);

	if (errno) {

		OPAE_ERR("Error parsing number: %s", inpstr);

		goto out_free;

	}

	res = FPGA_OK;

out_free:

	regfree(&re);

	return res;

}

STATIC int find_regions(sysfs_fpga_device *device)

{

	int num = -1;

	char type[8];

	fpga_result res = FPGA_OK;

	fpga_result match_res = FPGA_NOT_FOUND;

	fpga_objtype region_type = FPGA_DEVICE;

	sysfs_fpga_region **region_ptr = NULL;

	struct dirent *dirent = NULL;

	DIR *dir = opendir(device->sysfs_path);

	if (!dir) {

		OPAE_ERR("failed to open device path: %s", device->sysfs_path);

		return FPGA_EXCEPTION;

	}

	while ((dirent = readdir(dir)) != NULL) {

		res = FPGA_OK;

		if (!strcmp(dirent->d_name, "."))

			continue;

		if (!strcmp(dirent->d_name, ".."))

			continue;

		match_res = re_match_region(SYSFS_FORMAT(sysfs_region_fmt),

					    dirent->d_name, type, sizeof(type),

					    &num);

		if (match_res == FPGA_OK) {

			if (!strncmp(FPGA_SYSFS_FME, type,

				     FPGA_SYSFS_FME_LEN)) {

				region_type = FPGA_DEVICE;

				region_ptr = &device->fme;

			} else if (!strncmp(FPGA_SYSFS_PORT, type,

					    FPGA_SYSFS_PORT_LEN)) {

				region_type = FPGA_ACCELERATOR;

				region_ptr = &device->port;

			}

			if (region_ptr)

				*region_ptr = make_region(device,

				dirent->d_name, num, region_type);

			region_ptr = NULL;

		} else if (match_res != FPGA_NOT_FOUND) {

			res = match_res;

			break;

		}

	}

	if (dir)

		closedir(dir);

	if (!device->fme && !device->port) {

		OPAE_ERR("did not find fme/port in device: %s", device->sysfs_path);

		return FPGA_NOT_FOUND;

	}

	return res;

}

STATIC int make_device(sysfs_fpga_device *device, const char *sysfs_class_fpga,

		       char *dir_name, int num)

{

	int res = FPGA_OK;

	char buffer[SYSFS_PATH_MAX] = { 0, };

	ssize_t sym_link_len = 0;

	size_t len;

	if (snprintf(device->sysfs_path, SYSFS_PATH_MAX,

		     "%s/%s", sysfs_class_fpga, dir_name) < 0) {

		OPAE_ERR("snprintf buffer overflow");

		return FPGA_EXCEPTION;

	}

	len = strnlen(dir_name, SYSFS_PATH_MAX - 1);

	memcpy(device->sysfs_name, dir_name, len);

	device->sysfs_name[len] = '\0';

	sym_link_len = readlink(device->sysfs_path, buffer, SYSFS_PATH_MAX);

	if (sym_link_len < 0) {

		OPAE_ERR("Error reading sysfs link: %s", device->sysfs_path);

		return FPGA_EXCEPTION;

	}

	device->number = num;

	res = parse_pcie_info(device, buffer);

	if (res) {

		OPAE_ERR("Could not parse symlink");

		return res;

	}

	res = parse_device_vendor_id(device);

	if (res) {

		OPAE_MSG("Could not parse vendor/device id");

		return res;

	}

	return find_regions(device);

}

STATIC int sysfs_device_destroy(sysfs_fpga_device *device)

{

	ASSERT_NOT_NULL(device);

	if (device->fme) {

		free(device->fme);

		device->fme = NULL;

	}

	if (device->port) {

		free(device->port);

		device->port = NULL;

	}

	return FPGA_OK;

}

int sysfs_device_count(void)

{

	int res = 0, count = 0;

	if (!opae_mutex_lock(res, &_sysfs_device_lock)) {

		count = _sysfs_device_count;

	}

	if (opae_mutex_unlock(res, &_sysfs_device_lock)) {

		count = 0;

	}

	return count;

}

fpga_result sysfs_foreach_device(device_cb cb, void *context)

{

	uint32_t i = 0;

	int res = 0;

	fpga_result result = FPGA_OK;

	if (opae_mutex_lock(res, &_sysfs_device_lock)) {

		return FPGA_EXCEPTION;

	}

	result = sysfs_finalize();

	if (result) {

		goto out_unlock;

	}

	result = sysfs_initialize();

	if (result) {

		goto out_unlock;

	}

	for (; i < _sysfs_device_count; ++i) {

		result = cb(&_devices[i], context);

		if (result) {

			goto out_unlock;

		}

	}

out_unlock:

	opae_mutex_unlock(res, &_sysfs_device_lock);

	return result;

}

int sysfs_initialize(void)

{

	int stat_res = -1;

	int res = FPGA_OK;

	uint32_t i = 0;

	struct stat st;

	DIR *dir = NULL;

	struct dirent *dirent = NULL;

	int num = -1;

	char prefix[64] = {0};

	for (i = 0; i < OPAE_KERNEL_DRIVERS; ++i) {

		errno = 0;

		stat_res = stat(sysfs_path_table[i].sysfs_class_path, &st);

		if (!stat_res) {

			_sysfs_format_ptr = &sysfs_path_table[i];

			break;

		}

		if (errno != ENOENT) {

			OPAE_ERR("Error while inspecting sysfs: %s",

				 strerror(errno));

			return FPGA_EXCEPTION;

		}

	}

	if (i == OPAE_KERNEL_DRIVERS) {

		OPAE_ERR(

			"No valid sysfs class files found - a suitable driver may not be loaded");

		return FPGA_NO_DRIVER;

	}

	_sysfs_device_count = 0;

	const char *sysfs_class_fpga = SYSFS_FORMAT(sysfs_class_path);

	if (!sysfs_class_fpga) {

		OPAE_ERR("Invalid fpga class path: %s", sysfs_class_fpga);

		res = FPGA_EXCEPTION;

		goto out_free;

	}

	// open the root sysfs class directory

	// look in the directory and get device objects

	dir = opendir(sysfs_class_fpga);

	if (!dir) {

		OPAE_MSG("failed to open device path: %s", sysfs_class_fpga);

		res = FPGA_EXCEPTION;

		goto out_free;

	}

	while ((dirent = readdir(dir))) {

		if (!strcmp(dirent->d_name, "."))

			continue;

		if (!strcmp(dirent->d_name, ".."))

			continue;

		res = re_match_device(SYSFS_FORMAT(sysfs_device_fmt),

				      dirent->d_name, prefix, sizeof(prefix),

				      &num);

		if (res == FPGA_OK) {

			// increment our device count after filling out details

			// of the discovered device in our _devices array

			if (opae_mutex_lock(res, &_sysfs_device_lock)) {

				goto out_free;

			}

			if (make_device(&_devices[_sysfs_device_count++],

					sysfs_class_fpga, dirent->d_name,

					num)) {

				OPAE_MSG("Error processing device: %s",

					 dirent->d_name);

				_sysfs_device_count--;

			}

			if (opae_mutex_unlock(res, &_sysfs_device_lock)) {

				goto out_free;

			}

		}

	}

	if (!_sysfs_device_count) {

		OPAE_ERR("Error discovering fpga devices");

		res = FPGA_NO_DRIVER;

	}

out_free:

	if (dir)

		closedir(dir);

	return res;

}

int sysfs_finalize(void)

{

	uint32_t i = 0;

	int res = 0;

	if (opae_mutex_lock(res, &_sysfs_device_lock)) {

		OPAE_ERR("Error locking mutex");

		return FPGA_EXCEPTION;

	}

	for (; i < _sysfs_device_count; ++i) {

		sysfs_device_destroy(&_devices[i]);

	}

	_sysfs_device_count = 0;

	_sysfs_format_ptr = NULL;

	if (opae_mutex_unlock(res, &_sysfs_device_lock)) {

		OPAE_ERR("Error unlocking mutex");

		return FPGA_EXCEPTION;

	}

	return FPGA_OK;

}

const sysfs_fpga_device *sysfs_get_device(size_t num)

{

	const sysfs_fpga_device *ptr = NULL;

	int res = 0;

	if (!opae_mutex_lock(res, &_sysfs_device_lock)) {

		if (num >= _sysfs_device_count) {

			OPAE_ERR("No such device with index: %d", num);

		} else {

			ptr = &_devices[num];

		}

		if (opae_mutex_unlock(res, &_sysfs_device_lock)) {

			ptr = NULL;

		}

	}

	return ptr;

}

fpga_result sysfs_get_interface_id(fpga_token token, fpga_guid guid)

{

	fpga_result res = FPGA_OK;

	char path[SYSFS_PATH_MAX];

	struct _fpga_token *_token = (struct _fpga_token *)token;

	ASSERT_NOT_NULL(_token);

	res = cat_token_sysfs_path(path, token, SYSFS_FORMAT(sysfs_compat_id));

	if (res) {

		return res;

	}

	res = opae_glob_path(path, SYSFS_PATH_MAX - 1);

	if (res) {

		return res;

	}

	return sysfs_read_guid(path, guid);

}

fpga_result sysfs_get_fme_pwr_path(fpga_token token, char *sysfs_pwr)

{

	fpga_result res = FPGA_OK;

	struct _fpga_token *_token = (struct _fpga_token *)token;

	ASSERT_NOT_NULL(_token);

	if (sysfs_pwr == NULL) {

		OPAE_ERR("Invalid input parameters");

		return FPGA_INVALID_PARAM;

	}

	res = cat_token_sysfs_path(sysfs_pwr, token, SYSFS_FORMAT(sysfs_fme_pwr_glob));

	if (res != FPGA_OK) {

		return res;

	}

	// check for path is valid

	res = check_sysfs_path_is_valid(sysfs_pwr);

	if (res != FPGA_OK) {

		OPAE_MSG("Invalid path %s", sysfs_pwr);

		return res;

	}

	return res;

}

fpga_result sysfs_get_fme_temp_path(fpga_token token, char *sysfs_temp)

{

	fpga_result res = FPGA_OK;

	struct _fpga_token *_token = (struct _fpga_token *)token;

	ASSERT_NOT_NULL(_token);

	if (sysfs_temp == NULL) {

		OPAE_ERR("Invalid input parameters");

		return FPGA_INVALID_PARAM;

	}

	res = cat_token_sysfs_path(sysfs_temp, token, SYSFS_FORMAT(sysfs_fme_temp_glob));

	if (res != FPGA_OK) {

		return res;

	}

	// check for path is valid

	res = check_sysfs_path_is_valid(sysfs_temp);

	if (res != FPGA_OK) {

		OPAE_MSG("Invalid path %s", sysfs_temp);

		return res;

	}

	return res;

}

fpga_result sysfs_get_fme_perf_path(fpga_token token, char *sysfs_perf)

{

	fpga_result res = FPGA_OK;

	struct _fpga_token *_token = (struct _fpga_token *)token;

	ASSERT_NOT_NULL(_token);

	if (sysfs_perf == NULL) {

		OPAE_ERR("Invalid input parameters");

		return FPGA_INVALID_PARAM;

	}

	res = cat_token_sysfs_path(sysfs_perf, token, SYSFS_FORMAT(sysfs_fme_perf_glob));

	if (res != FPGA_OK) {

		return res;

	}

	// check for path is valid

	res = check_sysfs_path_is_valid(sysfs_perf);

	if (res != FPGA_OK) {

		OPAE_MSG("Invalid path %s", sysfs_perf);

		return res;

	}

	return res;

}

fpga_result sysfs_get_port_error_path(fpga_handle handle, char *sysfs_port_error)

{

	fpga_result result = FPGA_OK;

	char sysfs_path[SYSFS_PATH_MAX] = { 0, };

	if (sysfs_port_error == NULL) {

		OPAE_ERR("Invalid input parameters");

		return FPGA_INVALID_PARAM;

	}

	result = get_port_sysfs(handle, sysfs_path);

	if (result != FPGA_OK) {

		OPAE_ERR("Failed to get port syfs path");

		return result;

	}

	if (!SYSFS_FORMAT(sysfs_port_err)) {

		OPAE_ERR("_sysfs_format_ptr is not set.");

		return FPGA_EXCEPTION;

	}

	if (snprintf(sysfs_port_error, SYSFS_PATH_MAX,

		     "%s/%s", sysfs_path, _sysfs_format_ptr->sysfs_port_err) < 0) {

		OPAE_ERR("snprintf buffer overflow");

		return FPGA_EXCEPTION;

	}

	return result;

}

fpga_result sysfs_get_port_error_clear_path(fpga_handle handle, char *sysfs_port_error_clear)

{

	fpga_result result = FPGA_OK;

	char sysfs_path[SYSFS_PATH_MAX] = { 0, };

	if (sysfs_port_error_clear == NULL) {

		OPAE_ERR("Invalid input parameters");

		return FPGA_INVALID_PARAM;

	}

	result = get_port_sysfs(handle, sysfs_path);

	if (result != FPGA_OK) {

		OPAE_ERR("Failed to get port syfs path");

		return result;

	}

	if (!SYSFS_FORMAT(sysfs_port_err_clear)) {

		OPAE_ERR("_sysfs_format_ptr is not set.");

		return FPGA_EXCEPTION;

	}

	if (snprintf(sysfs_port_error_clear, SYSFS_PATH_MAX,

		     "%s/%s", sysfs_path,

		     _sysfs_format_ptr->sysfs_port_err_clear) < 0) {

		OPAE_ERR("snprintf buffer overflow");

		return FPGA_EXCEPTION;

	}

	return result;

}

fpga_result sysfs_get_bmc_path(fpga_token token, char *sysfs_bmc)

{

	fpga_result res = FPGA_OK;

	struct _fpga_token *_token = (struct _fpga_token *)token;

	ASSERT_NOT_NULL(_token);

	if (sysfs_bmc == NULL) {

		OPAE_ERR("Invalid input parameters");

		return FPGA_INVALID_PARAM;

	}

	res = cat_token_sysfs_path(sysfs_bmc, token, SYSFS_FORMAT(sysfs_bmc_glob));

	if (res != FPGA_OK) {

		return res;