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// Copyright(c) 2018, Intel Corporation
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of Intel Corporation nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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#pragma once
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#include <memory>
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#include <vector>
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#include <opae/cxx/core/token.h>
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#include <opae/enum.h>
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#include <opae/types.h>
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namespace opae {
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namespace fpga {
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namespace types {
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/** An allocated accelerator resource
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*
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* Represents an accelerator resource that has
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* been allocated by OPAE. Depending on the type
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* of resource, its register space may be
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* read/written using a handle object.
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*/
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class handle {
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public:
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typedef std::shared_ptr<handle> ptr_t;
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handle(const handle &) = delete;
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handle &operator=(const handle &) = delete;
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virtual ~handle();
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/** Retrieve the underlying OPAE handle.
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*/
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fpga_handle c_type() const { return handle_; }
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/** Retrieve the underlying OPAE handle.
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*/
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operator fpga_handle() const { return handle_; }
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/**
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* @brief Load a bitstream into an FPGA slot
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*
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* @param slot The slot number to program
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* @param bitstream The bitstream binary data
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* @param size The size of the bitstream
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* @param flags Flags that control behavior of reconfiguration.
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* Value of 0 indicates no flags. FPGA_RECONF_FORCE
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* indicates that the bitstream is programmed into
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* the slot without checking if the resource is
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* currently in use.
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*
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* @throws invalid_param if the handle is not an FPGA device handle
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* or if the other parameters are not valid.
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* @throws exception if an internal error is encountered.
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* @throws busy if the accelerator for the given slot is in use.
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* @throws reconf_error if errors are reported by the driver
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* (CRC or protocol errors).
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*/
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void reconfigure(uint32_t slot, const uint8_t *bitstream, size_t size,
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int flags);
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/**
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* @brief Read 32 bits from a CSR belonging to a resource associated
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* with a handle.
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*
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* @param[in] offset The register offset
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* @param[in] csr_space The CSR space to read from. Default is 0.
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*
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* @return The 32-bit value read from the CSR
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*/
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uint32_t read_csr32(uint64_t offset, uint32_t csr_space = 0) const;
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/**
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* @brief Write 32 bit to a CSR belonging to a resource associated
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* with a handle.
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*
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* @param[in] offset The register offset.
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* @param[in] value The 32-bit value to write to the register.
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* @param[in] csr_space The CSR space to read from. Default is 0.
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*
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*/
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void write_csr32(uint64_t offset, uint32_t value, uint32_t csr_space = 0);
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/**
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* @brief Read 64 bits from a CSR belonging to a resource associated
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* with a handle.
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*
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* @param[in] offset The register offset
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* @param[in] csr_space The CSR space to read from. Default is 0.
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*
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* @return The 64-bit value read from the CSR
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*/
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uint64_t read_csr64(uint64_t offset, uint32_t csr_space = 0) const;
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/**
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* @brief Write 64 bits to a CSR belonging to a resource associated
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* with a handle.
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*
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* @param[in] offset The register offset.
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* @param[in] value The 64-bit value to write to the register.
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* @param[in] csr_space The CSR space to read from. Default is 0.
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*
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*/
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void write_csr64(uint64_t offset, uint64_t value, uint32_t csr_space = 0);
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/**
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* @brief Write 512 bits to a CSR belonging to a resource associated
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* with a handle.
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*
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* @param[in] offset The register offset.
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* @param[in] value Pointer to the 512-bit value to write to the register.
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* @param[in] csr_space The CSR space to read from. Default is 0.
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*
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*/
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void write_csr512(uint64_t offset, const void *value, uint32_t csr_space = 0);
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/** Retrieve a pointer to the MMIO region.
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* @param[in] offset The byte offset to add to MMIO base.
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* @param[in] csr_space The desired CSR space. Default is 0.
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* @return MMIO base + offset
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*/
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uint8_t *mmio_ptr(uint64_t offset, uint32_t csr_space = 0) const;
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/** Open an accelerator resource, given a raw fpga_token
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*
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* @param[in] token A token describing the accelerator
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* resource to be allocated.
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*
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* @param[in] flags The flags parameter to fpgaOpen().
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*
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* @return pointer to the mmio base + offset for the given
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* csr space
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*
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*/
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static handle::ptr_t open(fpga_token token, int flags);
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/** Open an accelerator resource, given a token object
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*
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* @param[in] token A token object describing the
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* accelerator resource to be allocated.
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*
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* @param[in] flags The flags parameter to fpgaOpen().
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*
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* @return shared ptr to a handle object
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*/
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static handle::ptr_t open(token::ptr_t token, int flags);
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/** Reset the accelerator identified by this handle
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*/
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virtual void reset();
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/** Close an accelerator resource (if opened)
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*
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* @return fpga_result indication the result of closing the
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* handle or FPGA_EXCEPTION if handle is not opened
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*
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* @note This is available for explicitly closing a handle.
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* The destructor for handle will call close.
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*/
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fpga_result close();
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private:
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handle(fpga_handle h);
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fpga_handle handle_;
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fpga_token token_;
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};
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} // end of namespace types
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} // end of namespace fpga
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} // end of namespace opae
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