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/* [ICS VERSION STRING: unknown] */

#ifndef __IBA_STL_SM_TYPES_H__

#define __IBA_STL_SM_TYPES_H__

#include "iba/stl_types.h"

#include "iba/ib_sm_types.h"

#if defined (__cplusplus)

extern "C" {

#endif

#include "iba/public/ipackon.h"

/*

 * Defines 

 */

#define STL_SM_CLASS_VERSION				0x80 	/* Subnet Management */

/* SMP Attributes */

#define STL_MCLASS_ATTRIB_ID_NODE_DESCRIPTION	0x0010  /* Node Description */

#define STL_MCLASS_ATTRIB_ID_NODE_INFO			0x0011  /* Node Information */

#define STL_MCLASS_ATTRIB_ID_SWITCH_INFO	   	0x0012  /* Switch Information */

#define STL_MCLASS_ATTRIB_ID_PORT_INFO 			0x0015  /* Port Information */

#define STL_MCLASS_ATTRIB_ID_PART_TABLE			0x0016  /* Partition Table */

#define STL_MCLASS_ATTRIB_ID_SL_SC_MAPPING_TABLE	0x0017  /* Service Level to */

															/* Service Channel Mapping Table */

#define STL_MCLASS_ATTRIB_ID_VL_ARBITRATION		0x0018  /* Lists of VL Arbitration Weights */

#define STL_MCLASS_ATTRIB_ID_LINEAR_FWD_TABLE	0x0019  /* Linear Forwarding Table */

// reserved										0x001A	/* (was) Random Forwarding Table */

#define STL_MCLASS_ATTRIB_ID_MCAST_FWD_TABLE	0x001B  /* Multicast Forwarding Table */

#define STL_MCLASS_ATTRIB_ID_SM_INFO			0x0020  /* Subnet Manager Information */

#define STL_MCLASS_ATTRIB_ID_LED_INFO			0x0031  /* Turn on/off beaconing LED */

#define STL_MCLASS_ATTRIB_ID_CABLE_INFO			0x0032  /* Cable Information */

#define STL_MCLASS_ATTRIB_ID_AGGREGATE			0x0080  /* Aggregate */

#define STL_MCLASS_ATTRIB_ID_SC_SC_MAPPING_TABLE	0x0081  /* Service Channel to */

															/* Service Channel Mapping Table */

#define STL_MCLASS_ATTRIB_ID_SC_SL_MAPPING_TABLE	0x0082  /* Service Channel to */

															/* Service Level Mapping Table */

#define STL_MCLASS_ATTRIB_ID_SC_VLR_MAPPING_TABLE	0x0083  /* Service Channel to Virtual */

															/* Lane Receive Mapping Table */

#define STL_MCLASS_ATTRIB_ID_SC_VLT_MAPPING_TABLE	0x0084  /* Service Channel to Virtual */

															/* Lane Transmit Mapping Table */

#define STL_MCLASS_ATTRIB_ID_SC_VLNT_MAPPING_TABLE	0x0085  /* Service Channel to Virtual */

															/* Lane Credit Return Mapping Table */

#define STL_MCLASS_ATTRIB_ID_PORT_STATE_INFO		0x0087  /* Port State Information */

#define STL_MCLASS_ATTRIB_ID_PORT_GROUP_FWD_TABLE	0x0088  /* Adaptive Routing Port Group Forwarding Table */

#define STL_MCLASS_ATTRIB_ID_PORT_GROUP_TABLE		0x0089  /* Adaptive Routing Port Group Table */

#define STL_MCLASS_ATTRIB_ID_BUFFER_CONTROL_TABLE	0x008A  /* Buffer Control Table */

#define STL_MCLASS_ATTRIB_ID_CONGESTION_INFO		0x008B  /* Congestion Information */

#define STL_MCLASS_ATTRIB_ID_SWITCH_CONGESTION_LOG	0x008C  /* Congestion Log */

#define STL_MCLASS_ATTRIB_ID_SWITCH_CONGESTION_SETTING	0x008D	/* Switch Congestion Setting */

#define STL_MCLASS_ATTRIB_ID_SWITCH_PORT_CONGESTION_SETTING	0x008E	/* Switch Congestion Setting */

#define STL_MCLASS_ATTRIB_ID_HFI_CONGESTION_LOG		0x008F	/* Congestion Log */

#define STL_MCLASS_ATTRIB_ID_HFI_CONGESTION_SETTING	0x0090	/* HFI Congestion Setting */

#define STL_MCLASS_ATTRIB_ID_HFI_CONGESTION_CONTROL_TABLE	0x0091	/* HFI Congestion Control Table */

#define STL_MCLASS_ATTRIB_ID_SC_SC_MULTI_SET        0x0094  /* Service Channel to Service */

/* SMP Attribute Modifiers */

#define STL_SM_CONF_START_ATTR_MOD 0x00000200  /* PortInfo & PortStateInfo Attr Mod Flag */

/* *************************************************************************

 * SMPs

 */

/* SMP Fields (LID Routed/Directed Route) */

#define STL_MAX_PAYLOAD_SMP_DR	1872	/* Max size of DR SMP payload */

#define STL_MAX_PAYLOAD_SMP_LR	2016	/* Max size of LR SMP payload */

#define STL_MIN_SMP_DR_MAD	(STL_MAD_BLOCK_SIZE - STL_MAX_PAYLOAD_SMP_DR)

#define STL_MIN_SMP_LR_MAD	(STL_MAD_BLOCK_SIZE - STL_MAX_PAYLOAD_SMP_LR)

typedef struct {

	MAD_COMMON  common;

	uint64  M_Key;  					/* A 64 bit key, */

										/* employed for SM authentication */

	union {

		struct _STL_LIDRouted {

			uint8   SMPData[STL_MAX_PAYLOAD_SMP_LR];	/* Up to 'MAX' byte field of SMP */

														/* data used to contain the */

														/* method's attribute */

		} LIDRouted;

		struct _STL_DirectedRoute {

			STL_LID DrSLID; 			/* Directed route source LID */

			STL_LID DrDLID; 			/* Directed route destination LID */

			uint8   InitPath[64];   	/* 64-byte field containing the initial */

										/* directed path */

			uint8   RetPath[64];		/* 64-byte field containing the */

										/* returning directed path */

			uint8   Reserved2[8];		/* For the purpose of aligning the Data */

										/* field on a 16-byte boundary */

			uint8   SMPData[STL_MAX_PAYLOAD_SMP_DR];	/* Up to 'MAX' byte field of SMP */

														/* data used to contain the */

														/* method's attribute */

		} DirectedRoute;

	}SmpExt;

} PACK_SUFFIX STL_SMP;

/* **************************************************************************

 * Attribute specific SMP Packet Formats

 *

 * In the attributes which follow member fields are marked (where appropriate)

 * with usage information as: 'AccessType/NodeType/IB-Only'.  AccessType

 * refers to how members can be accessed; NodeType refers to which node

 * types the member applies; IB-Only refers to members which have been

 * deprecated for STL use but retained to report information about IB nodes.

 *

 * AccessType: Read Write ('RW'), Read Only ('RO')

 *

 * NodeType: HFI ('H'), External Switch Port ('S'), Base Switch Port 0 ('P'),

 * Enhanced Switch Port 0 ('E').  NodeType is shown as a 4-character string

 * with each character representing (in positional order) a node type 'HSPE'.

 * If a node type is not applicable for a member, its character position is

 * shown as '-' (ex. 'H-PE').

 *

 * Power-On-Default values are shown as 'POD: xxx'

 * Link-Up-Default values are shown as 'LUD: xxx'

 * 

 * Member fields which require a link bounce for new values to become effective

 * are marked 'LinkBounce'

 */

/*

 * SMA Notices/Traps (Data field for IB_NOTICE)

 */

/* Trap Numbers */

#define STL_TRAP_GID_NOW_IN_SERVICE		0x40

#define STL_TRAP_GID_OUT_OF_SERVICE		0x41

#define STL_TRAP_ADD_MULTICAST_GROUP	0x42

#define STL_TRAP_DEL_MULTICAST_GROUP	0x43

#define STL_TRAP_LINK_PORT_CHANGE_STATE	0x80

#define STL_TRAP_LINK_INTEGRITY			0x81

#define STL_TRAP_BUFFER_OVERRUN			0x82

#define STL_TRAP_FLOW_WATCHDOG			0x83

#define STL_TRAP_CHANGE_CAPABILITY		0x90

#define STL_TRAP_CHANGE_SYSGUID			0x91

#define STL_TRAP_BAD_M_KEY				0x100

#define STL_TRAP_BAD_P_KEY				0x101

#define STL_TRAP_BAD_Q_KEY				0x102

#define STL_TRAP_SWITCH_BAD_PKEY		0x103

#define STL_SMA_TRAP_LINK_WIDTH			0x800

#define STL_TRAP_COST_MATRIX_CHANGE		0x801

typedef struct {

	IB_GID		Gid;

} PACK_SUFFIX STL_TRAP_GID;

#define STL_TRAP_GID_NOW_IN_SERVICE_DATA STL_TRAP_GID

#define STL_TRAP_GID_OUT_OF_SERVICE_DATA STL_TRAP_GID

#define STL_TRAP_GID_ADD_MULTICAST_GROUP_DATA STL_TRAP_GID

#define STL_TRAP_GID_DEL_MULTICAST_GROUP_DATA STL_TRAP_GID

typedef struct {

	STL_LID		Lid;

} PACK_SUFFIX STL_TRAP_PORT_CHANGE_STATE_DATA;

typedef struct {

	STL_LID		Lid;

	uint8		Port;

} PACK_SUFFIX STL_TRAP_LINK;

#define STL_TRAP_LINK_INTEGRITY_DATA STL_TRAP_LINK

#define STL_TRAP_BUFFER_OVERRUN_DATA STL_TRAP_LINK

#define STL_TRAP_FLOW_WATCHDOG_DATA STL_TRAP_LINK

typedef STL_FIELDUNION16(STL_CAPABILITY_MASK, 32,

		CmReserved6:						1,  	/* shall be zero */

		CmReserved24:						2,  	/* shall be zero */

		CmReserved5:						2,  	/* shall be zero */

		CmReserved23:  						4,		/* shall be zero */

		IsCapabilityMaskNoticeSupported:	1,

		CmReserved22:						1,		/* shall be zero */

		IsVendorClassSupported: 			1,

		IsDeviceManagementSupported:		1,

		CmReserved21:   					2,		/* shall be zero */

		IsConnectionManagementSupported:	1,

		CmReserved25: 					   10,		/* shall be zero */

		IsAutomaticMigrationSupported:		1,

		CmReserved2:						1,		/* shall be zero */

		CmReserved20:						2,

		IsSM:   							1,

		CmReserved1:						1 );	/* shall be zero */

/* Capability Mask 3 - a bit set to 1 for affirmation of supported capability

 * by a given port

 */

typedef STL_FIELDUNION15(STL_CAPABILITY_MASK3, 16,

		CmReserved0:					1,

		CmReserved1:					1,

		CmReserved2:					1,

		IsMAXLIDSupported:			1,		/* RO/H--- Does the HFI support the MAX */

											/* LID being configured */

		CmReserved3:			 	1,

		CmReserved4:				1,

		VLSchedulingConfig:			2,		/* RO/H-PE VL Arbitration */

											/* see STL_VL_SCHEDULING_MODE */

											/* Port 0 indicates whole switch */

		IsSnoopSupported: 			1,		/* RO/--PE Packet snoop */

											/* Port 0 indicates whole switch */

		IsAsyncSC2VLSupported:	 	1,		/* RO/H-PE Port 0 indicates whole switch */

		IsAddrRangeConfigSupported:	1,		/* RO/H-PE Can addr range for Multicast */

											/* and Collectives be configured */

											/* Port 0 indicates whole switch */

		IsPassThroughSupported: 	1,		/* RO/--PE Packet pass through */

											/* Port 0 indicates whole switch */

		IsSharedSpaceSupported: 	1,		/* RO/H-PE Shared Space */

											/* Port 0 indicates whole switch */

		IsSharedGroupSpaceSupported:1,		/* RO/H-PE Shared Space */

											/* Port 0 indicates whole switch */

		IsVLMarkerSupported: 		1,		/* RO/H-PE VL Marker */

											/* Port 0 indicates whole switch */

		IsVLrSupported: 			1 );	/* RO/H-PE SC->VL_r table */

typedef enum {

	VL_SCHED_MODE_VLARB			= 0,	/* VL Arbitration Tables */

	VL_SCHED_MODE_AUTOMATIC		= 2,	/* harcoded, not configurable */

	/* reserved 3 */

} STL_VL_SCHEDULING_MODE;

typedef struct {

	STL_LID					Lid;

	STL_CAPABILITY_MASK		CapabilityMask;

	uint16					Reserved;

	STL_CAPABILITY_MASK3	CapabilityMask3;

	STL_FIELDUNION5(u,16,

							Reserved:12,

							LinkWidthDowngradeEnabledChange:1,	

							LinkSpeedEnabledChange:1,

							LinkWidthEnabledChange:1,

							NodeDescriptionChange:1);

} PACK_SUFFIX STL_TRAP_CHANGE_CAPABILITY_DATA;

typedef struct {

	uint64		SystemImageGuid;

	STL_LID		Lid;

} PACK_SUFFIX STL_TRAP_SYSGUID_CHANGE_DATA;

typedef struct {

	STL_LID		Lid;

	STL_LID		DRSLid;

	/*	8 bytes */

	uint8		Method;

	STL_FIELDUNION3(u,8,

				DRNotice:1,

				DRPathTruncated:1,

				DRHopCount:6);

	uint16		AttributeID;

	/*	12 bytes */

	uint32		AttributeModifier;

	/*	16 bytes */

	uint64		MKey;

	/* 	24 bytes */

	uint8		DRReturnPath[30]; // We can make this longer....

	/*  54 bytes */

} PACK_SUFFIX STL_TRAP_BAD_M_KEY_DATA;

typedef struct {

	STL_LID		Lid1;

	STL_LID		Lid2;

	/*	8 bytes */

	uint32		Key;	// pkey or qkey

	STL_FIELDUNION2(u,8,

				SL:5,

				Reserved:3);

	uint8		Reserved[3];

	/*	16 bytes */

	IB_GID		Gid1;

	/*	32 bytes */

	IB_GID		Gid2;

	/*	48 bytes */

	STL_FIELDUNION2(qp1,32,

				Reserved:8,

				qp:24);

	/*	52 bytes */

	STL_FIELDUNION2(qp2,32,

				Reserved:8,

				qp:24);

	/*	56 bytes */

} PACK_SUFFIX STL_TRAP_BAD_KEY_DATA;

#define STL_TRAP_BAD_P_KEY_DATA STL_TRAP_BAD_KEY_DATA

#define STL_TRAP_BAD_Q_KEY_DATA STL_TRAP_BAD_KEY_DATA

typedef struct {

	STL_FIELDUNION9(u,16,

				Lid1:1, Lid2:1, PKey:1, SL:1,

				QP1:1, QP2:1, Gid1:1, Gid2:1,

				Reserved:8);

	uint16		PKey;

	/*	4 bytes */

	STL_LID		Lid1;

	STL_LID		Lid2;

	STL_FIELDUNION2(u2,8,

				SL:5,

				Reserved:3);

	uint8		Reserved[3];

	/*	16 bytes */

	IB_GID		Gid1;

	/*	32 bytes */

	IB_GID		Gid2;

	/*	48 bytes */

	STL_FIELDUNION2(qp1,32,

				qp:24,

				Reserved:8);

	/*	52 bytes */

	STL_FIELDUNION2(qp2,32,

				qp:24,

				Reserved:8);

	/*	56 bytes */

} PACK_SUFFIX STL_TRAP_SWITCH_BAD_PKEY_DATA;

/* LinkWidth of at least one port of switch at <ReportingLID> has changed */

typedef struct {

	STL_LID  ReportingLID;   		

} PACK_SUFFIX STL_SMA_TRAP_DATA_LINK_WIDTH;

/*

 * NodeInfo

 *

 * Attribute Modifier as: 0 (not used)

 */

typedef struct {

	uint8	BaseVersion;		/* RO Supported MAD Base Version */

	uint8	ClassVersion;		/* RO Supported Subnet Management Class */

								/* (SMP) Version */

	uint8	NodeType;	

	uint8	NumPorts;			/* RO Number of link ports on this node */

	uint32	Reserved;

	uint64	SystemImageGUID;		

	uint64	NodeGUID;			/* RO GUID of the HFI or switch */

	uint64	PortGUID;			/* RO GUID of this end port itself */

	uint16	PartitionCap;		/* RO Number of entries in the Partition Table */

								/* for end ports */

	uint16	DeviceID;			/* RO Device ID information as assigned by */

								/* device manufacturer */

	uint32	Revision;			/* RO Device revision, assigned by manufacturer */

	STL_FIELDUNION2(u1, 32, 

			LocalPortNum:	8,		/* RO The link port number this */

									/* SMP came on in */

			VendorID:		24);	/* RO Device vendor, per IEEE */

} PACK_SUFFIX STL_NODE_INFO;

/*

 * NodeDescription

 *

 * Attribute Modifier as: 0 (not used)

 */

#define STL_NODE_DESCRIPTION_ARRAY_SIZE 64

typedef struct {

    /* Node String is an array of UTF-8 character that */

    /* describes the node in text format */

    /* Note that this string MUST BE NULL TERMINATED! */

    uint8   NodeString[STL_NODE_DESCRIPTION_ARRAY_SIZE];	/* RO */

} PACK_SUFFIX STL_NODE_DESCRIPTION;

/*

 * SwitchInfo

 *

 * Attribute Modifier as: 0 (not used)

 */

/* STL Routing Modes */

#define STL_ROUTE_NOP			0	/* No change */

#define STL_ROUTE_LINEAR		1	/* Linear routing algorithm */

typedef	union {

	uint16	AsReg16;

	struct { IB_BITFIELD5( uint16,

		Reserved:						12,

		IsExtendedSCSCSupported:		1,	/* RO Extended SCSC */

		IsAddrRangeConfigSupported:		1,	/* Can addr range for Multicast */

											/* and Collectives be configured */

		Reserved2:						1,

		IsAdaptiveRoutingSupported:		1 )

	} s; 

} SWITCH_CAPABILITY_MASK;

typedef union {

	uint16  AsReg16;

	struct	{

		uint16  Reserved;

	} s;

} CAPABILITY_MASK_COLLECTIVES;

typedef struct {

	uint32  LinearFDBCap;	  	/* RO Number of entries supported in the */

								/* Linear Unicast Forwarding Database */

	uint32  PortGroupFDBCap;	/* RO Number of entries supported in the */

								/* Port Group Forwarding Database */

	uint32  MulticastFDBCap;	/* RO Number of entries supported in the */

								/*  Multicast Forwarding Database */

	STL_LID  LinearFDBTop;		/* RW Indicates the maximum DLID programmed */

								/*  in the routing tables */

								/* POD: 0 */

	STL_LID  MulticastFDBTop;	/* RW Indicates the top of the Multicast */

								/*  Forwarding Table */

								/* POD: 0 */

	uint32  CollectiveCap;   	/* RO Number of entries supported in the */

								/*  Collective Table */

								/* Reserved in Gen1 */

	STL_LID  CollectiveTop;		/* RW Indicates the top of the Collective Table */

								/* POD: 0 */

								/* Reserved in Gen1 */

	uint32  Reserved;

	STL_IPV6_IP_ADDR  IPAddrIPV6;	       /* RO IP Address - IPV6 */

	STL_IPV4_IP_ADDR  IPAddrIPV4;	       /* RO IP Address - IPV4 */

	uint32  Reserved26;

	uint32  Reserved27;

	uint32	Reserved28;

	uint8	Reserved21;

	uint8	Reserved22;

	uint8	Reserved23;

	union {

		uint8   AsReg8;

		struct { IB_BITFIELD3( uint8,

			LifeTimeValue:		5,	/* LifeTimeValue */

			PortStateChange:	1,	/* RW This bit is set to zero by a */

									/*  management write */

			Reserved20:		2 )	

		} s;

	} u1;

	uint16	Reserved24;

	uint16  PartitionEnforcementCap;	/* RO Specifies the number of entries in the */

										/*  partition enforcement table */

	uint8	PortGroupCap;			/* RO Specifies the maximum number of */

									/* entries in the port group table */

	uint8	PortGroupTop;			/* RW The current number of entries in */

									/* port group table. */

	struct {					/* RW (see STL_ROUTING_MODE) */

		uint8   Supported;		/* Supported routing mode */

		uint8   Enabled;		/* Enabled routing mode */

	} RoutingMode;

	union {

		uint8   AsReg8;

		struct { IB_BITFIELD6( uint8,

			Reserved20:		1,	

			Reserved21:		1,

			Reserved22:		1,

			Reserved23:		1,

			EnhancedPort0:	1,	

			Reserved:		3 )

		} s;

	} u2;

	struct { IB_BITFIELD3( uint8,	/* Multicast/Collectives masks */

		Reserved:			2,

		CollectiveMask:		3,	/* RW Num of additional upper 1s in */

								/* Collective address */

								/* POD: 1 */

								/* Reserved in Gen1 */

		MulticastMask:		3 )	/* RW Num of upper 1s in Multicast address */

								/* POD: 4 */

	} MultiCollectMask;

	STL_FIELDUNION8(AdaptiveRouting, 16,

		Enable: 			1,	/* RW Enable/Disable AR */

		Pause:				1,	/* RW Pause AR when true */

		Algorithm:			3,	/* RW 0 = Random, 1 = Greedy, */

								/* 2 = Random Greedy. */

		Frequency:			3,	/* RW 0-7. Value expands to 2^F*64ms. */

		LostRoutesOnly:		1,  /* RW. Indicates that AR should only be done */

								/* for failed links. */

		Threshold:			3,  /* CCA-level at which switch uses AR. */

		Reserved2:			1,

		Reserved:			3);

	SWITCH_CAPABILITY_MASK  CapabilityMask;		/* RO */

	CAPABILITY_MASK_COLLECTIVES  CapabilityMaskCollectives;	/* RW */

} PACK_SUFFIX STL_SWITCH_INFO;

/*

 * PortInfo

 *

 * Attribute Modifier as: NNNN NNNN 0000 0000 0000 00SA PPPP PPPP

 *                        N:   Number of ports

 *                        S=1: Start of SM configuration

 *                        A=1: All ports starting at P (Set only)

 *                        P:   Port number (0 - management port, switches only;

 *								for HFIs P is ignored and the attribute is

 *								applicable only to the port that receives the packet)

 */

/* STL_PORT_STATE values continue from IB_PORT_STATE */

/* reserved 5-6 */

/* STL_PORT_PHYS_STATE values continue from IB_PORT_PHYS_STATE */

/* reserved 7-8 */

#define STL_PORT_PHYS_OFFLINE		9		/* offline */

/* reserved 10 */

#define STL_PORT_PHYS_TEST			11		/* test */

/* Offline Disabled Reason, indicated as follows: */

#define STL_OFFDIS_REASON_NONE					0	/* Nop/No specified reason */

#define STL_OFFDIS_REASON_DISCONNECTED			1	/* not connected in design*/

#define STL_OFFDIS_REASON_LOCAL_MEDIA_NOT_INSTALLED	2	/* Module not installed

														 * in connector (QSFP,

													 	 * SiPh_x16, etc) */

#define STL_OFFDIS_REASON_NOT_INSTALLED			3	/* internal link not

													 * installed, neighbor FRU

													 * absent */

#define STL_OFFDIS_REASON_CHASSIS_CONFIG		4	/* Chassis mgmt forced

													 * offline due to incompat

													 * or absent neighbor FRU */

/* reserved 5 */

#define STL_OFFDIS_REASON_END_TO_END_NOT_INSTALLED	6	/* local module present

													 * but unable to detect

													 * end to optical link */

/* reserved 7 */

#define STL_OFFDIS_REASON_POWER_POLICY			8	/* enabling port would

													 * exceed power policy */

#define STL_OFFDIS_REASON_LINKSPEED_POLICY		9	/* enabled speed unable to

													 * be met due to persistent

													 * cause */

#define STL_OFFDIS_REASON_LINKWIDTH_POLICY		10	/* enabled width unable to

													 * be met due to persistent

													 * cause */

/* reserved 11 */

#define STL_OFFDIS_REASON_SWITCH_MGMT			12	/* user disabled via switch

													 * mangement interface

													 */

#define STL_OFFDIS_REASON_SMA_DISABLED			13	/* user disabled via SMA

													 * Set to phys port state

													 * disabled */

/* reserved 14 */

#define STL_OFFDIS_REASON_TRANSIENT				15	/* Transient offline as part

													 * of sync with neighbor

													 * phys port state machine*/

/* Link Init Reason, indicated as follows: */

#define STL_LINKINIT_REASON_NOP			 0	/* None on Get/no change on Set */

#define STL_LINKINIT_REASON_LINKUP		 1	/* link just came up */

/* values from 2-7 will not be altered by transistions from Polling to Linkup/Init */

/* these can represent persistent reasons why the SM is ignoring a link */

#define STL_LINKINIT_REASON_FLAPPING	 2	/* FM ignoring flapping port */

/* reserved 3-7 */

/* values from 8-15 will be altered by transistions from Polling to LinkUp/Init */

/* these can represent transient reasons why the SM is ignoring a link */

#define STL_LINKINIT_OUTSIDE_POLICY		 8	/* FM ignoring, width or speed outside FM configured policy */

#define STL_LINKINIT_QUARANTINED		 9	/* FM ignoring, quarantined for security */

#define STL_LINKINIT_INSUFIC_CAPABILITY	 10	/* FM ignoring, link has insufficient capabilities*/

											/* for FM configuration (eg. MTU too small etc) */

/* reserved 11-15 */

/* these correspond to locally initiated link bounce due to PortErrorAction */

/* See Section 9.8.3, “Error Counters”, Table 9-23 */

#define STL_LINKDOWN_REASON_NONE				0	/* No specified reason */

#define STL_LINKDOWN_REASON_RCV_ERROR_0			1

#define STL_LINKDOWN_REASON_BAD_PKT_LEN			2

#define STL_LINKDOWN_REASON_PKT_TOO_LONG		3

#define STL_LINKDOWN_REASON_PKT_TOO_SHORT		4

#define STL_LINKDOWN_REASON_BAD_SLID			5

#define STL_LINKDOWN_REASON_BAD_DLID			6

#define STL_LINKDOWN_REASON_BAD_L2				7

#define STL_LINKDOWN_REASON_BAD_SC				8

#define STL_LINKDOWN_REASON_RCV_ERROR_8			9

#define STL_LINKDOWN_REASON_BAD_MID_TAIL		10

#define STL_LINKDOWN_REASON_RCV_ERROR_10		11

#define STL_LINKDOWN_REASON_PREEMPT_ERROR		12

#define STL_LINKDOWN_REASON_PREEMPT_VL15		13

#define STL_LINKDOWN_REASON_BAD_VL_MARKER		14

#define STL_LINKDOWN_REASON_RCV_ERROR_14		15

#define STL_LINKDOWN_REASON_RCV_ERROR_15		16

#define STL_LINKDOWN_REASON_BAD_HEAD_DIST		17

#define STL_LINKDOWN_REASON_BAD_TAIL_DIST		18

#define STL_LINKDOWN_REASON_BAD_CTRL_DIST		19

#define STL_LINKDOWN_REASON_BAD_CREDIT_ACK		20

#define STL_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21

#define STL_LINKDOWN_REASON_BAD_PREEMPT			22

#define STL_LINKDOWN_REASON_BAD_CONTROL_FLIT	23

#define STL_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT	24

#define STL_LINKDOWN_REASON_RCV_ERROR_24		25

#define STL_LINKDOWN_REASON_RCV_ERROR_25		26

#define STL_LINKDOWN_REASON_RCV_ERROR_26		27

#define STL_LINKDOWN_REASON_RCV_ERROR_27		28

#define STL_LINKDOWN_REASON_RCV_ERROR_28		29

#define STL_LINKDOWN_REASON_RCV_ERROR_29		30

#define STL_LINKDOWN_REASON_RCV_ERROR_30		31

#define STL_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32

/* the next two correspond to locally initiated intentional link down */

#define STL_LINKDOWN_REASON_UNKNOWN				33

			/* code 33 is used for locally initiated link downs which don't */

			/* match any of these reason code */

/* reserved 34 */

#define STL_LINKDOWN_REASON_REBOOT				35 /* reboot or device reset */

#define STL_LINKDOWN_REASON_NEIGHBOR_UNKNOWN	36

			/* This indicates the link down was not locally initiated */

			/* but no LinkGoingDown idle flit was received */

			/* See Section 6.3.11.1.2, "PlannedDownInform Substate" */

/* reserved 37 - 38 */

/*These correspond to locally initiated intentional link down */

#define STL_LINKDOWN_REASON_FM_BOUNCE			39	/* FM initiated bounce */

													/* by transitioning from linkup to Polling */

#define STL_LINKDOWN_REASON_SPEED_POLICY		40 /* link outside speed policy */

#define STL_LINKDOWN_REASON_WIDTH_POLICY		41 /* link downgrade outside */

													/* LinkWidthDowngrade.Enabled policy */

/* reserved 42-47 */

/* these correspond to locally initiated link down via transition to Offline or Disabled */

/* See Section 6.6.2, “Offline/Disabled Reasons”, Table 6-38*/

/* All values in that section are provided for here, although in practice a few */

/* such as 49 (Disconnected) represent links which can never reach LinkUp and hence */

/* could not have a transition to LinkDown */

/* reserved 48 */

#define STL_LINKDOWN_REASON_DISCONNECTED		49

#define STL_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED 50

#define STL_LINKDOWN_REASON_NOT_INSTALLED		51

#define STL_LINKDOWN_REASON_CHASSIS_CONFIG		52

/* reserved 53 */

#define STL_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54

/* reserved 55 */

#define STL_LINKDOWN_REASON_POWER_POLICY		56

#define STL_LINKDOWN_REASON_LINKSPEED_POLICY	57

#define STL_LINKDOWN_REASON_LINKWIDTH_POLICY	58

/* reserved 59 */

#define STL_LINKDOWN_REASON_SWITCH_MGMT			60

#define STL_LINKDOWN_REASON_SMA_DISABLED		61

/* reserved 62 */

#define STL_LINKDOWN_REASON_TRANSIENT			63

/* reserved 64-255 */

/* STL PORT TYPE values imply cable info availabilty and format */

#define STL_PORT_TYPE_UNKNOWN		0

#define STL_PORT_TYPE_DISCONNECTED		1	/* the port is not currently usable � CableInfo not available */

#define STL_PORT_TYPE_FIXED				2	/* A fixed backplane port in a director class switch � All STL ASICS */

#define STL_PORT_TYPE_VARIABLE			3	/* A backplane port in a blade system � possibly mixed configuration */

#define STL_PORT_TYPE_STANDARD			4	/* implies a SFF-8636 defined format for CableInfo (QSFP) */

#define STL_PORT_TYPE_SI_PHOTONICS		5	/* A silicon photonics module � 

											 * implies TBD defined format for CableInfo as defined by Intel SFO group */

/* 6 - 15 Reserved */

/* STL NEIGHBOR NODE TYPE indicate whether the neighbor is an HFI or 

 * a switch. */

#define STL_NEIGH_NODE_TYPE_HFI		0	/* Gen 1 HFIs are considered "untrusted" */

#define STL_NEIGH_NODE_TYPE_SW		1	/* Gen 1 Switches are considered "trusted" */

/* Values 2 & 3 are reserved in Gen1. */

typedef union {

	uint32  AsReg32;

	struct { IB_BITFIELD8( uint32,	/* Port states */

		Reserved:					9,

		LEDEnabled:					1, 	/* RO/HS-- Set to 1 if the port LED is active. */

		IsSMConfigurationStarted: 	1,  /* RO/HS-E - POD/LUD: 0 */

		NeighborNormal:				1,	/* RO/HS-- */

										/* POD/LUD: 0 */

		OfflineDisabledReason:		4,	/* RO/HS-E Reason for Offline (see STL_OFFDIS_REASON_XXX) */

		Reserved2:					8,	

		PortPhysicalState:			4,	/* RW/HS-E Port Physical State (see STL_PORT_PHYS_XXX) */

		PortState:					4 )	/* RW/HS-E Port State (see STL_PORT_XXX) */

	} s;

} STL_PORT_STATES;

typedef union {

	uint8   AsReg8;

	struct { IB_BITFIELD2( uint8,	/* RW/HS-E Neighbor MTU values per VL */

									/* LUD: 2048 MTU for STL VL15 */

				VL0_to_MTU:		4,

				VL1_to_MTU:		4 )

	} s;

} STL_VL_TO_MTU;

#define	STL_VL0_VL31		6

/* STL Link speed, continued from IB_LINK_SPEED and indicated as follows:

 * values are additive for Supported and Enabled fields

 */

#define STL_LINK_SPEED_NOP		 0		/* LinkSpeed.Enabled: no change */

										/* LinkSpeeed.Active: link is LinkDown*/

#define STL_LINK_SPEED_12_5G	 0x0001	/* 12.5 Gbps */

#define STL_LINK_SPEED_25G		 0x0002	/* 25.78125? Gbps (EDR) */

/* STL Link width, continued from IB_LINK_WIDTH and indicated as follows:

 * values are additive for Supported and Enabled fields

 */

#define		STL_LINK_WIDTH_NOP					 0	/* LinkWidth.Enabled: no changeon set (nop) */

													/* LinkWidth.Active: link is LinkDown*/

													/* LinkWidthDowngrade.Supported: unsupported */

													/* LinkWidthDowngrade.Enable: disabled */

													/* LinkWidthDowngrade.TxActive: link is LinkDown*/

													/* LinkWidthDowngrade.RxActive: link is LinkDown */

#define 	STL_LINK_WIDTH_1X					 0x0001

#define		STL_LINK_WIDTH_2X					 0x0002

#define		STL_LINK_WIDTH_3X					 0x0004

#define 	STL_LINK_WIDTH_4X					 0x0008

/* STL Port link mode, indicated as follows:

 * values are additive for Supported and Enabled fields

 */

#define STL_PORT_LINK_MODE_NOP	0		/* No change */

/* reserved 1 */

/* reserved 2 */

#define STL_PORT_LINK_MODE_STL	4		/* Port mode is STL */

/* STL Port link formats, indicated as follows:

 * values are additive for Supported and Enabled fields

 */

#define STL_PORT_PACKET_FORMAT_NOP	0		/* No change */

#define STL_PORT_PACKET_FORMAT_8B	1		/* Format 8B */

#define STL_PORT_PACKET_FORMAT_9B	2		/* Format 9B */

#define STL_PORT_PACKET_FORMAT_10B	4		/* Format 10B */

#define STL_PORT_PACKET_FORMAT_16B	8		/* Format 16B */

/* STL Port LTP CRC mode, indicated as follows:

 * values are additive for Supported and Enabled fields

 */

#define STL_PORT_LTP_CRC_MODE_NONE	0	/* No change */

#define STL_PORT_LTP_CRC_MODE_14	1	/* 14-bit LTP CRC mode (optional) */

#define STL_PORT_LTP_CRC_MODE_16	2	/* 16-bit LTP CRC mode */

#define STL_PORT_LTP_CRC_MODE_48	4	/* 48-bit LTP CRC mode (optional) */

#define STL_PORT_LTP_CRC_MODE_12_16_PER_LANE 8	/* 12/16-bit per lane LTP CRC mode */

/* STL Port Flit distance mode, indicated as follows:

 * values are additive for Supported and Enabled fields

 */

#define STL_PORT_FLIT_DISTANCE_MODE_NONE	0	/* No change */

#define STL_PORT_FLIT_DISTANCE_MODE_1		1	/* STL1 mode */

#define STL_PORT_FLIT_DISTANCE_MODE_2		2	/* STL2 mode */

/* STL VL Scheduling mode, indicated as follows:

 */

#define STL_VL_SCHED_MODE_VLARB		0	/* Gen1 VLARB */

#define STL_VL_SCHED_MODE_AUTOMATIC	2	/* hardcoded, not configurable */

/* STL Port Flit preemption limits of unlimited */

#define STL_PORT_PREEMPTION_LIMIT_NONE		255 /* Unlimited */

#define BYTES_PER_LTP 128

/* NOTE - first-pass ordering of PortInfo members:

 *   1  RW members before RO members;

 *   2  Roughly prioritize RW and RO sections;

 *   3  No separation of RO and RW members within sub-structures.

 *

 *   Attribute Modifier as NNNN NNNN 0000 0000 0000 000A PPPP PPPP

 *

 *   N = number of ports

 *   A = 1 - All ports starting at P

 *   P = port number

 */

typedef struct {

	STL_LID LID;					/* RW/HSPE H-PE: base LID of this node */

									/*               POD: 0 */

									/*         -S--: base LID of neighbor node */

									/*               POD/LUD: 0 */

	uint32  FlowControlMask;		/* RW/-S-- Flow control mask (1 bit per VL) */

									/* POD/LUD: flow control enabled all VLs except VL15 */

	struct {

		uint8	PreemptCap;		/* RO/HS-E size of Preempting VL Arbitration table */

						/* only used when VLSchedulingConfig */

						/* is VL_SCHED_MODE_VLARB, otherwise reserved */

		struct { IB_BITFIELD2( uint8,

			Reserved:		3,

			Cap:			5 )		/* RO/HS-E Virtual Lanes supported on this port */

		} s2;

		uint16  HighLimit;		/* RW/HS-E Limit of high priority component of */

						/*  VL Arbitration table */

						/* only used when VLSchedulingConfig */

						/* is VL_SCHED_MODE_VLARB, otherwise reserved */

						/* POD: 0 */

		uint16  PreemptingLimit;	/* RW/HS-E Limit of preempt component of */

						/*  VL Arbitration table */

						/* only used when VLSchedulingConfig */

						/* is VL_SCHED_MODE_VLARB, otherwise reserved */

						/* POD: 0 */

		union {

			uint8   ArbitrationHighCap;	/* RO/HS-E VL Arbitration table cap */

						/* only used when VLSchedulingConfig */

						/* is VL_SCHED_MODE_VLARB, otherwise reserved */

		};

		uint8   ArbitrationLowCap;	/* RO/HS-E VL Arbitration table cap */

						/* only used when VLSchedulingConfig */

						/* is VL_SCHED_MODE_VLARB, otherwise reserved */

	} VL;

	STL_PORT_STATES  PortStates;		/* Port states */

	STL_FIELDUNION2(PortPhysConfig,8,

			Reserved:4,				/* Reserved */

			PortType:4);            /* RO/HS-- PORT_TYPE */

						/* Switch port 0 shall report Fixed */

						/* reserved when PortLinkMode.Active is not STL */

	struct { IB_BITFIELD3( uint8,	/* Multicast/Collectives masks */

		Reserved:			2,

		CollectiveMask:		3,	/* RW/H--- Num of additional upper 1s in */

								/* Collective address */

								/* POD: 1 */

								/* Reserved in Gen1 */

		MulticastMask:		3 )	/* RW/H--- Num of upper 1s in Multicast address */

								/* POD: 4 */

	} MultiCollectMask;

	struct { IB_BITFIELD3( uint8,

		M_KeyProtectBits:   2,		/* RW/H-PE see mgmt key usage */

		Reserved:   		2,  	/* reserved, shall be zero */

		LMC:				4 )		/* RW/HSPE LID mask for multipath support */

									/*    H---: POD: 0 */

									/*    --PE: POD/LUD: 0 */

									/*    -S--: LID mask for Neighbor node */

									/*      POD/LUD: 0 */

	} s1;

	struct { IB_BITFIELD2( uint8,