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/*
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synth_neon64_s32: NEON optimized synth for AArch64 (32-bit output version)
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copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
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see COPYING and AUTHORS files in distribution or http://mpg123.org
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initially written by Taihei Monma
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*/
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#include "mangle.h"
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#ifndef __APPLE__
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.section .rodata
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#else
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.data
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#endif
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ALIGN16
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maxmin_s32:
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.word 1191182335
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.word -956301312
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.word 1199570944
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.text
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ALIGN4
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.globl ASM_NAME(synth_1to1_s32_neon64_asm)
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#ifdef __ELF__
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.type ASM_NAME(synth_1to1_s32_neon64_asm), %function
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#endif
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ASM_NAME(synth_1to1_s32_neon64_asm):
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add x0, x0, #64
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sub x0, x0, x3, lsl #2
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eor v31.16b, v31.16b, v31.16b
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adrp x5, AARCH64_PCREL_HI(maxmin_s32)
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add x5, x5, AARCH64_PCREL_LO(maxmin_s32)
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ld3r {v28.4s,v29.4s,v30.4s}, [x5]
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mov w4, #4
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mov x5, #128
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1:
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ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
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ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
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ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
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ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], #64
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fmul v24.4s, v0.4s, v16.4s
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fmul v25.4s, v4.4s, v20.4s
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fmla v24.4s, v1.4s, v17.4s
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fmla v25.4s, v5.4s, v21.4s
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fmla v24.4s, v2.4s, v18.4s
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fmla v25.4s, v6.4s, v22.4s
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fmla v24.4s, v3.4s, v19.4s
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fmla v25.4s, v7.4s, v23.4s
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ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
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ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
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ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
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ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], #64
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fmul v26.4s, v0.4s, v16.4s
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fmul v27.4s, v4.4s, v20.4s
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fmla v26.4s, v1.4s, v17.4s
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fmla v27.4s, v5.4s, v21.4s
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fmla v26.4s, v2.4s, v18.4s
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fmla v27.4s, v6.4s, v22.4s
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fmla v26.4s, v3.4s, v19.4s
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fmla v27.4s, v7.4s, v23.4s
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faddp v0.4s, v24.4s, v25.4s
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faddp v1.4s, v26.4s, v27.4s
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faddp v0.4s, v0.4s, v1.4s
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fmul v1.4s, v0.4s, v30.4s
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ld2 {v4.4s,v5.4s}, [x2]
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fcvtns v4.4s, v1.4s
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fcmgt v2.4s, v0.4s, v28.4s
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fcmgt v3.4s, v29.4s, v0.4s
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add v2.4s, v2.4s, v3.4s
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add v31.4s, v31.4s, v2.4s
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st2 {v4.4s,v5.4s}, [x2], #32
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subs w4, w4, #1
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b.ne 1b
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mov w4, #4
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mov x6, #-64
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2:
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ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
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ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
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ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
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ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], x6
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fmul v24.4s, v0.4s, v16.4s
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fmul v25.4s, v4.4s, v20.4s
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fmla v24.4s, v1.4s, v17.4s
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fmla v25.4s, v5.4s, v21.4s
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fmla v24.4s, v2.4s, v18.4s
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fmla v25.4s, v6.4s, v22.4s
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fmla v24.4s, v3.4s, v19.4s
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fmla v25.4s, v7.4s, v23.4s
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ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
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ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
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ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
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ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], x6
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fmul v26.4s, v0.4s, v16.4s
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fmul v27.4s, v4.4s, v20.4s
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fmla v26.4s, v1.4s, v17.4s
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fmla v27.4s, v5.4s, v21.4s
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fmla v26.4s, v2.4s, v18.4s
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fmla v27.4s, v6.4s, v22.4s
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fmla v26.4s, v3.4s, v19.4s
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fmla v27.4s, v7.4s, v23.4s
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faddp v0.4s, v24.4s, v25.4s
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faddp v1.4s, v26.4s, v27.4s
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faddp v0.4s, v0.4s, v1.4s
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fmul v1.4s, v0.4s, v30.4s
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ld2 {v4.4s,v5.4s}, [x2]
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fcvtns v4.4s, v1.4s
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fcmgt v2.4s, v0.4s, v28.4s
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fcmgt v3.4s, v29.4s, v0.4s
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add v2.4s, v2.4s, v3.4s
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add v31.4s, v31.4s, v2.4s
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st2 {v4.4s,v5.4s}, [x2], #32
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subs w4, w4, #1
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b.ne 2b
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AARCH64_DUP_2D(v0, v31, 1)
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add v0.4s, v0.4s, v31.4s
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AARCH64_DUP_4S(v1, v0, 1)
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add v0.4s, v0.4s, v1.4s
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umov w0, v0.s[0]
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neg w0, w0
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ret
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NONEXEC_STACK
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