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diff --git a/VERSION b/VERSION index 4adfbc3..dd0fe95 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -20.3.0 +20.3.1 diff --git a/docs/relnotes/20.3.0.rst b/docs/relnotes/20.3.0.rst index ca347ca..2de6a98 100644 --- a/docs/relnotes/20.3.0.rst +++ b/docs/relnotes/20.3.0.rst @@ -21,7 +21,7 @@ SHA256 checksum :: - TBD. + 2999738e888731531cd62b27519fa37566cc0ea2cd7d4d97f46abaa3e949c630 mesa-20.3.0.tar.xz New features diff --git a/docs/relnotes/20.3.1.rst b/docs/relnotes/20.3.1.rst new file mode 100644 index 0000000..bea77d3 --- /dev/null +++ b/docs/relnotes/20.3.1.rst @@ -0,0 +1,176 @@ +Mesa 20.3.1 Release Notes / 2020-12-16 +====================================== + +Mesa 20.3.1 is a bug fix release which fixes bugs found since the 20.3.0 release. + +Mesa 20.3.1 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 20.3.1 implements the Vulkan 1.2 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + TBD. + + +New features +------------ + +- None + + +Bug fixes +--------- + +- Crash and slowness in FreeCAD +- ci: Missing needs: in radeonsi-stoney-*? +- Triangles appear from the center of the field on PES2021 with Mesa 20.2.x +- \[gen9][iris][regression][bisected\] flaky piglit tests +- \[Intel][OpenGL\] Fail to get correct value when sampling from a texture in depth formats. +- Mesa 20.3.0 and older ATi/Radeon cards fails +- Storing pointer to temporary value inside the Iris driver. + + +Changes +------- + +Andrii Simiklit (1): + +- iris: update depth value for stages after fast clear depth + +Boris Brezillon (2): + +- panfrost: Make sure we always add a reader -\> write dependency when needed +- panfrost: Fix fencing + +Daniel Schürmann (1): + +- aco/ra: use get_reg_specified() for p_extract_vector + +Dave Airlie (1): + +- radeonsi: fix regression on gpus using the radeon winsys. + +Dylan Baker (11): + +- docs: Add sha256 sums for 20.3.0 +- .pick_status.json: Update to 872c4bcd27db7b7ca26abe9fc090ae26d502156f +- .pick_status.json: Mark a5e0a2e101bcda0132185a82c3e8c9b4c90ce94c as denominated +- .pick_status.json: Update to 72b68bd2a62d193e26bd6b31123182d7dbae3098 +- .pick_status.json: Update to ec3828add38a83b8c09fd5896265abc9d766162e +- .pick_status.json: Update to f93b7d14d66d8ba70d44772d1a1b6696310b7d17 +- .pick_status.json: Update to 3f0da800eb4b8184c24707c52d5a519abe948898 +- .pick_status.json: Update to cf3fc79cd0ab55776bbbabe76237c272ab07133e +- .pick_status.json: Update to 84c8a35aa2ca4d4de66192933735094ed07b4aaa +- .pick_status.json: Update to a7fb3954a1318a6b27e1405a9e799dd8f06eaa34 +- .pick_status.json: Update to ada9be1ec9e14fc045086411fbf2d3cb0efbbe2f + +Eric Anholt (2): + +- softpipe: Fix swizzled texture gather of int textures. +- nir: Redefine start/end_ip of blocks to fix NIR-to-TGSI liveness bugs. + +Erik Faye-Lund (3): + +- gallium: do not reset buffers for unsupported stages +- zink: fix channel ordering in format-mapping +- zink: fail if set failed to create + +Jonathan Gray (1): + +- aco: use UINT64_C on 64 bit constant arguments + +Jonathan Marek (4): + +- turnip: always emit LRZ draw state in DIRTY_DRAW_STATE path +- turnip: move up LRZ invalidate in CmdClearAttachments +- turnip: always set LRZ registers to zero for 3d clear/blit +- turnip: no linear_to_srgb for alpha channel for gmem clear value packing + +Lionel Landwerlin (1): + +- gallium/dri2: Don't forget protected content flag + +Marcin Ślusarz (1): + +- iris: store copy of the border color in the border color hash table + +Mauro Rossi (1): + +- android: spirv: fix '::' typo in gen rules + +Michel Dänzer (2): + +- ci: Drop x86_build_old image +- ci: .lava-test:amd64 template needs arm_build + +Mike Blumenkrantz (3): + +- zink: fix direct image mapping offset +- zink: really fix direct image mapping offset (I mean it this time) +- st/pbo: fix pbo uploads without PIPE_CAP_TGSI_VS_LAYER_VIEWPORT + +Nanley Chery (1): + +- iris: Fix resource ptr in resolve_sampler_views + +Pierre-Eric Pelloux-Prayer (1): + +- radeonsi: fix si_get_draw_start_count count value + +Rhys Perry (1): + +- aco: don't assume src=lower when splitting self-intersecting copies + +Robin Ole Heinemann (1): + +- anv: Add DRM_RDWR flag in anv_gem_handle_to_fd + +Samuel Pitoiset (9): + +- radv: mark GFX10.3 as a non-conformant Vulkan implementation +- radv: fix exporting multiviews with NGG +- radv: disable alphaToOne feature +- aco: fix combining max(-min(a, b), c) if a or b uses the neg modifier +- radv: ignore other blend targets if dual-source blending is enabled +- radv: disable SQTT support for unsupported GPUs +- radv: don't count unusable vertices to the NGG LDS size +- radv: fix applying the NGG minimum vertex count requirement +- radv: do VGT_FLUSH when switching NGG -\> legacy on Sienna Cichlid + +Simon Ser (1): + +- radv: fix access to uninitialized radeon_bo_metadata + +Tapani Pälli (1): + +- anv: fix calculation of buffer size in case dynamic size is used + +Timur Kristóf (1): + +- aco: Use program->num_waves as maximum in scheduler. + +Vinson Lee (1): + +- meson: Fix Clang microsoft-enum-value detection. + +Witold Baryluk (1): + +- zink: Cap PIPE_SHADER_CAP_MAX_CONST_BUFFERS to 32 + +cheyang (1): + +- android: fix build failure with libbacktrace + +yshi18 (1): + +- iris: fix memleak for query_buffer_uploader diff --git a/meson.build b/meson.build index b0107a2..c2843a3 100644 --- a/meson.build +++ b/meson.build @@ -1002,10 +1002,6 @@ if cc.get_id() == 'msvc' cpp_args += a endif endforeach - if cc.has_argument('-Wmicrosoft-enum-value') # Clang - c_args += '-Wno-microsoft-enum-value' - cpp_args += '-Wno-microsoft-enum-value' - endif else _trial = [ '-Werror=implicit-function-declaration', @@ -1074,6 +1070,11 @@ else cpp_msvc_compat_args += a endif endforeach + + if cc.has_argument('-Wmicrosoft-enum-value') # Clang + c_args += '-Wno-microsoft-enum-value' + cpp_args += '-Wno-microsoft-enum-value' + endif endif # set linker arguments diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index a321c56..bcd289f 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -808,7 +808,7 @@ void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode if (dst.size() == 1) bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp); else - bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp); + bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(UINT64_C(0x3FF0000000000000)), tmp); } else if (num_sources == 3) { bld.vop3(op, Definition(dst), src[0], src[1], src[2]); } else { @@ -1900,7 +1900,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src)); } else if (dst.regClass() == v2) { if (ctx->block->fp_mode.must_flush_denorms16_64) - src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src)); + src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(UINT64_C(0x3FF0000000000000)), as_vgpr(ctx, src)); Temp upper = bld.tmp(v1), lower = bld.tmp(v1); bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src); upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper); @@ -1922,7 +1922,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src)); } else if (dst.regClass() == v2) { if (ctx->block->fp_mode.must_flush_denorms16_64) - src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src)); + src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(UINT64_C(0x3FF0000000000000)), as_vgpr(ctx, src)); Temp upper = bld.tmp(v1), lower = bld.tmp(v1); bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src); upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper); diff --git a/src/amd/compiler/aco_lower_to_hw_instr.cpp b/src/amd/compiler/aco_lower_to_hw_instr.cpp index f7a4012..0c7ac00 100644 --- a/src/amd/compiler/aco_lower_to_hw_instr.cpp +++ b/src/amd/compiler/aco_lower_to_hw_instr.cpp @@ -1613,31 +1613,28 @@ void handle_operands(std::map& copy_map, lower_context* /* if this is self-intersecting, we have to split it because * self-intersecting swaps don't make sense */ - PhysReg lower = swap.def.physReg(); - PhysReg higher = swap.op.physReg(); - if (lower.reg_b > higher.reg_b) - std::swap(lower, higher); - if (higher.reg_b - lower.reg_b < (int)swap.bytes) { - unsigned offset = higher.reg_b - lower.reg_b; + PhysReg src = swap.op.physReg(), dst = swap.def.physReg(); + if (abs((int)src.reg_b - (int)dst.reg_b) < (int)swap.bytes) { + unsigned offset = abs((int)src.reg_b - (int)dst.reg_b); RegType type = swap.def.regClass().type(); copy_operation middle; - lower.reg_b += offset; - higher.reg_b += offset; + src.reg_b += offset; + dst.reg_b += offset; middle.bytes = swap.bytes - offset * 2; memcpy(middle.uses, swap.uses + offset, middle.bytes); - middle.op = Operand(lower, RegClass::get(type, middle.bytes)); - middle.def = Definition(higher, RegClass::get(type, middle.bytes)); - copy_map[higher] = middle; + middle.op = Operand(src, RegClass::get(type, middle.bytes)); + middle.def = Definition(dst, RegClass::get(type, middle.bytes)); + copy_map[dst] = middle; copy_operation end; - lower.reg_b += middle.bytes; - higher.reg_b += middle.bytes; + src.reg_b += middle.bytes; + dst.reg_b += middle.bytes; end.bytes = swap.bytes - (offset + middle.bytes); memcpy(end.uses, swap.uses + offset + middle.bytes, end.bytes); - end.op = Operand(lower, RegClass::get(type, end.bytes)); - end.def = Definition(higher, RegClass::get(type, end.bytes)); - copy_map[higher] = end; + end.op = Operand(src, RegClass::get(type, end.bytes)); + end.def = Definition(dst, RegClass::get(type, end.bytes)); + copy_map[dst] = end; memset(swap.uses + offset, 0, swap.bytes - offset); swap.bytes = offset; diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index 8b6b2f2..91ec841 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -2088,8 +2088,8 @@ bool combine_minmax(opt_ctx& ctx, aco_ptr& instr, aco_opcode opposi if (combine_three_valu_op(ctx, instr, instr->opcode, minmax3, "012", 1 | 2)) return true; - /* min(-max(a, b), c) -> min3(-a, -b, c) * - * max(-min(a, b), c) -> max3(-a, -b, c) */ + /* min(-max(a, b), c) -> min3(c, -a, -b) * + * max(-min(a, b), c) -> max3(c, -a, -b) */ for (unsigned swap = 0; swap < 2; swap++) { Operand operands[3]; bool neg[3], abs[3], clamp, precise; @@ -2101,8 +2101,8 @@ bool combine_minmax(opt_ctx& ctx, aco_ptr& instr, aco_opcode opposi &clamp, &omod, &inbetween_neg, NULL, NULL, &precise) && inbetween_neg) { ctx.uses[instr->operands[swap].tempId()]--; - neg[1] = true; - neg[2] = true; + neg[1] = !neg[1]; + neg[2] = !neg[2]; create_vop3_for_op3(ctx, minmax3, instr, operands, neg, abs, opsel, clamp, omod); return true; } diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index 39c7842..3cf0153 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -2202,14 +2202,10 @@ void register_allocation(Program *program, std::vector& live_out_per_bloc !register_file.test(reg, definition->bytes())) definition->setFixed(reg); } else if (instr->opcode == aco_opcode::p_extract_vector) { - PhysReg reg; - if (instr->operands[0].isKillBeforeDef() && - instr->operands[0].getTemp().type() == definition->getTemp().type()) { - reg = instr->operands[0].physReg(); - reg.reg_b += definition->bytes() * instr->operands[1].constantValue(); - assert(!register_file.test(reg, definition->bytes())); + PhysReg reg = instr->operands[0].physReg(); + reg.reg_b += definition->bytes() * instr->operands[1].constantValue(); + if (get_reg_specified(ctx, register_file, definition->regClass(), parallelcopy, instr, reg)) definition->setFixed(reg); - } } else if (instr->opcode == aco_opcode::p_create_vector) { PhysReg reg = get_reg_create_vector(ctx, register_file, definition->getTemp(), parallelcopy, instr); diff --git a/src/amd/compiler/aco_scheduler.cpp b/src/amd/compiler/aco_scheduler.cpp index 1ad01cb..1c6060a 100644 --- a/src/amd/compiler/aco_scheduler.cpp +++ b/src/amd/compiler/aco_scheduler.cpp @@ -910,9 +910,9 @@ void schedule_program(Program *program, live& live_vars) else ctx.num_waves = 7; ctx.num_waves = std::max(ctx.num_waves, program->min_waves); - ctx.num_waves = std::min(ctx.num_waves, program->max_waves); + ctx.num_waves = std::min(ctx.num_waves, program->num_waves); - assert(ctx.num_waves > 0 && ctx.num_waves <= program->num_waves); + assert(ctx.num_waves > 0); ctx.mv.max_registers = { int16_t(get_addr_vgpr_from_waves(program, ctx.num_waves) - 2), int16_t(get_addr_sgpr_from_waves(program, ctx.num_waves))}; diff --git a/src/amd/compiler/tests/test_optimizer.cpp b/src/amd/compiler/tests/test_optimizer.cpp index c6bff37..aee66c2 100644 --- a/src/amd/compiler/tests/test_optimizer.cpp +++ b/src/amd/compiler/tests/test_optimizer.cpp @@ -257,3 +257,26 @@ BEGIN_TEST(optimize.add3) finish_opt_test(); END_TEST + +BEGIN_TEST(optimize.minmax) + for (unsigned i = GFX8; i <= GFX10; i++) { + //>> v1: %a, s2: %_:exec = p_startpgm + if (!setup_cs("v1", (chip_class)i)) + continue; + + //! v1: %res0 = v_max3_f32 0, -0, %a + //! p_unit_test 0, %res0 + Temp xor0 = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), Operand(inputs[0])); + Temp min = bld.vop2(aco_opcode::v_min_f32, bld.def(v1), Operand(0u), xor0); + Temp xor1 = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), min); + writeout(0, bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), xor1)); + + //! v1: %res1 = v_max3_f32 0, -0, -%a + //! p_unit_test 1, %res1 + min = bld.vop2(aco_opcode::v_min_f32, bld.def(v1), Operand(0u), Operand(inputs[0])); + xor1 = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), min); + writeout(1, bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), xor1)); + + finish_opt_test(); + } +END_TEST diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 6b02bd5..25718e4 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4254,14 +4254,15 @@ void radv_CmdBindPipeline( /* Prefetch all pipeline shaders at first draw time. */ cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS; - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 && + if ((cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 || + cmd_buffer->device->physical_device->rad_info.family == CHIP_SIENNA_CICHLID) && cmd_buffer->state.emitted_pipeline && radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) && !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) { /* Transitioning from NGG to legacy GS requires - * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted - * at the beginning of IBs when legacy GS ring pointers - * are set. + * VGT_FLUSH on GFX10 and Sienna Cichlid. VGT_FLUSH + * is also emitted at the beginning of IBs when legacy + * GS ring pointers are set. */ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH; } diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 4801cbb..c606423 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -406,7 +406,8 @@ radv_physical_device_try_create(struct radv_instance *instance, disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2); device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags); - if (device->rad_info.chip_class < GFX8) + if (device->rad_info.chip_class < GFX8 || + device->rad_info.chip_class > GFX10) fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n"); radv_get_driver_uuid(&device->driver_uuid); @@ -977,7 +978,7 @@ void radv_GetPhysicalDeviceFeatures( .depthBounds = true, .wideLines = true, .largePoints = true, - .alphaToOne = true, + .alphaToOne = false, .multiViewport = true, .samplerAnisotropy = true, .textureCompressionETC2 = radv_device_supports_etc(pdevice), @@ -2855,6 +2856,12 @@ VkResult radv_CreateDevice( abort(); } + if (device->physical_device->rad_info.chip_class > GFX10) { + fprintf(stderr, "radv: Thread trace is not supported " + "for that GPU!\n"); + exit(1); + } + /* Default buffer size set to 1MB per SE. */ device->thread_trace_buffer_size = radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024); @@ -5140,9 +5147,8 @@ bool radv_get_memory_fd(struct radv_device *device, { struct radeon_bo_metadata metadata; - if (memory->image) { - if (memory->image->tiling != VK_IMAGE_TILING_LINEAR) - radv_init_metadata(device, memory->image, &metadata); + if (memory->image && memory->image->tiling != VK_IMAGE_TILING_LINEAR) { + radv_init_metadata(device, memory->image, &metadata); device->ws->buffer_set_metadata(memory->bo, &metadata); } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index f480a57..ee4dbba 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -555,8 +555,10 @@ radv_pipeline_compute_spi_color_formats(const struct radv_pipeline *pipeline, /* The output for dual source blending should have the same format as * the first output. */ - if (blend->mrt0_is_dual_src) + if (blend->mrt0_is_dual_src) { + assert(!(col_format >> 4)); col_format |= (col_format & 0xf) << 4; + } blend->spi_shader_col_format = col_format; blend->col_format_is_int8 = is_int8; @@ -684,6 +686,12 @@ radv_pipeline_init_blend_state(const struct radv_pipeline *pipeline, if (!att->colorWriteMask) continue; + /* Ignore other blend targets if dual-source blending + * is enabled to prevent wrong behaviour. + */ + if (blend.mrt0_is_dual_src) + continue; + blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i); blend.cb_target_enabled_4bit |= 0xfu << (4 * i); if (!att->blendEnable) { @@ -2073,21 +2081,33 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, (max_lds_size - max_gsprims * gsprim_lds_size) / esvert_lds_size); max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim); + /* Hardware restriction: minimum value of max_esverts */ + max_esverts = MAX2(max_esverts, min_esverts - 1 + max_verts_per_prim); max_gsprims = align(max_gsprims, wavesize); max_gsprims = MIN2(max_gsprims, max_gsprims_base); - if (gsprim_lds_size) - max_gsprims = MIN2(max_gsprims, - (max_lds_size - max_esverts * esvert_lds_size) / - gsprim_lds_size); + if (gsprim_lds_size) { + /* Don't count unusable vertices to the LDS + * size. Those are vertices above the maximum + * number of vertices that can occur in the + * workgroup, which is e.g. max_gsprims * 3 + * for triangles. + */ + unsigned usable_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim); + max_gsprims = + MIN2(max_gsprims, (max_lds_size - usable_esverts * esvert_lds_size) / gsprim_lds_size); + } clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency); assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1); } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims); - } - /* Hardware restriction: minimum value of max_esverts */ - max_esverts = MAX2(max_esverts, min_esverts - 1 + max_verts_per_prim); + /* Verify the restriction. */ + assert(max_esverts >= min_esverts - 1 + max_verts_per_prim); + } else { + /* Hardware restriction: minimum value of max_esverts */ + max_esverts = MAX2(max_esverts, min_esverts - 1 + max_verts_per_prim); + } unsigned max_out_vertices = max_vert_out_per_gs_instance ? gs_info->gs.vertices_out : @@ -2114,7 +2134,10 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, ngg->prim_amp_factor = prim_amp_factor; ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance; ngg->ngg_emit_size = max_gsprims * gsprim_lds_size; - ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size; + + /* Don't count unusable vertices. */ + ngg->esgs_ring_size = + MIN2(max_esverts, max_gsprims * max_verts_per_prim) * esvert_lds_size * 4; if (gs_type == MESA_SHADER_GEOMETRY) { ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4; diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index c6070df..ef6e170 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -89,11 +89,16 @@ static bool needs_view_index_sgpr(struct radv_shader_args *args, if (args->shader_info->needs_multiview_view_index || (!args->options->key.vs_common_out.as_es && args->options->key.has_multiview_view_index)) return true; break; - case MESA_SHADER_GEOMETRY: case MESA_SHADER_TESS_CTRL: if (args->shader_info->needs_multiview_view_index) return true; break; + case MESA_SHADER_GEOMETRY: + if (args->shader_info->needs_multiview_view_index || + (args->options->key.vs_common_out.as_ngg && + args->options->key.has_multiview_view_index)) + return true; + break; default: break; } diff --git a/src/compiler/Android.nir.gen.mk b/src/compiler/Android.nir.gen.mk index 2d2f772..1598261 100644 --- a/src/compiler/Android.nir.gen.mk +++ b/src/compiler/Android.nir.gen.mk @@ -100,11 +100,11 @@ $(intermediates)/spirv/spirv_info.c: $(LOCAL_PATH)/spirv/spirv_info_c.py $(LOCAL @mkdir -p $(dir $@) $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false) -$(intermediates)/spirv/vtn_gather_types.c:: $(LOCAL_PATH)/spirv/vtn_gather_types_c.py $(LOCAL_PATH)/spirv/spirv.core.grammar.json +$(intermediates)/spirv/vtn_gather_types.c: $(LOCAL_PATH)/spirv/vtn_gather_types_c.py $(LOCAL_PATH)/spirv/spirv.core.grammar.json @mkdir -p $(dir $@) $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false) -$(intermediates)/spirv/vtn_generator_ids.h:: $(LOCAL_PATH)/spirv/vtn_generator_ids_h.py $(LOCAL_PATH)/spirv/spir-v.xml +$(intermediates)/spirv/vtn_generator_ids.h: $(LOCAL_PATH)/spirv/vtn_generator_ids_h.py $(LOCAL_PATH)/spirv/spir-v.xml @mkdir -p $(dir $@) $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false) diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c index acedb05..2d1478f 100644 --- a/src/compiler/nir/nir.c +++ b/src/compiler/nir/nir.c @@ -1945,12 +1945,12 @@ nir_index_instrs(nir_function_impl *impl) unsigned index = 0; nir_foreach_block(block, impl) { - block->start_ip = index; + block->start_ip = index++; nir_foreach_instr(instr, block) instr->index = index++; - block->end_ip = index; + block->end_ip = index++; } return index; diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 9365c16..3979b6b 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -2796,15 +2796,13 @@ typedef struct nir_block { uint32_t dom_pre_index, dom_post_index; /** - * nir_instr->index for the first nir_instr in the block. If the block is - * empty, it will be the index of the immediately previous instr, or 0. - * Valid when the impl has nir_metadata_instr_index. + * Value just before the first nir_instr->index in the block, but after + * end_ip that of any predecessor block. */ uint32_t start_ip; /** - * nir_instr->index for the last nir_instr in the block. If the block is - * empty, it will be the same as start_ip. Valid when the impl has - * nir_metadata_instr_index. + * Value just after the last nir_instr->index in the block, but before the + * start_ip of any successor block. */ uint32_t end_ip; diff --git a/src/compiler/nir/nir_liveness.c b/src/compiler/nir/nir_liveness.c index 8ed6d84..04a00cb 100644 --- a/src/compiler/nir/nir_liveness.c +++ b/src/compiler/nir/nir_liveness.c @@ -326,36 +326,32 @@ nir_live_ssa_defs_per_instr(nir_function_impl *impl) for (int i = 0; i < impl->ssa_alloc; i++) liveness->defs->start = ~0; - unsigned last_instr = 0; nir_foreach_block(block, impl) { unsigned index; BITSET_FOREACH_SET(index, block->live_in, impl->ssa_alloc) { liveness->defs[index].start = MIN2(liveness->defs[index].start, - last_instr); + block->start_ip); } nir_foreach_instr(instr, block) { nir_foreach_ssa_def(instr, def_cb, liveness); - - last_instr = instr->index; }; /* track an if src's use. We need to make sure that our value is live * across the if reference, where we don't have an instr->index - * representing the use. Mark it as live through the next real - * instruction. + * representing the use. Mark it as live through the end of the block. */ nir_if *nif = nir_block_get_following_if(block); if (nif) { if (nif->condition.is_ssa) { liveness->defs[nif->condition.ssa->index].end = MAX2( - liveness->defs[nif->condition.ssa->index].end, - last_instr + 1); + liveness->defs[nif->condition.ssa->index].end, block->end_ip); } } BITSET_FOREACH_SET(index, block->live_out, impl->ssa_alloc) { - liveness->defs[index].end = MAX2(liveness->defs[index].end, last_instr); + liveness->defs[index].end = MAX2(liveness->defs[index].end, + block->end_ip); } } diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c index ff3f42e..30994be 100644 --- a/src/freedreno/vulkan/tu_clear_blit.c +++ b/src/freedreno/vulkan/tu_clear_blit.c @@ -785,6 +785,9 @@ r3d_setup(struct tu_cmd_buffer *cmd, tu_cs_emit_regs(cs, A6XX_RB_SRGB_CNTL(vk_format_is_srgb(vk_format))); tu_cs_emit_regs(cs, A6XX_SP_SRGB_CNTL(vk_format_is_srgb(vk_format))); + tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0)); + tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0)); + if (cmd->state.predication_active) { tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_LOCAL, 1); tu_cs_emit(cs, 0); @@ -1905,10 +1908,8 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd, .component_enable = COND(clear_rts & (1 << i), 0xf))); } - if (z_clear) { - tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0)); - tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0)); - } + tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0)); + tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0)); tu_cs_emit_regs(cs, A6XX_RB_DEPTH_PLANE_CNTL()); tu_cs_emit_regs(cs, A6XX_RB_DEPTH_CNTL( @@ -1982,7 +1983,7 @@ pack_gmem_clear_value(const VkClearValue *val, VkFormat format, uint32_t clear_v float tmp[4]; memcpy(tmp, val->color.float32, 4 * sizeof(float)); if (vk_format_is_srgb(format)) { - for (int i = 0; i < 4; i++) + for (int i = 0; i < 3; i++) tmp[i] = util_format_linear_to_srgb_float(tmp[i]); } @@ -2135,6 +2136,13 @@ tu_CmdClearAttachments(VkCommandBuffer commandBuffer, */ tu_emit_cache_flush_renderpass(cmd, cs); + for (uint32_t j = 0; j < attachmentCount; j++) { + if ((pAttachments[j].aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) == 0) + continue; + cmd->state.lrz.valid = false; + cmd->state.dirty |= TU_CMD_DIRTY_LRZ; + } + /* vkCmdClearAttachments is supposed to respect the predicate if active. * The easiest way to do this is to always use the 3d path, which always * works even with GMEM because it's just a simple draw using the existing @@ -2158,13 +2166,6 @@ tu_CmdClearAttachments(VkCommandBuffer commandBuffer, tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM); tu_clear_sysmem_attachments(cmd, attachmentCount, pAttachments, rectCount, pRects); tu_cond_exec_end(cs); - - for (uint32_t j = 0; j < attachmentCount; j++) { - if ((pAttachments[j].aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) == 0) - continue; - cmd->state.lrz.valid = false; - cmd->state.dirty |= TU_CMD_DIRTY_LRZ; - } } static void diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index dfcaca9..9ab2c2f 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -3340,8 +3340,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd, tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, pipeline->load_state); tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers); tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params); - if (cmd->state.dirty & TU_CMD_DIRTY_LRZ) - tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ, cmd->state.lrz.state); + tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ, cmd->state.lrz.state); for (uint32_t i = 0; i < ARRAY_SIZE(cmd->state.dynamic_state); i++) { tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i, diff --git a/src/gallium/auxiliary/Android.mk b/src/gallium/auxiliary/Android.mk index 664742f..57efc0e 100644 --- a/src/gallium/auxiliary/Android.mk +++ b/src/gallium/auxiliary/Android.mk @@ -36,7 +36,9 @@ LOCAL_SRC_FILES := \ $(VL_STUB_SOURCES) ifeq ($(USE_LIBBACKTRACE),true) - LOCAL_SRC_FILES += util/u_debug_stack_android.cpp + LOCAL_CFLAGS += -DHAVE_ANDROID_PLATFORM + LOCAL_SHARED_LIBRARIES += libbacktrace + LOCAL_SRC_FILES += ../../util/u_debug_stack_android.cpp endif LOCAL_C_INCLUDES := \ diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c b/src/gallium/auxiliary/cso_cache/cso_context.c index eda13c4..1eef6aa 100644 --- a/src/gallium/auxiliary/cso_cache/cso_context.c +++ b/src/gallium/auxiliary/cso_cache/cso_context.c @@ -376,6 +376,24 @@ void cso_destroy_context( struct cso_context *ctx ) struct pipe_screen *scr = ctx->pipe->screen; enum pipe_shader_type sh; for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) { + switch (sh) { + case PIPE_SHADER_GEOMETRY: + if (!ctx->has_geometry_shader) + continue; + break; + case PIPE_SHADER_TESS_CTRL: + case PIPE_SHADER_TESS_EVAL: + if (!ctx->has_tessellation) + continue; + break; + case PIPE_SHADER_COMPUTE: + if (!ctx->has_compute_shader) + continue; + break; + default: + break; + } + int maxsam = scr->get_shader_param(scr, sh, PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS); int maxview = scr->get_shader_param(scr, sh, @@ -387,6 +405,7 @@ void cso_destroy_context( struct cso_context *ctx ) assert(maxsam <= PIPE_MAX_SAMPLERS); assert(maxview <= PIPE_MAX_SHADER_SAMPLER_VIEWS); assert(maxssbo <= PIPE_MAX_SHADER_BUFFERS); + assert(maxcb <= PIPE_MAX_CONSTANT_BUFFERS); if (maxsam > 0) { ctx->pipe->bind_sampler_states(ctx->pipe, sh, 0, maxsam, zeros); } diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index d74eafd..7d23ab0 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -48,6 +48,9 @@ struct ntt_compile { unsigned loop_label; + /* if condition set up at the end of a block, for ntt_emit_if(). */ + struct ureg_src if_cond; + /* TGSI temps for our NIR SSA and register values. */ struct ureg_dst *reg_temp; struct ureg_dst *ssa_temp; @@ -2046,7 +2049,7 @@ static void ntt_emit_if(struct ntt_compile *c, nir_if *if_stmt) { unsigned label; - ureg_UIF(c->ureg, ntt_get_src(c, if_stmt->condition), &label); + ureg_UIF(c->ureg, c->if_cond, &label); ntt_emit_cf_list(c, &if_stmt->then_list); if (!exec_list_is_empty(&if_stmt->else_list)) { @@ -2116,6 +2119,15 @@ ntt_emit_block(struct ntt_compile *c, nir_block *block) nir_foreach_src(instr, ntt_src_live_interval_end_cb, c); } + /* Set up the if condition for ntt_emit_if(), which we have to do before + * freeing up the temps (the "if" is treated as inside the block for liveness + * purposes, despite not being an instruction) + */ + nir_if *nif = nir_block_get_following_if(block); + if (nif) + c->if_cond = ntt_get_src(c, nif->condition); + + /* Free up any SSA temps that are unused at the end of the block. */ unsigned index; BITSET_FOREACH_SET(index, block->live_out, BITSET_WORDS(c->impl->ssa_alloc)) { unsigned def_end_ip = c->liveness->defs[index].end; diff --git a/src/gallium/drivers/iris/iris_border_color.c b/src/gallium/drivers/iris/iris_border_color.c index ebed3e4..5f6bea9 100644 --- a/src/gallium/drivers/iris/iris_border_color.c +++ b/src/gallium/drivers/iris/iris_border_color.c @@ -147,7 +147,7 @@ iris_upload_border_color(struct iris_context *ice, memcpy(pool->map + offset, color, sizeof(*color)); pool->insert_point += BC_ALIGNMENT; - _mesa_hash_table_insert_pre_hashed(pool->ht, hash, color, + _mesa_hash_table_insert_pre_hashed(pool->ht, hash, pool->map + offset, (void *) (uintptr_t) offset); return offset; } diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c index 9be44e4..ff91030 100644 --- a/src/gallium/drivers/iris/iris_clear.c +++ b/src/gallium/drivers/iris/iris_clear.c @@ -545,6 +545,7 @@ fast_clear_depth(struct iris_context *ice, iris_resource_set_aux_state(ice, res, level, box->z, box->depth, ISL_AUX_STATE_CLEAR); ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER; + ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS; } static void diff --git a/src/gallium/drivers/iris/iris_query.c b/src/gallium/drivers/iris/iris_query.c index ef46158..548ce53 100644 --- a/src/gallium/drivers/iris/iris_query.c +++ b/src/gallium/drivers/iris/iris_query.c @@ -484,6 +484,7 @@ iris_destroy_query(struct pipe_context *ctx, struct pipe_query *p_query) iris_syncobj_reference(screen, &query->syncobj, NULL); screen->base.fence_reference(ctx->screen, &query->fence, NULL); } + pipe_resource_reference(&query->query_state_ref.res, NULL); free(query); } diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 5e924ad..276ad62 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -94,7 +94,7 @@ resolve_sampler_views(struct iris_context *ice, while (views) { const int i = u_bit_scan(&views); struct iris_sampler_view *isv = shs->textures[i]; - struct iris_resource *res = (void *) isv->base.texture; + struct iris_resource *res = isv->res; if (res->base.target != PIPE_BUFFER) { if (consider_framebuffer) { diff --git a/src/gallium/drivers/panfrost/pan_compute.c b/src/gallium/drivers/panfrost/pan_compute.c index e1044cc..a8c3ca3 100644 --- a/src/gallium/drivers/panfrost/pan_compute.c +++ b/src/gallium/drivers/panfrost/pan_compute.c @@ -156,7 +156,7 @@ panfrost_launch_grid(struct pipe_context *pipe, panfrost_add_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_COMPUTE, true, 0, &t, true); - panfrost_flush_all_batches(ctx, 0); + panfrost_flush_all_batches(ctx); } static void diff --git a/src/gallium/drivers/panfrost/pan_context.c b/src/gallium/drivers/panfrost/pan_context.c index c451bd7..11f6d34 100644 --- a/src/gallium/drivers/panfrost/pan_context.c +++ b/src/gallium/drivers/panfrost/pan_context.c @@ -160,16 +160,13 @@ panfrost_flush( { struct panfrost_context *ctx = pan_context(pipe); struct panfrost_device *dev = pan_device(pipe->screen); - uint32_t syncobj = 0; - if (fence) - drmSyncobjCreate(dev->fd, 0, &syncobj); /* Submit all pending jobs */ - panfrost_flush_all_batches(ctx, syncobj); + panfrost_flush_all_batches(ctx); if (fence) { - struct panfrost_fence *f = panfrost_fence_create(ctx, syncobj); + struct panfrost_fence *f = panfrost_fence_create(ctx); pipe->screen->fence_reference(pipe->screen, fence, NULL); *fence = (struct pipe_fence_handle *)f; } @@ -182,7 +179,7 @@ static void panfrost_texture_barrier(struct pipe_context *pipe, unsigned flags) { struct panfrost_context *ctx = pan_context(pipe); - panfrost_flush_all_batches(ctx, 0); + panfrost_flush_all_batches(ctx); } #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c; @@ -1428,7 +1425,7 @@ panfrost_get_query_result(struct pipe_context *pipe, case PIPE_QUERY_PRIMITIVES_GENERATED: case PIPE_QUERY_PRIMITIVES_EMITTED: - panfrost_flush_all_batches(ctx, 0); + panfrost_flush_all_batches(ctx); vresult->u64 = query->end - query->start; break; @@ -1616,5 +1613,13 @@ panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags) ctx->sample_mask = ~0; ctx->active_queries = true; + int ASSERTED ret; + + /* Create a syncobj in a signaled state. Will be updated to point to the + * last queued job out_sync every time we submit a new job. + */ + ret = drmSyncobjCreate(dev->fd, DRM_SYNCOBJ_CREATE_SIGNALED, &ctx->syncobj); + assert(!ret && ctx->syncobj); + return gallium; } diff --git a/src/gallium/drivers/panfrost/pan_context.h b/src/gallium/drivers/panfrost/pan_context.h index e607b82..2a4bfd9 100644 --- a/src/gallium/drivers/panfrost/pan_context.h +++ b/src/gallium/drivers/panfrost/pan_context.h @@ -109,6 +109,9 @@ struct panfrost_context { * size from the kernel is 4kb */ struct u_upload_mgr *state_uploader; + /* Sync obj used to keep track of in-flight jobs. */ + uint32_t syncobj; + /* Bound job batch and map of panfrost_batch_key to job batches */ struct panfrost_batch *batch; struct hash_table *batches; diff --git a/src/gallium/drivers/panfrost/pan_job.c b/src/gallium/drivers/panfrost/pan_job.c index e226b4c..eec81a9 100644 --- a/src/gallium/drivers/panfrost/pan_job.c +++ b/src/gallium/drivers/panfrost/pan_job.c @@ -46,7 +46,7 @@ * better GPU utilization. * * Each accessed BO has a corresponding entry in the ->accessed_bos hash table. - * A BO is either being written or read at any time (see if writer != NULL). + * A BO is either being written or read at any time (see last_is_write). * When the last access is a write, the batch writing the BO might have read * dependencies (readers that have not been executed yet and want to read the * previous BO content), and when the last access is a read, all readers might @@ -60,6 +60,7 @@ struct panfrost_bo_access { struct util_dynarray readers; struct panfrost_batch_fence *writer; + bool last_is_write; }; static struct panfrost_batch_fence * @@ -399,7 +400,7 @@ panfrost_batch_update_bo_access(struct panfrost_batch *batch, entry = _mesa_hash_table_search(ctx->accessed_bos, bo); access = entry ? entry->data : NULL; if (access) { - old_writes = access->writer != NULL; + old_writes = access->last_is_write; } else { access = rzalloc(ctx, struct panfrost_bo_access); util_dynarray_init(&access->readers, access); @@ -479,7 +480,6 @@ panfrost_batch_update_bo_access(struct panfrost_batch *batch, util_dynarray_append(&access->readers, struct panfrost_batch_fence *, batch->out_sync); - access->writer = NULL; } } else { /* We already accessed this BO before, so we should already be @@ -504,6 +504,8 @@ panfrost_batch_update_bo_access(struct panfrost_batch *batch, if (access->writer) panfrost_batch_add_dep(batch, access->writer); } + + access->last_is_write = writes; } void @@ -936,6 +938,7 @@ static int panfrost_batch_submit_ioctl(struct panfrost_batch *batch, mali_ptr first_job_desc, uint32_t reqs, + uint32_t in_sync, uint32_t out_sync) { struct panfrost_context *ctx = batch->ctx; @@ -950,16 +953,16 @@ panfrost_batch_submit_ioctl(struct panfrost_batch *batch, * after we're done but preventing double-frees if we were given a * syncobj */ - bool our_sync = false; - - if (!out_sync && dev->debug & (PAN_DBG_TRACE | PAN_DBG_SYNC)) { - drmSyncobjCreate(dev->fd, 0, &out_sync); - our_sync = true; - } + if (!out_sync && dev->debug & (PAN_DBG_TRACE | PAN_DBG_SYNC)) + out_sync = ctx->syncobj; submit.out_sync = out_sync; submit.jc = first_job_desc; submit.requirements = reqs; + if (in_sync) { + submit.in_syncs = (u64)(uintptr_t)(&in_sync); + submit.in_sync_count = 1; + } bo_handles = calloc(panfrost_pool_num_bos(&batch->pool) + panfrost_pool_num_bos(&batch->invisible_pool) + @@ -987,9 +990,6 @@ panfrost_batch_submit_ioctl(struct panfrost_batch *batch, if (dev->debug & PAN_DBG_MSGS) fprintf(stderr, "Error submitting: %m\n"); - if (our_sync) - drmSyncobjDestroy(dev->fd, out_sync); - return errno; } @@ -1004,10 +1004,6 @@ panfrost_batch_submit_ioctl(struct panfrost_batch *batch, pandecode_jc(submit.jc, dev->quirks & IS_BIFROST, dev->gpu_id, minimal); } - /* Cleanup if we created the syncobj */ - if (our_sync) - drmSyncobjDestroy(dev->fd, out_sync); - return 0; } @@ -1016,7 +1012,7 @@ panfrost_batch_submit_ioctl(struct panfrost_batch *batch, * implicit dep between them) */ static int -panfrost_batch_submit_jobs(struct panfrost_batch *batch, uint32_t out_sync) +panfrost_batch_submit_jobs(struct panfrost_batch *batch, uint32_t in_sync, uint32_t out_sync) { bool has_draws = batch->scoreboard.first_job; bool has_frag = batch->scoreboard.tiler_dep || batch->clear; @@ -1024,7 +1020,7 @@ panfrost_batch_submit_jobs(struct panfrost_batch *batch, uint32_t out_sync) if (has_draws) { ret = panfrost_batch_submit_ioctl(batch, batch->scoreboard.first_job, - 0, has_frag ? 0 : out_sync); + 0, in_sync, has_frag ? 0 : out_sync); assert(!ret); } @@ -1039,7 +1035,8 @@ panfrost_batch_submit_jobs(struct panfrost_batch *batch, uint32_t out_sync) mali_ptr fragjob = panfrost_fragment_job(batch, batch->scoreboard.tiler_dep != 0); ret = panfrost_batch_submit_ioctl(batch, fragjob, - PANFROST_JD_REQ_FS, out_sync); + PANFROST_JD_REQ_FS, 0, + out_sync); assert(!ret); } @@ -1047,7 +1044,8 @@ panfrost_batch_submit_jobs(struct panfrost_batch *batch, uint32_t out_sync) } static void -panfrost_batch_submit(struct panfrost_batch *batch, uint32_t out_sync) +panfrost_batch_submit(struct panfrost_batch *batch, + uint32_t in_sync, uint32_t out_sync) { assert(batch); struct panfrost_device *dev = pan_device(batch->ctx->base.screen); @@ -1057,17 +1055,14 @@ panfrost_batch_submit(struct panfrost_batch *batch, uint32_t out_sync) util_dynarray_foreach(&batch->dependencies, struct panfrost_batch_fence *, dep) { if ((*dep)->batch) - panfrost_batch_submit((*dep)->batch, 0); + panfrost_batch_submit((*dep)->batch, 0, 0); } int ret; /* Nothing to do! */ - if (!batch->scoreboard.first_job && !batch->clear) { - if (out_sync) - drmSyncobjSignal(dev->fd, &out_sync, 1); + if (!batch->scoreboard.first_job && !batch->clear) goto out; - } panfrost_batch_draw_wallpaper(batch); @@ -1090,7 +1085,7 @@ panfrost_batch_submit(struct panfrost_batch *batch, uint32_t out_sync) panfrost_scoreboard_initialize_tiler(&batch->pool, &batch->scoreboard, polygon_list); - ret = panfrost_batch_submit_jobs(batch, out_sync); + ret = panfrost_batch_submit_jobs(batch, in_sync, out_sync); if (ret && dev->debug & PAN_DBG_MSGS) fprintf(stderr, "panfrost_batch_submit failed: %d\n", ret); @@ -1120,16 +1115,16 @@ out: /* Submit all batches, applying the out_sync to the currently bound batch */ void -panfrost_flush_all_batches(struct panfrost_context *ctx, uint32_t out_sync) +panfrost_flush_all_batches(struct panfrost_context *ctx) { struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - panfrost_batch_submit(batch, out_sync); + panfrost_batch_submit(batch, ctx->syncobj, ctx->syncobj); hash_table_foreach(ctx->batches, hentry) { struct panfrost_batch *batch = hentry->data; assert(batch); - panfrost_batch_submit(batch, 0); + panfrost_batch_submit(batch, ctx->syncobj, ctx->syncobj); } assert(!ctx->batches->entries); @@ -1178,7 +1173,7 @@ panfrost_flush_batches_accessing_bo(struct panfrost_context *ctx, return; if (access->writer && access->writer->batch) - panfrost_batch_submit(access->writer->batch, 0); + panfrost_batch_submit(access->writer->batch, ctx->syncobj, ctx->syncobj); if (!flush_readers) return; @@ -1186,7 +1181,7 @@ panfrost_flush_batches_accessing_bo(struct panfrost_context *ctx, util_dynarray_foreach(&access->readers, struct panfrost_batch_fence *, reader) { if (*reader && (*reader)->batch) - panfrost_batch_submit((*reader)->batch, 0); + panfrost_batch_submit((*reader)->batch, ctx->syncobj, ctx->syncobj); } } diff --git a/src/gallium/drivers/panfrost/pan_job.h b/src/gallium/drivers/panfrost/pan_job.h index 69c30a4..6a905ee 100644 --- a/src/gallium/drivers/panfrost/pan_job.h +++ b/src/gallium/drivers/panfrost/pan_job.h @@ -157,7 +157,7 @@ panfrost_batch_create_bo(struct panfrost_batch *batch, size_t size, uint32_t create_flags, uint32_t access_flags); void -panfrost_flush_all_batches(struct panfrost_context *ctx, uint32_t out_sync); +panfrost_flush_all_batches(struct panfrost_context *ctx); bool panfrost_pending_batches_access_bo(struct panfrost_context *ctx, diff --git a/src/gallium/drivers/panfrost/pan_screen.c b/src/gallium/drivers/panfrost/pan_screen.c index 54ab84c..85e2646 100644 --- a/src/gallium/drivers/panfrost/pan_screen.c +++ b/src/gallium/drivers/panfrost/pan_screen.c @@ -670,17 +670,51 @@ panfrost_fence_finish(struct pipe_screen *pscreen, } struct panfrost_fence * -panfrost_fence_create(struct panfrost_context *ctx, - uint32_t syncobj) +panfrost_fence_create(struct panfrost_context *ctx) { struct panfrost_fence *f = calloc(1, sizeof(*f)); if (!f) return NULL; + struct panfrost_device *dev = pan_device(ctx->base.screen); + int fd = -1, ret; + + /* Snapshot the last rendering out fence. We'd rather have another + * syncobj instead of a sync file, but this is all we get. + * (HandleToFD/FDToHandle just gives you another syncobj ID for the + * same syncobj). + */ + ret = drmSyncobjExportSyncFile(dev->fd, ctx->syncobj, &fd); + if (ret || fd == -1) { + fprintf(stderr, "export failed\n"); + goto err_free_fence; + } + + ret = drmSyncobjCreate(dev->fd, 0, &f->syncobj); + if (ret) { + fprintf(stderr, "create syncobj failed\n"); + goto err_close_fd; + } + + ret = drmSyncobjImportSyncFile(dev->fd, f->syncobj, fd); + if (ret) { + fprintf(stderr, "create syncobj failed\n"); + goto err_destroy_syncobj; + } + + assert(f->syncobj != ctx->syncobj); + close(fd); pipe_reference_init(&f->reference, 1); - f->syncobj = syncobj; return f; + +err_destroy_syncobj: + drmSyncobjDestroy(dev->fd, f->syncobj); +err_close_fd: + close(fd); +err_free_fence: + free(f); + return NULL; } static const void * diff --git a/src/gallium/drivers/panfrost/pan_screen.h b/src/gallium/drivers/panfrost/pan_screen.h index 6730bae..259773d 100644 --- a/src/gallium/drivers/panfrost/pan_screen.h +++ b/src/gallium/drivers/panfrost/pan_screen.h @@ -62,6 +62,6 @@ pan_device(struct pipe_screen *p) } struct panfrost_fence * -panfrost_fence_create(struct panfrost_context *ctx, uint32_t syncobj); +panfrost_fence_create(struct panfrost_context *ctx); #endif /* PAN_SCREEN_H */ diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 27176e3..aba8a67 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1624,7 +1624,7 @@ static void si_get_draw_start_count(struct si_context *sctx, const struct pipe_d } *start = min_element; - *count = max_element; + *count = max_element - min_element; } } diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c b/src/gallium/drivers/softpipe/sp_tex_sample.c index ab7f73e..f7d7cee 100644 --- a/src/gallium/drivers/softpipe/sp_tex_sample.c +++ b/src/gallium/drivers/softpipe/sp_tex_sample.c @@ -1638,7 +1638,7 @@ get_gather_value(const struct sp_sampler_view *sp_sview, case PIPE_SWIZZLE_0: return 0.0; case PIPE_SWIZZLE_1: - return 1.0; + return sp_sview->oneval; default: return tx[chan][swizzle]; } @@ -2884,12 +2884,12 @@ do_swizzling(const struct pipe_sampler_view *sview, float in[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE], float out[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE]) { + struct sp_sampler_view *sp_sview = (struct sp_sampler_view *)sview; int j; const unsigned swizzle_r = sview->swizzle_r; const unsigned swizzle_g = sview->swizzle_g; const unsigned swizzle_b = sview->swizzle_b; const unsigned swizzle_a = sview->swizzle_a; - float oneval = util_format_is_pure_integer(sview->format) ? uif(1) : 1.0f; switch (swizzle_r) { case PIPE_SWIZZLE_0: @@ -2898,7 +2898,7 @@ do_swizzling(const struct pipe_sampler_view *sview, break; case PIPE_SWIZZLE_1: for (j = 0; j < 4; j++) - out[0][j] = oneval; + out[0][j] = sp_sview->oneval; break; default: assert(swizzle_r < 4); @@ -2913,7 +2913,7 @@ do_swizzling(const struct pipe_sampler_view *sview, break; case PIPE_SWIZZLE_1: for (j = 0; j < 4; j++) - out[1][j] = oneval; + out[1][j] = sp_sview->oneval; break; default: assert(swizzle_g < 4); @@ -2928,7 +2928,7 @@ do_swizzling(const struct pipe_sampler_view *sview, break; case PIPE_SWIZZLE_1: for (j = 0; j < 4; j++) - out[2][j] = oneval; + out[2][j] = sp_sview->oneval; break; default: assert(swizzle_b < 4); @@ -2943,7 +2943,7 @@ do_swizzling(const struct pipe_sampler_view *sview, break; case PIPE_SWIZZLE_1: for (j = 0; j < 4; j++) - out[3][j] = oneval; + out[3][j] = sp_sview->oneval; break; default: assert(swizzle_a < 4); @@ -3638,6 +3638,8 @@ softpipe_create_sampler_view(struct pipe_context *pipe, sview->xpot = util_logbase2( resource->width0 ); sview->ypot = util_logbase2( resource->height0 ); + + sview->oneval = util_format_is_pure_integer(view->format) ? uif(1) : 1.0f; } return (struct pipe_sampler_view *) sview; diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.h b/src/gallium/drivers/softpipe/sp_tex_sample.h index 96fab8e..2770aca 100644 --- a/src/gallium/drivers/softpipe/sp_tex_sample.h +++ b/src/gallium/drivers/softpipe/sp_tex_sample.h @@ -122,6 +122,8 @@ struct sp_sampler_view compute_lambda_func compute_lambda; compute_lambda_from_grad_func compute_lambda_from_grad; union pipe_color_union border_color; + /* Value to use for PIPE_SWIZZLE_1 (integer vs float) */ + float oneval; }; struct sp_filter_funcs { diff --git a/src/gallium/drivers/zink/zink_context.c b/src/gallium/drivers/zink/zink_context.c index ab38845..2f01fa7 100644 --- a/src/gallium/drivers/zink/zink_context.c +++ b/src/gallium/drivers/zink/zink_context.c @@ -1304,7 +1304,8 @@ zink_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) _mesa_hash_pointer, _mesa_key_pointer_equal); - if (!ctx->batches[i].resources || !ctx->batches[i].sampler_views) + if (!ctx->batches[i].resources || !ctx->batches[i].sampler_views || + !ctx->batches[i].programs) goto fail; util_dynarray_init(&ctx->batches[i].zombie_samplers, NULL); diff --git a/src/gallium/drivers/zink/zink_format.c b/src/gallium/drivers/zink/zink_format.c index f161512..b78278d 100644 --- a/src/gallium/drivers/zink/zink_format.c +++ b/src/gallium/drivers/zink/zink_format.c @@ -95,11 +95,11 @@ static const VkFormat formats[PIPE_FORMAT_COUNT] = { [PIPE_FORMAT_R10G10B10A2_UNORM] = VK_FORMAT_A2B10G10R10_UNORM_PACK32, [PIPE_FORMAT_R10G10B10A2_SNORM] = VK_FORMAT_A2B10G10R10_SNORM_PACK32, [PIPE_FORMAT_B10G10R10A2_UNORM] = VK_FORMAT_A2R10G10B10_UNORM_PACK32, - [PIPE_FORMAT_B10G10R10A2_SNORM] = VK_FORMAT_A2B10G10R10_SNORM_PACK32, + [PIPE_FORMAT_B10G10R10A2_SNORM] = VK_FORMAT_A2R10G10B10_SNORM_PACK32, [PIPE_FORMAT_R10G10B10A2_USCALED] = VK_FORMAT_A2B10G10R10_USCALED_PACK32, [PIPE_FORMAT_R10G10B10A2_SSCALED] = VK_FORMAT_A2B10G10R10_SSCALED_PACK32, [PIPE_FORMAT_B10G10R10A2_USCALED] = VK_FORMAT_A2R10G10B10_USCALED_PACK32, - [PIPE_FORMAT_B10G10R10A2_SSCALED] = VK_FORMAT_A2B10G10R10_SSCALED_PACK32, + [PIPE_FORMAT_B10G10R10A2_SSCALED] = VK_FORMAT_A2R10G10B10_SSCALED_PACK32, [PIPE_FORMAT_R10G10B10A2_UINT] = VK_FORMAT_A2B10G10R10_UINT_PACK32, [PIPE_FORMAT_B10G10R10A2_UINT] = VK_FORMAT_A2R10G10B10_UINT_PACK32, diff --git a/src/gallium/drivers/zink/zink_resource.c b/src/gallium/drivers/zink/zink_resource.c index dc7b669..dc4442f 100644 --- a/src/gallium/drivers/zink/zink_resource.c +++ b/src/gallium/drivers/zink/zink_resource.c @@ -599,9 +599,12 @@ zink_transfer_map(struct pipe_context *pctx, vkGetImageSubresourceLayout(screen->dev, res->image, &isr, &srl); trans->base.stride = srl.rowPitch; trans->base.layer_stride = srl.arrayPitch; - ptr = ((uint8_t *)ptr) + box->z * srl.depthPitch + - box->y * srl.rowPitch + - box->x; + const struct util_format_description *desc = util_format_description(res->base.format); + unsigned offset = srl.offset + + box->z * srl.depthPitch + + (box->y / desc->block.height) * srl.rowPitch + + (box->x / desc->block.width) * (desc->block.bits / 8); + ptr = ((uint8_t *)ptr) + offset; } } diff --git a/src/gallium/drivers/zink/zink_screen.c b/src/gallium/drivers/zink/zink_screen.c index 5ee02be..ce6e15b 100644 --- a/src/gallium/drivers/zink/zink_screen.c +++ b/src/gallium/drivers/zink/zink_screen.c @@ -449,7 +449,8 @@ zink_get_shader_param(struct pipe_screen *pscreen, return 65536; case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: - return MIN2(screen->info.props.limits.maxPerStageDescriptorUniformBuffers, INT_MAX); + return MIN2(screen->info.props.limits.maxPerStageDescriptorUniformBuffers, + PIPE_MAX_CONSTANT_BUFFERS); case PIPE_SHADER_CAP_MAX_TEMPS: return INT_MAX; diff --git a/src/gallium/frontends/dri/dri2.c b/src/gallium/frontends/dri/dri2.c index 6f98926..5c935e7 100644 --- a/src/gallium/frontends/dri/dri2.c +++ b/src/gallium/frontends/dri/dri2.c @@ -758,6 +758,8 @@ dri2_create_image_from_winsys(__DRIscreen *_screen, if (pscreen->is_format_supported(pscreen, map->pipe_format, screen->target, 0, 0, PIPE_BIND_SAMPLER_VIEW)) tex_usage |= PIPE_BIND_SAMPLER_VIEW; + if (is_protected_content) + tex_usage |= PIPE_BIND_PROTECTED; /* For NV12, see if we have support for sampling r8_b8g8 */ if (!tex_usage && map->pipe_format == PIPE_FORMAT_NV12 && diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 569d273..f0e1b9f 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -530,6 +530,8 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) } } + ws->info.num_se = ws->info.max_se; + radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL, &ws->info.max_sh_per_se); if (ws->gen == DRV_SI) { diff --git a/src/intel/genxml/gen_sort_tags.py b/src/intel/genxml/gen_sort_tags.py old mode 100644 new mode 100755 diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c index 81e2242..4c43f5f 100644 --- a/src/intel/vulkan/anv_gem.c +++ b/src/intel/vulkan/anv_gem.c @@ -437,7 +437,7 @@ anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle) { struct drm_prime_handle args = { .handle = gem_handle, - .flags = DRM_CLOEXEC, + .flags = DRM_CLOEXEC | DRM_RDWR, }; int ret = gen_ioctl(device->fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args); diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 6fb09bb..a9c49e0 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3464,8 +3464,14 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) if (buffer) { uint32_t stride = dynamic_stride ? cmd_buffer->state.vertex_bindings[vb].stride : pipeline->vb[vb].stride; - uint32_t size = dynamic_size ? - cmd_buffer->state.vertex_bindings[vb].size : buffer->size; + /* From the Vulkan spec (vkCmdBindVertexBuffers2EXT): + * + * "If pname:pSizes is not NULL then pname:pSizes[i] specifies + * the bound size of the vertex buffer starting from the corresponding + * elements of pname:pBuffers[i] plus pname:pOffsets[i]." + */ + UNUSED uint32_t size = dynamic_size ? + cmd_buffer->state.vertex_bindings[vb].size : buffer->size - offset; state = (struct GENX(VERTEX_BUFFER_STATE)) { .VertexBufferIndex = vb, @@ -3482,9 +3488,14 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) .NullVertexBuffer = offset >= buffer->size, #if GEN_GEN >= 8 - .BufferSize = size - offset + .BufferSize = size, #else - .EndAddress = anv_address_add(buffer->address, size - 1), + /* XXX: to handle dynamic offset for older gens we might want + * to modify Endaddress, but there are issues when doing so: + * + * https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7439 + */ + .EndAddress = anv_address_add(buffer->address, buffer->size - 1), #endif }; } else { diff --git a/src/mesa/state_tracker/st_pbo.c b/src/mesa/state_tracker/st_pbo.c index 2d86c35..e4464bd 100644 --- a/src/mesa/state_tracker/st_pbo.c +++ b/src/mesa/state_tracker/st_pbo.c @@ -202,7 +202,7 @@ st_pbo_draw(struct st_context *st, const struct st_pbo_addresses *addr, return false; } - if (addr->depth != 1 && st->pbo.use_gs && !st->pbo.gs) { + if (st->pbo.use_gs && !st->pbo.gs) { st->pbo.gs = st_pbo_create_gs(st); if (!st->pbo.gs) return false;