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"description": "radv: dump VA ranges history when a GPU hang is detected", + "nominated": false, + "nomination_type": null, + "resolution": 4, + "master_sha": null, + "because_sha": null + }, + { + "sha": "15e7e6443cb70139e428189f661c3ca648929521", + "description": "d3d12: Initialize local_resource member mapped in constructor.", + "nominated": false, + "nomination_type": null, + "resolution": 4, + "master_sha": null, + "because_sha": null + }, + { "sha": "6c8cc9be12dc5d6c0d2386d6addb69d8f2fb5399", "description": "glsl: default to compat shaders in compat profile", "nominated": true, diff --git a/VERSION b/VERSION index 3eda575..bbcf7fc 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -20.3.2 +20.3.3 diff --git a/docs/envvars.rst b/docs/envvars.rst index ed9d640..ad8e684 100644 --- a/docs/envvars.rst +++ b/docs/envvars.rst @@ -559,6 +559,9 @@ RADV driver environment variables if a GPU hang is detected ``info`` show GPU-related information + ``invariantgeom`` + Mark geometry-affecting outputs as invariant. This works around a common + class of application bugs appearing as flickering. ``metashaders`` dump internal meta shaders ``nobinning`` diff --git a/docs/relnotes/20.3.2.rst b/docs/relnotes/20.3.2.rst index ba5cfd3..3435c3c 100644 --- a/docs/relnotes/20.3.2.rst +++ b/docs/relnotes/20.3.2.rst @@ -19,7 +19,7 @@ SHA256 checksum :: - TBD. + cce001b685d23afb976b04138714906abcf7e7f996da6355e6a43e5ca486533d mesa-20.3.2.tar.xz New features diff --git a/docs/relnotes/20.3.3.rst b/docs/relnotes/20.3.3.rst new file mode 100644 index 0000000..7d3cc23 --- /dev/null +++ b/docs/relnotes/20.3.3.rst @@ -0,0 +1,133 @@ +Mesa 20.3.3 Release Notes / 2021-01-13 +====================================== + +Mesa 20.3.3 is a bug fix release which fixes bugs found since the 20.3.2 release. + +Mesa 20.3.3 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 20.3.3 implements the Vulkan 1.2 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + TBD. + + +New features +------------ + +- None + + +Bug fixes +--------- + +- \[RADV/ACO/SIENNA_CICHLID\] Into the game Shadow of the Tomb Raider the flickering artifacts are present on brushes. +- DOOM crashes on startup with OpenGL on RX 6800 +- Space Engineers rendering regression after 5f79e4e6 which triggers incorrect optimizations from 053be9f0 +- star conflict crashes on iris, but loads fine on i965, on HD 5500 + + +Changes +------- + +Andrii Simiklit (1): + +- st/mesa: don't affect original st_CompressedTexSubImage parameters + +Bas Nieuwenhuizen (3): + +- radv/winsys: Fix inequality for sparse buffer remapping. +- radv/winsys: Fix offset in range merging. +- radv: Add Android module info to linker script. + +Danylo Piliaiev (2): + +- nir: account for point-coord origin when lowering it +- nir: fix missing nir_lower_pntc_ytransform.c in the makefile + +Dylan Baker (6): + +- docs: Add sha256 sum for 20.3.2 +- .pick_status.json: Update to 9ef2c44ce682b7981bd7a68c65f338f1e33bb001 +- .pick_status.json: Update to b2d000513e4a9b06d3b073913741dae47a00526e +- .pick_status.json: Update to 96ceca33c1dd69a1feed13b0e19bfc38e6f7d979 +- .pick_status.json: Update to d9c8422c4168c7433f68b97065283ebf26631d56 +- .pick_status.json: Mark 52b6adfbfb51a3b1a54964cbcb2adb0299d1252b as backported + +Eric Anholt (4): + +- gallium/draw: Fix intermittent failure to bind new geometry shaders. +- gallium/ntt: Fix emitting UBO declarations. +- gallium/ntt: Fix leak of the per-instr liveness information. +- mesa/st: Free the NIR builtins TGSI tokens after passing to the driver. + +Erik Faye-Lund (2): + +- gallium/util: do not perform n^2 stencil blits +- zink: dot leak dummy_buffer + +Georg Lehmann (2): + +- vulkan/device-select: fix vkGetInstanceProcAddr self-resolving +- vulkan/overlay: fix vkGetInstanceProcAddr self-resolving + +Ian Romanick (3): + +- spir-v: Mark floating point comparisons exact +- Revert "nir: Replace an odd comparison involving fmin of -b2f" +- nir/algebraic: Fix broken NaN and -0.0 behavior + +Icecream95 (1): + +- pan/mdg: Fix promoted uniform moves with 64-bit types + +James Park (1): + +- util: Disable memstream for Apple builds + +Marek Olšák (2): + +- st/mesa: don't do glCopyPixels via blit if depth bounds test is enabled +- util: add AMD CPU family enums and enable L3 cache pinning on Zen3 + +Marek Vasut (1): + +- etnaviv: Fix rework ZSA into a derived state + +Pavel Asyutchenko (1): + +- vulkan/overay: fix violation of VUID-VkDeviceCreateInfo-pNext-00373 + +Pierre-Eric Pelloux-Prayer (1): + +- drirc: radeonsi workaround for CS:GO + +Rhys Perry (6): + +- aco: fix incorrect address calculation for load_barycentric_at_sample +- ac/nir: use llvm.readcyclecounter for LLVM9+ +- nir/load_store_vectorize: don't ignore subgroup memory barriers +- aco: fix unreachable() for uniform 8/16-bit nir_op_mov from VGPR +- radv: add RADV_DEBUG=invariantgeom +- radv: set invariantgeom for Shadow of the Tomb Raider + +Samuel Pitoiset (4): + +- nir: fix determining if an addition might overflow for phi sources +- radv: disable TC-compat HTILE in GENERAL for Detroit: Become Human +- aco: fix creating the dest vector when 16-bit vertex fetches are splitted +- radv/llvm,aco: always split typed vertex buffer loads on GFX6 and GFX10+ + +nia (1): + +- util: Avoid pthread_setaffinity_np on NetBSD diff --git a/meson.build b/meson.build index c2843a3..9fc09a4 100644 --- a/meson.build +++ b/meson.build @@ -1354,7 +1354,7 @@ endif dep_thread = dependency('threads') if dep_thread.found() and host_machine.system() != 'windows' pre_args += '-DHAVE_PTHREAD' - if cc.has_function( + if host_machine.system() != 'netbsd' and cc.has_function( 'pthread_setaffinity_np', dependencies : dep_thread, prefix : '#include ', diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index bcd289f..6d45407 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -1208,12 +1208,14 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } case nir_op_mov: { Temp src = get_alu_src(ctx, instr->src[0]); - if (src.bytes() != dst.bytes()) - unreachable("wrong src or dst register class for nir_op_mov"); - if (src.type() == RegType::vgpr && dst.type() == RegType::sgpr) + if (src.type() == RegType::vgpr && dst.type() == RegType::sgpr) { + /* use size() instead of bytes() for 8/16-bit */ + assert(src.size() == dst.size() && "wrong src or dst register class for nir_op_mov"); bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src); - else + } else { + assert(src.bytes() == dst.bytes() && "wrong src or dst register class for nir_op_mov"); bld.copy(Definition(dst), src); + } break; } case nir_op_inot: { @@ -4553,11 +4555,17 @@ void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info, unsigned offset, unsigned stride, unsigned channels) { - unsigned vertex_byte_size = vtx_info->chan_byte_size * channels; if (vtx_info->chan_byte_size != 4 && channels == 3) return false; + + /* Always split typed vertex buffer loads on GFX6 and GFX10+ to avoid any + * alignment issues that triggers memory violations and eventually a GPU + * hang. This can happen if the stride (static or dynamic) is unaligned and + * also if the VBO offset is aligned to a scalar (eg. stride is 8 and VBO + * offset is 2 for R16G16B16A16_SNORM). + */ return (ctx->options->chip_class >= GFX7 && ctx->options->chip_class <= GFX9) || - (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0); + (channels == 1); } uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info, @@ -4821,11 +4829,12 @@ void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr) static const unsigned swizzle_normal[4] = {0, 1, 2, 3}; static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3}; const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal; + unsigned num_components = instr->dest.ssa.num_components; - aco_ptr vec{create_instruction(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)}; + aco_ptr vec{create_instruction(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)}; std::array elems; unsigned num_temp = 0; - for (unsigned i = 0; i < dst.size(); i++) { + for (unsigned i = 0; i < num_components; i++) { unsigned idx = i + component; if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) { Temp channel = channels[swizzle[idx]]; @@ -4845,9 +4854,9 @@ void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr) } vec->definitions[0] = Definition(dst); ctx->block->instructions.emplace_back(std::move(vec)); - emit_split_vector(ctx, dst, dst.size()); + emit_split_vector(ctx, dst, num_components); - if (num_temp == dst.size()) + if (num_temp == num_components) ctx->allocated_vec.emplace(dst.id(), elems); } } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) { @@ -7587,7 +7596,7 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset)); } else { offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u)); - offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset)); + offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(sample_pos_offset)); } Operand off = bld.copy(bld.def(s1), Operand(offset)); diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c index 00a3346..27bfa41 100644 --- a/src/amd/llvm/ac_llvm_build.c +++ b/src/amd/llvm/ac_llvm_build.c @@ -427,8 +427,9 @@ void ac_build_optimization_barrier(struct ac_llvm_context *ctx, LLVMValueRef *pv LLVMValueRef ac_build_shader_clock(struct ac_llvm_context *ctx, nir_scope scope) { - const char *name = - scope == NIR_SCOPE_DEVICE ? "llvm.amdgcn.s.memrealtime" : "llvm.amdgcn.s.memtime"; + const char *subgroup = LLVM_VERSION_MAJOR >= 9 ? "llvm.readcyclecounter" : "llvm.amdgcn.s.memtime"; + const char *name = scope == NIR_SCOPE_DEVICE ? "llvm.amdgcn.s.memrealtime" : subgroup; + LLVMValueRef tmp = ac_build_intrinsic(ctx, name, ctx->i64, NULL, 0, 0); return LLVMBuildBitCast(ctx->builder, tmp, ctx->v2i32, ""); } diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 5555f7c..8488190 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1694,7 +1694,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, !radv_image_is_tc_compat_htile(image)) return; - if (!radv_layout_is_htile_compressed(image, layout, in_render_loop, + if (!radv_layout_is_htile_compressed(cmd_buffer->device, image, layout, in_render_loop, radv_image_queue_family_mask(image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index))) { @@ -1737,7 +1737,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, uint32_t db_z_info = ds->db_z_info; uint32_t db_stencil_info = ds->db_stencil_info; - if (!radv_layout_is_htile_compressed(image, layout, in_render_loop, + if (!radv_layout_is_htile_compressed(cmd_buffer->device, image, layout, in_render_loop, radv_image_queue_family_mask(image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index))) { @@ -5950,11 +5950,11 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { radv_initialize_htile(cmd_buffer, image, range); - } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) && - radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) { + } else if (!radv_layout_is_htile_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) && + radv_layout_is_htile_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) { radv_initialize_htile(cmd_buffer, image, range); - } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) && - !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) { + } else if (radv_layout_is_htile_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) && + !radv_layout_is_htile_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) { cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h index 0985be3..2c559d8 100644 --- a/src/amd/vulkan/radv_debug.h +++ b/src/amd/vulkan/radv_debug.h @@ -28,36 +28,37 @@ /* Please keep docs/envvars.rst up-to-date when you add/remove options. */ enum { - RADV_DEBUG_NO_FAST_CLEARS = 1 << 0, - RADV_DEBUG_NO_DCC = 1 << 1, - RADV_DEBUG_DUMP_SHADERS = 1 << 2, - RADV_DEBUG_NO_CACHE = 1 << 3, - RADV_DEBUG_DUMP_SHADER_STATS = 1 << 4, - RADV_DEBUG_NO_HIZ = 1 << 5, - RADV_DEBUG_NO_COMPUTE_QUEUE = 1 << 6, - RADV_DEBUG_ALL_BOS = 1 << 7, - RADV_DEBUG_NO_IBS = 1 << 8, - RADV_DEBUG_DUMP_SPIRV = 1 << 9, - RADV_DEBUG_VM_FAULTS = 1 << 10, - RADV_DEBUG_ZERO_VRAM = 1 << 11, - RADV_DEBUG_SYNC_SHADERS = 1 << 12, - RADV_DEBUG_PREOPTIR = 1 << 13, - RADV_DEBUG_NO_DYNAMIC_BOUNDS = 1 << 14, - RADV_DEBUG_NO_OUT_OF_ORDER = 1 << 15, - RADV_DEBUG_INFO = 1 << 16, - RADV_DEBUG_ERRORS = 1 << 17, - RADV_DEBUG_STARTUP = 1 << 18, - RADV_DEBUG_CHECKIR = 1 << 19, - RADV_DEBUG_NOTHREADLLVM = 1 << 20, - RADV_DEBUG_NOBINNING = 1 << 21, - RADV_DEBUG_NO_NGG = 1 << 22, - RADV_DEBUG_ALL_ENTRYPOINTS = 1 << 23, - RADV_DEBUG_DUMP_META_SHADERS = 1 << 24, - RADV_DEBUG_NO_MEMORY_CACHE = 1 << 25, - RADV_DEBUG_DISCARD_TO_DEMOTE = 1 << 26, - RADV_DEBUG_LLVM = 1 << 27, - RADV_DEBUG_FORCE_COMPRESS = 1 << 28, - RADV_DEBUG_HANG = 1 << 29, + RADV_DEBUG_NO_FAST_CLEARS = 1u << 0, + RADV_DEBUG_NO_DCC = 1u << 1, + RADV_DEBUG_DUMP_SHADERS = 1u << 2, + RADV_DEBUG_NO_CACHE = 1u << 3, + RADV_DEBUG_DUMP_SHADER_STATS = 1u << 4, + RADV_DEBUG_NO_HIZ = 1u << 5, + RADV_DEBUG_NO_COMPUTE_QUEUE = 1u << 6, + RADV_DEBUG_ALL_BOS = 1u << 7, + RADV_DEBUG_NO_IBS = 1u << 8, + RADV_DEBUG_DUMP_SPIRV = 1u << 9, + RADV_DEBUG_VM_FAULTS = 1u << 10, + RADV_DEBUG_ZERO_VRAM = 1u << 11, + RADV_DEBUG_SYNC_SHADERS = 1u << 12, + RADV_DEBUG_PREOPTIR = 1u << 13, + RADV_DEBUG_NO_DYNAMIC_BOUNDS = 1u << 14, + RADV_DEBUG_NO_OUT_OF_ORDER = 1u << 15, + RADV_DEBUG_INFO = 1u << 16, + RADV_DEBUG_ERRORS = 1u << 17, + RADV_DEBUG_STARTUP = 1u << 18, + RADV_DEBUG_CHECKIR = 1u << 19, + RADV_DEBUG_NOTHREADLLVM = 1u << 20, + RADV_DEBUG_NOBINNING = 1u << 21, + RADV_DEBUG_NO_NGG = 1u << 22, + RADV_DEBUG_ALL_ENTRYPOINTS = 1u << 23, + RADV_DEBUG_DUMP_META_SHADERS = 1u << 24, + RADV_DEBUG_NO_MEMORY_CACHE = 1u << 25, + RADV_DEBUG_DISCARD_TO_DEMOTE = 1u << 26, + RADV_DEBUG_LLVM = 1u << 27, + RADV_DEBUG_FORCE_COMPRESS = 1u << 28, + RADV_DEBUG_HANG = 1u << 29, + RADV_DEBUG_INVARIANT_GEOM = 1ull << 32, }; enum { diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index c606423..1284eec 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -553,6 +553,7 @@ static const struct debug_control radv_debug_options[] = { {"llvm", RADV_DEBUG_LLVM}, {"forcecompress", RADV_DEBUG_FORCE_COMPRESS}, {"hang", RADV_DEBUG_HANG}, + {"invariantgeom", RADV_DEBUG_INVARIANT_GEOM}, {NULL, 0} }; @@ -607,6 +608,10 @@ radv_handle_per_app_options(struct radv_instance *instance, } else if (!strcmp(name, "DOOMEternal")) { /* Zero VRAM for Doom Eternal to fix rendering issues. */ instance->debug_flags |= RADV_DEBUG_ZERO_VRAM; + } else if (!strcmp(name, "ShadowOfTheTomb")) { + /* Work around flickering foliage for native Shadow of the Tomb Raider + * on GFX10.3 */ + instance->debug_flags |= RADV_DEBUG_INVARIANT_GEOM; } } @@ -620,6 +625,14 @@ radv_handle_per_app_options(struct radv_instance *instance, /* Fix various artifacts in Detroit: Become Human */ instance->debug_flags |= RADV_DEBUG_ZERO_VRAM | RADV_DEBUG_DISCARD_TO_DEMOTE; + + /* Fix rendering issues in Detroit: Become Human + * because the game uses render loops (it + * samples/renders from/to the same depth/stencil + * texture inside the same draw) without input + * attachments and that is invalid Vulkan usage. + */ + instance->disable_tc_compat_htile_in_general = true; } } diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 2bad566..edf7cf6 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1738,7 +1738,8 @@ radv_image_view_init(struct radv_image_view *iview, } } -bool radv_layout_is_htile_compressed(const struct radv_image *image, +bool radv_layout_is_htile_compressed(const struct radv_device *device, + const struct radv_image *image, VkImageLayout layout, bool in_render_loop, unsigned queue_mask) @@ -1746,6 +1747,7 @@ bool radv_layout_is_htile_compressed(const struct radv_image *image, if (radv_image_is_tc_compat_htile(image)) { if (layout == VK_IMAGE_LAYOUT_GENERAL && !in_render_loop && + !device->instance->disable_tc_compat_htile_in_general && !(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) { /* It should be safe to enable TC-compat HTILE with * VK_IMAGE_LAYOUT_GENERAL if we are not in a render diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 4484895..0261a4d 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -733,7 +733,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer, iview->base_mip == 0 && iview->base_layer == 0 && iview->layer_count == iview->image->info.array_size && - radv_layout_is_htile_compressed(iview->image, layout, in_render_loop, queue_mask) && + radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop, queue_mask) && radv_image_extent_compare(iview->image, &iview->extent)) return true; return false; @@ -1090,7 +1090,7 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview)) return false; - if (!radv_layout_is_htile_compressed(iview->image, image_layout, in_render_loop, + if (!radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, image_layout, in_render_loop, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index))) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index f94411d..b591c96 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -1182,17 +1182,15 @@ handle_vs_input_decl(struct radv_shader_context *ctx, t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false); t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset); - /* Perform per-channel vertex fetch operations if unaligned - * access are detected. Only GFX6 and GFX10 are affected. + /* Always split typed vertex buffer loads on GFX6 and GFX10+ + * to avoid any alignment issues that triggers memory + * violations and eventually a GPU hang. This can happen if + * the stride (static or dynamic) is unaligned and also if the + * VBO offset is aligned to a scalar (eg. stride is 8 and VBO + * offset is 2 for R16G16B16A16_SNORM). */ - bool unaligned_vertex_fetches = false; - if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class >= GFX10) && - vtx_info->chan_format != data_format && - ((attrib_offset % vtx_info->element_size) || - (attrib_stride % vtx_info->element_size))) - unaligned_vertex_fetches = true; - - if (unaligned_vertex_fetches) { + if (ctx->ac.chip_class == GFX6 || + ctx->ac.chip_class >= GFX10) { unsigned chan_format = vtx_info->chan_format; LLVMValueRef values[4]; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index ee4dbba..e276082 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -223,6 +223,8 @@ static uint32_t get_hash_flags(const struct radv_device *device) hash_flags |= RADV_HASH_SHADER_DISCARD_TO_DEMOTE; if (device->instance->enable_mrt_output_nan_fixup) hash_flags |= RADV_HASH_SHADER_MRT_NAN_FIXUP; + if (device->instance->debug_flags & RADV_DEBUG_INVARIANT_GEOM) + hash_flags |= RADV_HASH_SHADER_INVARIANT_GEOM; return hash_flags; } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 6c3a166..82788fa 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -358,6 +358,7 @@ struct radv_instance { * Workarounds for game bugs. */ bool enable_mrt_output_nan_fixup; + bool disable_tc_compat_htile_in_general; }; VkResult radv_init_wsi(struct radv_physical_device *physical_device); @@ -1651,6 +1652,7 @@ struct radv_shader_module; #define RADV_HASH_SHADER_LLVM (1 << 4) #define RADV_HASH_SHADER_DISCARD_TO_DEMOTE (1 << 5) #define RADV_HASH_SHADER_MRT_NAN_FIXUP (1 << 6) +#define RADV_HASH_SHADER_INVARIANT_GEOM (1 << 7) void radv_hash_shaders(unsigned char *hash, @@ -1901,7 +1903,8 @@ struct radv_image { * If this is false reads that don't use the htile should be able to return * correct results. */ -bool radv_layout_is_htile_compressed(const struct radv_image *image, +bool radv_layout_is_htile_compressed(const struct radv_device *device, + const struct radv_image *image, VkImageLayout layout, bool in_render_loop, unsigned queue_mask); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 0c5579f..ae43b03 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -311,6 +311,27 @@ static void radv_compiler_debug(void *private_data, 0, 0, "radv", message); } +static void +mark_geom_invariant(nir_shader *nir) +{ + nir_foreach_shader_out_variable(var, nir) { + switch (var->data.location) { + case VARYING_SLOT_POS: + case VARYING_SLOT_PSIZ: + case VARYING_SLOT_CLIP_DIST0: + case VARYING_SLOT_CLIP_DIST1: + case VARYING_SLOT_CULL_DIST0: + case VARYING_SLOT_CULL_DIST1: + case VARYING_SLOT_TESS_LEVEL_OUTER: + case VARYING_SLOT_TESS_LEVEL_INNER: + var->data.invariant = true; + break; + default: + break; + } + } +} + static bool lower_load_vulkan_descriptor(nir_shader *nir) { @@ -528,6 +549,11 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared, NULL); + if (device->instance->debug_flags & RADV_DEBUG_INVARIANT_GEOM && + stage != MESA_SHADER_FRAGMENT) { + mark_geom_invariant(nir); + } + NIR_PASS_V(nir, nir_propagate_invariant); NIR_PASS_V(nir, nir_lower_system_values); diff --git a/src/amd/vulkan/vulkan.sym b/src/amd/vulkan/vulkan.sym index c85a22e..2ca40fa 100644 --- a/src/amd/vulkan/vulkan.sym +++ b/src/amd/vulkan/vulkan.sym @@ -4,6 +4,11 @@ vk_icdGetPhysicalDeviceProcAddr; vk_icdNegotiateLoaderICDInterfaceVersion; + # Andoid looks for this global in HAL modules. In the source it occurs + # as HAL_MODULE_INFO_SYM (which is just a #define for HMI) and it's an + # instance of struct hwvulkan_module_t. + HMI; + local: # When static linking LLVM, all its symbols are public API. # That may cause symbol collision, so explicitly demote everything. diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c index ee27455..7685c88 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c @@ -193,7 +193,7 @@ radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys_bo *_parent, ++first; last = first; - while(last + 1 < parent->range_count && parent->ranges[last].offset <= offset + size) + while(last + 1 < parent->range_count && parent->ranges[last + 1].offset <= offset + size) ++last; /* Whether the first or last range are going to be totally removed or just @@ -250,6 +250,7 @@ radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys_bo *_parent, if (!remove_last) { new_last.size -= offset + size - new_last.offset; + new_last.bo_offset += (offset + size - new_last.offset); new_last.offset = offset + size; radv_amdgpu_winsys_virtual_map(parent, &new_last); } diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources index 931af63..eeffb69 100644 --- a/src/compiler/Makefile.sources +++ b/src/compiler/Makefile.sources @@ -286,6 +286,7 @@ NIR_FILES = \ nir/nir_lower_passthrough_edgeflags.c \ nir/nir_lower_patch_vertices.c \ nir/nir_lower_phis_to_scalar.c \ + nir/nir_lower_pntc_ytransform.c \ nir/nir_lower_point_size.c \ nir/nir_lower_point_size_mov.c \ nir/nir_lower_regs_to_ssa.c \ diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build index dad896d..d04c30a 100644 --- a/src/compiler/nir/meson.build +++ b/src/compiler/nir/meson.build @@ -166,6 +166,7 @@ files_libnir = files( 'nir_lower_passthrough_edgeflags.c', 'nir_lower_patch_vertices.c', 'nir_lower_phis_to_scalar.c', + 'nir_lower_pntc_ytransform.c', 'nir_lower_point_size.c', 'nir_lower_point_size_mov.c', 'nir_lower_regs_to_ssa.c', diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 3979b6b..5f98baa 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -3398,7 +3398,10 @@ typedef struct nir_shader_compiler_options { bool lower_device_index_to_zero; - /* Set if nir_lower_wpos_ytransform() should also invert gl_PointCoord. */ + /* Set if nir_lower_pntc_ytransform() should invert gl_PointCoord. + * Either when frame buffer is flipped or GL_POINT_SPRITE_COORD_ORIGIN + * is GL_LOWER_LEFT. + */ bool lower_wpos_pntc; /** @@ -4900,6 +4903,9 @@ bool nir_lower_wpos_ytransform(nir_shader *shader, const nir_lower_wpos_ytransform_options *options); bool nir_lower_wpos_center(nir_shader *shader, const bool for_sample_shading); +bool nir_lower_pntc_ytransform(nir_shader *shader, + const gl_state_index16 clipplane_state_tokens[][STATE_LENGTH]); + bool nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data); bool nir_lower_fb_read(nir_shader *shader); diff --git a/src/compiler/nir/nir_lower_pntc_ytransform.c b/src/compiler/nir/nir_lower_pntc_ytransform.c new file mode 100644 index 0000000..f83d465 --- /dev/null +++ b/src/compiler/nir/nir_lower_pntc_ytransform.c @@ -0,0 +1,134 @@ +/* + * Copyright © 2020 Igalia S.L. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "nir.h" +#include "nir_builder.h" +#include "program/prog_instruction.h" + +/* Lower gl_PointCoord to account for user requested point-coord origin + * and for whether draw buffer is flipped. + */ + +typedef struct { + const gl_state_index16 *pntc_state_tokens; + nir_shader *shader; + nir_builder b; + nir_variable *pntc_transform; +} lower_pntc_ytransform_state; + +static nir_ssa_def * +get_pntc_transform(lower_pntc_ytransform_state *state) +{ + if (state->pntc_transform == NULL) { + /* NOTE: name must be prefixed w/ "gl_" to trigger slot based + * special handling in uniform setup: + */ + nir_variable *var = nir_variable_create(state->shader, + nir_var_uniform, + glsl_vec4_type(), + "gl_PntcYTransform"); + + var->num_state_slots = 1; + var->state_slots = ralloc_array(var, nir_state_slot, 1); + var->state_slots[0].swizzle = SWIZZLE_XYZW; + memcpy(var->state_slots[0].tokens, state->pntc_state_tokens, + sizeof(var->state_slots[0].tokens)); + var->data.how_declared = nir_var_hidden; + state->pntc_transform = var; + } + return nir_load_var(&state->b, state->pntc_transform); +} + +static void +lower_load_pointcoord(lower_pntc_ytransform_state *state, + nir_intrinsic_instr *intr) +{ + nir_builder *b = &state->b; + b->cursor = nir_after_instr(&intr->instr); + + nir_ssa_def *pntc = &intr->dest.ssa; + nir_ssa_def *transform = get_pntc_transform(state); + nir_ssa_def *y = nir_channel(b, pntc, 1); + /* The offset is 1 if we're flipping, 0 otherwise. */ + nir_ssa_def *offset = nir_channel(b, transform, 1); + /* Flip the sign of y if we're flipping. */ + nir_ssa_def *scaled = nir_fmul(b, y, nir_channel(b, transform, 0)); + + /* Reassemble the vector. */ + nir_ssa_def *flipped_pntc = nir_vec2(b, + nir_channel(b, pntc, 0), + nir_fadd(b, offset, scaled)); + + nir_ssa_def_rewrite_uses_after(&intr->dest.ssa, nir_src_for_ssa(flipped_pntc), + flipped_pntc->parent_instr); +} + +static void +lower_pntc_ytransform_block(lower_pntc_ytransform_state *state, + nir_block *block) +{ + nir_foreach_instr_safe(instr, block) { + if (instr->type == nir_instr_type_intrinsic) { + nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); + if (intr->intrinsic == nir_intrinsic_load_deref) { + nir_deref_instr *deref = nir_src_as_deref(intr->src[0]); + nir_variable *var = nir_deref_instr_get_variable(deref); + + if (var->data.mode == nir_var_shader_in && + var->data.location == VARYING_SLOT_PNTC) { + lower_load_pointcoord(state, intr); + } + } + } + } +} + +bool +nir_lower_pntc_ytransform(nir_shader *shader, + const gl_state_index16 pntc_state_tokens[][STATE_LENGTH]) +{ + if (!shader->options->lower_wpos_pntc) + return false; + + lower_pntc_ytransform_state state = { + .pntc_state_tokens = *pntc_state_tokens, + .shader = shader, + .pntc_transform = NULL, + }; + + assert(shader->info.stage == MESA_SHADER_FRAGMENT); + + nir_foreach_function(function, shader) { + if (function->impl) { + nir_builder_init(&state.b, function->impl); + + nir_foreach_block(block, function->impl) { + lower_pntc_ytransform_block(&state, block); + } + nir_metadata_preserve(function->impl, nir_metadata_block_index | + nir_metadata_dominance); + } + } + + return state.pntc_transform != NULL; +} diff --git a/src/compiler/nir/nir_lower_wpos_ytransform.c b/src/compiler/nir/nir_lower_wpos_ytransform.c index 2771f2a..56ae978 100644 --- a/src/compiler/nir/nir_lower_wpos_ytransform.c +++ b/src/compiler/nir/nir_lower_wpos_ytransform.c @@ -232,31 +232,6 @@ lower_fragcoord(lower_wpos_ytransform_state *state, nir_intrinsic_instr *intr) emit_wpos_adjustment(state, intr, invert, adjX, adjY); } -static void -lower_load_pointcoord(lower_wpos_ytransform_state *state, - nir_intrinsic_instr *intr) -{ - nir_builder *b = &state->b; - b->cursor = nir_after_instr(&intr->instr); - - nir_ssa_def *pntc = &intr->dest.ssa; - nir_ssa_def *transform = get_transform(state); - nir_ssa_def *y = nir_channel(b, pntc, 1); - /* The offset is 1 if we're flipping, 0 otherwise. */ - nir_ssa_def *offset = nir_fmax(b, nir_channel(b, transform, 2), - nir_imm_float(b, 0.0)); - /* Flip the sign of y if we're flipping. */ - nir_ssa_def *scaled = nir_fmul(b, y, nir_channel(b, transform, 0)); - - /* Reassemble the vector. */ - nir_ssa_def *flipped_pntc = nir_vec2(b, - nir_channel(b, pntc, 0), - nir_fadd(b, offset, scaled)); - - nir_ssa_def_rewrite_uses_after(&intr->dest.ssa, nir_src_for_ssa(flipped_pntc), - flipped_pntc->parent_instr); -} - /* turns 'fddy(p)' into 'fddy(fmul(p, transform.x))' */ static void lower_fddy(lower_wpos_ytransform_state *state, nir_alu_instr *fddy) @@ -339,10 +314,6 @@ lower_wpos_ytransform_block(lower_wpos_ytransform_state *state, nir_block *block } else if (var->data.mode == nir_var_system_value && var->data.location == SYSTEM_VALUE_SAMPLE_POS) { lower_load_sample_pos(state, intr); - } else if (var->data.mode == nir_var_shader_in && - var->data.location == VARYING_SLOT_PNTC && - state->shader->options->lower_wpos_pntc) { - lower_load_pointcoord(state, intr); } } else if (intr->intrinsic == nir_intrinsic_load_frag_coord) { lower_fragcoord(state, intr); diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 2fb4d5a..49bf6db 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++ b/src/compiler/nir/nir_opt_algebraic.py @@ -1,3 +1,4 @@ +# -*- coding: utf-8 -*- # # Copyright (C) 2014 Intel Corporation # @@ -423,19 +424,6 @@ optimizations.extend([ (('ieq', ('iadd', a, b), a), ('ieq', b, 0)), (('ine', ('iadd', a, b), a), ('ine', b, 0)), - # fmin(-b2f(a), b) >= 0.0 - # -b2f(a) >= 0.0 && b >= 0.0 - # -b2f(a) == 0.0 && b >= 0.0 -b2f can only be 0 or -1, never >0 - # b2f(a) == 0.0 && b >= 0.0 - # a == False && b >= 0.0 - # !a && b >= 0.0 - # - # The fge in the second replacement is not a typo. I leave the proof that - # "fmin(-b2f(a), b) >= 0 <=> fmin(-b2f(a), b) == 0" as an exercise for the - # reader. - (('fge', ('fmin', ('fneg', ('b2f', 'a@1')), 'b@1'), 0.0), ('iand', ('inot', a), ('fge', b, 0.0))), - (('feq', ('fmin', ('fneg', ('b2f', 'a@1')), 'b@1'), 0.0), ('iand', ('inot', a), ('fge', b, 0.0))), - (('feq', ('b2f', 'a@1'), 0.0), ('inot', a)), (('~fneu', ('b2f', 'a@1'), 0.0), a), (('ieq', ('b2i', 'a@1'), 0), ('inot', a)), @@ -639,8 +627,6 @@ optimizations.extend([ # Float sizes for s in [16, 32, 64]: - fp_one = {16: 0x3c00, 32: 0x3f800000, 64: 0x3ff0000000000000}[s] - optimizations.extend([ # These derive from the previous patterns with the application of b < 0 <=> # 0 < -b. The transformation should be applied if either comparison is @@ -656,11 +642,28 @@ for s in [16, 32, 64]: (('~iand', ('fge(is_used_once)', 0.0, 'a@{}'.format(s)), ('fge', 'b@{}'.format(s), 0.0)), ('fge', 0.0, ('fmax', a, ('fneg', b)))), (('~iand', ('fge', 0.0, 'a@{}'.format(s)), ('fge(is_used_once)', 'b@{}'.format(s), 0.0)), ('fge', 0.0, ('fmax', a, ('fneg', b)))), - # The (i2f32, ...) part is an open-coded fsign. When that is combined with - # the bcsel, it's basically copysign(1.0, a). There is no copysign in NIR, - # so emit an open-coded version of that. + # The (i2f32, ...) part is an open-coded fsign. When that is combined + # with the bcsel, it's basically copysign(1.0, a). There are some + # behavior differences between this pattern and copysign w.r.t. ±0 and + # NaN. copysign(x, y) blindly takes the sign bit from y and applies it + # to x, regardless of whether either or both values are NaN. + # + # If a != a: bcsel(False, 1.0, i2f(b2i(False) - b2i(False))) = 0, + # int(NaN >= 0.0) - int(NaN < 0.0) = 0 - 0 = 0 + # If a == ±0: bcsel(True, 1.0, ...) = 1.0, + # int(±0.0 >= 0.0) - int(±0.0 < 0.0) = 1 - 0 = 1 + # + # For all other values of 'a', the original and replacement behave as + # copysign. + # + # Marking the replacement comparisons as precise prevents any future + # optimizations from replacing either of the comparisons with the + # logical-not of the other. + # + # Note: Use b2i32 in the replacement because some platforms that + # support fp16 don't support int16. (('bcsel@{}'.format(s), ('feq', a, 0.0), 1.0, ('i2f{}'.format(s), ('iadd', ('b2i{}'.format(s), ('flt', 0.0, 'a@{}'.format(s))), ('ineg', ('b2i{}'.format(s), ('flt', 'a@{}'.format(s), 0.0)))))), - ('ior', fp_one, ('iand', a, 1 << (s - 1)))), + ('i2f{}'.format(s), ('iadd', ('b2i32', ('!fge', a, 0.0)), ('ineg', ('b2i32', ('!flt', a, 0.0)))))), (('bcsel', a, ('b2f(is_used_once)', 'b@{}'.format(s)), ('b2f', 'c@{}'.format(s))), ('b2f', ('bcsel', a, b, c))), diff --git a/src/compiler/nir/nir_opt_load_store_vectorize.c b/src/compiler/nir/nir_opt_load_store_vectorize.c index 6829694..8449be5 100644 --- a/src/compiler/nir/nir_opt_load_store_vectorize.c +++ b/src/compiler/nir/nir_opt_load_store_vectorize.c @@ -1196,7 +1196,6 @@ handle_barrier(struct vectorize_ctx *ctx, bool *progress, nir_function_impl *imp release = nir_intrinsic_memory_semantics(intrin) & NIR_MEMORY_RELEASE; switch (nir_intrinsic_memory_scope(intrin)) { case NIR_SCOPE_INVOCATION: - case NIR_SCOPE_SUBGROUP: /* a barier should never be required for correctness with these scopes */ modes = 0; break; diff --git a/src/compiler/nir/nir_range_analysis.c b/src/compiler/nir/nir_range_analysis.c index 04449a9..903f0b3 100644 --- a/src/compiler/nir/nir_range_analysis.c +++ b/src/compiler/nir/nir_range_analysis.c @@ -1456,36 +1456,38 @@ nir_addition_might_overflow(nir_shader *shader, struct hash_table *range_ht, nir_ssa_scalar ssa, unsigned const_val, const nir_unsigned_upper_bound_config *config) { - nir_op alu_op = nir_ssa_scalar_alu_op(ssa); - - /* iadd(imul(a, #b), #c) */ - if (alu_op == nir_op_imul || alu_op == nir_op_ishl) { - nir_ssa_scalar mul_src0 = nir_ssa_scalar_chase_alu_src(ssa, 0); - nir_ssa_scalar mul_src1 = nir_ssa_scalar_chase_alu_src(ssa, 1); - uint32_t stride = 1; - if (nir_ssa_scalar_is_const(mul_src0)) - stride = nir_ssa_scalar_as_uint(mul_src0); - else if (nir_ssa_scalar_is_const(mul_src1)) - stride = nir_ssa_scalar_as_uint(mul_src1); - - if (alu_op == nir_op_ishl) - stride = 1u << (stride % 32u); - - if (!stride || const_val <= UINT32_MAX - (UINT32_MAX / stride * stride)) - return false; - } + if (nir_ssa_scalar_is_alu(ssa)) { + nir_op alu_op = nir_ssa_scalar_alu_op(ssa); + + /* iadd(imul(a, #b), #c) */ + if (alu_op == nir_op_imul || alu_op == nir_op_ishl) { + nir_ssa_scalar mul_src0 = nir_ssa_scalar_chase_alu_src(ssa, 0); + nir_ssa_scalar mul_src1 = nir_ssa_scalar_chase_alu_src(ssa, 1); + uint32_t stride = 1; + if (nir_ssa_scalar_is_const(mul_src0)) + stride = nir_ssa_scalar_as_uint(mul_src0); + else if (nir_ssa_scalar_is_const(mul_src1)) + stride = nir_ssa_scalar_as_uint(mul_src1); + + if (alu_op == nir_op_ishl) + stride = 1u << (stride % 32u); + + if (!stride || const_val <= UINT32_MAX - (UINT32_MAX / stride * stride)) + return false; + } - /* iadd(iand(a, #b), #c) */ - if (alu_op == nir_op_iand) { - nir_ssa_scalar and_src0 = nir_ssa_scalar_chase_alu_src(ssa, 0); - nir_ssa_scalar and_src1 = nir_ssa_scalar_chase_alu_src(ssa, 1); - uint32_t mask = 0xffffffff; - if (nir_ssa_scalar_is_const(and_src0)) - mask = nir_ssa_scalar_as_uint(and_src0); - else if (nir_ssa_scalar_is_const(and_src1)) - mask = nir_ssa_scalar_as_uint(and_src1); - if (mask == 0 || const_val < (1u << (ffs(mask) - 1))) - return false; + /* iadd(iand(a, #b), #c) */ + if (alu_op == nir_op_iand) { + nir_ssa_scalar and_src0 = nir_ssa_scalar_chase_alu_src(ssa, 0); + nir_ssa_scalar and_src1 = nir_ssa_scalar_chase_alu_src(ssa, 1); + uint32_t mask = 0xffffffff; + if (nir_ssa_scalar_is_const(and_src0)) + mask = nir_ssa_scalar_as_uint(and_src0); + else if (nir_ssa_scalar_is_const(and_src1)) + mask = nir_ssa_scalar_as_uint(and_src1); + if (mask == 0 || const_val < (1u << (ffs(mask) - 1))) + return false; + } } uint32_t ub = nir_unsigned_upper_bound(shader, range_ht, ssa, config); diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index c031504..cc992da 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -2094,9 +2094,16 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode, bit_size = glsl_get_bit_size(val->type->type); }; - nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, + bool exact; + nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, &exact, nir_alu_type_get_type_size(src_alu_type), nir_alu_type_get_type_size(dst_alu_type)); + + /* No SPIR-V opcodes handled through this path should set exact. + * Since it is ignored, assert on it. + */ + assert(!exact); + nir_const_value src[3][NIR_MAX_VEC_COMPONENTS]; for (unsigned i = 0; i < count - 4; i++) { diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 1814fa7..1d8c69b 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -254,7 +254,7 @@ convert_op_dst_type(SpvOp opcode) nir_op vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, - SpvOp opcode, bool *swap, + SpvOp opcode, bool *swap, bool *exact, unsigned src_bit_size, unsigned dst_bit_size) { /* Indicates that the first two arguments should be swapped. This is @@ -262,6 +262,8 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, */ *swap = false; + *exact = false; + switch (opcode) { case SpvOpSNegate: return nir_op_ineg; case SpvOpFNegate: return nir_op_fneg; @@ -319,28 +321,28 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, * the logical operator to use since they also need to check if operands are * ordered. */ - case SpvOpFOrdEqual: return nir_op_feq; - case SpvOpFUnordEqual: return nir_op_feq; - case SpvOpINotEqual: return nir_op_ine; + case SpvOpFOrdEqual: *exact = true; return nir_op_feq; + case SpvOpFUnordEqual: *exact = true; return nir_op_feq; + case SpvOpINotEqual: return nir_op_ine; case SpvOpLessOrGreater: /* Deprecated, use OrdNotEqual */ - case SpvOpFOrdNotEqual: return nir_op_fneu; - case SpvOpFUnordNotEqual: return nir_op_fneu; - case SpvOpULessThan: return nir_op_ult; - case SpvOpSLessThan: return nir_op_ilt; - case SpvOpFOrdLessThan: return nir_op_flt; - case SpvOpFUnordLessThan: return nir_op_flt; - case SpvOpUGreaterThan: *swap = true; return nir_op_ult; - case SpvOpSGreaterThan: *swap = true; return nir_op_ilt; - case SpvOpFOrdGreaterThan: *swap = true; return nir_op_flt; - case SpvOpFUnordGreaterThan: *swap = true; return nir_op_flt; - case SpvOpULessThanEqual: *swap = true; return nir_op_uge; - case SpvOpSLessThanEqual: *swap = true; return nir_op_ige; - case SpvOpFOrdLessThanEqual: *swap = true; return nir_op_fge; - case SpvOpFUnordLessThanEqual: *swap = true; return nir_op_fge; - case SpvOpUGreaterThanEqual: return nir_op_uge; - case SpvOpSGreaterThanEqual: return nir_op_ige; - case SpvOpFOrdGreaterThanEqual: return nir_op_fge; - case SpvOpFUnordGreaterThanEqual: return nir_op_fge; + case SpvOpFOrdNotEqual: *exact = true; return nir_op_fneu; + case SpvOpFUnordNotEqual: *exact = true; return nir_op_fneu; + case SpvOpULessThan: return nir_op_ult; + case SpvOpSLessThan: return nir_op_ilt; + case SpvOpFOrdLessThan: *exact = true; return nir_op_flt; + case SpvOpFUnordLessThan: *exact = true; return nir_op_flt; + case SpvOpUGreaterThan: *swap = true; return nir_op_ult; + case SpvOpSGreaterThan: *swap = true; return nir_op_ilt; + case SpvOpFOrdGreaterThan: *swap = true; *exact = true; return nir_op_flt; + case SpvOpFUnordGreaterThan: *swap = true; *exact = true; return nir_op_flt; + case SpvOpULessThanEqual: *swap = true; return nir_op_uge; + case SpvOpSLessThanEqual: *swap = true; return nir_op_ige; + case SpvOpFOrdLessThanEqual: *swap = true; *exact = true; return nir_op_fge; + case SpvOpFUnordLessThanEqual: *swap = true; *exact = true; return nir_op_fge; + case SpvOpUGreaterThanEqual: return nir_op_uge; + case SpvOpSGreaterThanEqual: return nir_op_ige; + case SpvOpFOrdGreaterThanEqual: *exact = true; return nir_op_fge; + case SpvOpFUnordGreaterThanEqual: *exact = true; return nir_op_fge; /* Conversions: */ case SpvOpQuantizeToF16: return nir_op_fquantize2f16; @@ -554,19 +556,34 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, dest->def = nir_fmul(&b->nb, src[0], src[1]); break; - case SpvOpIsNan: + case SpvOpIsNan: { + const bool save_exact = b->nb.exact; + + b->nb.exact = true; dest->def = nir_fneu(&b->nb, src[0], src[0]); + b->nb.exact = save_exact; break; + } - case SpvOpOrdered: + case SpvOpOrdered: { + const bool save_exact = b->nb.exact; + + b->nb.exact = true; dest->def = nir_iand(&b->nb, nir_feq(&b->nb, src[0], src[0]), nir_feq(&b->nb, src[1], src[1])); + b->nb.exact = save_exact; break; + } - case SpvOpUnordered: + case SpvOpUnordered: { + const bool save_exact = b->nb.exact; + + b->nb.exact = true; dest->def = nir_ior(&b->nb, nir_fneu(&b->nb, src[0], src[0]), nir_fneu(&b->nb, src[1], src[1])); + b->nb.exact = save_exact; break; + } case SpvOpIsInf: { nir_ssa_def *inf = nir_imm_floatN_t(&b->nb, INFINITY, src[0]->bit_size); @@ -581,9 +598,11 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, case SpvOpFUnordLessThanEqual: case SpvOpFUnordGreaterThanEqual: { bool swap; + bool unused_exact; unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type); unsigned dst_bit_size = glsl_get_bit_size(dest_type); nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, + &unused_exact, src_bit_size, dst_bit_size); if (swap) { @@ -592,12 +611,18 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, src[1] = tmp; } + const bool save_exact = b->nb.exact; + + b->nb.exact = true; + dest->def = nir_ior(&b->nb, nir_build_alu(&b->nb, op, src[0], src[1], NULL, NULL), nir_ior(&b->nb, nir_fneu(&b->nb, src[0], src[0]), nir_fneu(&b->nb, src[1], src[1]))); + + b->nb.exact = save_exact; break; } @@ -608,12 +633,18 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, * ordered so we don’t need to handle it specially. */ bool swap; + bool exact; unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type); unsigned dst_bit_size = glsl_get_bit_size(dest_type); - nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, + nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, &exact, src_bit_size, dst_bit_size); assert(!swap); + assert(exact); + + const bool save_exact = b->nb.exact; + + b->nb.exact = true; dest->def = nir_iand(&b->nb, @@ -621,6 +652,8 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, nir_iand(&b->nb, nir_feq(&b->nb, src[0], src[0]), nir_feq(&b->nb, src[1], src[1]))); + + b->nb.exact = save_exact; break; } @@ -676,11 +709,14 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, case SpvOpShiftRightArithmetic: case SpvOpShiftRightLogical: { bool swap; + bool exact; unsigned src0_bit_size = glsl_get_bit_size(vtn_src[0]->type); unsigned dst_bit_size = glsl_get_bit_size(dest_type); - nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, + nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, &exact, src0_bit_size, dst_bit_size); + assert(!exact); + assert (op == nir_op_ushr || op == nir_op_ishr || op == nir_op_ishl || op == nir_op_bitfield_insert || op == nir_op_ubitfield_extract || op == nir_op_ibitfield_extract); @@ -725,9 +761,11 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, default: { bool swap; + bool exact; unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type); unsigned dst_bit_size = glsl_get_bit_size(dest_type); nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, + &exact, src_bit_size, dst_bit_size); if (swap) { @@ -747,7 +785,14 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, break; } + const bool save_exact = b->nb.exact; + + if (exact) + b->nb.exact = true; + dest->def = nir_build_alu(&b->nb, op, src[0], src[1], src[2], src[3]); + + b->nb.exact = save_exact; break; } /* default */ } diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h index c136db2..a1e8fa5 100644 --- a/src/compiler/spirv/vtn_private.h +++ b/src/compiler/spirv/vtn_private.h @@ -896,7 +896,7 @@ void vtn_foreach_execution_mode(struct vtn_builder *b, struct vtn_value *value, vtn_execution_mode_foreach_cb cb, void *data); nir_op vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, - SpvOp opcode, bool *swap, + SpvOp opcode, bool *swap, bool *exact, unsigned src_bit_size, unsigned dst_bit_size); void vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, diff --git a/src/gallium/auxiliary/draw/draw_gs.c b/src/gallium/auxiliary/draw/draw_gs.c index 9f9983d..3e087b9 100644 --- a/src/gallium/auxiliary/draw/draw_gs.c +++ b/src/gallium/auxiliary/draw/draw_gs.c @@ -964,6 +964,9 @@ void draw_delete_geometry_shader(struct draw_context *draw, } #endif + if (draw->gs.tgsi.machine && draw->gs.tgsi.machine->Tokens == dgs->state.tokens) + draw->gs.tgsi.machine->Tokens = NULL; + for (i = 0; i < TGSI_MAX_VERTEX_STREAMS; i++) FREE(dgs->stream[i].primitive_lengths); diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index 7d23ab0..58dd275 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -258,8 +258,6 @@ ntt_setup_uniforms(struct ntt_compile *c) var->data.image.format, !var->data.read_only, false); - } else if (var->data.mode == nir_var_mem_ubo) { - ureg_DECL_constant2D(c->ureg, 0, 0, var->data.driver_location + 1); } else { unsigned size; if (packed) { @@ -274,6 +272,10 @@ ntt_setup_uniforms(struct ntt_compile *c) } } + nir_foreach_variable_with_modes(var, c->s, nir_var_mem_ubo) { + ureg_DECL_constant2D(c->ureg, 0, 0, var->data.driver_location + 1); + } + for (int i = 0; i < PIPE_MAX_SAMPLERS; i++) { if (c->s->info.textures_used & (1 << i)) ureg_DECL_sampler(c->ureg, i); @@ -2183,6 +2185,9 @@ ntt_emit_impl(struct ntt_compile *c, nir_function_impl *impl) ntt_setup_registers(c, &impl->registers); ntt_emit_cf_list(c, &impl->body); + + ralloc_free(c->liveness); + c->liveness = NULL; } static int diff --git a/src/gallium/auxiliary/util/u_blitter.c b/src/gallium/auxiliary/util/u_blitter.c index 0019eb1..6ef6999 100644 --- a/src/gallium/auxiliary/util/u_blitter.c +++ b/src/gallium/auxiliary/util/u_blitter.c @@ -2918,7 +2918,7 @@ util_blitter_stencil_fallback(struct blitter_context *blitter, dstbox->x, dstbox->y, dstbox->x + dstbox->width, dstbox->y + dstbox->height, - 0, stencil_bits, + 0, 1, UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW, &coord); } diff --git a/src/gallium/drivers/etnaviv/etnaviv_zsa.c b/src/gallium/drivers/etnaviv/etnaviv_zsa.c index 66d0c29..b0f9499 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_zsa.c +++ b/src/gallium/drivers/etnaviv/etnaviv_zsa.c @@ -77,11 +77,13 @@ etna_zsa_state_create(struct pipe_context *pctx, if (so->stencil[0].fail_op != PIPE_STENCIL_OP_KEEP || so->stencil[0].zfail_op != PIPE_STENCIL_OP_KEEP || so->stencil[0].zpass_op != PIPE_STENCIL_OP_KEEP) { + cs->stencil_enabled = 1; cs->stencil_modified = 1; } else if (so->stencil[1].enabled) { if (so->stencil[1].fail_op != PIPE_STENCIL_OP_KEEP || so->stencil[1].zfail_op != PIPE_STENCIL_OP_KEEP || so->stencil[1].zpass_op != PIPE_STENCIL_OP_KEEP) { + cs->stencil_enabled = 1; cs->stencil_modified = 1; } } diff --git a/src/gallium/drivers/zink/zink_context.c b/src/gallium/drivers/zink/zink_context.c index 2f01fa7..67465b8 100644 --- a/src/gallium/drivers/zink/zink_context.c +++ b/src/gallium/drivers/zink/zink_context.c @@ -59,6 +59,7 @@ zink_context_destroy(struct pipe_context *pctx) if (vkQueueWaitIdle(ctx->queue) != VK_SUCCESS) debug_printf("vkQueueWaitIdle failed\n"); + pipe_resource_reference(&ctx->dummy_buffer, NULL); for (unsigned i = 0; i < ARRAY_SIZE(ctx->null_buffers); i++) pipe_resource_reference(&ctx->null_buffers[i], NULL); diff --git a/src/mesa/program/prog_statevars.c b/src/mesa/program/prog_statevars.c index 71c3313..aebff55 100644 --- a/src/mesa/program/prog_statevars.c +++ b/src/mesa/program/prog_statevars.c @@ -586,6 +586,18 @@ fetch_state(struct gl_context *ctx, const gl_state_index16 state[], } return; + case STATE_FB_PNTC_Y_TRANSFORM: + { + bool flip_y = (ctx->Point.SpriteOrigin == GL_LOWER_LEFT) ^ + (ctx->DrawBuffer->FlipY); + + value[0] = flip_y ? -1.0F : 1.0F; + value[1] = flip_y ? 1.0F : 0.0F; + value[2] = 0.0F; + value[3] = 0.0F; + } + return; + case STATE_TCS_PATCH_VERTICES_IN: val[0].i = ctx->TessCtrlProgram.patch_vertices; return; @@ -730,6 +742,9 @@ _mesa_program_state_flags(const gl_state_index16 state[STATE_LENGTH]) case STATE_FB_WPOS_Y_TRANSFORM: return _NEW_BUFFERS; + case STATE_FB_PNTC_Y_TRANSFORM: + return _NEW_BUFFERS | _NEW_POINT; + case STATE_ADVANCED_BLENDING_MODE: return _NEW_COLOR; @@ -942,6 +957,9 @@ append_token(char *dst, gl_state_index k) case STATE_FB_WPOS_Y_TRANSFORM: append(dst, "FbWposYTransform"); break; + case STATE_FB_PNTC_Y_TRANSFORM: + append(dst, "PntcYTransform"); + break; case STATE_ADVANCED_BLENDING_MODE: append(dst, "AdvancedBlendingMode"); break; diff --git a/src/mesa/program/prog_statevars.h b/src/mesa/program/prog_statevars.h index 4dc0123..8b14dd2 100644 --- a/src/mesa/program/prog_statevars.h +++ b/src/mesa/program/prog_statevars.h @@ -122,6 +122,7 @@ typedef enum gl_state_index_ { STATE_PT_BIAS, /**< Pixel transfer RGBA bias */ STATE_FB_SIZE, /**< (width-1, height-1, 0, 0) */ STATE_FB_WPOS_Y_TRANSFORM, /**< (1, 0, -1, height) if a FBO is bound, (-1, height, 1, 0) otherwise */ + STATE_FB_PNTC_Y_TRANSFORM, /**< (1, 0, 0, 0) if point origin is upper left, (-1, 1, 0, 0) otherwise */ STATE_TCS_PATCH_VERTICES_IN, /**< gl_PatchVerticesIn for TCS (integer) */ STATE_TES_PATCH_VERTICES_IN, /**< gl_PatchVerticesIn for TES (integer) */ /** diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c b/src/mesa/state_tracker/st_cb_drawpixels.c index c16ea1d..9180432 100644 --- a/src/mesa/state_tracker/st_cb_drawpixels.c +++ b/src/mesa/state_tracker/st_cb_drawpixels.c @@ -1570,6 +1570,7 @@ blit_copy_pixels(struct gl_context *ctx, GLint srcx, GLint srcy, !ctx->Color.BlendEnabled && !ctx->Color.AlphaEnabled && (!ctx->Color.ColorLogicOpEnabled || ctx->Color.LogicOp == GL_COPY) && + !ctx->Depth.BoundsTest && !ctx->Depth.Test && !ctx->Fog.Enabled && !ctx->Stencil.Enabled && diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c index 9f94566..326cbf5 100644 --- a/src/mesa/state_tracker/st_cb_texture.c +++ b/src/mesa/state_tracker/st_cb_texture.c @@ -1881,14 +1881,14 @@ st_CompressedTexSubImage(struct gl_context *ctx, GLuint dims, ? 0 : texImage->TexObject->MinLevel + texImage->Level; unsigned max_layer = util_max_layer(texture, level); - z += texImage->Face + texImage->TexObject->MinLayer; + GLint layer = z + texImage->Face + texImage->TexObject->MinLayer; struct pipe_surface templ; memset(&templ, 0, sizeof(templ)); templ.format = copy_format; templ.u.tex.level = level; - templ.u.tex.first_layer = MIN2(z, max_layer); - templ.u.tex.last_layer = MIN2(z + d - 1, max_layer); + templ.u.tex.first_layer = MIN2(layer, max_layer); + templ.u.tex.last_layer = MIN2(layer + d - 1, max_layer); surface = pipe->create_surface(pipe, texture, &templ); if (!surface) diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp b/src/mesa/state_tracker/st_glsl_to_nir.cpp index d483d52..a5bacc1 100644 --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp @@ -641,6 +641,14 @@ st_nir_lower_wpos_ytransform(struct nir_shader *nir, nir_validate_shader(nir, "after nir_lower_wpos_ytransform"); _mesa_add_state_reference(prog->Parameters, wposTransformState); } + + static const gl_state_index16 pntcTransformState[STATE_LENGTH] = { + STATE_INTERNAL, STATE_FB_PNTC_Y_TRANSFORM + }; + + if (nir_lower_pntc_ytransform(nir, &pntcTransformState)) { + _mesa_add_state_reference(prog->Parameters, pntcTransformState); + } } bool diff --git a/src/mesa/state_tracker/st_nir_builtins.c b/src/mesa/state_tracker/st_nir_builtins.c index b71edc6..0293023 100644 --- a/src/mesa/state_tracker/st_nir_builtins.c +++ b/src/mesa/state_tracker/st_nir_builtins.c @@ -26,6 +26,7 @@ #include "compiler/nir/nir_builder.h" #include "compiler/glsl/gl_nir.h" #include "nir/nir_to_tgsi.h" +#include "tgsi/tgsi_parse.h" struct pipe_shader_state * st_nir_finish_builtin_shader(struct st_context *st, @@ -83,21 +84,32 @@ st_nir_finish_builtin_shader(struct st_context *st, ralloc_free(nir); } + struct pipe_shader_state *shader; switch (stage) { case MESA_SHADER_VERTEX: - return pipe->create_vs_state(pipe, &state); + shader = pipe->create_vs_state(pipe, &state); + break; case MESA_SHADER_TESS_CTRL: - return pipe->create_tcs_state(pipe, &state); + shader = pipe->create_tcs_state(pipe, &state); + break; case MESA_SHADER_TESS_EVAL: - return pipe->create_tes_state(pipe, &state); + shader = pipe->create_tes_state(pipe, &state); + break; case MESA_SHADER_GEOMETRY: - return pipe->create_gs_state(pipe, &state); + shader = pipe->create_gs_state(pipe, &state); + break; case MESA_SHADER_FRAGMENT: - return pipe->create_fs_state(pipe, &state); + shader = pipe->create_fs_state(pipe, &state); + break; default: unreachable("unsupported shader stage"); return NULL; } + + if (state.type == PIPE_SHADER_IR_TGSI) + tgsi_free_tokens(state.tokens); + + return shader; } /** diff --git a/src/panfrost/midgard/mir_promote_uniforms.c b/src/panfrost/midgard/mir_promote_uniforms.c index 239020d..525ce59 100644 --- a/src/panfrost/midgard/mir_promote_uniforms.c +++ b/src/panfrost/midgard/mir_promote_uniforms.c @@ -195,7 +195,7 @@ midgard_promote_uniforms(compiler_context *ctx) unsigned type_size = nir_alu_type_get_type_size(ins->dest_type); midgard_instruction mov = v_mov(promoted, ins->dest); mov.dest_type = nir_type_uint | type_size; - mov.src_types[0] = mov.dest_type; + mov.src_types[1] = mov.dest_type; uint16_t rounded = mir_round_bytemask_up(mir_bytemask(ins), type_size); mir_set_bytemask(&mov, rounded); diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf index ca38c7d..fd5791f 100644 --- a/src/util/00-mesa-defaults.conf +++ b/src/util/00-mesa-defaults.conf @@ -637,6 +637,7 @@ TODO: document the other workarounds.