From c21fa6bb59ba6a9f5a8729d712ea686586a6679a Mon Sep 17 00:00:00 2001 From: Packit Service Date: Jan 12 2021 08:28:40 +0000 Subject: mesa-20.3.2 base --- diff --git a/.pick_status.json b/.pick_status.json index 607c9c4..d239861 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1,5 +1,3398 @@ [ { + "sha": "6c8cc9be12dc5d6c0d2386d6addb69d8f2fb5399", + "description": "glsl: default to compat shaders in compat profile", + "nominated": true, + "nomination_type": 1, + "resolution": 1, + "master_sha": null, + "because_sha": "c7e3d31b0b5f22299a6bd72655502ce8427b40bf" + }, + { + "sha": "5692e2dda5cac0d8042bc7637b8d201acdc7e2f8", + "description": "intel/isl: move get_tile dims/masks to common isl header", + "nominated": false, + "nomination_type": null, + "resolution": 4, + "master_sha": null, + "because_sha": null + }, + { + "sha": "02328637c1af9a4dce8d6743641241344b17d606", + "description": "freedreno: Enable GLSL 1.50, updating us to GL 3.2 contexts.", + "nominated": false, + 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"e640a9ca79f29814235fff388c5460d9b12cb529", + "description": "util: Fix memory leak in a hash table unit test.", + "nominated": false, + "nomination_type": null, + "resolution": 4, + "master_sha": null, + "because_sha": null + }, + { + "sha": "547d11de54c6863dc73446181b80f4f368808c3c", + "description": "etnaviv, v3d: Fix valgrind include paths.", + "nominated": false, + "nomination_type": null, + "resolution": 4, + "master_sha": null, + "because_sha": null + }, + { "sha": "ada9be1ec9e14fc045086411fbf2d3cb0efbbe2f", "description": "radv,aco: Compile with -Wimplicit-fallthrough when available", "nominated": false, @@ -256,7 +3649,7 @@ "description": "aco/spill: only prevent rematerializable vars from being DCE'd if they haven't been renamed", "nominated": false, "nomination_type": null, - "resolution": 4, + "resolution": 1, "master_sha": null, "because_sha": null }, @@ -265,7 +3658,7 @@ "description": "aco: fix DCE of rematerializable phi operands", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "d48d72e98af9436babeeb3a94b312f94bc582b36" }, diff --git a/VERSION b/VERSION index dd0fe95..3eda575 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -20.3.1 +20.3.2 diff --git a/docs/relnotes/20.3.1.rst b/docs/relnotes/20.3.1.rst index bea77d3..b6d8b74 100644 --- a/docs/relnotes/20.3.1.rst +++ b/docs/relnotes/20.3.1.rst @@ -19,7 +19,7 @@ SHA256 checksum :: - TBD. + af751b49bb2ab0264d58c31e73d869e80333de02b2d1becc93f1b28c67aa780f mesa-20.3.1.tar.xz New features diff --git a/docs/relnotes/20.3.2.rst b/docs/relnotes/20.3.2.rst new file mode 100644 index 0000000..ba5cfd3 --- /dev/null +++ b/docs/relnotes/20.3.2.rst @@ -0,0 +1,138 @@ +Mesa 20.3.2 Release Notes / 2020-12-30 +====================================== + +Mesa 20.3.2 is a bug fix release which fixes bugs found since the 20.3.1 release. + +Mesa 20.3.2 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 20.3.2 implements the Vulkan 1.2 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + TBD. + + +New features +------------ + +- None + + +Bug fixes +--------- + +- \`gl_FragColor' undeclared (AMDGPU) - tested stable Mesa 20.1 and latest git for 20.3 (Game/Wine/Proton) +- Mesa considers the framebuffer with mixed 3D and 2D array attachments to be incomplete. +- Multiple buffer definitions bound to single OpDecorate::Binding break SPIR-V module. +- Intel driver segfaults on SPIR-V with OpArrayLength + + +Changes +------- + +Bas Nieuwenhuizen (1): + +- radv: Don't skip layout transitions that only differ in render loop. + +Caio Marcelo de Oliveira Filho (3): + +- spirv: Implement OpArrayLength for OpenGL +- nir: Consider pointer initializers in nir_remove_dead_variables +- spirv: Remove more dead variables + +Daniel Schürmann (4): + +- aco: fix DCE of rematerializable phi operands +- aco/spill: only prevent rematerializable vars from being DCE'd if they haven't been renamed +- aco/ra: fix phi operand renaming +- nir/opt_if: split ALU from Phi more aggressively + +Danylo Piliaiev (4): + +- tu: Ignore pTessellationState if there is no tesselation shaders +- tu: pCounterBuffers can be NULL in vkCmd*TransformFeedbackEXT() +- freedreno/a6xx: Fix assert which checks the count of shader outputs +- ir3: Allow tesselation to use all 32 varying slots + +Dylan Baker (11): + +- docs: Add sha256 sums for 20.3.1 +- .pick_status.json: Update to 2d78e28ba702d366becabb8e241b861e6711c76e +- .pick_status.json: Update to 661922f6ac9576fc2077c5d50b53ef7edf9e8a18 +- .pick_status.json: Update to f65750d2215242b17309b5aa8845b717bb913e77 +- .pick_status.json: Update to b9fccafed616aa2906dad3c77dca0c67af5017b8 +- .pick_status.json: Mark f65750d2215242b17309b5aa8845b717bb913e77 as backported +- .pick_status.json: Update to 8db0775f4520e08b3c539f9bd2d1f567639c088c +- .pick_status.json: Update to a22b85ce5e825275533ca1be9fbd47667e991356 +- .pick_status.json: Update to 9ef23e428bd18c412499471b4e3550a489b72c3f +- .pick_status.json: Mark 967ae12931e0dc12855de903851222b2f0607878 as denominated +- .pick_status.json: Update to 6c8cc9be12dc5d6c0d2386d6addb69d8f2fb5399 + +Eric Anholt (5): + +- mesa/st: Finalize the texture before BlitFramebuffer from it. +- freedreno/a6xx: Flush depth at the end of bypass rendering, too. +- softpipe: count CS invocations for pipeline stats queries. +- mesa/st: Update FP state when textures change with an ATI_fs bound. +- ci/deqp: Fix inverted meaning of DEQP_NO_SAVE_RESULTS. + +Erik Faye-Lund (2): + +- zink: fix 8 bit index handling code +- zink: fix format-mapping + +Hyunjun Ko (1): + +- turnip: use ir3_compiler_destroy instead of ralloc_free + +Icecream95 (1): + +- panfrost: Fix panfrost_small_padded_vertex_count for 17 vertices + +Marek Olšák (1): + +- radeonsi: fix small primitive culling with MSAA force-disabled and smoothing + +Mike Blumenkrantz (3): + +- st/mesa: set drawpixels swizzle before creating sampler view +- zink: handle null ubos +- st/pbo: fix pbo uploads without PIPE_CAP_TGSI_VS_LAYER_VIEWPORT and skip gs + +Pierre-Eric Pelloux-Prayer (1): + +- egl: fix EGL_EXT_protected_content/surface mixup + +Rhys Perry (1): + +- aco: add block to worklist in mark_block_wqm() + +Ruijing Dong (1): + +- radeon/vcn: fix hevc 10bit profile error + +Ryan Neph (1): + +- virgl: fix BGRA emulation artifacts during window resize + +Samuel Pitoiset (1): + +- radv: add missing DB flush after depth/stencil resolve operations + +Tapani Pälli (1): + +- mesa: fix layered framebuffer attachment target check + +Timothy Arceri (1): + +- glsl: default to compat shaders in compat profile diff --git a/src/amd/compiler/aco_insert_exec_mask.cpp b/src/amd/compiler/aco_insert_exec_mask.cpp index 638157c..8a13564 100644 --- a/src/amd/compiler/aco_insert_exec_mask.cpp +++ b/src/amd/compiler/aco_insert_exec_mask.cpp @@ -165,6 +165,8 @@ void mark_block_wqm(wqm_ctx &ctx, unsigned block_idx) return; ctx.branch_wqm[block_idx] = true; + ctx.worklist.insert(block_idx); + Block& block = ctx.program->blocks[block_idx]; /* TODO: this sets more branch conditions to WQM than it needs to diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index 3cf0153..c2215da 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -1637,6 +1637,11 @@ Temp handle_live_in(ra_ctx& ctx, Temp val, Block* block) phi->operands[i].setFixed(ctx.assignments[ops[i].id()].reg); if (ops[i].regClass() == new_val.regClass()) ctx.affinities[new_val.id()] = ops[i].id(); + /* make sure the operand gets it's original name in case + * it comes from an incomplete phi */ + std::unordered_map::iterator it = ctx.phi_map.find(ops[i].id()); + if (it != ctx.phi_map.end()) + it->second.uses.emplace(phi.get()); } ctx.assignments.emplace_back(); assert(ctx.assignments.size() == ctx.program->peekAllocationId()); diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp index 67c6712..bfc1f66 100644 --- a/src/amd/compiler/aco_spill.cpp +++ b/src/amd/compiler/aco_spill.cpp @@ -832,6 +832,11 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) assert(phi->operands[i].isTemp() && phi->operands[i].isKill()); Temp var = phi->operands[i].getTemp(); + std::map::iterator rename_it = ctx.renames[pred_idx].find(var); + /* prevent the definining instruction from being DCE'd if it could be rematerialized */ + if (rename_it == ctx.renames[preds[i]].end() && ctx.remat.count(var)) + ctx.remat_used[ctx.remat[var].instr] = true; + /* build interferences between the phi def and all spilled variables at the predecessor blocks */ for (std::pair pair : ctx.spills_exit[pred_idx]) { if (var == pair.first) @@ -848,7 +853,6 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) } /* rename if necessary */ - std::map::iterator rename_it = ctx.renames[pred_idx].find(var); if (rename_it != ctx.renames[pred_idx].end()) { var = rename_it->second; ctx.renames[pred_idx].erase(rename_it); @@ -939,6 +943,9 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) std::map::iterator it = ctx.renames[pred_idx].find(phi->operands[i].getTemp()); if (it != ctx.renames[pred_idx].end()) phi->operands[i].setTemp(it->second); + /* prevent the definining instruction from being DCE'd if it could be rematerialized */ + else if (ctx.remat.count(phi->operands[i].getTemp())) + ctx.remat_used[ctx.remat[phi->operands[i].getTemp()].instr] = true; continue; } @@ -1028,12 +1035,16 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) rename = ctx.program->allocateTmp(pair.first.regClass()); for (unsigned i = 0; i < phi->operands.size(); i++) { Temp tmp; - if (ctx.renames[preds[i]].find(pair.first) != ctx.renames[preds[i]].end()) + if (ctx.renames[preds[i]].find(pair.first) != ctx.renames[preds[i]].end()) { tmp = ctx.renames[preds[i]][pair.first]; - else if (preds[i] >= block_idx) + } else if (preds[i] >= block_idx) { tmp = rename; - else + } else { tmp = pair.first; + /* prevent the definining instruction from being DCE'd if it could be rematerialized */ + if (ctx.remat.count(tmp)) + ctx.remat_used[ctx.remat[tmp].instr] = true; + } phi->operands[i] = Operand(tmp); } phi->definitions[0] = Definition(rename); @@ -1076,14 +1087,7 @@ void process_block(spill_ctx& ctx, unsigned block_idx, Block* block, /* phis are handled separetely */ while (block->instructions[idx]->opcode == aco_opcode::p_phi || block->instructions[idx]->opcode == aco_opcode::p_linear_phi) { - aco_ptr& instr = block->instructions[idx]; - for (const Operand& op : instr->operands) { - /* prevent it's definining instruction from being DCE'd if it could be rematerialized */ - if (op.isTemp() && ctx.remat.count(op.getTemp())) - ctx.remat_used[ctx.remat[op.getTemp()].instr] = true; - } - instructions.emplace_back(std::move(instr)); - idx++; + instructions.emplace_back(std::move(block->instructions[idx++])); } if (block->register_demand.exceeds(ctx.target_pressure)) @@ -1103,7 +1107,7 @@ void process_block(spill_ctx& ctx, unsigned block_idx, Block* block, if (ctx.renames[block_idx].find(op.getTemp()) != ctx.renames[block_idx].end()) op.setTemp(ctx.renames[block_idx][op.getTemp()]); /* prevent it's definining instruction from being DCE'd if it could be rematerialized */ - if (ctx.remat.count(op.getTemp())) + else if (ctx.remat.count(op.getTemp())) ctx.remat_used[ctx.remat[op.getTemp()].instr] = true; continue; } @@ -1247,16 +1251,6 @@ void spill_block(spill_ctx& ctx, unsigned block_idx) /* add coupling code to all loop header predecessors */ add_coupling_code(ctx, loop_header, loop_header->index); - /* update remat_used for phis added in add_coupling_code() */ - for (aco_ptr& instr : loop_header->instructions) { - if (!is_phi(instr)) - break; - for (const Operand& op : instr->operands) { - if (op.isTemp() && ctx.remat.count(op.getTemp())) - ctx.remat_used[ctx.remat[op.getTemp()].instr] = true; - } - } - /* propagate new renames through loop: i.e. repair the SSA */ renames.swap(ctx.renames[loop_header->index]); for (std::pair rename : renames) { diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 25718e4..5555f7c 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6214,7 +6214,7 @@ static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, return; } - if (src_layout == dst_layout) + if (src_layout == dst_layout && src_render_loop == dst_render_loop) return; unsigned src_queue_mask = diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index 809522b..9e42194 100644 --- a/src/amd/vulkan/radv_meta_resolve.c +++ b/src/amd/vulkan/radv_meta_resolve.c @@ -790,6 +790,26 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer) subpass->stencil_resolve_mode); } } + + /* From the Vulkan spec 1.2.165: + * + * "VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT specifies + * write access to a color, resolve, or depth/stencil + * resolve attachment during a render pass or via + * certain subpass load and store operations." + * + * Yes, it's counterintuitive but it makes sense because ds + * resolve operations happen late at the end of the subpass. + * + * That said, RADV is wrong because it executes the subpass + * end barrier *before* any subpass resolves instead of after. + * + * TODO: Fix this properly by executing subpass end barriers + * after subpass resolves. + */ + cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB; + if (radv_image_has_htile(dst_iview->image)) + cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; } if (!subpass->has_color_resolve) diff --git a/src/compiler/glsl/glsl_parser_extras.cpp b/src/compiler/glsl/glsl_parser_extras.cpp index 7daf65b..6c735ea 100644 --- a/src/compiler/glsl/glsl_parser_extras.cpp +++ b/src/compiler/glsl/glsl_parser_extras.cpp @@ -396,14 +396,13 @@ _mesa_glsl_parse_state::process_version_directive(YYLTYPE *locp, int version, { bool es_token_present = false; bool compat_token_present = false; + bool core_token_present = false; if (ident) { if (strcmp(ident, "es") == 0) { es_token_present = true; } else if (version >= 150) { if (strcmp(ident, "core") == 0) { - /* Accept the token. There's no need to record that this is - * a core profile shader since that's the only profile we support. - */ + core_token_present = true; } else if (strcmp(ident, "compatibility") == 0) { compat_token_present = true; @@ -444,7 +443,8 @@ _mesa_glsl_parse_state::process_version_directive(YYLTYPE *locp, int version, this->compat_shader = compat_token_present || (this->ctx->API == API_OPENGL_COMPAT && - this->language_version == 140) || + this->language_version >= 140 && + !core_token_present) || (!this->es_shader && this->language_version < 140); bool supported = false; diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c index 31195b1..e25c66f 100644 --- a/src/compiler/nir/nir_opt_if.c +++ b/src/compiler/nir/nir_opt_if.c @@ -295,6 +295,39 @@ alu_instr_is_type_conversion(const nir_alu_instr *alu) nir_op_infos[alu->op].output_type != nir_op_infos[alu->op].input_types[0]; } +static bool +is_trivial_bcsel(const nir_instr *instr, bool allow_non_phi_src) +{ + if (instr->type != nir_instr_type_alu) + return false; + + nir_alu_instr *const bcsel = nir_instr_as_alu(instr); + if (bcsel->op != nir_op_bcsel && + bcsel->op != nir_op_b32csel && + bcsel->op != nir_op_fcsel) + return false; + + for (unsigned i = 0; i < 3; i++) { + if (!nir_alu_src_is_trivial_ssa(bcsel, i) || + bcsel->src[i].src.ssa->parent_instr->block != instr->block) + return false; + + if (bcsel->src[i].src.ssa->parent_instr->type != nir_instr_type_phi) { + /* opt_split_alu_of_phi() is able to peel that src from the loop */ + if (i == 0 || !allow_non_phi_src) + return false; + allow_non_phi_src = false; + } + } + + nir_foreach_phi_src(src, nir_instr_as_phi(bcsel->src[0].src.ssa->parent_instr)) { + if (!nir_src_is_const(src->src)) + return false; + } + + return true; +} + /** * Splits ALU instructions that have a source that is a phi node * @@ -306,12 +339,13 @@ alu_instr_is_type_conversion(const nir_alu_instr *alu) * * - At least one source of the instruction is a phi node from the header block. * - * - The phi node selects a constant or undef from the block before the loop. - * * - Any non-phi sources of the ALU instruction come from a block that * dominates the block before the loop. The most common failure mode for * this check is sources that are generated in the loop header block. * + * - The phi node selects a constant or undef from the block before the loop or + * the only ALU user is a trivial bcsel that gets removed by peeling the ALU + * * The split process splits the original ALU instruction into two, one at the * bottom of the loop and one at the block before the loop. The instruction * before the loop computes the value on the first iteration, and the @@ -450,60 +484,72 @@ opt_split_alu_of_phi(nir_builder *b, nir_loop *loop) } } - if (has_phi_src_from_prev_block && all_non_phi_exist_in_prev_block && - (is_prev_result_undef || is_prev_result_const)) { - nir_block *const continue_block = find_continue_block(loop); + if (!has_phi_src_from_prev_block || !all_non_phi_exist_in_prev_block) + continue; - b->cursor = nir_after_block(prev_block); - nir_ssa_def *prev_value = clone_alu_and_replace_src_defs(b, alu, prev_srcs); + if (!is_prev_result_undef && !is_prev_result_const) { + /* check if the only user is a trivial bcsel */ + if (!list_is_empty(&alu->dest.dest.ssa.if_uses) || + !list_is_singular(&alu->dest.dest.ssa.uses)) + continue; - /* Make a copy of the original ALU instruction. Replace the sources - * of the new instruction that read a phi with an undef source from - * prev_block with the non-undef source of that phi. - * - * Insert the new instruction at the end of the continue block. - */ - b->cursor = nir_after_block_before_jump(continue_block); + nir_src *use = list_first_entry(&alu->dest.dest.ssa.uses, nir_src, use_link); + if (!is_trivial_bcsel(use->parent_instr, true)) + continue; + } + + /* Split ALU of Phi */ + nir_block *const continue_block = find_continue_block(loop); - nir_ssa_def *const alu_copy = - clone_alu_and_replace_src_defs(b, alu, continue_srcs); + b->cursor = nir_after_block(prev_block); + nir_ssa_def *prev_value = clone_alu_and_replace_src_defs(b, alu, prev_srcs); - /* Make a new phi node that selects a value from prev_block and the - * result of the new instruction from continue_block. - */ - nir_phi_instr *const phi = nir_phi_instr_create(b->shader); - nir_phi_src *phi_src; + /* Make a copy of the original ALU instruction. Replace the sources + * of the new instruction that read a phi with an undef source from + * prev_block with the non-undef source of that phi. + * + * Insert the new instruction at the end of the continue block. + */ + b->cursor = nir_after_block_before_jump(continue_block); + + nir_ssa_def *const alu_copy = + clone_alu_and_replace_src_defs(b, alu, continue_srcs); + + /* Make a new phi node that selects a value from prev_block and the + * result of the new instruction from continue_block. + */ + nir_phi_instr *const phi = nir_phi_instr_create(b->shader); + nir_phi_src *phi_src; - phi_src = ralloc(phi, nir_phi_src); - phi_src->pred = prev_block; - phi_src->src = nir_src_for_ssa(prev_value); - exec_list_push_tail(&phi->srcs, &phi_src->node); + phi_src = ralloc(phi, nir_phi_src); + phi_src->pred = prev_block; + phi_src->src = nir_src_for_ssa(prev_value); + exec_list_push_tail(&phi->srcs, &phi_src->node); - phi_src = ralloc(phi, nir_phi_src); - phi_src->pred = continue_block; - phi_src->src = nir_src_for_ssa(alu_copy); - exec_list_push_tail(&phi->srcs, &phi_src->node); + phi_src = ralloc(phi, nir_phi_src); + phi_src->pred = continue_block; + phi_src->src = nir_src_for_ssa(alu_copy); + exec_list_push_tail(&phi->srcs, &phi_src->node); - nir_ssa_dest_init(&phi->instr, &phi->dest, - alu_copy->num_components, alu_copy->bit_size, NULL); + nir_ssa_dest_init(&phi->instr, &phi->dest, + alu_copy->num_components, alu_copy->bit_size, NULL); - b->cursor = nir_after_phis(header_block); - nir_builder_instr_insert(b, &phi->instr); + b->cursor = nir_after_phis(header_block); + nir_builder_instr_insert(b, &phi->instr); - /* Modify all readers of the original ALU instruction to read the - * result of the phi. - */ - nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, - nir_src_for_ssa(&phi->dest.ssa)); + /* Modify all readers of the original ALU instruction to read the + * result of the phi. + */ + nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, + nir_src_for_ssa(&phi->dest.ssa)); - /* Since the original ALU instruction no longer has any readers, just - * remove it. - */ - nir_instr_remove_v(&alu->instr); - ralloc_free(alu); + /* Since the original ALU instruction no longer has any readers, just + * remove it. + */ + nir_instr_remove_v(&alu->instr); + ralloc_free(alu); - progress = true; - } + progress = true; } return progress; @@ -624,32 +670,10 @@ opt_simplify_bcsel_of_phi(nir_builder *b, nir_loop *loop) * https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/170#note_110305 */ nir_foreach_instr_safe(instr, header_block) { - if (instr->type != nir_instr_type_alu) + if (!is_trivial_bcsel(instr, false)) continue; nir_alu_instr *const bcsel = nir_instr_as_alu(instr); - if (bcsel->op != nir_op_bcsel && - bcsel->op != nir_op_b32csel && - bcsel->op != nir_op_fcsel) - continue; - - bool match = true; - for (unsigned i = 0; i < 3; i++) { - /* FINISHME: The abs, negate and swizzled cases could be handled by - * adding move instructions at the bottom of the continue block and - * more phi nodes in the header_block. - */ - if (!nir_alu_src_is_trivial_ssa(bcsel, i) || - bcsel->src[i].src.ssa->parent_instr->type != nir_instr_type_phi || - bcsel->src[i].src.ssa->parent_instr->block != header_block) { - match = false; - break; - } - } - - if (!match) - continue; - nir_phi_instr *const cond_phi = nir_instr_as_phi(bcsel->src[0].src.ssa->parent_instr); diff --git a/src/compiler/nir/nir_remove_dead_variables.c b/src/compiler/nir/nir_remove_dead_variables.c index 01ea18c..5555ca3 100644 --- a/src/compiler/nir/nir_remove_dead_variables.c +++ b/src/compiler/nir/nir_remove_dead_variables.c @@ -67,14 +67,21 @@ add_var_use_deref(nir_deref_instr *deref, struct set *live) if (deref->deref_type != nir_deref_type_var) return; - /* If it's not a local that never escapes the shader, then any access at - * all means we need to keep it alive. + /* Since these local variables don't escape the shader, writing doesn't + * make them live. Only keep them if they are used by some intrinsic. */ - if (!(deref->var->data.mode & (nir_var_function_temp | - nir_var_shader_temp | - nir_var_mem_shared)) || - deref_used_for_not_store(deref)) - _mesa_set_add(live, deref->var); + if ((deref->var->data.mode & (nir_var_function_temp | + nir_var_shader_temp | + nir_var_mem_shared)) && + !deref_used_for_not_store(deref)) + return; + + nir_variable *var = deref->var; + do { + _mesa_set_add(live, var); + /* Also mark the chain of variables used to initialize it. */ + var = var->pointer_initializer; + } while (var); } static void diff --git a/src/compiler/nir/tests/vars_tests.cpp b/src/compiler/nir/tests/vars_tests.cpp index 6d27830..593f183 100644 --- a/src/compiler/nir/tests/vars_tests.cpp +++ b/src/compiler/nir/tests/vars_tests.cpp @@ -197,6 +197,7 @@ class nir_copy_prop_vars_test : public nir_vars_test {}; class nir_dead_write_vars_test : public nir_vars_test {}; class nir_combine_stores_test : public nir_vars_test {}; class nir_split_vars_test : public nir_vars_test {}; +class nir_remove_dead_variables_test : public nir_vars_test {}; } // namespace @@ -2185,3 +2186,50 @@ TEST_F(nir_split_vars_test, split_wildcard_copy) ASSERT_EQ(count_function_temp_vars(), 8); ASSERT_EQ(count_intrinsics(nir_intrinsic_copy_deref), 4); } + +TEST_F(nir_remove_dead_variables_test, pointer_initializer_used) +{ + nir_variable *x = create_int(nir_var_shader_temp, "x"); + nir_variable *y = create_int(nir_var_shader_temp, "y"); + y->pointer_initializer = x; + nir_variable *out = create_int(nir_var_shader_out, "out"); + + nir_validate_shader(b->shader, NULL); + + nir_copy_var(b, out, y); + + bool progress = nir_remove_dead_variables(b->shader, nir_var_all, NULL); + EXPECT_FALSE(progress); + + nir_validate_shader(b->shader, NULL); + + unsigned count = 0; + nir_foreach_variable_in_shader(var, b->shader) + count++; + + ASSERT_EQ(count, 3); +} + +TEST_F(nir_remove_dead_variables_test, pointer_initializer_dead) +{ + nir_variable *x = create_int(nir_var_shader_temp, "x"); + nir_variable *y = create_int(nir_var_shader_temp, "y"); + nir_variable *z = create_int(nir_var_shader_temp, "z"); + y->pointer_initializer = x; + z->pointer_initializer = y; + + nir_validate_shader(b->shader, NULL); + + bool progress = nir_remove_dead_variables(b->shader, nir_var_all, NULL); + EXPECT_TRUE(progress); + + nir_validate_shader(b->shader, NULL); + + unsigned count = 0; + nir_foreach_variable_in_shader(var, b->shader) + count++; + + ASSERT_EQ(count, 0); +} + + diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h index 5964184..750c777 100644 --- a/src/compiler/spirv/nir_spirv.h +++ b/src/compiler/spirv/nir_spirv.h @@ -69,6 +69,11 @@ struct spirv_to_nir_options { /* Create a nir library. */ bool create_library; + /* Whether to use nir_intrinsic_deref_buffer_array_length intrinsic instead + * of nir_intrinsic_get_ssbo_size to lower OpArrayLength. + */ + bool use_deref_buffer_array_length; + struct spirv_supported_capabilities caps; /* Address format for various kinds of pointers. */ diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index a5288a6..c031504 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -5841,19 +5841,23 @@ spirv_to_nir(const uint32_t *words, size_t word_count, /* structurize the CFG */ nir_lower_goto_ifs(b->shader); - /* When multiple shader stages exist in the same SPIR-V module, we - * generate input and output variables for every stage, in the same - * NIR program. These dead variables can be invalid NIR. For example, - * TCS outputs must be per-vertex arrays (or decorated 'patch'), while - * VS output variables wouldn't be. + /* A SPIR-V module can have multiple shaders stages and also multiple + * shaders of the same stage. Global variables are declared per-module, so + * they are all collected when parsing a single shader. These dead + * variables can result in invalid NIR, e.g. * - * To ensure we have valid NIR, we eliminate any dead inputs and outputs - * right away. In order to do so, we must lower any constant initializers - * on outputs so nir_remove_dead_variables sees that they're written to. + * - TCS outputs must be per-vertex arrays (or decorated 'patch'), while VS + * output variables wouldn't be; + * - Two vertex shaders have two different typed blocks associated to the + * same Binding. + * + * Before cleaning the dead variables, we must lower any constant + * initializers on outputs so nir_remove_dead_variables sees that they're + * written to. */ - nir_lower_variable_initializers(b->shader, nir_var_shader_out); - nir_remove_dead_variables(b->shader, - nir_var_shader_in | nir_var_shader_out, NULL); + nir_lower_variable_initializers(b->shader, nir_var_shader_out | + nir_var_system_value); + nir_remove_dead_variables(b->shader, ~nir_var_function_temp, NULL); /* We sometimes generate bogus derefs that, while never used, give the * validator a bit of heartburn. Run dead code to get rid of them. diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 168d0e5..8317116 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src/compiler/spirv/vtn_variables.c @@ -2434,36 +2434,55 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode, "OpArrayLength must reference the last memeber of the " "structure and that must be an array"); - const uint32_t offset = ptr->type->offsets[field]; - const uint32_t stride = ptr->type->members[field]->stride; - - if (!ptr->block_index) { + if (b->options->use_deref_buffer_array_length) { struct vtn_access_chain chain = { - .length = 0, + .length = 1, + .link = { + { .mode = vtn_access_mode_literal, .id = field }, + } }; - ptr = vtn_pointer_dereference(b, ptr, &chain); - vtn_assert(ptr->block_index); - } + struct vtn_pointer *array = vtn_pointer_dereference(b, ptr, &chain); - nir_intrinsic_instr *instr = - nir_intrinsic_instr_create(b->nb.shader, - nir_intrinsic_get_ssbo_size); - instr->src[0] = nir_src_for_ssa(ptr->block_index); - nir_ssa_dest_init(&instr->instr, &instr->dest, 1, 32, NULL); - nir_builder_instr_insert(&b->nb, &instr->instr); - nir_ssa_def *buf_size = &instr->dest.ssa; - - /* array_length = max(buffer_size - offset, 0) / stride */ - nir_ssa_def *array_length = - nir_idiv(&b->nb, - nir_imax(&b->nb, - nir_isub(&b->nb, - buf_size, - nir_imm_int(&b->nb, offset)), - nir_imm_int(&b->nb, 0u)), - nir_imm_int(&b->nb, stride)); - - vtn_push_nir_ssa(b, w[2], array_length); + nir_intrinsic_instr *instr = + nir_intrinsic_instr_create(b->nb.shader, + nir_intrinsic_deref_buffer_array_length); + instr->src[0] = nir_src_for_ssa(vtn_pointer_to_ssa(b, array)); + nir_ssa_dest_init(&instr->instr, &instr->dest, 1, 32, NULL); + nir_builder_instr_insert(&b->nb, &instr->instr); + + vtn_push_nir_ssa(b, w[2], &instr->dest.ssa); + } else { + const uint32_t offset = ptr->type->offsets[field]; + const uint32_t stride = ptr->type->members[field]->stride; + + if (!ptr->block_index) { + struct vtn_access_chain chain = { + .length = 0, + }; + ptr = vtn_pointer_dereference(b, ptr, &chain); + vtn_assert(ptr->block_index); + } + + nir_intrinsic_instr *instr = + nir_intrinsic_instr_create(b->nb.shader, + nir_intrinsic_get_ssbo_size); + instr->src[0] = nir_src_for_ssa(ptr->block_index); + nir_ssa_dest_init(&instr->instr, &instr->dest, 1, 32, NULL); + nir_builder_instr_insert(&b->nb, &instr->instr); + nir_ssa_def *buf_size = &instr->dest.ssa; + + /* array_length = max(buffer_size - offset, 0) / stride */ + nir_ssa_def *array_length = + nir_idiv(&b->nb, + nir_imax(&b->nb, + nir_isub(&b->nb, + buf_size, + nir_imm_int(&b->nb, offset)), + nir_imm_int(&b->nb, 0u)), + nir_imm_int(&b->nb, stride)); + + vtn_push_nir_ssa(b, w[2], array_length); + } break; } diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index df5e354..a58e355 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -1021,7 +1021,7 @@ dri2_setup_screen(_EGLDisplay *disp) if (dri2_dpy->buffer_damage && dri2_dpy->buffer_damage->set_damage_region) disp->Extensions.KHR_partial_update = EGL_TRUE; - disp->Extensions.EXT_protected_content = + disp->Extensions.EXT_protected_surface = dri2_renderer_query_integer(dri2_dpy, __DRI2_RENDERER_HAS_PROTECTED_CONTENT); } diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c index 56dafca..9613d69 100644 --- a/src/egl/main/eglapi.c +++ b/src/egl/main/eglapi.c @@ -496,7 +496,7 @@ _eglCreateExtensionsString(_EGLDisplay *disp) _EGL_CHECK_EXTENSION(EXT_create_context_robustness); _EGL_CHECK_EXTENSION(EXT_image_dma_buf_import); _EGL_CHECK_EXTENSION(EXT_image_dma_buf_import_modifiers); - _EGL_CHECK_EXTENSION(EXT_protected_content); + _EGL_CHECK_EXTENSION(EXT_protected_surface); _EGL_CHECK_EXTENSION(EXT_surface_CTA861_3_metadata); _EGL_CHECK_EXTENSION(EXT_surface_SMPTE2086_metadata); _EGL_CHECK_EXTENSION(EXT_swap_buffers_with_damage); diff --git a/src/egl/main/egldisplay.h b/src/egl/main/egldisplay.h index 46c3008..ff33e91 100644 --- a/src/egl/main/egldisplay.h +++ b/src/egl/main/egldisplay.h @@ -106,7 +106,7 @@ struct _egl_extensions EGLBoolean EXT_image_dma_buf_import; EGLBoolean EXT_image_dma_buf_import_modifiers; EGLBoolean EXT_pixel_format_float; - EGLBoolean EXT_protected_content; + EGLBoolean EXT_protected_surface; EGLBoolean EXT_surface_CTA861_3_metadata; EGLBoolean EXT_surface_SMPTE2086_metadata; EGLBoolean EXT_swap_buffers_with_damage; diff --git a/src/egl/main/eglimage.c b/src/egl/main/eglimage.c index 1c0ebe8..64bf7f2 100644 --- a/src/egl/main/eglimage.c +++ b/src/egl/main/eglimage.c @@ -59,7 +59,7 @@ _eglParseKHRImageAttribs(_EGLImageAttribs *attrs, _EGLDisplay *disp, attrs->GLTextureZOffset = val; break; case EGL_PROTECTED_CONTENT_EXT: - if (!disp->Extensions.EXT_protected_content) + if (!disp->Extensions.EXT_protected_surface) return EGL_BAD_PARAMETER; attrs->ProtectedContent = val; diff --git a/src/egl/main/eglsurface.c b/src/egl/main/eglsurface.c index 9faa800..aee5217 100644 --- a/src/egl/main/eglsurface.c +++ b/src/egl/main/eglsurface.c @@ -304,7 +304,7 @@ _eglParseSurfaceAttribList(_EGLSurface *surf, const EGLint *attrib_list) surf->MipmapTexture = !!val; break; case EGL_PROTECTED_CONTENT_EXT: - if (!disp->Extensions.EXT_protected_content) { + if (!disp->Extensions.EXT_protected_surface) { err = EGL_BAD_ATTRIBUTE; break; } @@ -591,7 +591,7 @@ _eglQuerySurface(_EGLDisplay *disp, _EGLSurface *surface, *value = surface->HdrMetadata.max_fall; break; case EGL_PROTECTED_CONTENT_EXT: - if (!disp->Extensions.EXT_protected_content) + if (!disp->Extensions.EXT_protected_surface) return _eglError(EGL_BAD_ATTRIBUTE, "eglQuerySurface"); *value = surface->ProtectedContent; break; diff --git a/src/freedreno/ir3/ir3_nir_lower_tess.c b/src/freedreno/ir3/ir3_nir_lower_tess.c index 87b49c9..fbb0541 100644 --- a/src/freedreno/ir3/ir3_nir_lower_tess.c +++ b/src/freedreno/ir3/ir3_nir_lower_tess.c @@ -29,7 +29,7 @@ struct state { uint32_t topology; struct primitive_map { - unsigned loc[32]; + unsigned loc[32 + 4]; /* +POSITION +PSIZE +CLIP_DIST0 +CLIP_DIST1 */ unsigned stride; } map; diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h index 36aba4f..59c68d5 100644 --- a/src/freedreno/ir3/ir3_shader.h +++ b/src/freedreno/ir3/ir3_shader.h @@ -581,7 +581,7 @@ struct ir3_shader_variant { * HS, where varyings are read in the next stage via ldg with a dword * offset, and in bytes for all other stages. */ - unsigned output_loc[32]; + unsigned output_loc[32 + 4]; /* +POSITION +PSIZE +CLIP_DIST0 +CLIP_DIST1 */ /* attributes (VS) / varyings (FS): * Note that sysval's should come *after* normal inputs. diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index 9ab2c2f..ca6026b 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -1898,7 +1898,7 @@ tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++) tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, cmd->state.streamout_offset[i])); - for (uint32_t i = 0; i < counterBufferCount; i++) { + for (uint32_t i = 0; i < (pCounterBuffers ? counterBufferCount : 0); i++) { uint32_t idx = firstCounterBuffer + i; uint32_t offset = cmd->state.streamout_offset[idx]; @@ -1946,7 +1946,7 @@ void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i); } - for (uint32_t i = 0; i < counterBufferCount; i++) { + for (uint32_t i = 0; i < (pCounterBuffers ? counterBufferCount : 0); i++) { uint32_t idx = firstCounterBuffer + i; uint32_t offset = cmd->state.streamout_offset[idx]; diff --git a/src/freedreno/vulkan/tu_device.c b/src/freedreno/vulkan/tu_device.c index bb7f06f..267f07b 100644 --- a/src/freedreno/vulkan/tu_device.c +++ b/src/freedreno/vulkan/tu_device.c @@ -1137,7 +1137,7 @@ fail_global_bo_map: tu_bo_finish(device, &device->global_bo); fail_global_bo: - ralloc_free(device->compiler); + ir3_compiler_destroy(device->compiler); fail_queues: for (unsigned i = 0; i < TU_MAX_QUEUE_FAMILIES; i++) { diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index 19f22cd..32bab4f 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -2335,12 +2335,13 @@ static void tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline) { + if (!(pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) || + !(pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)) + return; + const VkPipelineTessellationStateCreateInfo *tess_info = builder->create_info->pTessellationState; - if (!tess_info) - return; - assert(!(pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY))); assert(pipeline->ia.primtype == DI_PT_PATCHES0); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index 47fe130..110060c 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -1447,6 +1447,7 @@ fd6_emit_sysmem_fini(struct fd_batch *batch) fd6_emit_lrz_flush(ring); fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true); + fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true); } void diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index 64690c9..67fac48 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -545,7 +545,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, setup_stream_out(state, last_shader, &l); } - debug_assert(l.cnt < 32); + debug_assert(l.cnt <= 32); if (gs) OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2)); else if (ds) diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c index 56c6bf9..7ab8efc 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c @@ -120,7 +120,12 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc) radeon_enc_code_fixed_bits(enc, 0x0, 2); radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1); radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5); - radeon_enc_code_fixed_bits(enc, 0x60000000, 32); + + if (enc->enc_pic.general_profile_idc == 2) + radeon_enc_code_fixed_bits(enc, 0x20000000, 32); + else + radeon_enc_code_fixed_bits(enc, 0x60000000, 32); + radeon_enc_code_fixed_bits(enc, 0xb0000000, 32); radeon_enc_code_fixed_bits(enc, 0x0, 16); radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8); diff --git a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c index d540f26..b4053ca 100644 --- a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c +++ b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c @@ -1314,19 +1314,6 @@ void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx, desc[10] = fui(cull_info.translate[0]); desc[11] = fui(cull_info.translate[1]); - /* Better subpixel precision increases the efficiency of small - * primitive culling. */ - unsigned num_samples = sctx->framebuffer.nr_samples; - unsigned quant_mode = sctx->viewports.as_scissor[0].quant_mode; - float small_prim_cull_precision; - - if (quant_mode == SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH) - small_prim_cull_precision = num_samples / 4096.0; - else if (quant_mode == SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH) - small_prim_cull_precision = num_samples / 1024.0; - else - small_prim_cull_precision = num_samples / 256.0; - /* Set user data SGPRs. */ /* This can't be greater than 14 if we want the fastest launch rate. */ unsigned user_sgprs = 13; @@ -1490,7 +1477,7 @@ void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx, radeon_emit(cs, num_prims_udiv.post_shift | (num_prims_per_instance << 5)); radeon_emit(cs, info->restart_index); /* small-prim culling precision (same as rasterizer precision = QUANT_MODE) */ - radeon_emit(cs, fui(small_prim_cull_precision)); + radeon_emit(cs, fui(cull_info.small_prim_precision)); } else { assert(VERTEX_COUNTER_GDS_MODE == 2); /* Only update the SGPRs that changed. */ diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index 436a111..e7c169e 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -494,15 +494,14 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs) ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8); ctx->framebuffer.dirty_zsbuf = true; } - /* This should always be marked as dirty to set the framebuffer scissor - * at least. - * - * Even with shadowed registers, we have to add buffers to the buffer list. - * All of these do that. + + /* Even with shadowed registers, we have to add buffers to the buffer list. + * These atoms are the only ones that add buffers. */ si_mark_atom_dirty(ctx, &ctx->atoms.s.framebuffer); si_mark_atom_dirty(ctx, &ctx->atoms.s.render_cond); - si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports); + if (ctx->screen->use_ngg_culling) + si_mark_atom_dirty(ctx, &ctx->atoms.s.ngg_cull_state); if (first_cs || !ctx->shadowed_regs) { /* These don't add any buffers, so skip them with shadowing. */ @@ -532,6 +531,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs) si_mark_atom_dirty(ctx, &ctx->atoms.s.window_rectangles); si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband); si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors); + si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports); /* Invalidate various draw states so that they are emitted before * the first draw call. */ @@ -576,7 +576,6 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs) assert(!ctx->gfx_cs->prev_dw); ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw; - ctx->small_prim_cull_info_dirty = ctx->small_prim_cull_info_buf != NULL; ctx->prim_discard_compute_ib_initialized = false; /* Compute-based primitive discard: diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index a5c7dae..b36d695 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -891,6 +891,7 @@ struct si_sdma_upload { struct si_small_prim_cull_info { float scale[2], translate[2]; + float small_prim_precision; }; struct si_context { @@ -1133,7 +1134,6 @@ struct si_context { struct si_small_prim_cull_info last_small_prim_cull_info; struct si_resource *small_prim_cull_info_buf; uint64_t small_prim_cull_info_address; - bool small_prim_cull_info_dirty; /* Scratch buffer */ struct si_resource *scratch_buffer; @@ -1518,7 +1518,6 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe, const struct pipe_video_buffer *tmpl); /* si_viewport.c */ -void si_update_ngg_small_prim_precision(struct si_context *ctx); void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small_prim_cull_info *out); void si_update_vs_viewport_state(struct si_context *ctx); void si_init_viewport_functions(struct si_context *ctx); @@ -1933,6 +1932,20 @@ static inline unsigned si_get_shader_wave_size(struct si_shader *shader) shader->key.opt.vs_as_prim_discard_cs); } +/* Return the number of samples that the rasterizer uses. */ +static inline unsigned si_get_num_coverage_samples(struct si_context *sctx) +{ + if (sctx->framebuffer.nr_samples > 1 && + sctx->queued.named.rasterizer->multisample_enable) + return sctx->framebuffer.nr_samples; + + /* Note that smoothing_enabled is set by si_update_shaders. */ + if (sctx->smoothing_enabled) + return SI_NUM_SMOOTH_AA_SAMPLES; + + return 1; +} + #define PRINT_ERR(fmt, args...) \ fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 0352345..6f01800 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -988,6 +988,10 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state) /* Update the small primitive filter workaround if necessary. */ if (sctx->screen->info.has_msaa_sample_loc_bug && sctx->framebuffer.nr_samples > 1) si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs); + + /* NGG cull state uses multisample_enable. */ + if (sctx->screen->use_ngg_culling) + si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state); } sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR; @@ -2812,10 +2816,13 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, si_update_ps_colorbuf0_slot(sctx); si_update_poly_offset_state(sctx); - si_update_ngg_small_prim_precision(sctx); si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state); si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); + /* NGG cull state uses the sample count. */ + if (sctx->screen->use_ngg_culling) + si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state); + if (sctx->screen->dpbb_allowed) si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state); @@ -3417,8 +3424,9 @@ static void si_emit_msaa_config(struct si_context *sctx) * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry * EQAA 2s 2z 2f = 2x MSAA */ + coverage_samples = color_samples = z_samples = si_get_num_coverage_samples(sctx); + if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) { - coverage_samples = sctx->framebuffer.nr_samples; color_samples = sctx->framebuffer.nr_color_samples; if (sctx->framebuffer.state.zsbuf) { @@ -3427,10 +3435,6 @@ static void si_emit_msaa_config(struct si_context *sctx) } else { z_samples = coverage_samples; } - } else if (sctx->smoothing_enabled) { - coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES; - } else { - coverage_samples = color_samples = z_samples = 1; } /* Required by OpenGL line rasterization. diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 9ac4d51..6f585af 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -228,6 +228,7 @@ union si_state_atoms { struct si_atom scratch_state; struct si_atom window_rectangles; struct si_atom shader_query; + struct si_atom ngg_cull_state; } s; struct si_atom array[sizeof(struct si_atoms_s) / sizeof(struct si_atom)]; }; diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 8df7b9b..8370ed7 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -4061,6 +4061,10 @@ bool si_update_shaders(struct si_context *sctx) sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing; si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config); + /* NGG cull state uses smoothing_enabled. */ + if (sctx->screen->use_ngg_culling) + si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state); + if (sctx->chip_class == GFX6) si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c index 9d62b2c..c431c6a 100644 --- a/src/gallium/drivers/radeonsi/si_state_viewport.c +++ b/src/gallium/drivers/radeonsi/si_state_viewport.c @@ -28,34 +28,13 @@ #define SI_MAX_SCISSOR 16384 -void si_update_ngg_small_prim_precision(struct si_context *ctx) -{ - if (!ctx->screen->use_ngg_culling) - return; - - /* Set VS_STATE.SMALL_PRIM_PRECISION for NGG culling. */ - unsigned num_samples = ctx->framebuffer.nr_samples; - unsigned quant_mode = ctx->viewports.as_scissor[0].quant_mode; - float precision; - - if (quant_mode == SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH) - precision = num_samples / 4096.0; - else if (quant_mode == SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH) - precision = num_samples / 1024.0; - else - precision = num_samples / 256.0; - - ctx->current_vs_state &= C_VS_STATE_SMALL_PRIM_PRECISION; - ctx->current_vs_state |= S_VS_STATE_SMALL_PRIM_PRECISION(fui(precision) >> 23); -} - void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small_prim_cull_info *out) { /* This is needed by the small primitive culling, because it's done * in screen space. */ struct si_small_prim_cull_info info; - unsigned num_samples = sctx->framebuffer.nr_samples; + unsigned num_samples = si_get_num_coverage_samples(sctx); assert(num_samples >= 1); info.scale[0] = sctx->viewports.states[0].scale[0]; @@ -85,9 +64,64 @@ void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small_prim_c info.scale[i] *= num_samples; info.translate[i] *= num_samples; } + + /* Better subpixel precision increases the efficiency of small + * primitive culling. (more precision means a tighter bounding box + * around primitives and more accurate elimination) + */ + unsigned quant_mode = sctx->viewports.as_scissor[0].quant_mode; + + if (quant_mode == SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH) + info.small_prim_precision = num_samples / 4096.0; + else if (quant_mode == SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH) + info.small_prim_precision = num_samples / 1024.0; + else + info.small_prim_precision = num_samples / 256.0; + *out = info; } +static void si_emit_cull_state(struct si_context *sctx) +{ + assert(sctx->screen->use_ngg_culling); + + struct si_small_prim_cull_info info; + si_get_small_prim_cull_info(sctx, &info); + + if (!sctx->small_prim_cull_info_buf || + memcmp(&info, &sctx->last_small_prim_cull_info, sizeof(info))) { + unsigned offset = 0; + + /* Align to 256, because the address is shifted by 8 bits. */ + u_upload_data(sctx->b.const_uploader, 0, sizeof(info), 256, &info, &offset, + (struct pipe_resource **)&sctx->small_prim_cull_info_buf); + + sctx->small_prim_cull_info_address = sctx->small_prim_cull_info_buf->gpu_address + offset; + sctx->last_small_prim_cull_info = info; + } + + /* This will end up in SGPR6 as (value << 8), shifted by the hw. */ + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->small_prim_cull_info_buf, + RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER); + radeon_set_sh_reg(sctx->gfx_cs, R_00B220_SPI_SHADER_PGM_LO_GS, + sctx->small_prim_cull_info_address >> 8); + + /* Set VS_STATE.SMALL_PRIM_PRECISION for NGG culling. + * + * small_prim_precision is 1 / 2^n. We only need n between 5 (1/32) and 12 (1/4096). + * Such a floating point value can be packed into 4 bits as follows: + * If we pass the first 4 bits of the exponent to the shader and set the next 3 bits + * to 1, we'll get the number exactly because all other bits are always 0. See: + * 1 + * value = (0x70 | value.exponent[0:3]) << 23 = ------------------------------ + * 2 ^ (15 - value.exponent[0:3]) + * + * So pass only the first 4 bits of the float exponent to the shader. + */ + sctx->current_vs_state &= C_VS_STATE_SMALL_PRIM_PRECISION; + sctx->current_vs_state |= S_VS_STATE_SMALL_PRIM_PRECISION(fui(info.small_prim_precision) >> 23); +} + static void si_set_scissor_states(struct pipe_context *pctx, unsigned start_slot, unsigned num_scissors, const struct pipe_scissor_state *state) { @@ -330,8 +364,6 @@ static void si_emit_guardband(struct si_context *ctx) S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH + vp_as_scissor.quant_mode)); if (initial_cdw != ctx->gfx_cs->current.cdw) ctx->context_roll = true; - - si_update_ngg_small_prim_precision(ctx); } static void si_emit_scissors(struct si_context *ctx) @@ -430,6 +462,10 @@ static void si_set_viewport_states(struct pipe_context *pctx, unsigned start_slo if (start_slot == 0) { ctx->viewports.y_inverted = -state->scale[1] + state->translate[1] > state->scale[1] + state->translate[1]; + + /* NGG cull state uses the viewport and quant mode. */ + if (ctx->screen->use_ngg_culling) + si_mark_atom_dirty(ctx, &ctx->atoms.s.ngg_cull_state); } si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports); @@ -454,33 +490,6 @@ static void si_emit_viewports(struct si_context *ctx) struct radeon_cmdbuf *cs = ctx->gfx_cs; struct pipe_viewport_state *states = ctx->viewports.states; - if (ctx->screen->use_ngg_culling) { - /* Set the viewport info for small primitive culling. */ - struct si_small_prim_cull_info info; - si_get_small_prim_cull_info(ctx, &info); - - if (memcmp(&info, &ctx->last_small_prim_cull_info, sizeof(info))) { - unsigned offset = 0; - - /* Align to 256, because the address is shifted by 8 bits. */ - u_upload_data(ctx->b.const_uploader, 0, sizeof(info), 256, &info, &offset, - (struct pipe_resource **)&ctx->small_prim_cull_info_buf); - - ctx->small_prim_cull_info_address = ctx->small_prim_cull_info_buf->gpu_address + offset; - ctx->last_small_prim_cull_info = info; - ctx->small_prim_cull_info_dirty = true; - } - - if (ctx->small_prim_cull_info_dirty) { - /* This will end up in SGPR6 as (value << 8), shifted by the hw. */ - radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->small_prim_cull_info_buf, - RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER); - radeon_set_sh_reg(ctx->gfx_cs, R_00B220_SPI_SHADER_PGM_LO_GS, - ctx->small_prim_cull_info_address >> 8); - ctx->small_prim_cull_info_dirty = false; - } - } - /* The simple case: Only 1 viewport is active. */ if (!ctx->vs_writes_viewport_index) { radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6); @@ -655,6 +664,7 @@ void si_init_viewport_functions(struct si_context *ctx) ctx->atoms.s.scissors.emit = si_emit_scissors; ctx->atoms.s.viewports.emit = si_emit_viewport_states; ctx->atoms.s.window_rectangles.emit = si_emit_window_rectangles; + ctx->atoms.s.ngg_cull_state.emit = si_emit_cull_state; ctx->b.set_scissor_states = si_set_scissor_states; ctx->b.set_viewport_states = si_set_viewport_states; diff --git a/src/gallium/drivers/softpipe/sp_compute.c b/src/gallium/drivers/softpipe/sp_compute.c index 7e9a945..ac8d511 100644 --- a/src/gallium/drivers/softpipe/sp_compute.c +++ b/src/gallium/drivers/softpipe/sp_compute.c @@ -227,6 +227,11 @@ softpipe_launch_grid(struct pipe_context *context, } } + if (softpipe->active_statistics_queries) { + softpipe->pipeline_statistics.cs_invocations += + grid_size[0] * grid_size[1] * grid_size[2]; + } + for (i = 0; i < num_threads_in_group; i++) { cs_delete(cs, machines[i]); tgsi_exec_machine_destroy(machines[i]); diff --git a/src/gallium/drivers/softpipe/sp_query.c b/src/gallium/drivers/softpipe/sp_query.c index bb86194..91fa0c6 100644 --- a/src/gallium/drivers/softpipe/sp_query.c +++ b/src/gallium/drivers/softpipe/sp_query.c @@ -201,6 +201,8 @@ softpipe_end_query(struct pipe_context *pipe, struct pipe_query *q) softpipe->pipeline_statistics.c_primitives - sq->stats.c_primitives; sq->stats.ps_invocations = softpipe->pipeline_statistics.ps_invocations - sq->stats.ps_invocations; + sq->stats.cs_invocations = + softpipe->pipeline_statistics.cs_invocations - sq->stats.cs_invocations; softpipe->active_statistics_queries--; break; diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c index 92944f4..5416dc8 100644 --- a/src/gallium/drivers/virgl/virgl_screen.c +++ b/src/gallium/drivers/virgl/virgl_screen.c @@ -873,7 +873,9 @@ virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *c fixup_formats(&screen->caps.caps, &screen->caps.caps.v2.scanout); union virgl_caps *caps = &screen->caps.caps; - screen->tweak_gles_emulate_bgra &= !virgl_format_check_bitmask(PIPE_FORMAT_B8G8R8A8_SRGB, caps->v1.render.bitmask, false); + bool may_emulate_bgra = (caps->v2.capability_bits & VIRGL_CAP_APP_TWEAK_SUPPORT); + screen->tweak_gles_emulate_bgra &= !virgl_format_check_bitmask( + PIPE_FORMAT_B8G8R8A8_SRGB, caps->v1.render.bitmask, may_emulate_bgra); screen->refcnt = 1; slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16); diff --git a/src/gallium/drivers/zink/zink_draw.c b/src/gallium/drivers/zink/zink_draw.c index 3daafcf..64e216c 100644 --- a/src/gallium/drivers/zink/zink_draw.c +++ b/src/gallium/drivers/zink/zink_draw.c @@ -272,7 +272,7 @@ zink_draw_vbo(struct pipe_context *pctx, if (dinfo->index_size > 0) { uint32_t restart_index = util_prim_restart_index_from_size(dinfo->index_size); if ((dinfo->primitive_restart && (dinfo->restart_index != restart_index)) || - (!screen->info.have_EXT_index_type_uint8 && dinfo->index_size == 8)) { + (!screen->info.have_EXT_index_type_uint8 && dinfo->index_size == 1)) { util_translate_prim_restart_ib(pctx, dinfo, &index_buffer); need_index_buffer_unref = true; } else { @@ -314,14 +314,17 @@ zink_draw_vbo(struct pipe_context *pctx, for (int j = 0; j < shader->num_bindings; j++) { int index = shader->bindings[j].index; if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) { - assert(ctx->ubos[i][index].buffer_size > 0); assert(ctx->ubos[i][index].buffer_size <= screen->info.props.limits.maxUniformBufferRange); - assert(ctx->ubos[i][index].buffer); struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer); + assert(!res || ctx->ubos[i][index].buffer_size > 0); + assert(!res || ctx->ubos[i][index].buffer); write_desc_resources[num_wds] = res; - buffer_infos[num_buffer_info].buffer = res->buffer; - buffer_infos[num_buffer_info].offset = ctx->ubos[i][index].buffer_offset; - buffer_infos[num_buffer_info].range = ctx->ubos[i][index].buffer_size; + buffer_infos[num_buffer_info].buffer = res ? res->buffer : + (screen->info.rb2_feats.nullDescriptor ? + VK_NULL_HANDLE : + zink_resource(ctx->dummy_buffer)->buffer); + buffer_infos[num_buffer_info].offset = res ? ctx->ubos[i][index].buffer_offset : 0; + buffer_infos[num_buffer_info].range = res ? ctx->ubos[i][index].buffer_size : VK_WHOLE_SIZE; wds[num_wds].pBufferInfo = buffer_infos + num_buffer_info; ++num_buffer_info; } else { diff --git a/src/gallium/drivers/zink/zink_format.c b/src/gallium/drivers/zink/zink_format.c index b78278d..598cb98 100644 --- a/src/gallium/drivers/zink/zink_format.c +++ b/src/gallium/drivers/zink/zink_format.c @@ -76,7 +76,7 @@ static const VkFormat formats[PIPE_FORMAT_COUNT] = { [PIPE_FORMAT_B8G8R8X8_UNORM] = VK_FORMAT_B8G8R8A8_UNORM, MAP_FORMAT_SRGB(B8G8R8A8) [PIPE_FORMAT_B8G8R8X8_SRGB] = VK_FORMAT_B8G8R8A8_SRGB, - [PIPE_FORMAT_A8B8G8R8_SRGB] = VK_FORMAT_A8B8G8R8_SRGB_PACK32, + [PIPE_FORMAT_R8G8B8A8_SRGB] = VK_FORMAT_A8B8G8R8_SRGB_PACK32, // 16-bits MAP_FORMAT_NORM(R16G16B16A16) MAP_FORMAT_SCALED(R16G16B16A16) @@ -88,7 +88,7 @@ static const VkFormat formats[PIPE_FORMAT_COUNT] = { // other color formats [PIPE_FORMAT_B5G6R5_UNORM] = VK_FORMAT_R5G6B5_UNORM_PACK16, - [PIPE_FORMAT_B5G5R5A1_UNORM] = VK_FORMAT_B5G5R5A1_UNORM_PACK16, + [PIPE_FORMAT_A1R5G5B5_UNORM] = VK_FORMAT_B5G5R5A1_UNORM_PACK16, [PIPE_FORMAT_R11G11B10_FLOAT] = VK_FORMAT_B10G11R11_UFLOAT_PACK32, [PIPE_FORMAT_R9G9B9E5_FLOAT] = VK_FORMAT_E5B9G9R9_UFLOAT_PACK32, /* ARB_vertex_type_2_10_10_10 */ diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c index 600c941..103b285 100644 --- a/src/mesa/main/fbobject.c +++ b/src/mesa/main/fbobject.c @@ -1320,15 +1320,33 @@ _mesa_test_framebuffer_completeness(struct gl_context *ctx, att_layer_count = att->Renderbuffer->Height; else att_layer_count = att->Renderbuffer->Depth; + + /* From OpenGL ES 3.2 spec, chapter 9.4. FRAMEBUFFER COMPLETENESS: + * + * "If any framebuffer attachment is layered, all populated + * attachments must be layered. Additionally, all populated color + * attachments must be from textures of the same target + * (three-dimensional, one- or two-dimensional array, cube map, or + * cube map array textures)." + * + * Same text can be found from OpenGL 4.6 spec. + * + * Setup the checked layer target with first color attachment here + * so that mismatch check below will not trigger between depth, + * stencil, only between color attachments. + */ + if (i == 0) + layer_tex_target = att_tex_target; + } else { att_layer_count = 0; } if (!layer_info_valid) { is_layered = att->Layered; max_layer_count = att_layer_count; - layer_tex_target = att_tex_target; layer_info_valid = true; - } else if (max_layer_count > 0 && layer_tex_target != att_tex_target) { + } else if (max_layer_count > 0 && layer_tex_target && + layer_tex_target != att_tex_target) { fb->_Status = GL_FRAMEBUFFER_INCOMPLETE_LAYER_TARGETS; fbo_incomplete(ctx, "layered framebuffer has mismatched targets", i); return; diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c index 92c521b..1668be0 100644 --- a/src/mesa/main/glspirv.c +++ b/src/mesa/main/glspirv.c @@ -244,6 +244,7 @@ _mesa_spirv_to_nir(struct gl_context *ctx, const struct spirv_to_nir_options spirv_options = { .environment = NIR_SPIRV_OPENGL, .frag_coord_is_sysval = ctx->Const.GLSLFragCoordIsSysVal, + .use_deref_buffer_array_length = true, .caps = ctx->Const.SpirVCapabilities, .ubo_addr_format = nir_address_format_32bit_index_offset, .ssbo_addr_format = nir_address_format_32bit_index_offset, diff --git a/src/mesa/state_tracker/st_cb_blit.c b/src/mesa/state_tracker/st_cb_blit.c index d91cc96..cf55eff 100644 --- a/src/mesa/state_tracker/st_cb_blit.c +++ b/src/mesa/state_tracker/st_cb_blit.c @@ -39,6 +39,7 @@ #include "st_cb_bitmap.h" #include "st_cb_blit.h" #include "st_cb_fbo.h" +#include "st_cb_texture.h" #include "st_manager.h" #include "st_scissor.h" #include "st_util.h" @@ -180,6 +181,12 @@ st_BlitFramebuffer(struct gl_context *ctx, blit.mask = PIPE_MASK_RGBA; if (srcAtt->Type == GL_TEXTURE) { + /* Make sure that the st_texture_object->pt is the current storage for + * our miplevel. The finalize would happen at some point anyway, might + * as well be now. + */ + st_finalize_texture(ctx, st->pipe, srcAtt->Texture, srcAtt->CubeMapFace); + struct st_texture_object *srcObj = st_texture_object(srcAtt->Texture); if (!srcObj || !srcObj->pt) { diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c b/src/mesa/state_tracker/st_cb_drawpixels.c index 4b8242c..c16ea1d 100644 --- a/src/mesa/state_tracker/st_cb_drawpixels.c +++ b/src/mesa/state_tracker/st_cb_drawpixels.c @@ -1237,7 +1237,7 @@ setup_sampler_swizzle(struct pipe_sampler_view *sv, GLenum format, GLenum type) { if ((format == GL_RGBA || format == GL_BGRA) && type == GL_UNSIGNED_BYTE) { const struct util_format_description *desc = - util_format_description(sv->texture->format); + util_format_description(sv->format); unsigned c0, c1, c2, c3; /* Every gallium driver supports at least one 32-bit packed RGBA format. @@ -1384,17 +1384,22 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y, st_upload_constants(st, &st->fp->Base); } - /* create sampler view for the image */ - sv[0] = st_create_texture_sampler_view(st->pipe, pt); + { + /* create sampler view for the image */ + struct pipe_sampler_view templ; + + u_sampler_view_default_template(&templ, pt, pt->format); + /* Set up the sampler view's swizzle */ + setup_sampler_swizzle(&templ, format, type); + + sv[0] = st->pipe->create_sampler_view(st->pipe, pt, &templ); + } if (!sv[0]) { _mesa_error(ctx, GL_OUT_OF_MEMORY, "glDrawPixels"); pipe_resource_reference(&pt, NULL); return; } - /* Set up the sampler view's swizzle */ - setup_sampler_swizzle(sv[0], format, type); - /* Create a second sampler view to read stencil. The stencil is * written using the shader stencil export functionality. */ diff --git a/src/mesa/state_tracker/st_cb_readpixels.c b/src/mesa/state_tracker/st_cb_readpixels.c index 642ea0d..e2edcbc 100644 --- a/src/mesa/state_tracker/st_cb_readpixels.c +++ b/src/mesa/state_tracker/st_cb_readpixels.c @@ -235,7 +235,7 @@ try_pbo_readpixels(struct st_context *st, struct st_renderbuffer *strb, /* Set up the fragment shader */ { - void *fs = st_pbo_get_download_fs(st, view_target, src_format, dst_format); + void *fs = st_pbo_get_download_fs(st, view_target, src_format, dst_format, addr.depth != 1); if (!fs) goto fail; diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c index 2296dd6..9f94566 100644 --- a/src/mesa/state_tracker/st_cb_texture.c +++ b/src/mesa/state_tracker/st_cb_texture.c @@ -1271,7 +1271,7 @@ try_pbo_upload_common(struct gl_context *ctx, bool success = false; void *fs; - fs = st_pbo_get_upload_fs(st, src_format, surface->format); + fs = st_pbo_get_upload_fs(st, src_format, surface->format, addr->depth != 1); if (!fs) return false; diff --git a/src/mesa/state_tracker/st_context.c b/src/mesa/state_tracker/st_context.c index 1605e46..4036429 100644 --- a/src/mesa/state_tracker/st_context.c +++ b/src/mesa/state_tracker/st_context.c @@ -271,9 +271,11 @@ st_invalidate_state(struct gl_context *ctx) (ST_NEW_SAMPLER_VIEWS | ST_NEW_SAMPLERS | ST_NEW_IMAGE_UNITS); - if (ctx->FragmentProgram._Current && - ctx->FragmentProgram._Current->ExternalSamplersUsed) { - st->dirty |= ST_NEW_FS_STATE; + if (ctx->FragmentProgram._Current) { + struct st_program *stfp = st_program(ctx->FragmentProgram._Current); + + if (stfp->Base.ExternalSamplersUsed || stfp->ati_fs) + st->dirty |= ST_NEW_FS_STATE; } } } diff --git a/src/mesa/state_tracker/st_context.h b/src/mesa/state_tracker/st_context.h index d467dee..b1fda06 100644 --- a/src/mesa/state_tracker/st_context.h +++ b/src/mesa/state_tracker/st_context.h @@ -317,8 +317,8 @@ struct st_context struct pipe_blend_state upload_blend; void *vs; void *gs; - void *upload_fs[3]; - void *download_fs[3][PIPE_MAX_TEXTURE_TYPES]; + void *upload_fs[3][2]; + void *download_fs[3][PIPE_MAX_TEXTURE_TYPES][2]; bool upload_enabled; bool download_enabled; bool rgba_only; diff --git a/src/mesa/state_tracker/st_pbo.c b/src/mesa/state_tracker/st_pbo.c index e4464bd..65a1ce8 100644 --- a/src/mesa/state_tracker/st_pbo.c +++ b/src/mesa/state_tracker/st_pbo.c @@ -202,7 +202,7 @@ st_pbo_draw(struct st_context *st, const struct st_pbo_addresses *addr, return false; } - if (st->pbo.use_gs && !st->pbo.gs) { + if (addr->depth != 1 && st->pbo.use_gs && !st->pbo.gs) { st->pbo.gs = st_pbo_create_gs(st); if (!st->pbo.gs) return false; @@ -403,7 +403,8 @@ sampler_type_for_target(enum pipe_texture_target target) static void * create_fs(struct st_context *st, bool download, enum pipe_texture_target target, - enum st_pbo_conversion conversion) + enum st_pbo_conversion conversion, + bool need_layer) { struct pipe_screen *screen = st->pipe->screen; struct nir_builder b; @@ -430,11 +431,11 @@ create_fs(struct st_context *st, bool download, nir_ssa_def *coord = nir_load_var(&b, fragcoord); nir_ssa_def *layer = NULL; - if (st->pbo.layers && (!download || target == PIPE_TEXTURE_1D_ARRAY || - target == PIPE_TEXTURE_2D_ARRAY || - target == PIPE_TEXTURE_3D || - target == PIPE_TEXTURE_CUBE || - target == PIPE_TEXTURE_CUBE_ARRAY)) { + if (st->pbo.layers && need_layer && (!download || target == PIPE_TEXTURE_1D_ARRAY || + target == PIPE_TEXTURE_2D_ARRAY || + target == PIPE_TEXTURE_3D || + target == PIPE_TEXTURE_CUBE || + target == PIPE_TEXTURE_CUBE_ARRAY)) { nir_variable *var = nir_variable_create(b.shader, nir_var_shader_in, glsl_int_type(), "gl_Layer"); var->data.location = VARYING_SLOT_LAYER; @@ -563,32 +564,34 @@ get_pbo_conversion(enum pipe_format src_format, enum pipe_format dst_format) void * st_pbo_get_upload_fs(struct st_context *st, enum pipe_format src_format, - enum pipe_format dst_format) + enum pipe_format dst_format, + bool need_layer) { STATIC_ASSERT(ARRAY_SIZE(st->pbo.upload_fs) == ST_NUM_PBO_CONVERSIONS); enum st_pbo_conversion conversion = get_pbo_conversion(src_format, dst_format); - if (!st->pbo.upload_fs[conversion]) - st->pbo.upload_fs[conversion] = create_fs(st, false, 0, conversion); + if (!st->pbo.upload_fs[conversion][need_layer]) + st->pbo.upload_fs[conversion][need_layer] = create_fs(st, false, 0, conversion, need_layer); - return st->pbo.upload_fs[conversion]; + return st->pbo.upload_fs[conversion][need_layer]; } void * st_pbo_get_download_fs(struct st_context *st, enum pipe_texture_target target, enum pipe_format src_format, - enum pipe_format dst_format) + enum pipe_format dst_format, + bool need_layer) { STATIC_ASSERT(ARRAY_SIZE(st->pbo.download_fs) == ST_NUM_PBO_CONVERSIONS); assert(target < PIPE_MAX_TEXTURE_TYPES); enum st_pbo_conversion conversion = get_pbo_conversion(src_format, dst_format); - if (!st->pbo.download_fs[conversion][target]) - st->pbo.download_fs[conversion][target] = create_fs(st, true, target, conversion); + if (!st->pbo.download_fs[conversion][target][need_layer]) + st->pbo.download_fs[conversion][target][need_layer] = create_fs(st, true, target, conversion, need_layer); - return st->pbo.download_fs[conversion][target]; + return st->pbo.download_fs[conversion][target][need_layer]; } void @@ -638,17 +641,21 @@ st_destroy_pbo_helpers(struct st_context *st) unsigned i; for (i = 0; i < ARRAY_SIZE(st->pbo.upload_fs); ++i) { - if (st->pbo.upload_fs[i]) { - st->pipe->delete_fs_state(st->pipe, st->pbo.upload_fs[i]); - st->pbo.upload_fs[i] = NULL; + for (unsigned j = 0; j < ARRAY_SIZE(st->pbo.upload_fs[0]); j++) { + if (st->pbo.upload_fs[i][j]) { + st->pipe->delete_fs_state(st->pipe, st->pbo.upload_fs[i][j]); + st->pbo.upload_fs[i][j] = NULL; + } } } for (i = 0; i < ARRAY_SIZE(st->pbo.download_fs); ++i) { for (unsigned j = 0; j < ARRAY_SIZE(st->pbo.download_fs[0]); ++j) { - if (st->pbo.download_fs[i][j]) { - st->pipe->delete_fs_state(st->pipe, st->pbo.download_fs[i][j]); - st->pbo.download_fs[i][j] = NULL; + for (unsigned k = 0; k < ARRAY_SIZE(st->pbo.download_fs[0][0]); k++) { + if (st->pbo.download_fs[i][j][k]) { + st->pipe->delete_fs_state(st->pipe, st->pbo.download_fs[i][j][k]); + st->pbo.download_fs[i][j][k] = NULL; + } } } } diff --git a/src/mesa/state_tracker/st_pbo.h b/src/mesa/state_tracker/st_pbo.h index 54ae776..5462658 100644 --- a/src/mesa/state_tracker/st_pbo.h +++ b/src/mesa/state_tracker/st_pbo.h @@ -87,12 +87,14 @@ st_pbo_create_gs(struct st_context *st); void * st_pbo_get_upload_fs(struct st_context *st, enum pipe_format src_format, - enum pipe_format dst_format); + enum pipe_format dst_format, + bool need_layer); void * st_pbo_get_download_fs(struct st_context *st, enum pipe_texture_target target, enum pipe_format src_format, - enum pipe_format dst_format); + enum pipe_format dst_format, + bool need_layer); extern void st_init_pbo_helpers(struct st_context *st); diff --git a/src/panfrost/lib/pan_attributes.c b/src/panfrost/lib/pan_attributes.c index 1fe6d8c..3af657f 100644 --- a/src/panfrost/lib/pan_attributes.c +++ b/src/panfrost/lib/pan_attributes.c @@ -40,10 +40,10 @@ static unsigned panfrost_small_padded_vertex_count(unsigned idx) { - if (idx == 11 || idx == 13 || idx == 15 || idx == 19) - return idx + 1; - else + if (idx < 10) return idx; + else + return (idx + 1) & ~1; } static unsigned