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; Copyright (c) 2014-2017, Intel Corporation
;
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; Test MTC and CYC-based TSC estimation.
;
; Variant: CBR-based calibration
;
; opt:ptdump --time --time-delta
; opt:ptdump --nom-freq 4 --mtc-freq 8 --cpuid-0x15.eax 1 --cpuid-0x15.ebx 4

org 0x100000
bits 64

; @pt p1: psb()
; @pt p2: psbend()

; @pt p3: tsc(0xa0000)
; @pt p4: tma(0x102, 0x8)
; @pt p5: cbr(0x2)
; @pt p6: mtc(0x2)
; @pt p7: cyc(0x3)
; @pt p8: cyc(0x1)


; @pt .exp(ptdump)
;%0p1   psb
;%0p2   psbend
;%0p3   tsc a0000       tsc +a0000
;%0p4   tma 102, 8      tsc +0
;%0p5   cbr 2
;%0p6   mtc 2           tsc +3f0
;%0p7   cyc 3           tsc +6
;%0p8   cyc 1           tsc +2