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<html>
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<head>
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<title>A20 - a pain from the past</title>
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</head>
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<body>
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A20 - a pain from the past
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Everybody hates the CapsLock key, but keyboard manufacturers continue
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producing keyboards with CapsLock - it could be that someone wants it.
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With A20 it is similar but worse. Really nobody wants it, but it
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continues to haunt us.
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History
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The 8088 in the original PC had only 20 address lines, good for 1 MB.
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The maximum address FFFF:FFFF addresses 0x10ffef, and this would silently
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wrap to 0x0ffef.
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When the 286 (with 24 address lines) was introduced, it had a real mode
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that was intended to be 100% compatible with the 8088. However, it failed
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to do this address truncation (a bug), and people found that there existed
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programs that actually depended on this truncation.
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Trying to achieve perfect compatibility, IBM invented a switch
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to enable/disable the 0x100000 address bit.
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Since the 8042 keyboard controller happened to have a spare pin,
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that was used to control the AND gate that disables this address bit.
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The signal is called A20, and if it is zero, bit 20 of all addresses
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is cleared.
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Present
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Why do we have to worry about this nonsense?
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Because by default the A20 address line is disabled at boot time,
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so the operating system has to find out how to enable it, and that
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may be nontrivial since the details depend on the chipset used.
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Classical A20 control, via the keyboard controller
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The output port of the keyboard controller has a number of functions.
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Bit 0 is used to reset the CPU (go to real mode) - a reset happens
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when bit 0 is 0.
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Bit 1 is used to control A20 - it is enabled when bit 1 is 1,
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disabled when bit 1 is 0.
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One sets the output port of the keyboard controller by first writing
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0xd1 to port 0x64, and the the desired value of the output port
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to port 0x60. One usually sees the values 0xdd and 0xdf used to
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disable/enable A20. Thus:
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call empty_8042
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mov al,#0xd1 ! command write
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out #0x64,al
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call empty_8042
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mov al,#0xdf ! A20 on
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out #0x60,al
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call empty_8042
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where <tt>empty_8042</tt> has to wait for the kbd to finish
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handling input, say
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empty_8042:
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call delay
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in al,#0x64
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test al,#2
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jnz empty_8042
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ret
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Variation
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The HP Vectra accepts a shortcut, where writing
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0xdd or 0xdf to port 0x64 will disable/enable A20.
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! For the HP Vectra
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call empty_8042
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jnz err
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mov al,#0xdf
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out #0x64,al
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call empty_8042
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jnz err
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mov al,#0xdf ! Do it again
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out #0x64,al
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call empty_8042
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jnz err
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! Success
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(HIMEM.SYS in DOS 5.0 incorrectly identifies some computers as HP Vectra -
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this may cause a hang at boot. Fixed in DOS5.0a.)
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A20 control via System Control Port A
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Some operating systems use the switching off and on of A20 as part
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of the standard procedure to switch between real (16-bit) and protected
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mode. Since the keyboard microcontroller is slow, it was desirable to
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avoid it, and a Fast Gate A20 Option was introduced, where I/O port
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0x92 (System Control Port A) is used to handle A20, circumventing
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the keyboard controller.
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Thus, MCA, EISA and other systems can also control A20 via port 0x92.
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This port has a number of functions, and the details depend on
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the manufacturer. Bits 0,1,3,6,7 seem to have the same meaning
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everywhere this port is implemented.
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Bit 0 (w): writing 1 to this bit causes a
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fast reset (used to switch back to real mode; for MCA this took 13.4 ms).
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Bit 1 (rw): 0: disable A20, 1: enable A20.
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Bit 3 (rw?): 0/1: power-on password bytes (stored in CMOS bytes 0x38-0x3f
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or 0x36-0x3f) accessible/inaccessible. This bit can be written to only
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when it is 0.
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Bits 6-7 (rw): 00: hard disk activity LED off,
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01,10,11: hard disk activity LED on.
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Bits 2,4,5 are unused or have varying meanings.
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(On MCA bit 4 (r): 1: watchdog timeout occurred.)
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Using 0x92 may be necessary
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Sometimes (especially on embedded systems, maybe also on some
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"legacy-free" systems) no keyboard controller is present,
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and it may be necessary to use 0x92.
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Often however, the chip will catch accesses to ports 0x64 and 0x60
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and simulate the expected behaviour, also when no keyboard controller
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is present. Sometimes, this snooping behaviour must be enabled first.
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Using 0x92 may be dangerous
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Gianluca Anzolin <g.anzolin@inwind.it> reports:
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I have an Olivetti M4 (P166) with TRIDENT 9660 video card integrated
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on the mainboard. Linux boots well, but after LILO has loaded the kernel,
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the screen becomes black and remains black ever after. Removing
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inb $0x92, %al #
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orb $02, %al # "fast A20" version
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outb %al, $0x92 # some chips have only this
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from <tt>setup.S</tt> solved this. Apparently on his machine
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writing to some of these bits is dangerous and does something
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to the on-board video card (disable it? lspci shows it only when
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0x92 is not touched).
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Similar things are reported by others:
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I am trying to install Linux on an old Olivetti pc M4 Modulo P75 but
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I am quickly stopped. I always got the same display problem very soon
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during the installation.The display is not updated anymore.
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The embedded display adapter is a "Trident 9xxx PCI".
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and
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I have a strange problem with an old Olivetti M4 (pentium 75)
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machine. I buy for a very cheap price 5 of these, but when I
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boot the machine the screen goes blank. The (embedded on MoBo)
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video chip is a Trident TGUI9780.
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Petr Vandrovec <vandrove@vc.cvut.cz> suggests to do the write
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only when it is really necessary:
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inb $0x92, %al #
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+ testb $02, %al
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+ jnz no92
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orb $02, %al # "fast A20" version
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outb %al, $0x92 # some chips have only this
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+no92:
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Since bit 0 sometimes is write-only, and writing a one there
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causes a reset, it must be a good idea to add the line
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andb $0xfe, %al
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before the <tt>outb</tt>.
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Using only 0x92 may be dangerous
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Kai Germaschewski reports that he gets a spontaneous kernel reboot
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(on a Sony PCG-Z600NE) after suspend/resume when A20 was enabled
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using 0x92 but not via the keyboard controller. Apparently state
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set via keyboard controller is correctly saved and restored, but
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state set via 0x92 is not.
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Port 0x92 may have to be enabled
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Various SMSC super I/O chips will emulate the keyboard controller,
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but emulate port 0x92 only when that has been enabled.
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CMOS indicating the presence of a Fast A20 Gate
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Depending on the BIOS, the possibility of using a fast A20 switch
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may be visible in the CMOS. For example, some AMI BIOSes have
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in CMOS location 0x2d a byte with contents
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System Operational Flags
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Bit 7 = 1: Weitek math coprocessor present
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Bit 6 = 1: Floppy drive seek at boot disabled
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Bit 5 = 1: System boot sequence A:,C: (otherwise C:,A:)
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Bit 4 = 1: System boot CPU speed high
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Bit 3 = 1: External cache enabled
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Bit 2 = 1: Internal cache enabled
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Bit 1 = 1: Fast gate A20 operation enabled
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Bit 0 = 1: Turbo switch function enabled
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Of course, this does not help at all.
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FreeBSD
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FreeBSD does
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/*
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* Gate A20 for high memory
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*/
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void
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gateA20(void)
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{
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#ifdef PC98
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outb(0xf2, 0x00);
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outb(0xf6, 0x02);
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#else
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#ifdef IBM_L40
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outb(0x92, 0x2);
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#else IBM_L40
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while (inb(K_STATUS) & K_IBUF_FUL);
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while (inb(K_STATUS) & K_OBUF_FUL)
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(void)inb(K_RDWR);
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outb(K_CMD, KC_CMD_WOUT);
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while (inb(K_STATUS) & K_IBUF_FUL);
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outb(K_RDWR, KB_A20);
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while (inb(K_STATUS) & K_IBUF_FUL);
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#endif IBM_L40
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#endif
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}
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that is, uses 0x92 only for a IBM_L40 (whatever that may be).
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The FreeBSD handbook describes PC98 as
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"an alternative development branch of PC hardware, popular in Japan"
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and "the NEC PC98 platform".
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Minix and HIMEM.ASM
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Here is a patch fragment for minix.
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It contains the interesting part
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! movb al, #0xff ! Pulse output port
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! outb 0x64
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! call kb_wait ! Wait for the A20 line to settle down
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from some old HIMEM.ASM source (that one still can find on the net).
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I have seen no other places where command 0xff is described as
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doing something useful.
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Access of 0xee
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On some systems reading ioport 0xee enables A20, and writing it
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disables A20. (Or, sometimes, this action only occurs when ioport
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0xee is enabled.) And similar things hold for ioport 0xef and
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reset (a write causes a reset).
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The i386SL/i486SL documents say
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The following ports are visible only when enabled,
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Any writes to these ports cause the action named.
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Name of Register Address Default Value Where placed Size
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FAST CPU RESET EFh N/A 82360SL 8
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FAST A20 GATE EEh N/A 82360SL 8
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The AMD Elan SC400 docs
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(21032.pdf) say:
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Register EEh can be used to cause the same type of masking of the CPU
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A20 signal that was historically performed by an external SCP (System
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Control Processor) in a PC/AT Compatible system, but much faster. This
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control defaults to not forcing the propagation of A20:
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Dummy Read = Returns FFh, and forces the A20 signal to propagate.
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Dummy Write = Deasserts the forcing of the propagation of the A20 signal
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via this particular control, data value written is N/A.
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For software compatibility and other reasons, there are several sources
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of GateA20 control. These controls are effectively ORed together with
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the output of the OR gate driving the Enhanced Am486 microprocessor
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A20M pin. Therefore, A20 will propagate if ANY of the independent sources
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are forcing A20 to propagate.
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Other ports
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It is rumoured that systems exist that use bit 2 of ioport 0x65
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or bit 0 of ioport 0x1f8 for A20 control (0: disabled, 1: enabled).
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Don't know what systems that might be.
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The AT&T 6300+ needs a write of 0x90 to port 0x3f20 to enable
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(and a write of 0x0 to disable) A20.
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Disabling A20
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It may be necessary to do both the keyboard controller write and
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the 0x92 write (and the 0xee write) to disable A20.
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A20 and reset
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If (in protected mode) A20 is disabled, the odd megabytes are inaccessible.
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After a reset, execution begins at top-of-memory:
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0xfffff0 on the 286 and 0xfffffff0 on 386 and later.
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With disabled A20 this becomes 0xeffff0 or 0xffeffff0
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and the machine will probably crash, having no memory mapped there.
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A20 and cache
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One tests A20 by writing something to an address with bit 0x100000 set,
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and seeing whether the corresponding location in low memory changes.
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However, this plan may be thwarted by the cache that remembers the
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old value and doesn't know about A20.
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Neutrino describes the following function <tt>x86_enable_a20()</tt>:
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Enable address line A20, which is often disabled on many PCs on reset.
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It first checks if address line A20 is enabled and if so returns 0.
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Otherwise, it sets bit 0x02 in port 0x92, which is used by many systems
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as a fast A20 enable. It again checks to see if A20 is enabled and if so
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returns 0. Otherwise, it uses the keyboard microcontroller to enable A20
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as defined by the old PC/AT standard. It again checks to see if A20 is
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enabled and if so returns 0. Otherwise, it returns -1.
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If cpu is a 486 or greater, it issues a <tt>wbinvd</tt> opcode
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to invalidate the cache when doing a read/write test of memory to see
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if A20 is enabled.
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In the rare case where setting bit 0x02 in port 0x92 may affect
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other hardware, you can skip this by setting <tt>only_keyboard</tt> to 1.
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In this case, it will attempt to use only the keyboard microcontroller.
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hpa comments:
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As far as I know the only machines which have the cache
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problem are i386 boxen, but the i386 doesn't have WBINVD. The i486
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has a pin on the CPU for A20, which takes effect inside the L1 cache,
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and so it shouldn't have any A20 cache issues.
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Jens Maurer
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reported
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in 1996 on boot problems with a bzImage kernel:
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On the Toshiba laptop, the first two bytes at 0x100000 are incorrect and
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identical to those from address 0x000000 (which was an alias for
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0x100000 before the A20 gate enable). At a second read from 0x100000
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immediately afterwards, the correct memory content is returned.
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Asus P55TP5XE boards (Triton I chipset) show quite the same
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problem, but there, only the first byte is incorrect and booting
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bzImage kernels works fine.
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To me, this looks like some buffer or cache coherency problem
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although I think that caches are organized in at least 16 byte cache lines.
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...
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This exact same problem reportedly also exists on Fujitsu 555T
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(report from Andrea Caltroni) laptop and Compudyne Pentium 60
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(report from David Kerr) desktop computers.
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He gives a patch, and adds
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"Unfortunately, Philip Hands reports that the above patch makes some people
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with other non-laptop computers unable to boot."
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Using zImage instead of bzImage avoids the problem (since zImage
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is not loaded high).
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Debian has distributed special Tecra boot floppies for a while.
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Later it was found out that these laptops just have an incredibly
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slow keyboard controller and that all is fine with a larger timeout.
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BIOS
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If it is difficult, maybe impossible, to write a routine that
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will enable A20 on all PCs, one might ask the BIOS to do so.
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Many recent BIOS versions implement INT15 AX=240x functions,
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as follows:
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INT 15 AX=2400 disable A20
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INT 15 AX=2401 enable A20
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INT 15 AX=2402 query status A20
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INT 15 AX=2403 query A20 support (kbd or port 92)
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Return:
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If successful: CF clear, AH = 00h
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On error: CF set, AH = status
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Status: 01h keyboard controller is in secure mode
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86h function not supported
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For AX=2402 the status (0: disabled, 1: enabled) is returned in AL
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For AX=2403 the status (bit 0: kbd, bit 1: port 92) is returned in BX
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</body>
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</html>
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