From b92bd815f6540aa765737804d802feb96bd51f92 Mon Sep 17 00:00:00 2001
From: Packit Service <user-cont-team+packit-service@redhat.com>
Date: Mar 03 2021 08:40:14 +0000
Subject: Apply patch glibc-rh1783303-10.patch


patch_name: glibc-rh1783303-10.patch
present_in_specfile: true
location_in_specfile: 325

---

diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
index b244770..e8d40ea 100644
--- a/sysdeps/powerpc/fpu/fenv_libc.h
+++ b/sysdeps/powerpc/fpu/fenv_libc.h
@@ -36,9 +36,12 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
         ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
 
 /* Equivalent to fegetenv_register, but only returns bits for
-   status, exception enables, and mode.  */
-
-#define fegetenv_status_ISA300()					\
+   status, exception enables, and mode.
+   Nicely, it turns out that the 'mffsl' instruction will decode to
+   'mffs' on architectures older than "power9" because the additional
+   bits set for 'mffsl' are "don't care" for 'mffs'.  'mffs' is a superset
+   of 'mffsl'.  */
+#define fegetenv_status()					\
   ({register double __fr;						\
     __asm__ __volatile__ (						\
       ".machine push; .machine \"power9\"; mffsl %0; .machine pop"	\
@@ -46,18 +49,6 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
     __fr;								\
   })
 
-#ifdef _ARCH_PWR9
-# define fegetenv_status() fegetenv_status_ISA300()
-#elif defined __BUILTIN_CPU_SUPPORTS__
-# define fegetenv_status()						\
-  (__glibc_likely (__builtin_cpu_supports ("arch_3_00"))		\
-   ? fegetenv_status_ISA300()						\
-   : fegetenv_register()						\
-  )
-#else
-# define fegetenv_status() fegetenv_register ()
-#endif
-
 /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
 #define fesetenv_register(env) \
 	do { \