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/* Internal libc stuff for floating point environment routines.
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Copyright (C) 1997-2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _FENV_LIBC_H
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#define _FENV_LIBC_H 1
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#include <fenv.h>
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#include <ldsodefs.h>
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#include <sysdep.h>
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extern const fenv_t *__fe_nomask_env_priv (void);
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extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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/* The sticky bits in the FPSCR indicating exceptions have occurred. */
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#define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
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/* Equivalent to fegetenv, but returns a fenv_t instead of taking a
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pointer. */
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#define fegetenv_register() \
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({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
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/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */
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#define fesetenv_register(env) \
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do { \
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double d = (env); \
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if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
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asm volatile (".machine push; " \
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".machine \"power6\"; " \
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"mtfsf 0xff,%0,1,0; " \
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".machine pop" : : "f" (d)); \
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else \
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asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \
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} while(0)
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/* This very handy macro:
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- Sets the rounding mode to 'round to nearest';
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- Sets the processor into IEEE mode; and
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- Prevents exceptions from being raised for inexact results.
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These things happen to be exactly what you need for typical elementary
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functions. */
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#define relax_fenv_state() \
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do { \
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if (GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
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asm volatile (".machine push; .machine \"power6\"; " \
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"mtfsfi 7,0,1; .machine pop"); \
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asm volatile ("mtfsfi 7,0"); \
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} while(0)
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/* Set/clear a particular FPSCR bit (for instance,
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reset_fpscr_bit(FPSCR_VE);
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prevents INVALID exceptions from being raised). */
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#define set_fpscr_bit(x) asm volatile ("mtfsb1 %0" : : "i"(x))
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#define reset_fpscr_bit(x) asm volatile ("mtfsb0 %0" : : "i"(x))
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typedef union
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{
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fenv_t fenv;
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unsigned long long l;
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} fenv_union_t;
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static inline int
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__fesetround_inline (int round)
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{
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if ((unsigned int) round < 2)
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{
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asm volatile ("mtfsb0 30");
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if ((unsigned int) round == 0)
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asm volatile ("mtfsb0 31");
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else
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asm volatile ("mtfsb1 31");
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}
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else
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{
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asm volatile ("mtfsb1 30");
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if ((unsigned int) round == 2)
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asm volatile ("mtfsb0 31");
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else
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asm volatile ("mtfsb1 31");
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}
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bc2dc3 |
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return 0;
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}
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/* Same as __fesetround_inline, however without runtime check to use DFP
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mtfsfi syntax (as relax_fenv_state) or if round value is valid. */
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static inline void
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__fesetround_inline_nocheck (const int round)
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{
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asm volatile ("mtfsfi 7,%0" : : "i" (round));
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}
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/* Definitions of all the FPSCR bit numbers */
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enum {
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FPSCR_FX = 0, /* exception summary */
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FPSCR_FEX, /* enabled exception summary */
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FPSCR_VX, /* invalid operation summary */
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FPSCR_OX, /* overflow */
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FPSCR_UX, /* underflow */
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FPSCR_ZX, /* zero divide */
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FPSCR_XX, /* inexact */
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FPSCR_VXSNAN, /* invalid operation for sNaN */
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FPSCR_VXISI, /* invalid operation for Inf-Inf */
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FPSCR_VXIDI, /* invalid operation for Inf/Inf */
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FPSCR_VXZDZ, /* invalid operation for 0/0 */
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FPSCR_VXIMZ, /* invalid operation for Inf*0 */
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FPSCR_VXVC, /* invalid operation for invalid compare */
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FPSCR_FR, /* fraction rounded [fraction was incremented by round] */
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FPSCR_FI, /* fraction inexact */
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FPSCR_FPRF_C, /* result class descriptor */
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FPSCR_FPRF_FL, /* result less than (usually, less than 0) */
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FPSCR_FPRF_FG, /* result greater than */
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FPSCR_FPRF_FE, /* result equal to */
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FPSCR_FPRF_FU, /* result unordered */
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FPSCR_20, /* reserved */
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FPSCR_VXSOFT, /* invalid operation set by software */
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FPSCR_VXSQRT, /* invalid operation for square root */
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FPSCR_VXCVI, /* invalid operation for invalid integer convert */
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FPSCR_VE, /* invalid operation exception enable */
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FPSCR_OE, /* overflow exception enable */
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FPSCR_UE, /* underflow exception enable */
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FPSCR_ZE, /* zero divide exception enable */
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FPSCR_XE, /* inexact exception enable */
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#ifdef _ARCH_PWR6
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FPSCR_29, /* Reserved in ISA 2.05 */
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#else
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FPSCR_NI /* non-IEEE mode (typically, no denormalised numbers) */
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#endif /* _ARCH_PWR6 */
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/* the remaining two least-significant bits keep the rounding mode */
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};
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static inline int
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fenv_reg_to_exceptions (unsigned long long l)
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{
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int result = 0;
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if (l & (1 << (31 - FPSCR_XE)))
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result |= FE_INEXACT;
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if (l & (1 << (31 - FPSCR_ZE)))
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result |= FE_DIVBYZERO;
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if (l & (1 << (31 - FPSCR_UE)))
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result |= FE_UNDERFLOW;
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if (l & (1 << (31 - FPSCR_OE)))
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result |= FE_OVERFLOW;
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if (l & (1 << (31 - FPSCR_VE)))
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result |= FE_INVALID;
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return result;
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}
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#ifdef _ARCH_PWR6
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/* Not supported in ISA 2.05. Provided for source compat only. */
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# define FPSCR_NI 29
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#endif /* _ARCH_PWR6 */
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/* This operation (i) sets the appropriate FPSCR bits for its
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parameter, (ii) converts sNaN to the corresponding qNaN, and (iii)
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otherwise passes its parameter through unchanged (in particular, -0
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and +0 stay as they were). The `obvious' way to do this is optimised
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out by gcc. */
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#define f_wash(x) \
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({ double d; asm volatile ("fmul %0,%1,%2" \
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: "=f"(d) \
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: "f" (x), "f"((float)1.0)); d; })
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#define f_washf(x) \
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({ float f; asm volatile ("fmuls %0,%1,%2" \
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: "=f"(f) \
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: "f" (x), "f"((float)1.0)); f; })
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#endif /* fenv_libc.h */
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