Blame sysdeps/aarch64/fpu/feenablxcpt.c
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/* Copyright (C) 2001-2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public License as
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published by the Free Software Foundation; either version 2.1 of the
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License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <fenv.h>
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#include <fpu_control.h>
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int
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feenableexcept (int excepts)
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{
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fpu_control_t fpcr;
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fpu_control_t fpcr_new;
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fpu_control_t updated_fpcr;
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_FPU_GETCW (fpcr);
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excepts &= FE_ALL_EXCEPT;
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fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT);
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if (fpcr != fpcr_new)
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{
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_FPU_SETCW (fpcr_new);
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/* Trapping exceptions are optional in AArch64; the relevant enable
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bits in FPCR are RES0 hence the absence of support can be detected
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by reading back the FPCR and comparing with the required value. */
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_FPU_GETCW (updated_fpcr);
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if (fpcr_new & ~updated_fpcr)
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return -1;
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}
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return (fpcr >> FE_EXCEPT_SHIFT) & FE_ALL_EXCEPT;
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}
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