/* rx.c --- opcode semantics for stand-alone RX simulator.

Copyright (C) 2008-2018 Free Software Foundation, Inc.

Contributed by Red Hat, Inc.

This file is part of the GNU simulators.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 3 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "config.h"

#include <stdio.h>

#include <stdlib.h>

#include <string.h>

#include <signal.h>

#include "libiberty.h"

#include "opcode/rx.h"

#include "cpu.h"

#include "mem.h"

#include "syscalls.h"

#include "fpu.h"

#include "err.h"

#include "misc.h"

#ifdef CYCLE_STATS

static const char * id_names[] = {

  "RXO_unknown",

  "RXO_mov",	/* d = s (signed) */

  "RXO_movbi",	/* d = [s,s2] (signed) */

  "RXO_movbir",	/* [s,s2] = d (signed) */

  "RXO_pushm",	/* s..s2 */

  "RXO_popm",	/* s..s2 */

  "RXO_xchg",	/* s <-> d */

  "RXO_stcc",	/* d = s if cond(s2) */

  "RXO_rtsd",	/* rtsd, 1=imm, 2-0 = reg if reg type */

  /* These are all either d OP= s or, if s2 is set, d = s OP s2.  Note

     that d may be "None".  */

  "RXO_and",

  "RXO_or",

  "RXO_xor",

  "RXO_add",

  "RXO_sub",

  "RXO_mul",

  "RXO_div",

  "RXO_divu",

  "RXO_shll",

  "RXO_shar",

  "RXO_shlr",

  "RXO_adc",	/* d = d + s + carry */

  "RXO_sbb",	/* d = d - s - ~carry */

  "RXO_abs",	/* d = |s| */

  "RXO_max",	/* d = max(d,s) */

  "RXO_min",	/* d = min(d,s) */

  "RXO_emul",	/* d:64 = d:32 * s */

  "RXO_emulu",	/* d:64 = d:32 * s (unsigned) */

  "RXO_rolc",	/* d <<= 1 through carry */

  "RXO_rorc",	/* d >>= 1 through carry*/

  "RXO_rotl",	/* d <<= #s without carry */

  "RXO_rotr",	/* d >>= #s without carry*/

  "RXO_revw",	/* d = revw(s) */

  "RXO_revl",	/* d = revl(s) */

  "RXO_branch",	/* pc = d if cond(s) */

  "RXO_branchrel",/* pc += d if cond(s) */

  "RXO_jsr",	/* pc = d */

  "RXO_jsrrel",	/* pc += d */

  "RXO_rts",

  "RXO_nop",

  "RXO_nop2",

  "RXO_nop3",

  "RXO_nop4",

  "RXO_nop5",

  "RXO_nop6",

  "RXO_nop7",

  "RXO_scmpu",

  "RXO_smovu",

  "RXO_smovb",

  "RXO_suntil",

  "RXO_swhile",

  "RXO_smovf",

  "RXO_sstr",

  "RXO_rmpa",

  "RXO_mulhi",

  "RXO_mullo",

  "RXO_machi",

  "RXO_maclo",

  "RXO_mvtachi",

  "RXO_mvtaclo",

  "RXO_mvfachi",

  "RXO_mvfacmi",

  "RXO_mvfaclo",

  "RXO_racw",

  "RXO_sat",	/* sat(d) */

  "RXO_satr",

  "RXO_fadd",	/* d op= s */

  "RXO_fcmp",

  "RXO_fsub",

  "RXO_ftoi",

  "RXO_fmul",

  "RXO_fdiv",

  "RXO_round",

  "RXO_itof",

  "RXO_bset",	/* d |= (1<

  "RXO_bclr",	/* d &= ~(1<

  "RXO_btst",	/* s & (1<

  "RXO_bnot",	/* d ^= (1<

  "RXO_bmcc",	/* d<s> = cond(s2) */

  "RXO_clrpsw",	/* flag index in d */

  "RXO_setpsw",	/* flag index in d */

  "RXO_mvtipl",	/* new IPL in s */

  "RXO_rtfi",

  "RXO_rte",

  "RXO_rtd",	/* undocumented */

  "RXO_brk",

  "RXO_dbt",	/* undocumented */

  "RXO_int",	/* vector id in s */

  "RXO_stop",

  "RXO_wait",

  "RXO_sccnd",	/* d = cond(s) ? 1 : 0 */

};

static const char * optype_names[] = {

  " -  ",

  "#Imm",	/* #addend */

  " Rn ",	/* Rn */

  "[Rn]",	/* [Rn + addend] */

  "Ps++",	/* [Rn+] */

  "--Pr",	/* [-Rn] */

  " cc ",	/* eq, gtu, etc */

  "Flag",	/* [UIOSZC] */

  "RbRi"	/* [Rb + scale * Ri] */

};

#define N_RXO ARRAY_SIZE (id_names)

#define N_RXT ARRAY_SIZE (optype_names)

#define N_MAP 90

static unsigned long long benchmark_start_cycle;

static unsigned long long benchmark_end_cycle;

static int op_cache[N_RXT][N_RXT][N_RXT];

static int op_cache_rev[N_MAP];

static int op_cache_idx = 0;

static int

op_lookup (int a, int b, int c)

{

  if (op_cache[a][b][c])

    return op_cache[a][b][c];

  op_cache_idx ++;

  if (op_cache_idx >= N_MAP)

    {

      printf("op_cache_idx exceeds %d\n", N_MAP);

      exit(1);

    }

  op_cache[a][b][c] = op_cache_idx;

  op_cache_rev[op_cache_idx] = (a<<8) | (b<<4) | c;

  return op_cache_idx;

}

static char *

op_cache_string (int map)

{

  static int ci;

  static char cb[5][20];

  int a, b, c;

  map = op_cache_rev[map];

  a = (map >> 8) & 15;

  b = (map >> 4) & 15;

  c = (map >> 0) & 15;

  ci = (ci + 1) % 5;

  sprintf(cb[ci], "%s %s %s", optype_names[a], optype_names[b], optype_names[c]);

  return cb[ci];

}

static unsigned long long cycles_per_id[N_RXO][N_MAP];

static unsigned long long times_per_id[N_RXO][N_MAP];

static unsigned long long memory_stalls;

static unsigned long long register_stalls;

static unsigned long long branch_stalls;

static unsigned long long branch_alignment_stalls;

static unsigned long long fast_returns;

static unsigned long times_per_pair[N_RXO][N_MAP][N_RXO][N_MAP];

static int prev_opcode_id = RXO_unknown;

static int po0;

#define STATS(x) x

#else

#define STATS(x)

#endif /* CYCLE_STATS */

#ifdef CYCLE_ACCURATE

static int new_rt = -1;

/* Number of cycles to add if an insn spans an 8-byte boundary.  */

static int branch_alignment_penalty = 0;

#endif

static int running_benchmark = 1;

#define tprintf if (trace && running_benchmark) printf

jmp_buf decode_jmp_buf;

unsigned int rx_cycles = 0;

#ifdef CYCLE_ACCURATE

/* If nonzero, memory was read at some point and cycle latency might

   take effect.  */

static int memory_source = 0;

/* If nonzero, memory was written and extra cycles might be

   needed.  */

static int memory_dest = 0;

static void

cycles (int throughput)

{

  tprintf("%d cycles\n", throughput);

  regs.cycle_count += throughput;

}

/* Number of execution (E) cycles the op uses.  For memory sources, we

   include the load micro-op stall as two extra E cycles.  */

#define E(c) cycles (memory_source ? c + 2 : c)

#define E1 cycles (1)

#define E2 cycles (2)

#define EBIT cycles (memory_source ? 2 : 1)

/* Check to see if a read latency must be applied for a given register.  */

#define RL(r) \

  if (regs.rt == r )							\

    {									\

      tprintf("register %d load stall\n", r);				\

      regs.cycle_count ++;						\

      STATS(register_stalls ++);					\

      regs.rt = -1;							\

    }

#define RLD(r)					\

  if (memory_source)				\

    {						\

      tprintf ("Rt now %d\n", r);		\

      new_rt = r;				\

    }

static int

lsb_count (unsigned long v, int is_signed)

{

  int i, lsb;

  if (is_signed && (v & 0x80000000U))

    v = (unsigned long)(long)(-v);

  for (i=31; i>=0; i--)

    if (v & (1 << i))

      {

	/* v is 0..31, we want 1=1-2, 2=3-4, 3=5-6, etc. */

	lsb = (i + 2) / 2;

	return lsb;

      }

  return 0;

}

static int

divu_cycles(unsigned long num, unsigned long den)

{

  int nb = lsb_count (num, 0);

  int db = lsb_count (den, 0);

  int rv;

  if (nb < db)

    rv = 2;

  else

    rv = 3 + nb - db;

  E (rv);

  return rv;

}

static int

div_cycles(long num, long den)

{

  int nb = lsb_count ((unsigned long)num, 1);

  int db = lsb_count ((unsigned long)den, 1);

  int rv;

  if (nb < db)

    rv = 3;

  else

    rv = 5 + nb - db;

  E (rv);

  return rv;

}

#else /* !CYCLE_ACCURATE */

#define cycles(t)

#define E(c)

#define E1

#define E2

#define EBIT

#define RL(r)

#define RLD(r)

#define divu_cycles(n,d)

#define div_cycles(n,d)

#endif /* else CYCLE_ACCURATE */

static int size2bytes[] = {

  4, 1, 1, 1, 2, 2, 2, 3, 4

};

typedef struct {

  unsigned long dpc;

} RX_Data;

#define rx_abort() _rx_abort(__FILE__, __LINE__)

static void

_rx_abort (const char *file, int line)

{

  if (strrchr (file, '/'))

    file = strrchr (file, '/') + 1;

  fprintf(stderr, "abort at %s:%d\n", file, line);

  abort();

}

static unsigned char *get_byte_base;

static RX_Opcode_Decoded **decode_cache_base;

static SI get_byte_page;

void

reset_decoder (void)

{

  get_byte_base = 0;

  decode_cache_base = 0;

  get_byte_page = 0;

}

static inline void

maybe_get_mem_page (SI tpc)

{

  if (((tpc ^ get_byte_page) & NONPAGE_MASK) || enable_counting)

    {

      get_byte_page = tpc & NONPAGE_MASK;

      get_byte_base = rx_mem_ptr (get_byte_page, MPA_READING) - get_byte_page;

      decode_cache_base = rx_mem_decode_cache (get_byte_page) - get_byte_page;

    }

}

/* This gets called a *lot* so optimize it.  */

static int

rx_get_byte (void *vdata)

{

  RX_Data *rx_data = (RX_Data *)vdata;

  SI tpc = rx_data->dpc;

  /* See load.c for an explanation of this.  */

  if (rx_big_endian)

    tpc ^= 3;

  maybe_get_mem_page (tpc);

  rx_data->dpc ++;

  return get_byte_base [tpc];

}

static int

get_op (const RX_Opcode_Decoded *rd, int i)

{

  const RX_Opcode_Operand *o = rd->op + i;

  int addr, rv = 0;

  switch (o->type)

    {

    case RX_Operand_None:

      rx_abort ();

    case RX_Operand_Immediate:	/* #addend */

      return o->addend;

    case RX_Operand_Register:	/* Rn */

      RL (o->reg);

      rv = get_reg (o->reg);

      break;

    case RX_Operand_Predec:	/* [-Rn] */

      put_reg (o->reg, get_reg (o->reg) - size2bytes[o->size]);

      /* fall through */

    case RX_Operand_Postinc:	/* [Rn+] */

    case RX_Operand_Zero_Indirect:	/* [Rn + 0] */

    case RX_Operand_Indirect:	/* [Rn + addend] */

    case RX_Operand_TwoReg:	/* [Rn + scale * R2] */

#ifdef CYCLE_ACCURATE

      RL (o->reg);

      if (o->type == RX_Operand_TwoReg)

	RL (rd->op[2].reg);

      regs.rt = -1;

      if (regs.m2m == M2M_BOTH)

	{

	  tprintf("src memory stall\n");

#ifdef CYCLE_STATS

	  memory_stalls ++;

#endif

	  regs.cycle_count ++;

	  regs.m2m = 0;

	}

      memory_source = 1;

#endif

      if (o->type == RX_Operand_TwoReg)

	addr = get_reg (o->reg) * size2bytes[rd->size] + get_reg (rd->op[2].reg);

      else

	addr = get_reg (o->reg) + o->addend;

      switch (o->size)

	{

	default:

	case RX_AnySize:

	  rx_abort ();

	case RX_Byte: /* undefined extension */

	case RX_UByte:

	case RX_SByte:

	  rv = mem_get_qi (addr);

	  break;

	case RX_Word: /* undefined extension */

	case RX_UWord:

	case RX_SWord:

	  rv = mem_get_hi (addr);

	  break;

	case RX_3Byte:

	  rv = mem_get_psi (addr);

	  break;

	case RX_Long:

	  rv = mem_get_si (addr);

	  break;

	}

      if (o->type == RX_Operand_Postinc)

	put_reg (o->reg, get_reg (o->reg) + size2bytes[o->size]);

      break;

    case RX_Operand_Condition:	/* eq, gtu, etc */

      return condition_true (o->reg);

    case RX_Operand_Flag:	/* [UIOSZC] */

      return (regs.r_psw & (1 << o->reg)) ? 1 : 0;

    }

  /* if we've gotten here, we need to clip/extend the value according

     to the size.  */

  switch (o->size)

    {

    default:

    case RX_AnySize:

      rx_abort ();

    case RX_Byte: /* undefined extension */

      rv |= 0xdeadbe00; /* keep them honest */

      break;

    case RX_UByte:

      rv &= 0xff;

      break;

    case RX_SByte:

      rv = sign_ext (rv, 8);

      break;

    case RX_Word: /* undefined extension */

      rv |= 0xdead0000; /* keep them honest */

      break;

    case RX_UWord:

      rv &=  0xffff;

      break;

    case RX_SWord:

      rv = sign_ext (rv, 16);

      break;

    case RX_3Byte:

      rv &= 0xffffff;

      break;

    case RX_Long:

      break;

    }

  return rv;

}

static void

put_op (const RX_Opcode_Decoded *rd, int i, int v)

{

  const RX_Opcode_Operand *o = rd->op + i;

  int addr;

  switch (o->size)

    {

    default:

    case RX_AnySize:

      if (o->type != RX_Operand_Register)

	rx_abort ();

      break;

    case RX_Byte: /* undefined extension */

      v |= 0xdeadbe00; /* keep them honest */

      break;

    case RX_UByte:

      v &= 0xff;

      break;

    case RX_SByte:

      v = sign_ext (v, 8);

      break;

    case RX_Word: /* undefined extension */

      v |= 0xdead0000; /* keep them honest */

      break;

    case RX_UWord:

      v &=  0xffff;

      break;

    case RX_SWord:

      v = sign_ext (v, 16);

      break;

    case RX_3Byte:

      v &= 0xffffff;

      break;

    case RX_Long:

      break;

    }

  switch (o->type)

    {

    case RX_Operand_None:

      /* Opcodes like TST and CMP use this.  */

      break;

    case RX_Operand_Immediate:	/* #addend */

    case RX_Operand_Condition:	/* eq, gtu, etc */

      rx_abort ();

    case RX_Operand_Register:	/* Rn */

      put_reg (o->reg, v);

      RLD (o->reg);

      break;

    case RX_Operand_Predec:	/* [-Rn] */

      put_reg (o->reg, get_reg (o->reg) - size2bytes[o->size]);

      /* fall through */

    case RX_Operand_Postinc:	/* [Rn+] */

    case RX_Operand_Zero_Indirect:	/* [Rn + 0] */

    case RX_Operand_Indirect:	/* [Rn + addend] */

    case RX_Operand_TwoReg:	/* [Rn + scale * R2] */

#ifdef CYCLE_ACCURATE

      if (regs.m2m == M2M_BOTH)

	{

	  tprintf("dst memory stall\n");

	  regs.cycle_count ++;

#ifdef CYCLE_STATS

	  memory_stalls ++;

#endif

	  regs.m2m = 0;

	}

      memory_dest = 1;

#endif

      if (o->type == RX_Operand_TwoReg)

	addr = get_reg (o->reg) * size2bytes[rd->size] + get_reg (rd->op[2].reg);

      else

	addr = get_reg (o->reg) + o->addend;

      switch (o->size)

	{

	default:

	case RX_AnySize:

	  rx_abort ();

	case RX_Byte: /* undefined extension */

	case RX_UByte:

	case RX_SByte:

	  mem_put_qi (addr, v);

	  break;

	case RX_Word: /* undefined extension */

	case RX_UWord:

	case RX_SWord:

	  mem_put_hi (addr, v);

	  break;

	case RX_3Byte:

	  mem_put_psi (addr, v);

	  break;

	case RX_Long:

	  mem_put_si (addr, v);

	  break;

	}

      if (o->type == RX_Operand_Postinc)

	put_reg (o->reg, get_reg (o->reg) + size2bytes[o->size]);

      break;

    case RX_Operand_Flag:	/* [UIOSZC] */

      if (v)

	regs.r_psw |= (1 << o->reg);

      else

	regs.r_psw &= ~(1 << o->reg);

      break;

    }

}

#define PD(x) put_op (opcode, 0, x)

#define PS(x) put_op (opcode, 1, x)

#define PS2(x) put_op (opcode, 2, x)

#define GD() get_op (opcode, 0)

#define GS() get_op (opcode, 1)

#define GS2() get_op (opcode, 2)

#define DSZ() size2bytes[opcode->op[0].size]

#define SSZ() size2bytes[opcode->op[0].size]

#define S2SZ() size2bytes[opcode->op[0].size]

/* "Universal" sources.  */

#define US1() ((opcode->op[2].type == RX_Operand_None) ? GD() : GS())

#define US2() ((opcode->op[2].type == RX_Operand_None) ? GS() : GS2())

static void

push(int val)

{

  int rsp = get_reg (sp);

  rsp -= 4;

  put_reg (sp, rsp);

  mem_put_si (rsp, val);

}

/* Just like the above, but tag the memory as "pushed pc" so if anyone

   tries to write to it, it will cause an error.  */

static void

pushpc(int val)

{

  int rsp = get_reg (sp);

  rsp -= 4;

  put_reg (sp, rsp);

  mem_put_si (rsp, val);

  mem_set_content_range (rsp, rsp+3, MC_PUSHED_PC);

}

static int

pop()

{

  int rv;

  int rsp = get_reg (sp);

  rv = mem_get_si (rsp);

  rsp += 4;

  put_reg (sp, rsp);

  return rv;

}

static int

poppc()

{

  int rv;

  int rsp = get_reg (sp);

  if (mem_get_content_type (rsp) != MC_PUSHED_PC)

    execution_error (SIM_ERR_CORRUPT_STACK, rsp);

  rv = mem_get_si (rsp);

  mem_set_content_range (rsp, rsp+3, MC_UNINIT);

  rsp += 4;

  put_reg (sp, rsp);

  return rv;

}

#define MATH_OP(vop,c)				\

{ \

  umb = US2(); \

  uma = US1(); \

  ll = (unsigned long long) uma vop (unsigned long long) umb vop c; \

  tprintf ("0x%x " #vop " 0x%x " #vop " 0x%x = 0x%llx\n", uma, umb, c, ll); \

  ma = sign_ext (uma, DSZ() * 8);					\

  mb = sign_ext (umb, DSZ() * 8);					\

  sll = (long long) ma vop (long long) mb vop c; \

  tprintf ("%d " #vop " %d " #vop " %d = %lld\n", ma, mb, c, sll); \

  set_oszc (sll, DSZ(), (long long) ll > ((1 vop 1) ? (long long) b2mask[DSZ()] : (long long) -1)); \

  PD (sll); \

  E (1);    \

}

#define LOGIC_OP(vop) \

{ \

  mb = US2(); \

  ma = US1(); \

  v = ma vop mb; \

  tprintf("0x%x " #vop " 0x%x = 0x%x\n", ma, mb, v); \

  set_sz (v, DSZ()); \

  PD(v); \

  E (1); \

}

#define SHIFT_OP(val, type, count, OP, carry_mask)	\

{ \

  int i, c=0; \

  count = US2(); \

  val = (type)US1();				\

  tprintf("%lld " #OP " %d\n", val, count); \

  for (i = 0; i < count; i ++) \

    { \

      c = val & carry_mask; \

      val OP 1; \

    } \

  set_oszc (val, 4, c); \

  PD (val); \

}

typedef union {

  int i;

  float f;

} FloatInt;

static inline int

float2int (float f)

{

  FloatInt fi;

  fi.f = f;

  return fi.i;

}

static inline float

int2float (int i)

{

  FloatInt fi;

  fi.i = i;

  return fi.f;

}

static int

fop_fadd (fp_t s1, fp_t s2, fp_t *d)

{

  *d = rxfp_add (s1, s2);

  return 1;

}

static int

fop_fmul (fp_t s1, fp_t s2, fp_t *d)

{

  *d = rxfp_mul (s1, s2);

  return 1;

}

static int

fop_fdiv (fp_t s1, fp_t s2, fp_t *d)

{

  *d = rxfp_div (s1, s2);

  return 1;

}

static int

fop_fsub (fp_t s1, fp_t s2, fp_t *d)

{

  *d = rxfp_sub (s1, s2);

  return 1;

}

#define FPPENDING() (regs.r_fpsw & (FPSWBITS_CE | (FPSWBITS_FMASK & (regs.r_fpsw << FPSW_EFSH))))

#define FPCLEAR() regs.r_fpsw &= FPSWBITS_CLEAR

#define FPCHECK() \

  if (FPPENDING()) \

    return do_fp_exception (opcode_pc)

#define FLOAT_OP(func) \

{ \

  int do_store;   \

  fp_t fa, fb, fc; \

  FPCLEAR(); \

  fb = GS (); \

  fa = GD (); \

  do_store = fop_##func (fa, fb, &fc); \

  tprintf("%g " #func " %g = %g %08x\n", int2float(fa), int2float(fb), int2float(fc), fc); \

  FPCHECK(); \

  if (do_store) \

    PD (fc);	\

  mb = 0; \

  if ((fc & 0x80000000UL) != 0) \

    mb |= FLAGBIT_S; \

  if ((fc & 0x7fffffffUL) == 0)			\

    mb |= FLAGBIT_Z; \

  set_flags (FLAGBIT_S | FLAGBIT_Z, mb); \

}

#define carry (FLAG_C ? 1 : 0)

static struct {

  unsigned long vaddr;

  const char *str;

  int signal;

} exception_info[] = {

  { 0xFFFFFFD0UL, "priviledged opcode", SIGILL },

  { 0xFFFFFFD4UL, "access violation", SIGSEGV },

  { 0xFFFFFFDCUL, "undefined opcode", SIGILL },

  { 0xFFFFFFE4UL, "floating point", SIGFPE }

};

#define EX_PRIVILEDGED	0

#define EX_ACCESS	1

#define EX_UNDEFINED	2

#define EX_FLOATING	3

#define EXCEPTION(n)  \

  return generate_exception (n, opcode_pc)

#define PRIVILEDGED() \

  if (FLAG_PM) \

    EXCEPTION (EX_PRIVILEDGED)

static int

generate_exception (unsigned long type, SI opcode_pc)

{

  SI old_psw, old_pc, new_pc;

  new_pc = mem_get_si (exception_info[type].vaddr);

  /* 0x00020000 is the value used to initialise the known

     exception vectors (see rx.ld), but it is a reserved

     area of memory so do not try to access it, and if the

     value has not been changed by the program then the

     vector has not been installed.  */

  if (new_pc == 0 || new_pc == 0x00020000)

    {

      if (rx_in_gdb)

	return RX_MAKE_STOPPED (exception_info[type].signal);

      fprintf(stderr, "Unhandled %s exception at pc = %#lx\n",

	      exception_info[type].str, (unsigned long) opcode_pc);

      if (type == EX_FLOATING)

	{

	  int mask = FPPENDING ();

	  fprintf (stderr, "Pending FP exceptions:");

	  if (mask & FPSWBITS_FV)

	    fprintf(stderr, " Invalid");

	  if (mask & FPSWBITS_FO)

	    fprintf(stderr, " Overflow");

	  if (mask & FPSWBITS_FZ)

	    fprintf(stderr, " Division-by-zero");

	  if (mask & FPSWBITS_FU)

	    fprintf(stderr, " Underflow");

	  if (mask & FPSWBITS_FX)

	    fprintf(stderr, " Inexact");

	  if (mask & FPSWBITS_CE)