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commit 83d776f979342f923b5c3d2a5b43afab841c6086
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Author: Andrew Senkevich <andrew.senkevich@intel.com>
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Date: Sat Dec 19 02:47:28 2015 +0300
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Added memset optimized with AVX512 for KNL hardware.
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It shows improvement up to 28% over AVX2 memset (performance results
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attached at <https://sourceware.org/ml/libc-alpha/2015-12/msg00052.html>).
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* sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S: New file.
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* sysdeps/x86_64/multiarch/Makefile (sysdep_routines): Added new file.
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* sysdeps/x86_64/multiarch/ifunc-impl-list.c: Added new tests.
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* sysdeps/x86_64/multiarch/memset.S: Added new IFUNC branch.
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* sysdeps/x86_64/multiarch/memset_chk.S: Likewise.
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* sysdeps/x86/cpu-features.h (bit_Prefer_No_VZEROUPPER,
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index_Prefer_No_VZEROUPPER): New.
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* sysdeps/x86/cpu-features.c (init_cpu_features): Set the
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Prefer_No_VZEROUPPER for Knights Landing.
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Index: glibc-2.17-c758a686/sysdeps/x86/cpu-features.c
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===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/x86/cpu-features.c
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+++ glibc-2.17-c758a686/sysdeps/x86/cpu-features.c
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@@ -76,6 +76,8 @@ init_cpu_features (struct cpu_features *
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case 0x57:
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/* Knights Landing. Enable Silvermont optimizations. */
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+ cpu_features->feature[index_Prefer_No_VZEROUPPER]
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+ |= bit_Prefer_No_VZEROUPPER;
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case 0x37:
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case 0x4a:
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Index: glibc-2.17-c758a686/sysdeps/x86/cpu-features.h
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===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/x86/cpu-features.h
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+++ glibc-2.17-c758a686/sysdeps/x86/cpu-features.h
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@@ -33,6 +33,7 @@
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#define bit_AVX512F_Usable (1 << 12)
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#define bit_AVX512DQ_Usable (1 << 13)
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#define bit_Prefer_MAP_32BIT_EXEC (1 << 16)
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+#define bit_Prefer_No_VZEROUPPER (1 << 17)
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/* CPUID Feature flags. */
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@@ -93,6 +94,7 @@
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# define index_AVX512F_Usable FEATURE_INDEX_1*FEATURE_SIZE
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# define index_AVX512DQ_Usable FEATURE_INDEX_1*FEATURE_SIZE
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# define index_Prefer_MAP_32BIT_EXEC FEATURE_INDEX_1*FEATURE_SIZE
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+# define index_Prefer_No_VZEROUPPER FEATURE_INDEX_1*FEATURE_SIZE
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# if defined (_LIBC) && !IS_IN (nonlib)
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# ifdef __x86_64__
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@@ -270,6 +272,7 @@ extern const struct cpu_features *__get_
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# define index_AVX512F_Usable FEATURE_INDEX_1
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# define index_AVX512DQ_Usable FEATURE_INDEX_1
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# define index_Prefer_MAP_32BIT_EXEC FEATURE_INDEX_1
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+# define index_Prefer_No_VZEROUPPER FEATURE_INDEX_1
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#endif /* !__ASSEMBLER__ */
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Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/Makefile
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===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/Makefile
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+++ glibc-2.17-c758a686/sysdeps/x86_64/multiarch/Makefile
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@@ -16,7 +16,8 @@ sysdep_routines += strncat-c stpncpy-c s
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strcat-sse2-unaligned strncat-sse2-unaligned \
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strcat-ssse3 strncat-ssse3 strlen-sse2-pminub \
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strnlen-sse2-no-bsf strrchr-sse2-no-bsf strchr-sse2-no-bsf \
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- memcmp-ssse3 strstr-sse2-unaligned
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+ memcmp-ssse3 strstr-sse2-unaligned \
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+ memset-avx512-no-vzeroupper
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ifeq (yes,$(config-cflags-sse4))
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sysdep_routines += strcspn-c strpbrk-c strspn-c strstr-c strcasestr-c varshift
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CFLAGS-varshift.c += -msse4
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Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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+++ glibc-2.17-c758a686/sysdeps/x86_64/multiarch/ifunc-impl-list.c
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@@ -20,6 +20,7 @@
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#include <string.h>
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#include <wchar.h>
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#include <ifunc-impl-list.h>
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+#include <sysdep.h>
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#include "init-arch.h"
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/* Maximum number of IFUNC implementations. */
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@@ -66,12 +67,24 @@ __libc_ifunc_impl_list (const char *name
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IFUNC_IMPL (i, name, __memset_chk,
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IFUNC_IMPL_ADD (array, i, __memset_chk, 1, __memset_chk_sse2)
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IFUNC_IMPL_ADD (array, i, __memset_chk, 1,
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- __memset_chk_x86_64))
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+ __memset_chk_x86_64)
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+#ifdef HAVE_AVX512_ASM_SUPPORT
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+ IFUNC_IMPL_ADD (array, i, __memset_chk,
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+ HAS_ARCH_FEATURE (AVX512F_Usable),
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+ __memset_chk_avx512_no_vzeroupper)
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+#endif
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+ )
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/* Support sysdeps/x86_64/multiarch/memset.S. */
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IFUNC_IMPL (i, name, memset,
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IFUNC_IMPL_ADD (array, i, memset, 1, __memset_sse2)
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- IFUNC_IMPL_ADD (array, i, memset, 1, __memset_x86_64))
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+ IFUNC_IMPL_ADD (array, i, memset, 1, __memset_x86_64)
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+#ifdef HAVE_AVX512_ASM_SUPPORT
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+ IFUNC_IMPL_ADD (array, i, memset,
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+ HAS_ARCH_FEATURE (AVX512F_Usable),
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+ __memset_avx512_no_vzeroupper)
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+#endif
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+ )
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/* Support sysdeps/x86_64/multiarch/rawmemchr.S. */
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IFUNC_IMPL (i, name, rawmemchr,
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Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S
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===================================================================
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--- /dev/null
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+++ glibc-2.17-c758a686/sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S
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@@ -0,0 +1,194 @@
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+/* memset optimized with AVX512 for KNL hardware.
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+ Copyright (C) 2015 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <http://www.gnu.org/licenses/>. */
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+
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+#include <sysdep.h>
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+
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+#if defined HAVE_AVX512_ASM_SUPPORT && IS_IN (libc)
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+
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+#include "asm-syntax.h"
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+#ifndef MEMSET
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+# define MEMSET __memset_avx512_no_vzeroupper
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+# define MEMSET_CHK __memset_chk_avx512_no_vzeroupper
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+#endif
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+
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+ .section .text,"ax",@progbits
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+#if defined PIC
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+ENTRY (MEMSET_CHK)
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+ cmpq %rdx, %rcx
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+ jb HIDDEN_JUMPTARGET (__chk_fail)
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+END (MEMSET_CHK)
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+#endif
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+
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+ENTRY (MEMSET)
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+ vpxor %xmm0, %xmm0, %xmm0
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+ vmovd %esi, %xmm1
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+ lea (%rdi, %rdx), %rsi
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+ mov %rdi, %rax
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+ vpshufb %xmm0, %xmm1, %xmm0
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+ cmp $16, %rdx
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+ jb L(less_16bytes)
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+ cmp $512, %rdx
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+ vbroadcastss %xmm0, %zmm2
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+ ja L(512bytesormore)
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+ cmp $256, %rdx
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+ jb L(less_256bytes)
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+ vmovups %zmm2, (%rdi)
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+ vmovups %zmm2, 0x40(%rdi)
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+ vmovups %zmm2, 0x80(%rdi)
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+ vmovups %zmm2, 0xC0(%rdi)
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+ vmovups %zmm2, -0x100(%rsi)
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+ vmovups %zmm2, -0xC0(%rsi)
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+ vmovups %zmm2, -0x80(%rsi)
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+ vmovups %zmm2, -0x40(%rsi)
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+ ret
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+
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+L(less_256bytes):
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+ cmp $128, %dl
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+ jb L(less_128bytes)
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+ vmovups %zmm2, (%rdi)
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+ vmovups %zmm2, 0x40(%rdi)
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+ vmovups %zmm2, -0x80(%rsi)
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+ vmovups %zmm2, -0x40(%rsi)
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+ ret
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+
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+L(less_128bytes):
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+ cmp $64, %dl
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+ jb L(less_64bytes)
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+ vmovups %zmm2, (%rdi)
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+ vmovups %zmm2, -0x40(%rsi)
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+ ret
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+
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+L(less_64bytes):
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+ cmp $32, %dl
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+ jb L(less_32bytes)
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+ vmovdqu %ymm2, (%rdi)
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+ vmovdqu %ymm2, -0x20(%rsi)
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+ ret
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+
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+L(less_32bytes):
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+ vmovdqu %xmm0, (%rdi)
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+ vmovdqu %xmm0, -0x10(%rsi)
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+ ret
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+
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+L(less_16bytes):
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+ cmp $8, %dl
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+ jb L(less_8bytes)
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+ vmovq %xmm0, (%rdi)
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+ vmovq %xmm0, -0x08(%rsi)
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+ ret
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+
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+L(less_8bytes):
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+ vmovd %xmm0, %ecx
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+ cmp $4, %dl
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+ jb L(less_4bytes)
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+ mov %ecx, (%rdi)
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+ mov %ecx, -0x04(%rsi)
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+ ret
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+
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+L(less_4bytes):
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+ cmp $2, %dl
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+ jb L(less_2bytes)
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+ mov %cx, (%rdi)
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+ mov %cx, -0x02(%rsi)
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+ ret
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+
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+L(less_2bytes):
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+ cmp $1, %dl
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+ jb L(less_1bytes)
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+ mov %cl, (%rdi)
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+L(less_1bytes):
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+ ret
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+
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+L(512bytesormore):
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+ mov __x86_64_shared_cache_size_half(%rip), %rcx
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+ cmp %rcx, %rdx
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+ ja L(preloop_large)
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+ cmp $1024, %rdx
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+ ja L(1024bytesormore)
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+
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+ vmovups %zmm2, (%rdi)
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+ vmovups %zmm2, 0x40(%rdi)
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+ vmovups %zmm2, 0x80(%rdi)
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+ vmovups %zmm2, 0xC0(%rdi)
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+ vmovups %zmm2, 0x100(%rdi)
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+ vmovups %zmm2, 0x140(%rdi)
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+ vmovups %zmm2, 0x180(%rdi)
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+ vmovups %zmm2, 0x1C0(%rdi)
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+ vmovups %zmm2, -0x200(%rsi)
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+ vmovups %zmm2, -0x1C0(%rsi)
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+ vmovups %zmm2, -0x180(%rsi)
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ce426f |
+ vmovups %zmm2, -0x140(%rsi)
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ce426f |
+ vmovups %zmm2, -0x100(%rsi)
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+ vmovups %zmm2, -0xC0(%rsi)
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ce426f |
+ vmovups %zmm2, -0x80(%rsi)
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+ vmovups %zmm2, -0x40(%rsi)
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+ ret
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+
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+/* Align on 64 and loop with aligned stores. */
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+L(1024bytesormore):
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+ sub $0x100, %rsi
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+ vmovups %zmm2, (%rax)
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+ and $-0x40, %rdi
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+ add $0x40, %rdi
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+
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+L(gobble_256bytes_loop):
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+ vmovaps %zmm2, (%rdi)
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+ vmovaps %zmm2, 0x40(%rdi)
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ce426f |
+ vmovaps %zmm2, 0x80(%rdi)
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ce426f |
+ vmovaps %zmm2, 0xC0(%rdi)
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ce426f |
+ add $0x100, %rdi
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ce426f |
+ cmp %rsi, %rdi
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+ jb L(gobble_256bytes_loop)
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ce426f |
+ vmovups %zmm2, (%rsi)
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ce426f |
+ vmovups %zmm2, 0x40(%rsi)
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ce426f |
+ vmovups %zmm2, 0x80(%rsi)
|
|
|
ce426f |
+ vmovups %zmm2, 0xC0(%rsi)
|
|
|
ce426f |
+ ret
|
|
|
ce426f |
+
|
|
|
ce426f |
+/* Align on 128 and loop with non-temporal stores. */
|
|
|
ce426f |
+L(preloop_large):
|
|
|
ce426f |
+ and $-0x80, %rdi
|
|
|
ce426f |
+ add $0x80, %rdi
|
|
|
ce426f |
+ vmovups %zmm2, (%rax)
|
|
|
ce426f |
+ vmovups %zmm2, 0x40(%rax)
|
|
|
ce426f |
+ sub $0x200, %rsi
|
|
|
ce426f |
+
|
|
|
ce426f |
+L(gobble_512bytes_nt_loop):
|
|
|
ce426f |
+ vmovntdq %zmm2, (%rdi)
|
|
|
ce426f |
+ vmovntdq %zmm2, 0x40(%rdi)
|
|
|
ce426f |
+ vmovntdq %zmm2, 0x80(%rdi)
|
|
|
ce426f |
+ vmovntdq %zmm2, 0xC0(%rdi)
|
|
|
ce426f |
+ vmovntdq %zmm2, 0x100(%rdi)
|
|
|
ce426f |
+ vmovntdq %zmm2, 0x140(%rdi)
|
|
|
ce426f |
+ vmovntdq %zmm2, 0x180(%rdi)
|
|
|
ce426f |
+ vmovntdq %zmm2, 0x1C0(%rdi)
|
|
|
ce426f |
+ add $0x200, %rdi
|
|
|
ce426f |
+ cmp %rsi, %rdi
|
|
|
ce426f |
+ jb L(gobble_512bytes_nt_loop)
|
|
|
ce426f |
+ sfence
|
|
|
ce426f |
+ vmovups %zmm2, (%rsi)
|
|
|
ce426f |
+ vmovups %zmm2, 0x40(%rsi)
|
|
|
ce426f |
+ vmovups %zmm2, 0x80(%rsi)
|
|
|
ce426f |
+ vmovups %zmm2, 0xC0(%rsi)
|
|
|
ce426f |
+ vmovups %zmm2, 0x100(%rsi)
|
|
|
ce426f |
+ vmovups %zmm2, 0x140(%rsi)
|
|
|
ce426f |
+ vmovups %zmm2, 0x180(%rsi)
|
|
|
ce426f |
+ vmovups %zmm2, 0x1C0(%rsi)
|
|
|
ce426f |
+ ret
|
|
|
ce426f |
+END (MEMSET)
|
|
|
ce426f |
+#endif
|
|
|
ce426f |
Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/memset.S
|
|
|
ce426f |
===================================================================
|
|
|
ce426f |
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/memset.S
|
|
|
ce426f |
+++ glibc-2.17-c758a686/sysdeps/x86_64/multiarch/memset.S
|
|
|
ce426f |
@@ -29,6 +29,13 @@ ENTRY(memset)
|
|
|
ce426f |
HAS_ARCH_FEATURE (Prefer_SSE_for_memop)
|
|
|
ce426f |
jz 2f
|
|
|
ce426f |
leaq __memset_sse2(%rip), %rax
|
|
|
ce426f |
+#ifdef HAVE_AVX512_ASM_SUPPORT
|
|
|
ce426f |
+ HAS_ARCH_FEATURE (AVX512F_Usable)
|
|
|
ce426f |
+ jz 2f
|
|
|
ce426f |
+ HAS_ARCH_FEATURE (Prefer_No_VZEROUPPER)
|
|
|
ce426f |
+ jz 2f
|
|
|
ce426f |
+ leaq __memset_avx512_no_vzeroupper(%rip), %rax
|
|
|
ce426f |
+#endif
|
|
|
ce426f |
2: ret
|
|
|
ce426f |
END(memset)
|
|
|
ce426f |
|
|
|
ce426f |
Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/memset_chk.S
|
|
|
ce426f |
===================================================================
|
|
|
ce426f |
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/memset_chk.S
|
|
|
ce426f |
+++ glibc-2.17-c758a686/sysdeps/x86_64/multiarch/memset_chk.S
|
|
|
ce426f |
@@ -30,6 +30,13 @@ ENTRY(__memset_chk)
|
|
|
ce426f |
HAS_ARCH_FEATURE (Prefer_SSE_for_memop)
|
|
|
ce426f |
jz 2f
|
|
|
ce426f |
leaq __memset_chk_sse2(%rip), %rax
|
|
|
ce426f |
+#ifdef HAVE_AVX512_ASM_SUPPORT
|
|
|
ce426f |
+ HAS_ARCH_FEATURE (AVX512F_Usable)
|
|
|
ce426f |
+ jz 2f
|
|
|
ce426f |
+ HAS_ARCH_FEATURE (Prefer_No_VZEROUPPER)
|
|
|
ce426f |
+ jz 2f
|
|
|
ce426f |
+ leaq __memset_chk_avx512_no_vzeroupper(%rip), %rax
|
|
|
ce426f |
+#endif
|
|
|
ce426f |
2: ret
|
|
|
ce426f |
END(__memset_chk)
|
|
|
ce426f |
|