diff --git a/.binutils.metadata b/.binutils.metadata index 7d18766..56f721c 100644 --- a/.binutils.metadata +++ b/.binutils.metadata @@ -1 +1,2 @@ 6e472ddae565a2b1447e6f2393809bb8799982cf SOURCES/binutils-2.27.tar.bz2 +d3e5c9fc829ed40648110da6fe46c2fb1ed8aadb SOURCES/standards.info.gz diff --git a/.gitignore b/.gitignore index 1dc826f..69ceadb 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,2 @@ SOURCES/binutils-2.27.tar.bz2 +SOURCES/standards.info.gz diff --git a/SOURCES/binutils-2.22.52.0.1-relro-on-by-default.patch b/SOURCES/binutils-2.22.52.0.1-relro-on-by-default.patch deleted file mode 100644 index 8d9b6c1..0000000 --- a/SOURCES/binutils-2.22.52.0.1-relro-on-by-default.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- binutils-2.27.orig/ld/configure.tgt 2016-07-07 11:16:49.967963649 +0100 -+++ binutils-2.27/ld/configure.tgt 2016-07-07 11:17:02.252045673 +0100 -@@ -901,8 +901,8 @@ frv-*-* | hppa*-*-* | ia64-*-* | mips*-* - # FAIL: objcopy -shared -z relro (tbss2) - # FAIL: objcopy -shared -z relro (tbss3) - ;; --*-*-linux*) -- if test ${ac_default_ld_z_relro} = unset; then -+*) -+ if test x${ac_default_ld_z_relro} = xunset; then - ac_default_ld_z_relro=1 - fi - ;; diff --git a/SOURCES/binutils-2.27-ARMv8.2.patch b/SOURCES/binutils-2.27-ARMv8.2.patch new file mode 100644 index 0000000..63a54eb --- /dev/null +++ b/SOURCES/binutils-2.27-ARMv8.2.patch @@ -0,0 +1,3590 @@ +diff -rup binutils.orig/gas/config/tc-arm.c binutils-2.27/gas/config/tc-arm.c +--- binutils.orig/gas/config/tc-arm.c 2017-08-09 10:26:30.032741952 +0100 ++++ binutils-2.27/gas/config/tc-arm.c 2017-08-09 11:17:17.747598541 +0100 +@@ -147,8 +147,10 @@ static const arm_feature_set *legacy_cpu + static const arm_feature_set *legacy_fpu = NULL; + + static const arm_feature_set *mcpu_cpu_opt = NULL; ++static arm_feature_set *dyn_mcpu_ext_opt = NULL; + static const arm_feature_set *mcpu_fpu_opt = NULL; + static const arm_feature_set *march_cpu_opt = NULL; ++static arm_feature_set *dyn_march_ext_opt = NULL; + static const arm_feature_set *march_fpu_opt = NULL; + static const arm_feature_set *mfpu_opt = NULL; + static const arm_feature_set *object_arch = NULL; +@@ -187,7 +189,6 @@ static const arm_feature_set arm_ext_v5j + static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6); + static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K); + static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2); +-static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M); + static const arm_feature_set arm_ext_v6_notm = + ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM); + static const arm_feature_set arm_ext_v6_dsp = +@@ -201,11 +202,11 @@ static const arm_feature_set arm_ext_v7 + static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A); + static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R); + #ifdef OBJ_ELF +-static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M); ++static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M); + #endif + static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8); + static const arm_feature_set arm_ext_m = +- ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, ++ ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M, + ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN); + static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP); + static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC); +@@ -234,14 +235,16 @@ static const arm_feature_set arm_ext_ras + /* FP16 instructions. */ + static const arm_feature_set arm_ext_fp16 = + ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); ++static const arm_feature_set arm_ext_v8_3 = ++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A); + + static const arm_feature_set arm_arch_any = ARM_ANY; ++#ifdef OBJ_ELF ++static const arm_feature_set fpu_any = FPU_ANY; ++#endif + static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1); + static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; + static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; +-#ifdef OBJ_ELF +-static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; +-#endif + + static const arm_feature_set arm_cext_iwmmxt2 = + ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2); +@@ -291,6 +294,8 @@ static const arm_feature_set crc_ext_arm + ARM_FEATURE_COPROC (CRC_EXT_ARMV8); + static const arm_feature_set fpu_neon_ext_v8_1 = + ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA); ++static const arm_feature_set fpu_neon_ext_dotprod = ++ ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD); + + static int mfloat_abi_opt = -1; + /* Record user cpu selection for object attributes. */ +@@ -685,9 +690,11 @@ struct asm_opcode + #define T2_SUBS_PC_LR 0xf3de8f00 + + #define DATA_OP_SHIFT 21 ++#define SBIT_SHIFT 20 + + #define T2_OPCODE_MASK 0xfe1fffff + #define T2_DATA_OP_SHIFT 21 ++#define T2_SBIT_SHIFT 20 + + #define A_COND_MASK 0xf0000000 + #define A_PUSH_POP_OP_MASK 0x0fff0000 +@@ -1276,6 +1283,7 @@ arm_reg_alt_syntax (char **ccp, char *st + if (*ccp != start && processor <= 15) + return processor; + } ++ /* Fall through. */ + + case REG_TYPE_MMXWC: + /* WC includes WCG. ??? I'm not sure this is true for all +@@ -2705,7 +2713,7 @@ mapping_state (enum mstate state) + + Some Thumb instructions are alignment-sensitive modulo 4 bytes, + but themselves require 2-byte alignment; this applies to some +- PC- relative forms. However, these cases will invovle implicit ++ PC- relative forms. However, these cases will involve implicit + literal pool generation or an explicit .align >=2, both of + which will cause the section to me marked with sufficient + alignment. Thus, we don't handle those cases here. */ +@@ -3042,7 +3050,7 @@ s_ccs_ref (int unused ATTRIBUTE_UNUSED) + } + + /* If name is not NULL, then it is used for marking the beginning of a +- function, wherease if it is NULL then it means the function end. */ ++ function, whereas if it is NULL then it means the function end. */ + static void + asmfunc_debug (const char * name) + { +@@ -3375,7 +3383,7 @@ tc_start_label_without_colon (void) + } + + /* Can't use symbol_new here, so have to create a symbol and then at +- a later date assign it a value. Thats what these functions do. */ ++ a later date assign it a value. That's what these functions do. */ + + static void + symbol_locate (symbolS * symbolP, +@@ -4964,9 +4972,13 @@ parse_ifimm_zero (char **in) + int error_code; + + if (!is_immediate_prefix (**in)) +- return FALSE; +- +- ++*in; ++ { ++ /* In unified syntax, all prefixes are optional. */ ++ if (!unified_syntax) ++ return FALSE; ++ } ++ else ++ ++*in; + + /* Accept #0x0 as a synonym for #0. */ + if (strncmp (*in, "0x", 2) == 0) +@@ -6530,6 +6542,8 @@ enum operand_parse_code + OP_EXPi, /* same, with optional immediate prefix */ + OP_EXPr, /* same, with optional relocation suffix */ + OP_HALF, /* 0 .. 65535 or low/high reloc. */ ++ OP_IROT1, /* VCADD rotate immediate: 90, 270. */ ++ OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */ + + OP_CPSF, /* CPS flags */ + OP_ENDI, /* Endianness specifier */ +@@ -6541,7 +6555,7 @@ enum operand_parse_code + OP_APSR_RR, /* ARM register or "APSR_nzcv". */ + + OP_RRnpc_I0, /* ARM register or literal 0 */ +- OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ ++ OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */ + OP_RR_EXi, /* ARM register or expression with imm prefix */ + OP_RF_IF, /* FPA register or immediate */ + OP_RIWR_RIWC, /* iWMMXt R or C reg */ +@@ -7178,8 +7192,14 @@ parse_operands (char *str, const unsigne + { + if (inst.operands[i].reg == REG_PC) + inst.error = BAD_PC; +- else if (inst.operands[i].reg == REG_SP) +- inst.error = BAD_SP; ++ else if (inst.operands[i].reg == REG_SP ++ /* The restriction on Rd/Rt/Rt2 on Thumb mode has been ++ relaxed since ARMv8-A. */ ++ && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) ++ { ++ gas_assert (thumb); ++ inst.error = BAD_SP; ++ } + } + break; + +@@ -7277,14 +7297,23 @@ parse_operands (char *str, const unsigne + + /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 + instructions are unpredictable if these registers are used. This +- is the BadReg predicate in ARM's Thumb-2 documentation. */ +-#define reject_bad_reg(reg) \ +- do \ +- if (reg == REG_SP || reg == REG_PC) \ +- { \ +- inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ +- return; \ +- } \ ++ is the BadReg predicate in ARM's Thumb-2 documentation. ++ ++ Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few ++ places, while the restriction on REG_SP was relaxed since ARMv8-A. */ ++#define reject_bad_reg(reg) \ ++ do \ ++ if (reg == REG_PC) \ ++ { \ ++ inst.error = BAD_PC; \ ++ return; \ ++ } \ ++ else if (reg == REG_SP \ ++ && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \ ++ { \ ++ inst.error = BAD_SP; \ ++ return; \ ++ } \ + while (0) + + /* If REG is R13 (the stack pointer), warn that its use is +@@ -7303,7 +7332,7 @@ parse_operands (char *str, const unsigne + + The only binary encoding difference is the Coprocessor number. Coprocessor + 9 is used for half-precision calculations or conversions. The format of the +- instruction is the same as the equivalent Coprocessor 10 instuction that ++ instruction is the same as the equivalent Coprocessor 10 instruction that + exists for Single-Precision operation. */ + + static void +@@ -7426,6 +7455,24 @@ encode_arm_vfp_reg (int reg, enum vfp_re + static void + encode_arm_shift (int i) + { ++ /* Register-shifted register. */ ++ if (inst.operands[i].immisreg) ++ { ++ int op_index; ++ for (op_index = 0; op_index <= i; ++op_index) ++ { ++ /* Check the operand only when it's presented. In pre-UAL syntax, ++ if the destination register is the same as the first operand, two ++ register form of the instruction can be used. */ ++ if (inst.operands[op_index].present && inst.operands[op_index].isreg ++ && inst.operands[op_index].reg == REG_PC) ++ as_warn (UNPRED_REG ("r15")); ++ } ++ ++ if (inst.operands[i].imm == REG_PC) ++ as_warn (UNPRED_REG ("r15")); ++ } ++ + if (inst.operands[i].shift_kind == SHIFT_RRX) + inst.instruction |= SHIFT_ROR << 5; + else +@@ -7930,17 +7977,13 @@ move_or_literal_pool (int i, enum lit_ty + { + if (thumb_p) + { +- /* This can be encoded only for a low register. */ +- if ((v & ~0xFF) == 0 && (inst.operands[i].reg < 8)) +- { +- /* This can be done with a mov(1) instruction. */ +- inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); +- inst.instruction |= v; +- return TRUE; +- } ++ /* LDR should not use lead in a flag-setting instruction being ++ chosen so we do not check whether movs can be used. */ + +- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) ++ if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) + || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) ++ && inst.operands[i].reg != 13 ++ && inst.operands[i].reg != 15) + { + /* Check if on thumb2 it can be done with a mov.w, mvn or + movw instruction. */ +@@ -8326,6 +8369,12 @@ do_adr (void) + inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; + inst.reloc.pc_rel = 1; + inst.reloc.exp.X_add_number -= 8; ++ ++ if (inst.reloc.exp.X_op == O_symbol ++ && inst.reloc.exp.X_add_symbol != NULL ++ && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) ++ && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) ++ inst.reloc.exp.X_add_number += 1; + } + + /* This is a pseudo-op of the form "adrl rd, label" to be converted +@@ -8344,6 +8393,12 @@ do_adrl (void) + inst.reloc.pc_rel = 1; + inst.size = INSN_SIZE * 2; + inst.reloc.exp.X_add_number -= 8; ++ ++ if (inst.reloc.exp.X_op == O_symbol ++ && inst.reloc.exp.X_add_symbol != NULL ++ && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) ++ && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) ++ inst.reloc.exp.X_add_number += 1; + } + + static void +@@ -8622,7 +8677,7 @@ do_co_reg (void) + || inst.instruction == 0xfe000010) + /* MCR, MCR2 */ + reject_bad_reg (Rd); +- else ++ else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) + /* MRC, MRC2 */ + constraint (Rd == REG_SP, BAD_SP); + } +@@ -8691,6 +8746,14 @@ do_co_reg2c (void) + constraint (Rn == REG_PC, BAD_PC); + } + ++ /* Only check the MRRC{2} variants. */ ++ if ((inst.instruction & 0x0FF00000) == 0x0C500000) ++ { ++ /* If Rd == Rn, error that the operation is ++ unpredictable (example MRRC p3,#1,r1,r1,c4). */ ++ constraint (Rd == Rn, BAD_OVERLAP); ++ } ++ + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].imm << 4; + inst.instruction |= Rd << 12; +@@ -8916,7 +8979,7 @@ check_ldr_r15_aligned (void) + && (inst.operands[0].reg == REG_PC + && inst.operands[1].reg == REG_PC + && (inst.reloc.exp.X_add_number & 0x3)), +- _("ldr to register 15 must be 4-byte alligned")); ++ _("ldr to register 15 must be 4-byte aligned")); + } + + static void +@@ -9025,9 +9088,9 @@ do_mov16 (void) + + top = (inst.instruction & 0x00400000) != 0; + constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, +- _(":lower16: not allowed this instruction")); ++ _(":lower16: not allowed in this instruction")); + constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, +- _(":upper16: not allowed instruction")); ++ _(":upper16: not allowed in this instruction")); + inst.instruction |= inst.operands[0].reg << 12; + if (inst.reloc.type == BFD_RELOC_UNUSED) + { +@@ -9079,6 +9142,11 @@ do_vmrs (void) + return; + } + ++ /* MVFR2 is only valid at ARMv8-A. */ ++ if (inst.operands[1].reg == 5) ++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), ++ _(BAD_FPU)); ++ + /* APSR_ sets isvec. All other refs to PC are illegal. */ + if (!inst.operands[0].isvec && Rt == REG_PC) + { +@@ -9105,6 +9173,11 @@ do_vmsr (void) + return; + } + ++ /* MVFR2 is only valid for ARMv8-A. */ ++ if (inst.operands[0].reg == 5) ++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), ++ _(BAD_FPU)); ++ + /* If we get through parsing the register name, we just insert the number + generated into the instruction without further validation. */ + inst.instruction |= (inst.operands[0].reg << 16); +@@ -10453,7 +10526,7 @@ do_t_add_sub_w (void) + } + + /* Parse an add or subtract instruction. We get here with inst.instruction +- equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ ++ equaling any of THUMB_OPCODE_add, adds, sub, or subs. */ + + static void + do_t_add_sub (void) +@@ -10484,7 +10557,8 @@ do_t_add_sub (void) + { + int add; + +- constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); ++ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) ++ constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); + + add = (inst.instruction == T_MNEM_add + || inst.instruction == T_MNEM_adds); +@@ -10608,7 +10682,8 @@ do_t_add_sub (void) + } + + constraint (Rd == REG_PC, BAD_PC); +- constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); ++ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) ++ constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); + constraint (Rs == REG_PC, BAD_PC); + reject_bad_reg (Rn); + +@@ -10701,9 +10776,14 @@ do_t_adr (void) + inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; + inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ + inst.reloc.pc_rel = 1; +- + inst.instruction |= Rd << 4; + } ++ ++ if (inst.reloc.exp.X_op == O_symbol ++ && inst.reloc.exp.X_add_symbol != NULL ++ && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) ++ && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) ++ inst.reloc.exp.X_add_number += 1; + } + + /* Arithmetic instructions for which there is just one 16-bit +@@ -11856,7 +11936,8 @@ do_t_mov_cmp (void) + /* This is mov.w. */ + constraint (Rn == REG_PC, BAD_PC); + constraint (Rm == REG_PC, BAD_PC); +- constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); ++ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) ++ constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); + } + } + else +@@ -12082,12 +12163,12 @@ do_t_mov16 (void) + top = (inst.instruction & 0x00800000) != 0; + if (inst.reloc.type == BFD_RELOC_ARM_MOVW) + { +- constraint (top, _(":lower16: not allowed this instruction")); ++ constraint (top, _(":lower16: not allowed in this instruction")); + inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; + } + else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) + { +- constraint (!top, _(":upper16: not allowed this instruction")); ++ constraint (!top, _(":upper16: not allowed in this instruction")); + inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; + } + +@@ -13049,17 +13130,6 @@ do_t_sxth (void) + static void + do_t_swi (void) + { +- /* We have to do the following check manually as ARM_EXT_OS only applies +- to ARM_EXT_V6M. */ +- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) +- { +- if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) +- /* This only applies to the v6m howver, not later architectures. */ +- && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) +- as_bad (_("SVC is not permitted on this architecture")); +- ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); +- } +- + inst.reloc.type = BFD_RELOC_ARM_SWI; + } + +@@ -13077,7 +13147,8 @@ do_t_tb (void) + Rn = inst.operands[0].reg; + Rm = inst.operands[0].imm; + +- constraint (Rn == REG_SP, BAD_SP); ++ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) ++ constraint (Rn == REG_SP, BAD_SP); + reject_bad_reg (Rm); + + constraint (!half && inst.operands[0].shifted, +@@ -13317,6 +13388,8 @@ NEON_ENC_TAB + X(3, (D, Q, S), MIXED), \ + X(4, (D, D, D, I), DOUBLE), \ + X(4, (Q, Q, Q, I), QUAD), \ ++ X(4, (D, D, S, I), DOUBLE), \ ++ X(4, (Q, Q, S, I), QUAD), \ + X(2, (F, F), SINGLE), \ + X(3, (F, F, F), SINGLE), \ + X(2, (F, I), SINGLE), \ +@@ -14390,6 +14463,11 @@ static void + do_vfp_nsyn_push (void) + { + nsyn_insert_sp (); ++ ++ constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, ++ _("register list must contain at least 1 and at most 16 " ++ "registers")); ++ + if (inst.operands[1].issingle) + do_vfp_nsyn_opcode ("fstmdbs"); + else +@@ -14400,6 +14478,11 @@ static void + do_vfp_nsyn_pop (void) + { + nsyn_insert_sp (); ++ ++ constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, ++ _("register list must contain at least 1 and at most 16 " ++ "registers")); ++ + if (inst.operands[1].issingle) + do_vfp_nsyn_opcode ("fldmias"); + else +@@ -14952,7 +15035,14 @@ do_neon_ceq (void) + scalars, which are encoded in 5 bits, M : Rm. + For 16-bit scalars, the register is encoded in Rm[2:0] and the index in + M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the +- index in M. */ ++ index in M. ++ ++ Dot Product instructions are similar to multiply instructions except elsize ++ should always be 32. ++ ++ This function translates SCALAR, which is GAS's internal encoding of indexed ++ scalar register, to raw encoding. There is also register and index range ++ check based on ELSIZE. */ + + static unsigned + neon_scalar_for_mul (unsigned scalar, unsigned elsize) +@@ -17220,6 +17310,153 @@ do_vrintm (void) + do_vrint_1 (neon_cvt_mode_m); + } + ++static unsigned ++neon_scalar_for_vcmla (unsigned opnd, unsigned elsize) ++{ ++ unsigned regno = NEON_SCALAR_REG (opnd); ++ unsigned elno = NEON_SCALAR_INDEX (opnd); ++ ++ if (elsize == 16 && elno < 2 && regno < 16) ++ return regno | (elno << 4); ++ else if (elsize == 32 && elno == 0) ++ return regno; ++ ++ first_error (_("scalar out of range")); ++ return 0; ++} ++ ++static void ++do_vcmla (void) ++{ ++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), ++ _(BAD_FPU)); ++ constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex")); ++ unsigned rot = inst.reloc.exp.X_add_number; ++ constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, ++ _("immediate out of range")); ++ rot /= 90; ++ if (inst.operands[2].isscalar) ++ { ++ enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL); ++ unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, ++ N_KEY | N_F16 | N_F32).size; ++ unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size); ++ inst.is_neon = 1; ++ inst.instruction = 0xfe000800; ++ inst.instruction |= LOW4 (inst.operands[0].reg) << 12; ++ inst.instruction |= HI1 (inst.operands[0].reg) << 22; ++ inst.instruction |= LOW4 (inst.operands[1].reg) << 16; ++ inst.instruction |= HI1 (inst.operands[1].reg) << 7; ++ inst.instruction |= LOW4 (m); ++ inst.instruction |= HI1 (m) << 5; ++ inst.instruction |= neon_quad (rs) << 6; ++ inst.instruction |= rot << 20; ++ inst.instruction |= (size == 32) << 23; ++ } ++ else ++ { ++ enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); ++ unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, ++ N_KEY | N_F16 | N_F32).size; ++ neon_three_same (neon_quad (rs), 0, -1); ++ inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ ++ inst.instruction |= 0xfc200800; ++ inst.instruction |= rot << 23; ++ inst.instruction |= (size == 32) << 20; ++ } ++} ++ ++static void ++do_vcadd (void) ++{ ++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), ++ _(BAD_FPU)); ++ constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex")); ++ unsigned rot = inst.reloc.exp.X_add_number; ++ constraint (rot != 90 && rot != 270, _("immediate out of range")); ++ enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); ++ unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, ++ N_KEY | N_F16 | N_F32).size; ++ neon_three_same (neon_quad (rs), 0, -1); ++ inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ ++ inst.instruction |= 0xfc800800; ++ inst.instruction |= (rot == 270) << 24; ++ inst.instruction |= (size == 32) << 20; ++} ++ ++/* Dot Product instructions encoding support. */ ++ ++static void ++do_neon_dotproduct (int unsigned_p) ++{ ++ enum neon_shape rs; ++ unsigned scalar_oprd2 = 0; ++ int high8; ++ ++ if (inst.cond != COND_ALWAYS) ++ as_warn (_("Dot Product instructions cannot be conditional, the behaviour " ++ "is UNPREDICTABLE")); ++ ++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), ++ _(BAD_FPU)); ++ ++ /* Dot Product instructions are in three-same D/Q register format or the third ++ operand can be a scalar index register. */ ++ if (inst.operands[2].isscalar) ++ { ++ scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32); ++ high8 = 0xfe000000; ++ rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); ++ } ++ else ++ { ++ high8 = 0xfc000000; ++ rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); ++ } ++ ++ if (unsigned_p) ++ neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8); ++ else ++ neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8); ++ ++ /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot ++ Product instruction, so we pass 0 as the "ubit" parameter. And the ++ "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */ ++ neon_three_same (neon_quad (rs), 0, 32); ++ ++ /* Undo neon_dp_fixup. Dot Product instructions are using a slightly ++ different NEON three-same encoding. */ ++ inst.instruction &= 0x00ffffff; ++ inst.instruction |= high8; ++ /* Encode 'U' bit which indicates signedness. */ ++ inst.instruction |= (unsigned_p ? 1 : 0) << 4; ++ /* Re-encode operand2 if it's indexed scalar operand. What has been encoded ++ from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not ++ the instruction encoding. */ ++ if (inst.operands[2].isscalar) ++ { ++ inst.instruction &= 0xffffffd0; ++ inst.instruction |= LOW4 (scalar_oprd2); ++ inst.instruction |= HI1 (scalar_oprd2) << 5; ++ } ++} ++ ++/* Dot Product instructions for signed integer. */ ++ ++static void ++do_neon_dotproduct_s (void) ++{ ++ return do_neon_dotproduct (0); ++} ++ ++/* Dot Product instructions for unsigned integer. */ ++ ++static void ++do_neon_dotproduct_u (void) ++{ ++ return do_neon_dotproduct (1); ++} ++ + /* Crypto v1 instructions. */ + static void + do_crypto_2op_1 (unsigned elttype, int op) +@@ -17401,6 +17638,16 @@ do_crc32cw (void) + do_crc32_1 (1, 2); + } + ++static void ++do_vjcvt (void) ++{ ++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), ++ _(BAD_FPU)); ++ neon_check_type (2, NS_FD, N_S32, N_F64); ++ do_vfp_sp_dp_cvt (); ++ do_vfp_cond_or_thumb (); ++} ++ + + /* Overall per-instruction processing. */ + +@@ -17755,7 +18002,7 @@ opcode_lookup (char **str) + case OT_odd_infix_unc: + if (!unified_syntax) + return 0; +- /* else fall through */ ++ /* Fall through. */ + + case OT_csuffix: + case OT_csuffixF: +@@ -17878,7 +18125,7 @@ now_it_add_mask (int cond) + set_it_insn_type_last () ditto + in_it_block () ditto + it_fsm_post_encode () from md_assemble () +- force_automatic_it_block_close () from label habdling functions ++ force_automatic_it_block_close () from label handling functions + + Rationale: + 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), +@@ -17911,7 +18158,7 @@ now_it_add_mask (int cond) + for covering other cases. + + Calling handle_it_state () may not transition the IT block state to +- OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be ++ OUTSIDE_IT_BLOCK immediately, since the (current) state could be + still queried. Instead, if the FSM determines that the state should + be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed + after the tencode () function: that's what it_fsm_post_encode () does. +@@ -18002,7 +18249,7 @@ handle_it_state (void) + switch (inst.it_insn_type) + { + case OUTSIDE_IT_INSN: +- /* The closure of the block shall happen immediatelly, ++ /* The closure of the block shall happen immediately, + so any in_it_block () call reports the block as closed. */ + force_automatic_it_block_close (); + break; +@@ -18236,6 +18483,13 @@ t32_insn_ok (arm_feature_set arch, const + && opcode->tencode == do_t_branch) + return TRUE; + ++ /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */ ++ if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) ++ && opcode->tencode == do_t_mov_cmp ++ /* Make sure CMP instruction is not affected. */ ++ && opcode->aencode == do_mov) ++ return TRUE; ++ + /* Wide instruction variants of all instructions with narrow *and* wide + variants become available with ARMv6t2. Other opcodes are either + narrow-only or wide-only and are thus available if OPCODE is valid. */ +@@ -18296,7 +18550,10 @@ md_assemble (char *str) + || (thumb_mode == 1 + && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) + { +- as_bad (_("selected processor does not support `%s' in Thumb mode"), str); ++ if (opcode->tencode == do_t_swi) ++ as_bad (_("SVC is not permitted on this architecture")); ++ else ++ as_bad (_("selected processor does not support `%s' in Thumb mode"), str); + return; + } + if (inst.cond != COND_ALWAYS && !unified_syntax +@@ -18663,6 +18920,7 @@ static const struct reg_entry reg_names[ + REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), + REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), + REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), ++ REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC), + + /* Maverick DSP coprocessor registers. */ + REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), +@@ -18780,24 +19038,32 @@ static const struct asm_psr psrs[] = + /* Table of V7M psr names. */ + static const struct asm_psr v7m_psrs[] = + { +- {"apsr", 0 }, {"APSR", 0 }, +- {"iapsr", 1 }, {"IAPSR", 1 }, +- {"eapsr", 2 }, {"EAPSR", 2 }, +- {"psr", 3 }, {"PSR", 3 }, +- {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, +- {"ipsr", 5 }, {"IPSR", 5 }, +- {"epsr", 6 }, {"EPSR", 6 }, +- {"iepsr", 7 }, {"IEPSR", 7 }, +- {"msp", 8 }, {"MSP", 8 }, {"msp_s", 8 }, {"MSP_S", 8 }, +- {"psp", 9 }, {"PSP", 9 }, {"psp_s", 9 }, {"PSP_S", 9 }, +- {"primask", 16}, {"PRIMASK", 16}, +- {"basepri", 17}, {"BASEPRI", 17}, +- {"basepri_max", 18}, {"BASEPRI_MAX", 18}, +- {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ +- {"faultmask", 19}, {"FAULTMASK", 19}, +- {"control", 20}, {"CONTROL", 20}, +- {"msp_ns", 0x88}, {"MSP_NS", 0x88}, +- {"psp_ns", 0x89}, {"PSP_NS", 0x89} ++ {"apsr", 0x0 }, {"APSR", 0x0 }, ++ {"iapsr", 0x1 }, {"IAPSR", 0x1 }, ++ {"eapsr", 0x2 }, {"EAPSR", 0x2 }, ++ {"psr", 0x3 }, {"PSR", 0x3 }, ++ {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 }, ++ {"ipsr", 0x5 }, {"IPSR", 0x5 }, ++ {"epsr", 0x6 }, {"EPSR", 0x6 }, ++ {"iepsr", 0x7 }, {"IEPSR", 0x7 }, ++ {"msp", 0x8 }, {"MSP", 0x8 }, ++ {"psp", 0x9 }, {"PSP", 0x9 }, ++ {"msplim", 0xa }, {"MSPLIM", 0xa }, ++ {"psplim", 0xb }, {"PSPLIM", 0xb }, ++ {"primask", 0x10}, {"PRIMASK", 0x10}, ++ {"basepri", 0x11}, {"BASEPRI", 0x11}, ++ {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12}, ++ {"faultmask", 0x13}, {"FAULTMASK", 0x13}, ++ {"control", 0x14}, {"CONTROL", 0x14}, ++ {"msp_ns", 0x88}, {"MSP_NS", 0x88}, ++ {"psp_ns", 0x89}, {"PSP_NS", 0x89}, ++ {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a}, ++ {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b}, ++ {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90}, ++ {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91}, ++ {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93}, ++ {"control_ns", 0x94}, {"CONTROL_NS", 0x94}, ++ {"sp_ns", 0x98}, {"SP_NS", 0x98 } + }; + + /* Table of all shift-in-operand names. */ +@@ -19112,8 +19378,6 @@ static const struct asm_opcode insns[] = + tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), + tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), + +- TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), +- TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), + tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), + TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), + +@@ -19142,6 +19406,12 @@ static const struct asm_opcode insns[] = + TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), + + #undef THUMB_VARIANT ++#define THUMB_VARIANT & arm_ext_os ++ ++ TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), ++ TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), ++ ++#undef THUMB_VARIANT + #define THUMB_VARIANT & arm_ext_v6 + + TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), +@@ -19729,6 +19999,21 @@ static const struct asm_opcode insns[] = + TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs), + + #undef ARM_VARIANT ++#define ARM_VARIANT & arm_ext_v8_3 ++#undef THUMB_VARIANT ++#define THUMB_VARIANT & arm_ext_v8_3 ++ NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt), ++ NUF (vcmla, 0, 4, (RNDQ, RNDQ, RNDQ_RNSC, EXPi), vcmla), ++ NUF (vcadd, 0, 4, (RNDQ, RNDQ, RNDQ, EXPi), vcadd), ++ ++#undef ARM_VARIANT ++#define ARM_VARIANT & fpu_neon_ext_dotprod ++#undef THUMB_VARIANT ++#define THUMB_VARIANT & fpu_neon_ext_dotprod ++ NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s), ++ NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u), ++ ++#undef ARM_VARIANT + #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ + #undef THUMB_VARIANT + #define THUMB_VARIANT NULL +@@ -21706,7 +21991,7 @@ arm_frag_align_code (int n, int max) + Note - despite the name this initialisation is not done when the frag + is created, but only when its type is assigned. A frag can be created + and used a long time before its type is set, so beware of assuming that +- this initialisationis performed first. */ ++ this initialisation is performed first. */ + + #ifndef OBJ_ELF + void +@@ -21720,7 +22005,7 @@ arm_init_frag (fragS * fragP, int max_ch + void + arm_init_frag (fragS * fragP, int max_chars) + { +- int frag_thumb_mode; ++ bfd_boolean frag_thumb_mode; + + /* If the current ARM vs THUMB mode has not already + been recorded into this frag then do so now. */ +@@ -22731,6 +23016,23 @@ md_apply_fix (fixS * fixP, + changing the opcode. */ + if (newimm == (unsigned int) FAIL) + newimm = negate_data_op (&temp, value); ++ /* MOV accepts both ARM modified immediate (A1 encoding) and ++ UINT16 (A2 encoding) when possible, MOVW only accepts UINT16. ++ When disassembling, MOV is preferred when there is no encoding ++ overlap. */ ++ if (newimm == (unsigned int) FAIL ++ && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV ++ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) ++ && !((temp >> SBIT_SHIFT) & 0x1) ++ && value >= 0 && value <= 0xffff) ++ { ++ /* Clear bits[23:20] to change encoding from A1 to A2. */ ++ temp &= 0xff0fffff; ++ /* Encoding high 4bits imm. Code below will encode the remaining ++ low 12bits. */ ++ temp |= (value & 0x0000f000) << 4; ++ newimm = value & 0x00000fff; ++ } + } + + if (newimm == (unsigned int) FAIL) +@@ -22816,6 +23118,7 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_ARM_OFFSET_IMM: + if (!fixP->fx_done && seg->use_rela_p) + value = 0; ++ /* Fall through. */ + + case BFD_RELOC_ARM_LITERAL: + sign = value > 0; +@@ -23046,32 +23349,59 @@ md_apply_fix (fixS * fixP, + newval |= md_chars_to_number (buf+2, THUMB_SIZE); + + newimm = FAIL; +- if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE ++ if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE ++ /* ARMv8-M Baseline MOV will reach here, but it doesn't support ++ Thumb2 modified immediate encoding (T2). */ ++ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) + || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) + { + newimm = encode_thumb32_immediate (value); + if (newimm == (unsigned int) FAIL) + newimm = thumb32_negate_data_op (&newval, value); + } +- if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE +- && newimm == (unsigned int) FAIL) ++ if (newimm == (unsigned int) FAIL) + { +- /* Turn add/sum into addw/subw. */ +- if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) +- newval = (newval & 0xfeffffff) | 0x02000000; +- /* No flat 12-bit imm encoding for addsw/subsw. */ +- if ((newval & 0x00100000) == 0) ++ if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE) + { +- /* 12 bit immediate for addw/subw. */ +- if (value < 0) ++ /* Turn add/sum into addw/subw. */ ++ if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) ++ newval = (newval & 0xfeffffff) | 0x02000000; ++ /* No flat 12-bit imm encoding for addsw/subsw. */ ++ if ((newval & 0x00100000) == 0) + { +- value = -value; +- newval ^= 0x00a00000; ++ /* 12 bit immediate for addw/subw. */ ++ if (value < 0) ++ { ++ value = -value; ++ newval ^= 0x00a00000; ++ } ++ if (value > 0xfff) ++ newimm = (unsigned int) FAIL; ++ else ++ newimm = value; ++ } ++ } ++ else ++ { ++ /* MOV accepts both Thumb2 modified immediate (T2 encoding) and ++ UINT16 (T3 encoding), MOVW only accepts UINT16. When ++ disassembling, MOV is preferred when there is no encoding ++ overlap. ++ NOTE: MOV is using ORR opcode under Thumb 2 mode. */ ++ if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR ++ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m) ++ && !((newval >> T2_SBIT_SHIFT) & 0x1) ++ && value >= 0 && value <=0xffff) ++ { ++ /* Toggle bit[25] to change encoding from T2 to T3. */ ++ newval ^= 1 << 25; ++ /* Clear bits[19:16]. */ ++ newval &= 0xfff0ffff; ++ /* Encoding high 4bits imm. Code below will encode the ++ remaining low 12bits. */ ++ newval |= (value & 0x0000f000) << 4; ++ newimm = value & 0x00000fff; + } +- if (value > 0xfff) +- newimm = (unsigned int) FAIL; +- else +- newimm = value; + } + } + +@@ -23174,6 +23504,7 @@ md_apply_fix (fixS * fixP, + newval = md_chars_to_number (buf, INSN_SIZE); + fixP->fx_done = 0; + } ++ /* Fall through. */ + + case BFD_RELOC_ARM_PLT32: + #endif +@@ -23210,7 +23541,7 @@ md_apply_fix (fixS * fixP, + /* We are going to store value (shifted right by two) in the + instruction, in a 24 bit, signed field. Bits 26 through 32 either + all clear or all set and bit 0 must be clear. For B/BL bit 1 must +- also be be clear. */ ++ also be clear. */ + if (value & temp) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("misaligned branch destination")); +@@ -24066,6 +24397,7 @@ tc_gen_reloc (asection *section, fixS *f + code = BFD_RELOC_8_PCREL; + break; + } ++ /* Fall through. */ + + case BFD_RELOC_16: + if (fixp->fx_pcrel) +@@ -24073,6 +24405,7 @@ tc_gen_reloc (asection *section, fixS *f + code = BFD_RELOC_16_PCREL; + break; + } ++ /* Fall through. */ + + case BFD_RELOC_32: + if (fixp->fx_pcrel) +@@ -24080,6 +24413,7 @@ tc_gen_reloc (asection *section, fixS *f + code = BFD_RELOC_32_PCREL; + break; + } ++ /* Fall through. */ + + case BFD_RELOC_ARM_MOVW: + if (fixp->fx_pcrel) +@@ -24087,6 +24421,7 @@ tc_gen_reloc (asection *section, fixS *f + code = BFD_RELOC_ARM_MOVW_PCREL; + break; + } ++ /* Fall through. */ + + case BFD_RELOC_ARM_MOVT: + if (fixp->fx_pcrel) +@@ -24094,6 +24429,7 @@ tc_gen_reloc (asection *section, fixS *f + code = BFD_RELOC_ARM_MOVT_PCREL; + break; + } ++ /* Fall through. */ + + case BFD_RELOC_ARM_THUMB_MOVW: + if (fixp->fx_pcrel) +@@ -24101,6 +24437,7 @@ tc_gen_reloc (asection *section, fixS *f + code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; + break; + } ++ /* Fall through. */ + + case BFD_RELOC_ARM_THUMB_MOVT: + if (fixp->fx_pcrel) +@@ -24108,6 +24445,7 @@ tc_gen_reloc (asection *section, fixS *f + code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; + break; + } ++ /* Fall through. */ + + case BFD_RELOC_NONE: + case BFD_RELOC_ARM_PCREL_BRANCH: +@@ -24791,7 +25129,12 @@ md_begin (void) + mcpu_cpu_opt = legacy_cpu; + } + else if (!mcpu_cpu_opt) +- mcpu_cpu_opt = march_cpu_opt; ++ { ++ mcpu_cpu_opt = march_cpu_opt; ++ dyn_mcpu_ext_opt = dyn_march_ext_opt; ++ /* Avoid double free in arm_md_end. */ ++ dyn_march_ext_opt = NULL; ++ } + + if (legacy_fpu) + { +@@ -24831,16 +25174,22 @@ md_begin (void) + mcpu_cpu_opt = &cpu_default; + selected_cpu = cpu_default; + } +- else if (no_cpu_selected ()) +- selected_cpu = cpu_default; ++ else if (dyn_mcpu_ext_opt) ++ ARM_MERGE_FEATURE_SETS (selected_cpu, *mcpu_cpu_opt, *dyn_mcpu_ext_opt); ++ else ++ selected_cpu = *mcpu_cpu_opt; + #else +- if (mcpu_cpu_opt) ++ if (mcpu_cpu_opt && dyn_mcpu_ext_opt) ++ ARM_MERGE_FEATURE_SETS (selected_cpu, *mcpu_cpu_opt, *dyn_mcpu_ext_opt); ++ else if (mcpu_cpu_opt) + selected_cpu = *mcpu_cpu_opt; + else + mcpu_cpu_opt = &arm_arch_any; + #endif + + ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); ++ if (dyn_mcpu_ext_opt) ++ ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, *dyn_mcpu_ext_opt); + + autoselect_thumb_from_cpu_variant (); + +@@ -25215,6 +25564,7 @@ struct arm_cpu_option_table + const char *name; + size_t name_len; + const arm_feature_set value; ++ const arm_feature_set ext; + /* For some CPUs we assume an FPU unless the user explicitly sets + -mfpu=... */ + const arm_feature_set default_fpu; +@@ -25225,174 +25575,387 @@ struct arm_cpu_option_table + + /* This list should, at a minimum, contain all the cpu names + recognized by GCC. */ +-#define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN } ++#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN } + static const struct arm_cpu_option_table arm_cpus[] = + { +- ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"), +- ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), +- ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), ++ ARM_CPU_OPT ("all", NULL, ARM_ANY, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4, ++ ARM_ARCH_NONE, ++ FPU_ARCH_FPA), ++ + /* For V5 or later processors we default to using VFP; but the user + should really set the FPU type explicitly. */ +- ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), +- ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), +- ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"), +- ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"), +- ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), +- ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), +- ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"), +- ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), +- ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, +- "ARM1026EJ-S"), +- ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"), +- ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL), +- ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, +- "ARM1136JF-S"), +- ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"), +- ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"), +- ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL), +- ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ, FPU_NONE, NULL), +- ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC, +- FPU_NONE, "Cortex-A5"), +- ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, +- "Cortex-A7"), +- ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC, +- ARM_FEATURE_COPROC (FPU_VFP_V3 +- | FPU_NEON_EXT_V1), +- "Cortex-A8"), +- ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC, +- ARM_FEATURE_COPROC (FPU_VFP_V3 +- | FPU_NEON_EXT_V1), +- "Cortex-A9"), +- ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, +- "Cortex-A12"), +- ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, +- "Cortex-A15"), +- ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, +- "Cortex-A17"), +- ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "Cortex-A32"), +- ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "Cortex-A35"), +- ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "Cortex-A53"), +- ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "Cortex-A57"), +- ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "Cortex-A72"), +- ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "Cortex-A73"), +- ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"), +- ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, +- "Cortex-R4F"), +- ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV, +- FPU_NONE, "Cortex-R5"), +- ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV, +- FPU_ARCH_VFP_V3D16, +- "Cortex-R7"), +- ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV, +- FPU_ARCH_VFP_V3D16, +- "Cortex-R8"), +- ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"), +- ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"), +- ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"), +- ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"), +- ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"), +- ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"), +- ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "Samsung " \ +- "Exynos M1"), +- ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "Qualcomm " +- "QDF24XX"), ++ ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V1), ++ ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V1), ++ ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V1), ++ ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A, ++ ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_NEON_VFP_V4), ++ ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A, ++ ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), ++ ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), ++ ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A, ++ ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), ++ ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), ++ ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_NEON_VFP_V4), ++ ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_NEON_VFP_V4), ++ ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_NEON_VFP_V4), ++ ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A, ++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A, ++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A, ++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A, ++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A, ++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A, ++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A, ++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A, ++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V3D16), ++ ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R, ++ ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R, ++ ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), ++ FPU_ARCH_VFP_V3D16), ++ ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R, ++ ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), ++ FPU_ARCH_VFP_V3D16), ++ ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R, ++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8), ++ FPU_ARCH_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN, ++ ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM, ++ ARM_ARCH_NONE, ++ FPU_NONE), ++ ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A, ++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), + + /* ??? XSCALE is really an architecture. */ +- ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), ++ ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ + /* ??? iwmmxt is not a processor. */ +- ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL), +- ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), ++ ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE, ++ ARM_ARCH_NONE, ++ FPU_ARCH_VFP_V2), ++ + /* Maverick */ +- ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), +- FPU_ARCH_MAVERICK, "ARM920T"), ++ ARM_CPU_OPT ("ep9312", "ARM920T", ++ ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), ++ ARM_ARCH_NONE, FPU_ARCH_MAVERICK), ++ + /* Marvell processors. */ +- ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP +- | ARM_EXT_SEC, +- ARM_EXT2_V6T2_V8M), +- FPU_ARCH_VFP_V3D16, NULL), +- ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP +- | ARM_EXT_SEC, +- ARM_EXT2_V6T2_V8M), +- FPU_ARCH_NEON_VFP_V4, NULL), ++ ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A, ++ ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), ++ FPU_ARCH_VFP_V3D16), ++ ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A, ++ ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), ++ FPU_ARCH_NEON_VFP_V4), ++ + /* APM X-Gene family. */ +- ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "APM X-Gene 1"), +- ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, +- "APM X-Gene 2"), ++ ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A, ++ ARM_ARCH_NONE, ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), ++ ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A, ++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8), ++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), + +- { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } ++ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } + }; + #undef ARM_CPU_OPT + +@@ -25459,6 +26022,8 @@ static const struct arm_arch_option_tabl + ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), + ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP), + ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP), ++ ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP), ++ ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP), + ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), + ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), + ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP), +@@ -25490,6 +26055,9 @@ static const struct arm_option_extension + ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8), + ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), ++ ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ++ ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), ++ ARM_ARCH_V8_2A), + ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), + ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), + ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)), +@@ -25502,6 +26070,13 @@ static const struct arm_option_extension + ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), + ARM_FEATURE_CORE_LOW (ARM_EXT_V7A), + ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)), ++ /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of ++ Thumb divide instruction. Due to this having the same name as the ++ previous entry, this will be ignored when doing command-line parsing and ++ only considered by build attribute selection code. */ ++ ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), ++ ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), ++ ARM_FEATURE_CORE_LOW (ARM_EXT_V7)), + ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), + ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE), + ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), +@@ -25517,13 +26092,13 @@ static const struct arm_option_extension + ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)), + ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), + ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0), +- ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), ++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), + ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), + ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0), +- ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), ++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), + ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1, + ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA), +- ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), ++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), + ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), + ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), + ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), +@@ -25581,6 +26156,7 @@ static const struct arm_option_fpu_value + {"arm1136jf-s", FPU_ARCH_VFP_V2}, + {"maverick", FPU_ARCH_MAVERICK}, + {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, ++ {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, + {"neon-fp16", FPU_ARCH_NEON_FP16}, + {"vfpv4", FPU_ARCH_VFP_V4}, + {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, +@@ -25632,10 +26208,9 @@ struct arm_long_option_table + }; + + static bfd_boolean +-arm_parse_extension (const char *str, const arm_feature_set **opt_p) ++arm_parse_extension (const char *str, const arm_feature_set *opt_set, ++ arm_feature_set **ext_set_p) + { +- arm_feature_set *ext_set = XNEW (arm_feature_set); +- + /* We insist on extensions being specified in alphabetical order, and with + extensions being added before being removed. We achieve this by having + the global ARM_EXTENSIONS table in alphabetical order, and using the +@@ -25646,9 +26221,11 @@ arm_parse_extension (const char *str, co + const arm_feature_set arm_any = ARM_ANY; + int adding_value = -1; + +- /* Copy the feature set, so that we can modify it. */ +- *ext_set = **opt_p; +- *opt_p = ext_set; ++ if (!*ext_set_p) ++ { ++ *ext_set_p = XNEW (arm_feature_set); ++ **ext_set_p = arm_arch_none; ++ } + + while (str != NULL && *str != 0) + { +@@ -25716,7 +26293,7 @@ arm_parse_extension (const char *str, co + /* Empty entry. */ + if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any)) + continue; +- if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *ext_set)) ++ if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set)) + break; + } + if (i == nb_allowed_archs) +@@ -25727,10 +26304,15 @@ arm_parse_extension (const char *str, co + + /* Add or remove the extension. */ + if (adding_value) +- ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value); ++ ARM_MERGE_FEATURE_SETS (**ext_set_p, **ext_set_p, ++ opt->merge_value); + else +- ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value); ++ ARM_CLEAR_FEATURE (**ext_set_p, **ext_set_p, opt->clear_value); + ++ /* Allowing Thumb division instructions for ARMv7 in autodetection ++ rely on this break so that duplicate extensions (extensions ++ with the same name as a previous extension in the list) are not ++ considered for command-line parsing. */ + break; + } + +@@ -25786,6 +26368,9 @@ arm_parse_cpu (const char *str) + if (opt->name_len == len && strncmp (opt->name, str, len) == 0) + { + mcpu_cpu_opt = &opt->value; ++ if (!dyn_mcpu_ext_opt) ++ dyn_mcpu_ext_opt = XNEW (arm_feature_set); ++ *dyn_mcpu_ext_opt = opt->ext; + mcpu_fpu_opt = &opt->default_fpu; + if (opt->canonical_name) + { +@@ -25805,7 +26390,7 @@ arm_parse_cpu (const char *str) + } + + if (ext != NULL) +- return arm_parse_extension (ext, &mcpu_cpu_opt); ++ return arm_parse_extension (ext, mcpu_cpu_opt, &dyn_mcpu_ext_opt); + + return TRUE; + } +@@ -25840,7 +26425,7 @@ arm_parse_arch (const char *str) + strcpy (selected_cpu_name, opt->name); + + if (ext != NULL) +- return arm_parse_extension (ext, &march_cpu_opt); ++ return arm_parse_extension (ext, march_cpu_opt, &dyn_march_ext_opt); + + return TRUE; + } +@@ -26080,30 +26665,62 @@ typedef struct + arm_feature_set flags; + } cpu_arch_ver_table; + +-/* Mapping from CPU features to EABI CPU arch values. As a general rule, table +- must be sorted least features first but some reordering is needed, eg. for +- Thumb-2 instructions to be detected as coming from ARMv6T2. */ ++/* Mapping from CPU features to EABI CPU arch values. Table must be sorted ++ chronologically for architectures, with an exception for ARMv6-M and ++ ARMv6S-M due to legacy reasons. No new architecture should have a ++ special case. This allows for build attribute selection results to be ++ stable when new architectures are added. */ + static const cpu_arch_ver_table cpu_arch_ver[] = + { ++ {0, ARM_ARCH_V1}, ++ {0, ARM_ARCH_V2}, ++ {0, ARM_ARCH_V2S}, ++ {0, ARM_ARCH_V3}, ++ {0, ARM_ARCH_V3M}, ++ {1, ARM_ARCH_V4xM}, + {1, ARM_ARCH_V4}, ++ {2, ARM_ARCH_V4TxM}, + {2, ARM_ARCH_V4T}, ++ {3, ARM_ARCH_V5xM}, + {3, ARM_ARCH_V5}, ++ {3, ARM_ARCH_V5TxM}, + {3, ARM_ARCH_V5T}, ++ {4, ARM_ARCH_V5TExP}, + {4, ARM_ARCH_V5TE}, + {5, ARM_ARCH_V5TEJ}, + {6, ARM_ARCH_V6}, +- {9, ARM_ARCH_V6K}, + {7, ARM_ARCH_V6Z}, ++ {7, ARM_ARCH_V6KZ}, ++ {9, ARM_ARCH_V6K}, ++ {8, ARM_ARCH_V6T2}, ++ {8, ARM_ARCH_V6KT2}, ++ {8, ARM_ARCH_V6ZT2}, ++ {8, ARM_ARCH_V6KZT2}, ++ ++ /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as ++ always selected build attributes to match those of ARMv6-M ++ (resp. ARMv6S-M). However, due to these architectures being a strict ++ subset of ARMv7-M in terms of instructions available, ARMv7-M attributes ++ would be selected when fully respecting chronology of architectures. ++ It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and ++ move them before ARMv7 architectures. */ + {11, ARM_ARCH_V6M}, + {12, ARM_ARCH_V6SM}, +- {8, ARM_ARCH_V6T2}, +- {10, ARM_ARCH_V7VE}, ++ ++ {10, ARM_ARCH_V7}, ++ {10, ARM_ARCH_V7A}, + {10, ARM_ARCH_V7R}, + {10, ARM_ARCH_V7M}, ++ {10, ARM_ARCH_V7VE}, ++ {13, ARM_ARCH_V7EM}, + {14, ARM_ARCH_V8A}, ++ {14, ARM_ARCH_V8_1A}, ++ {14, ARM_ARCH_V8_2A}, ++ {14, ARM_ARCH_V8_3A}, + {16, ARM_ARCH_V8M_BASE}, + {17, ARM_ARCH_V8M_MAIN}, +- {0, ARM_ARCH_NONE} ++ {15, ARM_ARCH_V8R}, ++ {-1, ARM_ARCH_NONE} + }; + + /* Set an attribute if it has not already been set by the user. */ +@@ -26125,92 +26742,210 @@ aeabi_set_attribute_string (int tag, con + bfd_elf_add_proc_attr_string (stdoutput, tag, value); + } + +-/* Set the public EABI object attributes. */ +-void +-aeabi_set_public_attributes (void) ++/* Return whether features in the *NEEDED feature set are available via ++ extensions for the architecture whose feature set is *ARCH_FSET. */ ++static bfd_boolean ++have_ext_for_needed_feat_p (const arm_feature_set *arch_fset, ++ const arm_feature_set *needed) + { +- int arch; +- char profile; +- int virt_sec = 0; +- int fp16_optional = 0; +- arm_feature_set arm_arch = ARM_ARCH_NONE; +- arm_feature_set flags; +- arm_feature_set tmp; +- arm_feature_set arm_arch_v8m_base = ARM_ARCH_V8M_BASE; +- const cpu_arch_ver_table *p; +- +- /* Choose the architecture based on the capabilities of the requested cpu +- (if any) and/or the instructions actually used. */ +- ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); +- ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); +- ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); ++ int i, nb_allowed_archs; ++ arm_feature_set ext_fset; ++ const struct arm_option_extension_value_table *opt; + +- if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) +- ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); ++ ext_fset = arm_arch_none; ++ for (opt = arm_extensions; opt->name != NULL; opt++) ++ { ++ /* Extension does not provide any feature we need. */ ++ if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value)) ++ continue; + +- if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) +- ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); ++ nb_allowed_archs = ++ sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]); ++ for (i = 0; i < nb_allowed_archs; i++) ++ { ++ /* Empty entry. */ ++ if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any)) ++ break; + +- selected_cpu = flags; ++ /* Extension is available, add it. */ ++ if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset)) ++ ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value); ++ } ++ } + +- /* Allow the user to override the reported architecture. */ +- if (object_arch) ++ /* Can we enable all features in *needed? */ ++ return ARM_FSET_CPU_SUBSET (*needed, ext_fset); ++} ++ ++/* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for ++ a given architecture feature set *ARCH_EXT_FSET including extension feature ++ set *EXT_FSET. Selection logic used depend on EXACT_MATCH: ++ - if true, check for an exact match of the architecture modulo extensions; ++ - otherwise, select build attribute value of the first superset ++ architecture released so that results remains stable when new architectures ++ are added. ++ For -march/-mcpu=all the build attribute value of the most featureful ++ architecture is returned. Tag_CPU_arch_profile result is returned in ++ PROFILE. */ ++static int ++get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset, ++ const arm_feature_set *ext_fset, ++ char *profile, int exact_match) ++{ ++ arm_feature_set arch_fset; ++ const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL; ++ ++ /* Select most featureful architecture with all its extensions if building ++ for -march=all as the feature sets used to set build attributes. */ ++ if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any)) + { +- ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); +- ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); ++ /* Force revisiting of decision for each new architecture. */ ++ gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8M_MAIN); ++ *profile = 'A'; ++ return TAG_CPU_ARCH_V8; + } + +- /* We need to make sure that the attributes do not identify us as v6S-M +- when the only v6S-M feature in use is the Operating System Extensions. */ +- if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) +- if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) +- ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); ++ ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset); + +- tmp = flags; +- arch = 0; +- for (p = cpu_arch_ver; p->val; p++) ++ for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++) + { +- if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) ++ arm_feature_set known_arch_fset; ++ ++ ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any); ++ if (exact_match) + { +- arch = p->val; +- arm_arch = p->flags; +- ARM_CLEAR_FEATURE (tmp, tmp, p->flags); ++ /* Base architecture match user-specified architecture and ++ extensions, eg. ARMv6S-M matching -march=armv6-m+os. */ ++ if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset)) ++ { ++ p_ver_ret = p_ver; ++ goto found; ++ } ++ /* Base architecture match user-specified architecture only ++ (eg. ARMv6-M in the same case as above). Record it in case we ++ find a match with above condition. */ ++ else if (p_ver_ret == NULL ++ && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset)) ++ p_ver_ret = p_ver; + } +- } ++ else ++ { + +- /* The table lookup above finds the last architecture to contribute +- a new feature. Unfortunately, Tag13 is a subset of the union of +- v6T2 and v7-M, so it is never seen as contributing a new feature. +- We can not search for the last entry which is entirely used, +- because if no CPU is specified we build up only those flags +- actually used. Perhaps we should separate out the specified +- and implicit cases. Avoid taking this path for -march=all by +- checking for contradictory v7-A / v7-M features. */ +- if (arch == TAG_CPU_ARCH_V7 +- && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) +- && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) +- && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) +- { +- arch = TAG_CPU_ARCH_V7E_M; +- arm_arch = (arm_feature_set) ARM_ARCH_V7EM; ++ /* Architecture has all features wanted. */ ++ if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset)) ++ { ++ arm_feature_set added_fset; ++ ++ /* Compute features added by this architecture over the one ++ recorded in p_ver_ret. */ ++ if (p_ver_ret != NULL) ++ ARM_CLEAR_FEATURE (added_fset, known_arch_fset, ++ p_ver_ret->flags); ++ /* First architecture that match incl. with extensions, or the ++ only difference in features over the recorded match is ++ features that were optional and are now mandatory. */ ++ if (p_ver_ret == NULL ++ || ARM_FSET_CPU_SUBSET (added_fset, arch_fset)) ++ { ++ p_ver_ret = p_ver; ++ goto found; ++ } ++ } ++ else if (p_ver_ret == NULL) ++ { ++ arm_feature_set needed_ext_fset; ++ ++ ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset); ++ ++ /* Architecture has all features needed when using some ++ extensions. Record it and continue searching in case there ++ exist an architecture providing all needed features without ++ the need for extensions (eg. ARMv6S-M Vs ARMv6-M with ++ OS extension). */ ++ if (have_ext_for_needed_feat_p (&known_arch_fset, ++ &needed_ext_fset)) ++ p_ver_ret = p_ver; ++ } ++ } + } + +- ARM_CLEAR_FEATURE (tmp, flags, arm_arch_v8m_base); +- if (arch == TAG_CPU_ARCH_V8M_BASE && ARM_CPU_HAS_FEATURE (tmp, arm_arch_any)) ++ if (p_ver_ret == NULL) ++ return -1; ++ ++found: ++ /* Tag_CPU_arch_profile. */ ++ if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a) ++ || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8) ++ || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics) ++ && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only))) ++ *profile = 'A'; ++ else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r)) ++ *profile = 'R'; ++ else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m)) ++ *profile = 'M'; ++ else ++ *profile = '\0'; ++ return p_ver_ret->val; ++} ++ ++/* Set the public EABI object attributes. */ ++static void ++aeabi_set_public_attributes (void) ++{ ++ char profile; ++ int arch = -1; ++ int virt_sec = 0; ++ int fp16_optional = 0; ++ int skip_exact_match = 0; ++ arm_feature_set flags, flags_arch, flags_ext; ++ ++ /* Autodetection mode, choose the architecture based the instructions ++ actually used. */ ++ if (no_cpu_selected ()) + { +- arch = TAG_CPU_ARCH_V8M_MAIN; +- arm_arch = (arm_feature_set) ARM_ARCH_V8M_MAIN; ++ ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); ++ ++ if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) ++ ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); ++ ++ if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) ++ ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); ++ ++ /* Code run during relaxation relies on selected_cpu being set. */ ++ selected_cpu = flags; + } ++ /* Otherwise, choose the architecture based on the capabilities of the ++ requested cpu. */ ++ else ++ flags = selected_cpu; ++ ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); + +- /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as +- coming from ARMv8-A. However, since ARMv8-A has more instructions than +- ARMv8-M, -march=all must be detected as ARMv8-A. */ +- if (arch == TAG_CPU_ARCH_V8M_MAIN +- && ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any)) ++ /* Allow the user to override the reported architecture. */ ++ if (object_arch) + { +- arch = TAG_CPU_ARCH_V8; +- arm_arch = (arm_feature_set) ARM_ARCH_V8A; ++ ARM_CLEAR_FEATURE (flags_arch, *object_arch, fpu_any); ++ flags_ext = arm_arch_none; + } ++ else ++ { ++ ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); ++ flags_ext = dyn_mcpu_ext_opt ? *dyn_mcpu_ext_opt : arm_arch_none; ++ skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any); ++ } ++ ++ /* When this function is run again after relaxation has happened there is no ++ way to determine whether an architecture or CPU was specified by the user: ++ - selected_cpu is set above for relaxation to work; ++ - march_cpu_opt is not set if only -mcpu or .cpu is used; ++ - mcpu_cpu_opt is set to arm_arch_any for autodetection. ++ Therefore, if not in -march=all case we first try an exact match and fall ++ back to autodetection. */ ++ if (!skip_exact_match) ++ arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1); ++ if (arch == -1) ++ arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0); ++ if (arch == -1) ++ as_bad (_("no architecture contains all the instructions used\n")); + + /* Tag_CPU_name. */ + if (selected_cpu_name[0]) +@@ -26233,40 +26968,22 @@ aeabi_set_public_attributes (void) + aeabi_set_attribute_int (Tag_CPU_arch, arch); + + /* Tag_CPU_arch_profile. */ +- if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) +- || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) +- || (ARM_CPU_HAS_FEATURE (flags, arm_ext_atomics) +- && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))) +- profile = 'A'; +- else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) +- profile = 'R'; +- else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) +- profile = 'M'; +- else +- profile = '\0'; +- + if (profile != '\0') + aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); + + /* Tag_DSP_extension. */ +- if (ARM_CPU_HAS_FEATURE (flags, arm_ext_dsp)) +- { +- arm_feature_set ext; +- +- /* DSP instructions not in architecture. */ +- ARM_CLEAR_FEATURE (ext, flags, arm_arch); +- if (ARM_CPU_HAS_FEATURE (ext, arm_ext_dsp)) +- aeabi_set_attribute_int (Tag_DSP_extension, 1); +- } ++ if (dyn_mcpu_ext_opt && ARM_CPU_HAS_FEATURE (*dyn_mcpu_ext_opt, arm_ext_dsp)) ++ aeabi_set_attribute_int (Tag_DSP_extension, 1); + ++ ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); + /* Tag_ARM_ISA_use. */ + if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) +- || arch == 0) ++ || ARM_FEATURE_ZERO (flags_arch)) + aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); + + /* Tag_THUMB_ISA_use. */ + if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) +- || arch == 0) ++ || ARM_FEATURE_ZERO (flags_arch)) + { + int thumb_isa_use; + +@@ -26348,9 +27065,7 @@ aeabi_set_public_attributes (void) + by the base architecture. + + For new architectures we will have to check these tests. */ +- gas_assert (arch <= TAG_CPU_ARCH_V8 +- || (arch >= TAG_CPU_ARCH_V8M_BASE +- && arch <= TAG_CPU_ARCH_V8M_MAIN)); ++ gas_assert (arch <= TAG_CPU_ARCH_V8M_MAIN); + if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) + || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m)) + aeabi_set_attribute_int (Tag_DIV_use, 0); +@@ -26373,6 +27088,18 @@ aeabi_set_public_attributes (void) + aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); + } + ++/* Post relaxation hook. Recompute ARM attributes now that relaxation is ++ finished and free extension feature bits which will not be used anymore. */ ++void ++arm_md_post_relax (void) ++{ ++ aeabi_set_public_attributes (); ++ XDELETE (dyn_mcpu_ext_opt); ++ dyn_mcpu_ext_opt = NULL; ++ XDELETE (dyn_march_ext_opt); ++ dyn_march_ext_opt = NULL; ++} ++ + /* Add the default contents for the .ARM.attributes section. */ + void + arm_md_end (void) +@@ -26405,7 +27132,10 @@ s_arm_cpu (int ignored ATTRIBUTE_UNUSED) + if (streq (opt->name, name)) + { + mcpu_cpu_opt = &opt->value; +- selected_cpu = opt->value; ++ if (!dyn_mcpu_ext_opt) ++ dyn_mcpu_ext_opt = XNEW (arm_feature_set); ++ *dyn_mcpu_ext_opt = opt->ext; ++ ARM_MERGE_FEATURE_SETS (selected_cpu, *mcpu_cpu_opt, *dyn_mcpu_ext_opt); + if (opt->canonical_name) + strcpy (selected_cpu_name, opt->canonical_name); + else +@@ -26417,6 +27147,8 @@ s_arm_cpu (int ignored ATTRIBUTE_UNUSED) + selected_cpu_name[i] = 0; + } + ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); ++ if (dyn_mcpu_ext_opt) ++ ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, *dyn_mcpu_ext_opt); + *input_line_pointer = saved_char; + demand_empty_rest_of_line (); + return; +@@ -26447,9 +27179,11 @@ s_arm_arch (int ignored ATTRIBUTE_UNUSED + if (streq (opt->name, name)) + { + mcpu_cpu_opt = &opt->value; +- selected_cpu = opt->value; ++ XDELETE (dyn_mcpu_ext_opt); ++ dyn_mcpu_ext_opt = NULL; ++ selected_cpu = *mcpu_cpu_opt; + strcpy (selected_cpu_name, opt->name); +- ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); ++ ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, *mfpu_opt); + *input_line_pointer = saved_char; + demand_empty_rest_of_line (); + return; +@@ -26536,16 +27270,26 @@ s_arm_arch_extension (int ignored ATTRIB + break; + } + ++ if (!dyn_mcpu_ext_opt) ++ { ++ dyn_mcpu_ext_opt = XNEW (arm_feature_set); ++ *dyn_mcpu_ext_opt = arm_arch_none; ++ } + if (adding_value) +- ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, ++ ARM_MERGE_FEATURE_SETS (*dyn_mcpu_ext_opt, *dyn_mcpu_ext_opt, + opt->merge_value); + else +- ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value); ++ ARM_CLEAR_FEATURE (*dyn_mcpu_ext_opt, *dyn_mcpu_ext_opt, ++ opt->clear_value); + +- mcpu_cpu_opt = &selected_cpu; +- ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); ++ ARM_MERGE_FEATURE_SETS (selected_cpu, *mcpu_cpu_opt, *dyn_mcpu_ext_opt); ++ ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, *mfpu_opt); + *input_line_pointer = saved_char; + demand_empty_rest_of_line (); ++ /* Allowing Thumb division instructions for ARMv7 in autodetection rely ++ on this return so that duplicate extensions (extensions with the ++ same name as a previous extension in the list) are not considered ++ for command-line parsing. */ + return; + } + +@@ -26576,6 +27320,8 @@ s_arm_fpu (int ignored ATTRIBUTE_UNUSED) + { + mfpu_opt = &opt->value; + ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); ++ if (dyn_mcpu_ext_opt) ++ ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, *dyn_mcpu_ext_opt); + *input_line_pointer = saved_char; + demand_empty_rest_of_line (); + return; +diff -rup binutils.orig/gas/config/tc-arm.h binutils-2.27/gas/config/tc-arm.h +--- binutils.orig/gas/config/tc-arm.h 2017-08-09 10:26:30.032741952 +0100 ++++ binutils-2.27/gas/config/tc-arm.h 2017-08-09 11:17:35.442400257 +0100 +@@ -118,8 +118,8 @@ extern bfd_boolean tc_start_label_withou + extern void arm_md_end (void); + bfd_boolean arm_is_eabi (void); + +-#define md_post_relax_hook aeabi_set_public_attributes () +-extern void aeabi_set_public_attributes (void); ++#define md_post_relax_hook arm_md_post_relax () ++extern void arm_md_post_relax (void); + #endif + + /* NOTE: The fake label creation in stabs.c:s_stab_generic() has +diff -rup binutils.orig/gas/doc/c-arm.texi binutils-2.27/gas/doc/c-arm.texi +--- binutils.orig/gas/doc/c-arm.texi 2017-08-09 10:26:30.039741874 +0100 ++++ binutils-2.27/gas/doc/c-arm.texi 2017-08-09 10:28:00.216732329 +0100 +@@ -172,6 +172,7 @@ been added, again in ascending alphabeti + The following extensions are currently supported: + @code{crc} + @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}), ++@code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}), + @code{fp} (Floating Point Extensions for v8-A architecture), + @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures), + @code{iwmmxt}, +@@ -185,7 +186,7 @@ architectures), + @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), + @code{virt} (Virtualization Extensions for v7-A architecture, implies + @code{idiv}), +-@code{pan} (Priviliged Access Never Extensions for v8-A architecture), ++@code{pan} (Privileged Access Never Extensions for v8-A architecture), + @code{ras} (Reliability, Availability and Serviceability extensions + for v8-A architecture), + @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies +@@ -230,6 +231,8 @@ names are recognized: + @code{armv8-a}, + @code{armv8.1-a}, + @code{armv8.2-a}, ++@code{armv8.3-a}, ++@code{armv8-r}, + @code{iwmmxt} + @code{iwmmxt2} + and +@@ -281,7 +284,7 @@ The following format options are recogni + @code{arm1136jf-s}, + @code{maverick}, + @code{neon}, +-@code{neon-vfpv4}, ++@code{neon-vfpv3}, + @code{neon-fp-armv8}, + @code{crypto-neon-fp-armv8}, + @code{neon-fp-armv8.1} +@@ -293,7 +296,7 @@ also affects the way in which the @code{ + when assembling little-endian code. + + The default is dependent on the processor selected. For Architecture 5 or +-later, the default is to assembler for VFP instructions; for earlier ++later, the default is to assemble for VFP instructions; for earlier + architectures the default is to assemble for FPA instructions. + + @cindex @code{-mthumb} command line option, ARM +@@ -931,7 +934,7 @@ between Arm and Thumb instructions and s + interworking is not going to be performed. The presence of this + directive also implies @code{.thumb} + +-This directive is not neccessary when generating EABI objects. On these ++This directive is not necessary when generating EABI objects. On these + targets the encoding is implicit when generating Thumb code. + + @cindex @code{.thumb_set} directive, ARM +@@ -966,7 +969,7 @@ should only be done if it is really nece + + @cindex @code{.unwind_raw} directive, ARM + @item .unwind_raw @var{offset}, @var{byte1}, @dots{} +-Insert one of more arbitary unwind opcode bytes, which are known to adjust ++Insert one of more arbitrary unwind opcode bytes, which are known to adjust + the stack pointer by @var{offset} bytes. + + For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to +diff -rup binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr-base.d binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr-base.d +--- binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr-base.d 2017-08-09 10:26:30.056741684 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr-base.d 2017-08-09 11:51:59.357287965 +0100 +@@ -6,27 +6,71 @@ + .*: +file format .*arm.* + + Disassembly of section .text: +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8888 msr MSP_NS, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8889 msr PSP_NS, r0 +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8888 msr MSP_NS, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8889 msr PSP_NS, r0 +-0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS +-0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS ++0+.* <[^>]*> f3ef 8109 mrs r1, PSP ++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS ++0+.* <[^>]*> f3ef 8109 mrs r1, PSP ++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS ++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM ++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS ++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM ++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS ++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM ++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS ++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM ++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS ++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK ++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS ++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK ++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS ++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI ++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS ++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI ++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS ++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK ++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS ++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK ++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS ++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL ++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS ++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL ++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS ++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS ++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS ++0+.* <[^>]*> f380 8808 msr MSP, r0 ++0+.* <[^>]*> f380 8888 msr MSP_NS, r0 ++0+.* <[^>]*> f380 8808 msr MSP, r0 ++0+.* <[^>]*> f380 8888 msr MSP_NS, r0 ++0+.* <[^>]*> f381 8809 msr PSP, r1 ++0+.* <[^>]*> f381 8889 msr PSP_NS, r1 ++0+.* <[^>]*> f381 8809 msr PSP, r1 ++0+.* <[^>]*> f381 8889 msr PSP_NS, r1 ++0+.* <[^>]*> f382 880a msr MSPLIM, r2 ++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2 ++0+.* <[^>]*> f382 880a msr MSPLIM, r2 ++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2 ++0+.* <[^>]*> f383 880b msr PSPLIM, r3 ++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3 ++0+.* <[^>]*> f383 880b msr PSPLIM, r3 ++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3 ++0+.* <[^>]*> f384 8810 msr PRIMASK, r4 ++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4 ++0+.* <[^>]*> f384 8810 msr PRIMASK, r4 ++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4 ++0+.* <[^>]*> f385 8811 msr BASEPRI, r5 ++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5 ++0+.* <[^>]*> f385 8811 msr BASEPRI, r5 ++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5 ++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6 ++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6 ++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6 ++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6 ++0+.* <[^>]*> f387 8814 msr CONTROL, r7 ++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7 ++0+.* <[^>]*> f387 8814 msr CONTROL, r7 ++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7 ++0+.* <[^>]*> f388 8898 msr SP_NS, r8 ++0+.* <[^>]*> f388 8898 msr SP_NS, r8 +diff -rup binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr-main.d binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr-main.d +--- binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr-main.d 2017-08-09 10:26:30.056741684 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr-main.d 2017-08-09 11:52:33.776902849 +0100 +@@ -6,27 +6,71 @@ + .*: +file format .*arm.* + + Disassembly of section .text: +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8888 msr MSP_NS, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8889 msr PSP_NS, r0 +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8888 msr MSP_NS, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8889 msr PSP_NS, r0 +-0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS +-0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS ++0+.* <[^>]*> f3ef 8109 mrs r1, PSP ++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS ++0+.* <[^>]*> f3ef 8109 mrs r1, PSP ++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS ++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM ++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS ++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM ++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS ++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM ++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS ++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM ++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS ++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK ++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS ++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK ++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS ++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI ++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS ++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI ++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS ++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK ++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS ++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK ++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS ++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL ++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS ++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL ++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS ++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS ++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS ++0+.* <[^>]*> f380 8808 msr MSP, r0 ++0+.* <[^>]*> f380 8888 msr MSP_NS, r0 ++0+.* <[^>]*> f380 8808 msr MSP, r0 ++0+.* <[^>]*> f380 8888 msr MSP_NS, r0 ++0+.* <[^>]*> f381 8809 msr PSP, r1 ++0+.* <[^>]*> f381 8889 msr PSP_NS, r1 ++0+.* <[^>]*> f381 8809 msr PSP, r1 ++0+.* <[^>]*> f381 8889 msr PSP_NS, r1 ++0+.* <[^>]*> f382 880a msr MSPLIM, r2 ++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2 ++0+.* <[^>]*> f382 880a msr MSPLIM, r2 ++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2 ++0+.* <[^>]*> f383 880b msr PSPLIM, r3 ++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3 ++0+.* <[^>]*> f383 880b msr PSPLIM, r3 ++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3 ++0+.* <[^>]*> f384 8810 msr PRIMASK, r4 ++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4 ++0+.* <[^>]*> f384 8810 msr PRIMASK, r4 ++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4 ++0+.* <[^>]*> f385 8811 msr BASEPRI, r5 ++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5 ++0+.* <[^>]*> f385 8811 msr BASEPRI, r5 ++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5 ++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6 ++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6 ++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6 ++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6 ++0+.* <[^>]*> f387 8814 msr CONTROL, r7 ++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7 ++0+.* <[^>]*> f387 8814 msr CONTROL, r7 ++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7 ++0+.* <[^>]*> f388 8898 msr SP_NS, r8 ++0+.* <[^>]*> f388 8898 msr SP_NS, r8 +diff -rup binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr.s binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr.s +--- binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr.s 2017-08-09 10:26:30.056741684 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr.s 2017-08-09 11:50:44.728124484 +0100 +@@ -1,25 +1,109 @@ + T: +-msr MSP, r0 +-msr MSP_S, r0 +-msr MSP_NS, r0 +-msr PSP, r0 +-msr PSP_S, r0 +-msr PSP_NS, r0 +-msr msp, r0 +-msr msp_s, r0 +-msr msp_ns, r0 +-msr psp, r0 +-msr psp_s, r0 +-msr psp_ns, r0 ++## MRS ## ++ ++# MSP + mrs r0, MSP +-mrs r0, MSP_S + mrs r0, MSP_NS +-mrs r0, PSP +-mrs r0, PSP_S +-mrs r0, PSP_NS + mrs r0, msp +-mrs r0, msp_s + mrs r0, msp_ns +-mrs r0, psp +-mrs r0, psp_s +-mrs r0, psp_ns ++ ++# PSP ++mrs r1, PSP ++mrs r1, PSP_NS ++mrs r1, psp ++mrs r1, psp_ns ++ ++# MSPLIM ++mrs r2, MSPLIM ++mrs r2, MSPLIM_NS ++mrs r2, msplim ++mrs r2, msplim_ns ++ ++# PSPLIM ++mrs r3, PSPLIM ++mrs r3, PSPLIM_NS ++mrs r3, psplim ++mrs r3, psplim_ns ++ ++# PRIMASK ++mrs r4, PRIMASK ++mrs r4, PRIMASK_NS ++mrs r4, primask ++mrs r4, primask_ns ++ ++# BASEPRI ++mrs r5, BASEPRI ++mrs r5, BASEPRI_NS ++mrs r5, basepri ++mrs r5, basepri_ns ++ ++# FAULTMASK ++mrs r6, FAULTMASK ++mrs r6, FAULTMASK_NS ++mrs r6, faultmask ++mrs r6, faultmask_ns ++ ++# CONTROL ++mrs r7, CONTROL ++mrs r7, CONTROL_NS ++mrs r7, control ++mrs r7, control_ns ++ ++# SP_NS ++mrs r8, SP_NS ++mrs r8, sp_ns ++ ++ ++## MSR ## ++ ++# MSP ++msr MSP, r0 ++msr MSP_NS, r0 ++msr msp, r0 ++msr msp_ns, r0 ++ ++# PSP ++msr PSP, r1 ++msr PSP_NS, r1 ++msr psp, r1 ++msr psp_ns, r1 ++ ++# MSPLIM ++msr MSPLIM, r2 ++msr MSPLIM_NS, r2 ++msr msplim, r2 ++msr msplim_ns, r2 ++ ++# PSPLIM ++msr PSPLIM, r3 ++msr PSPLIM_NS, r3 ++msr psplim, r3 ++msr psplim_ns, r3 ++ ++# PRIMASK ++msr PRIMASK, r4 ++msr PRIMASK_NS, r4 ++msr primask, r4 ++msr primask_ns, r4 ++ ++# BASEPRI ++msr BASEPRI, r5 ++msr BASEPRI_NS, r5 ++msr basepri, r5 ++msr basepri_ns, r5 ++ ++# FAULTMASK ++msr FAULTMASK, r6 ++msr FAULTMASK_NS, r6 ++msr faultmask, r6 ++msr faultmask_ns, r6 ++ ++# CONTROL ++msr CONTROL, r7 ++msr CONTROL_NS, r7 ++msr control, r7 ++msr control_ns, r7 ++ ++# SP_NS ++msr SP_NS, r8 ++msr sp_ns, r8 +diff -rup binutils.orig/gas/testsuite/gas/arm/archv8m-main-dsp-4.d binutils-2.27/gas/testsuite/gas/arm/archv8m-main-dsp-4.d +--- binutils.orig/gas/testsuite/gas/arm/archv8m-main-dsp-4.d 2017-08-09 10:26:30.056741684 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/archv8m-main-dsp-4.d 2017-08-09 11:54:37.162524973 +0100 +@@ -6,27 +6,71 @@ + .*: +file format .*arm.* + + Disassembly of section .text: +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8888 msr MSP_NS, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8889 msr PSP_NS, r0 +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8808 msr MSP, r0 +-0+.* <[^>]*> f380 8888 msr MSP_NS, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8809 msr PSP, r0 +-0+.* <[^>]*> f380 8889 msr PSP_NS, r0 +-0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS +-0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8008 mrs r0, MSP + 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8009 mrs r0, PSP +-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS ++0+.* <[^>]*> f3ef 8109 mrs r1, PSP ++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS ++0+.* <[^>]*> f3ef 8109 mrs r1, PSP ++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS ++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM ++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS ++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM ++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS ++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM ++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS ++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM ++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS ++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK ++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS ++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK ++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS ++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI ++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS ++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI ++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS ++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK ++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS ++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK ++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS ++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL ++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS ++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL ++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS ++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS ++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS ++0+.* <[^>]*> f380 8808 msr MSP, r0 ++0+.* <[^>]*> f380 8888 msr MSP_NS, r0 ++0+.* <[^>]*> f380 8808 msr MSP, r0 ++0+.* <[^>]*> f380 8888 msr MSP_NS, r0 ++0+.* <[^>]*> f381 8809 msr PSP, r1 ++0+.* <[^>]*> f381 8889 msr PSP_NS, r1 ++0+.* <[^>]*> f381 8809 msr PSP, r1 ++0+.* <[^>]*> f381 8889 msr PSP_NS, r1 ++0+.* <[^>]*> f382 880a msr MSPLIM, r2 ++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2 ++0+.* <[^>]*> f382 880a msr MSPLIM, r2 ++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2 ++0+.* <[^>]*> f383 880b msr PSPLIM, r3 ++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3 ++0+.* <[^>]*> f383 880b msr PSPLIM, r3 ++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3 ++0+.* <[^>]*> f384 8810 msr PRIMASK, r4 ++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4 ++0+.* <[^>]*> f384 8810 msr PRIMASK, r4 ++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4 ++0+.* <[^>]*> f385 8811 msr BASEPRI, r5 ++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5 ++0+.* <[^>]*> f385 8811 msr BASEPRI, r5 ++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5 ++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6 ++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6 ++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6 ++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6 ++0+.* <[^>]*> f387 8814 msr CONTROL, r7 ++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7 ++0+.* <[^>]*> f387 8814 msr CONTROL, r7 ++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7 ++0+.* <[^>]*> f388 8898 msr SP_NS, r8 ++0+.* <[^>]*> f388 8898 msr SP_NS, r8 +diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv1.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv1.d +--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv1.d 2017-08-09 10:26:30.058741661 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv1.d 2017-08-09 11:56:00.992588823 +0100 +@@ -8,5 +8,4 @@ + Attribute Section: aeabi + File Attributes + Tag_CPU_name: "1" +- Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes +diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv2a.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2a.d +--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv2a.d 2017-08-09 10:26:30.058741661 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2a.d 2017-08-09 11:56:27.548292268 +0100 +@@ -8,5 +8,4 @@ + Attribute Section: aeabi + File Attributes + Tag_CPU_name: "2A" +- Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes +diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv2.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2.d +--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv2.d 2017-08-09 10:26:30.058741661 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2.d 2017-08-09 11:56:09.713491434 +0100 +@@ -8,5 +8,4 @@ + Attribute Section: aeabi + File Attributes + Tag_CPU_name: "2" +- Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes +diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv2s.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2s.d +--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv2s.d 2017-08-09 10:26:30.058741661 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2s.d 2017-08-09 11:56:35.794200184 +0100 +@@ -8,5 +8,4 @@ + Attribute Section: aeabi + File Attributes + Tag_CPU_name: "2S" +- Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes +diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv3.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv3.d +--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv3.d 2017-08-09 10:26:30.058741661 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv3.d 2017-08-09 11:56:52.435014353 +0100 +@@ -8,5 +8,4 @@ + Attribute Section: aeabi + File Attributes + Tag_CPU_name: "3" +- Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes +diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv3m.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv3m.d +--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv3m.d 2017-08-09 10:26:30.058741661 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv3m.d 2017-08-09 11:56:57.715955379 +0100 +@@ -8,5 +8,4 @@ + Attribute Section: aeabi + File Attributes + Tag_CPU_name: "3M" +- Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes +diff -rup binutils.orig/gas/testsuite/gas/arm/ldr-bad.l binutils-2.27/gas/testsuite/gas/arm/ldr-bad.l +--- binutils.orig/gas/testsuite/gas/arm/ldr-bad.l 2017-08-09 10:26:30.062741616 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/ldr-bad.l 2017-08-09 11:59:45.777078600 +0100 +@@ -1,7 +1,7 @@ + [^:]*: Assembler messages: + [^:]*:5: Warning: destination register same as write-back base +-[^:]*:9: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]' +-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7' ++[^:]*:9: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]' ++[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7' + [^:]*:15: Warning: destination register same as write-back base + [^:]*:16: Error: cannot use register index with PC-relative addressing -- `ldr r2,\[r15,r2\]!' + [^:]*:19: Error: cannot use register index with PC-relative addressing -- `ldr r1,\[r1,r15\]' +diff -rup binutils.orig/gas/testsuite/gas/arm/ldr-t-bad.l binutils-2.27/gas/testsuite/gas/arm/ldr-t-bad.l +--- binutils.orig/gas/testsuite/gas/arm/ldr-t-bad.l 2017-08-09 10:26:30.062741616 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/ldr-t-bad.l 2017-08-09 12:00:06.268849764 +0100 +@@ -1,9 +1,9 @@ + [^:]*: Assembler messages: + [^:]*:8: Error: registers may not be the same -- `ldr r1,\[r1,#5\]!' +-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]' ++[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]' + [^:]*:16: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,#4\]' + [^:]*:25: Error: branch must be last instruction in IT block -- `ldrge r15,.0x4' +-[^:]*:30: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7' ++[^:]*:30: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7' + [^:]*:36: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,r1\]' + [^:]*:41: Error: r13 not allowed here -- `ldr r1,\[r2,r13\]' + [^:]*:42: Error: r15 not allowed here -- `ldr r2,\[r2,r15\]' +diff -rup binutils.orig/gas/testsuite/gas/arm/ld-sp-warn.l binutils-2.27/gas/testsuite/gas/arm/ld-sp-warn.l +--- binutils.orig/gas/testsuite/gas/arm/ld-sp-warn.l 2017-08-09 10:26:30.062741616 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/ld-sp-warn.l 2017-08-09 11:59:02.223564973 +0100 +@@ -2,4 +2,3 @@ + [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. + [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. + [^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!' +-[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!' +diff -rup binutils.orig/gas/testsuite/gas/arm/strex-bad-t.d binutils-2.27/gas/testsuite/gas/arm/strex-bad-t.d +--- binutils.orig/gas/testsuite/gas/arm/strex-bad-t.d 2017-08-09 10:26:30.066741571 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/strex-bad-t.d 2017-08-09 12:01:22.679996462 +0100 +@@ -1,3 +1,4 @@ + # name: Bad addressing modes STREXH/STREXB. - THUMB ++# as: -march=armv7-a + # error-output: strex-bad-t.l + +diff -rup binutils.orig/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d binutils-2.27/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d +--- binutils.orig/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d 2017-08-09 10:26:30.067741560 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d 2017-08-09 11:57:45.943416812 +0100 +@@ -6,19 +6,23 @@ + .*: +file format .*arm.* + + Disassembly of section \.text: +-0[0-9a-f]+ <[^>]+> 2000[[:space:]]+movs[[:space:]]+r0, #0.* +-0[0-9a-f]+ <[^>]+> 2108[[:space:]]+movs[[:space:]]+r1, #8.* +-0[0-9a-f]+ <[^>]+> 2251[[:space:]]+movs[[:space:]]+r2, #81.* +-0[0-9a-f]+ <[^>]+> 231f[[:space:]]+movs[[:space:]]+r3, #31.* +-0[0-9a-f]+ <[^>]+> 242f[[:space:]]+movs[[:space:]]+r4, #47.* +-0[0-9a-f]+ <[^>]+> 253f[[:space:]]+movs[[:space:]]+r5, #63.* +-0[0-9a-f]+ <[^>]+> 2680[[:space:]]+movs[[:space:]]+r6, #128.* +-0[0-9a-f]+ <[^>]+> 27ff[[:space:]]+movs[[:space:]]+r7, #255.* ++0[0-9a-f]+ <[^>]+> f04f 0000[[:space:]]+mov\.w[[:space:]]+r0, #0.* ++0[0-9a-f]+ <[^>]+> f04f 0108[[:space:]]+mov\.w[[:space:]]+r1, #8.* ++0[0-9a-f]+ <[^>]+> f04f 0251[[:space:]]+mov\.w[[:space:]]+r2, #81.* ++0[0-9a-f]+ <[^>]+> f04f 031f[[:space:]]+mov\.w[[:space:]]+r3, #31.* ++0[0-9a-f]+ <[^>]+> f04f 042f[[:space:]]+mov\.w[[:space:]]+r4, #47.* ++0[0-9a-f]+ <[^>]+> f04f 053f[[:space:]]+mov\.w[[:space:]]+r5, #63.* ++0[0-9a-f]+ <[^>]+> f04f 0680[[:space:]]+mov\.w[[:space:]]+r6, #128.* ++0[0-9a-f]+ <[^>]+> f04f 07ff[[:space:]]+mov\.w[[:space:]]+r7, #255.* + 0[0-9a-f]+ <[^>]+> f04f 0800[[:space:]]+mov\.w[[:space:]]+r8, #0.* + 0[0-9a-f]+ <[^>]+> f04f 0908[[:space:]]+mov\.w[[:space:]]+r9, #8.* + 0[0-9a-f]+ <[^>]+> f04f 0a51[[:space:]]+mov\.w[[:space:]]+sl, #81.* + 0[0-9a-f]+ <[^>]+> f04f 0b1f[[:space:]]+mov\.w[[:space:]]+fp, #31.* + 0[0-9a-f]+ <[^>]+> f04f 0c2f[[:space:]]+mov\.w[[:space:]]+ip, #47.* +-0[0-9a-f]+ <[^>]+> f04f 0d3f[[:space:]]+mov\.w[[:space:]]+sp, #63.* + 0[0-9a-f]+ <[^>]+> f04f 0e80[[:space:]]+mov\.w[[:space:]]+lr, #128.* +-0[0-9a-f]+ <[^>]+> f04f 0fff[[:space:]]+mov\.w[[:space:]]+pc, #255.* ++0[0-9a-f]+ <[^>]+> f64f 78ff[[:space:]]+movw[[:space:]]+r8, #65535.* ++0[0-9a-f]+ <[^>]+> f24f 09f0[[:space:]]+movw[[:space:]]+r9, #61680.* ++0[0-9a-f]+ <[^>]+> f8df d004[[:space:]]+ldr\.w[[:space:]]+sp, \[pc, #4\].* ++0[0-9a-f]+ <[^>]+> f8df f004[[:space:]]+ldr\.w[[:space:]]+pc, \[pc, #4\].* ++0[0-9a-f]+ <[^>]+> 0000003f[[:space:]]+.word[[:space:]]+0x0000003f.* ++0[0-9a-f]+ <[^>]+> 000000ff[[:space:]]+.word[[:space:]]+0x000000ff.* +diff -rup binutils.orig/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s binutils-2.27/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s +--- binutils.orig/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s 2017-08-09 10:26:30.067741560 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s 2017-08-09 11:58:27.561952048 +0100 +@@ -2,8 +2,8 @@ + .syntax unified + .thumb_func + thumb2_ldr: +- # These can be encoded into movs since constant is small +- # And register can be encoded in 3 bits ++ # These must be encoded into mov.w despite constant and register being ++ # small enough as ldr should not generate a flag-setting instruction. + ldr r0,=0x00 + ldr r1,=0x08 + ldr r2,=0x51 +@@ -12,13 +12,19 @@ thumb2_ldr: + ldr r5,=0x3F + ldr r6,=0x80 + ldr r7,=0xFF +- # These shall be encoded into mov.w +- # Since register cannot be encoded in 3 bits ++ # These shall be encoded into mov.w since register cannot be encoded in ++ # 3 bits + ldr r8,=0x00 + ldr r9,=0x08 + ldr r10,=0x51 + ldr r11,=0x1F + ldr r12,=0x2F +- ldr r13,=0x3F + ldr r14,=0x80 ++ # These shall be encoded into movw since immediate cannot be encoded ++ # with mov.w ++ ldr r8,=0xFFFF ++ ldr r9,=0xF0F0 ++ # These should be encoded as ldr since mov immediate is unpredictable ++ # for sp and pc ++ ldr r13,=0x3F + ldr r15,=0xFF +diff -rup binutils.orig/include/opcode/arm.h binutils-2.27/include/opcode/arm.h +--- binutils.orig/include/opcode/arm.h 2017-08-09 10:26:30.209739969 +0100 ++++ binutils-2.27/include/opcode/arm.h 2017-08-09 11:11:08.487736404 +0100 +@@ -64,6 +64,8 @@ + #define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */ + #define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */ + #define ARM_EXT2_RAS 0x00000080 /* RAS extension. */ ++#define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */ ++#define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */ + + /* Co-processor space extensions. */ + #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ +@@ -92,6 +94,7 @@ + #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ + #define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */ + #define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */ ++#define FPU_NEON_EXT_DOTPROD 0x00000800 /* Dot Product extension. */ + + /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) + defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, +@@ -105,12 +108,14 @@ + #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) + #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) + #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) +-#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) +-#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) ++#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T | ARM_EXT_OS) ++#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T | ARM_EXT_OS) + #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) + #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) +-#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) +-#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) ++#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T \ ++ | ARM_EXT_OS) ++#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T \ ++ | ARM_EXT_OS) + #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) + #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) + #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) +@@ -135,7 +140,7 @@ + #define ARM_AEXT_V6M_ONLY \ + ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM)) + #define ARM_AEXT_V6M \ +- ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM)) ++ ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM | ARM_EXT_OS)) + #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) + #define ARM_AEXT_V7M \ + ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ +@@ -146,13 +151,19 @@ + #define ARM_AEXT_V8A \ + (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ + | ARM_EXT_VIRT | ARM_EXT_V8) +-#define ARM_AEXT2_V8A (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS) ++#define ARM_AEXT2_V8AR (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS) ++#define ARM_AEXT2_V8A (ARM_AEXT2_V8AR | ARM_EXT2_V8A) + #define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN) + #define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS) ++#define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A) + #define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV) + #define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M ++#define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM + #define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M) + #define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN) ++#define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN ++#define ARM_AEXT_V8R ARM_AEXT_V8A ++#define ARM_AEXT2_V8R ARM_AEXT2_V8AR + + /* Processors with specific extensions in the co-processor space. */ + #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) +@@ -224,6 +235,8 @@ + #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \ + ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \ + | FPU_NEON_EXT_RDMA) ++#define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8 \ ++ ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) + + + #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) +@@ -263,18 +276,26 @@ + #define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M) + #define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M) + #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A) ++#define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, \ ++ CRC_EXT_ARMV8) + #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, \ + CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) + #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \ + CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) ++#define ARM_ARCH_V8_3A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_3A, \ ++ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) + #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M) + #define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \ + ARM_AEXT2_V8M_MAIN) ++#define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \ ++ ARM_AEXT2_V8M_MAIN_DSP) ++#define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R) + + /* Some useful combinations: */ + #define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) + #define FPU_NONE ARM_FEATURE_LOW (0, 0) + #define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */ ++#define FPU_ANY ARM_FEATURE_COPROC (-1) /* Any FPU. */ + #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */ + #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) + /* Extensions containing some Thumb-2 instructions. If any is present, Thumb +diff -rup binutils.orig/opcodes/arm-dis.c binutils-2.27/opcodes/arm-dis.c +--- binutils.orig/opcodes/arm-dis.c 2017-08-09 10:26:30.352738367 +0100 ++++ binutils-2.27/opcodes/arm-dis.c 2017-08-09 11:44:50.913090391 +0100 +@@ -26,6 +26,7 @@ + #include "opcode/arm.h" + #include "opintl.h" + #include "safe-ctype.h" ++#include "libiberty.h" + #include "floatformat.h" + + /* FIXME: This shouldn't be done here. */ +@@ -41,10 +42,6 @@ + #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) + #endif + +-#ifndef NUM_ELEM +-#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) +-#endif +- + /* Cached mapping symbol state. */ + enum map_type + { +@@ -116,6 +113,7 @@ struct opcode16 + %G print as an iWMMXt general purpose or control register + %D print as a NEON D register + %Q print as a NEON Q register ++ %V print as a NEON D or Q register + %E print a quarter-float immediate value + + %y print a single precision VFP reg. +@@ -505,6 +503,8 @@ static const struct opcode32 coprocessor + 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, ++ {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), ++ 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), +@@ -517,6 +517,8 @@ static const struct opcode32 coprocessor + 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, ++ {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), ++ 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), +@@ -882,6 +884,34 @@ static const struct opcode32 coprocessor + 0xfc400000, 0xfff00000, + "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, + ++ /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"}, ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"}, ++ ++ /* Dot Product instructions in the space of coprocessor 13. */ ++ {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), ++ 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, ++ {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), ++ 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"}, ++ + /* V5 coprocessor instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, +@@ -971,6 +1001,10 @@ static const struct opcode32 coprocessor + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, + ++ /* ARMv8.3 javascript conversion instruction. */ ++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), ++ 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, ++ + {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} + }; + +@@ -2286,8 +2320,6 @@ static const struct opcode32 arm_opcodes + 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, +- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), +- 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, +@@ -3171,18 +3203,20 @@ arm_regname; + + static const arm_regname regnames[] = + { +- { "raw" , "Select raw register names", ++ { "reg-names-raw", N_("Select raw register names"), + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, +- { "gcc", "Select register names used by GCC", ++ { "reg-names-gcc", N_("Select register names used by GCC"), + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, +- { "std", "Select register names used in ARM's ISA documentation", ++ { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, +- { "apcs", "Select register names used in the APCS", ++ { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} }, ++ { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} }, ++ { "reg-names-apcs", N_("Select register names used in the APCS"), + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, +- { "atpcs", "Select register names used in the ATPCS", ++ { "reg-names-atpcs", N_("Select register names used in the ATPCS"), + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, +- { "special-atpcs", "Select special register names used in the ATPCS", +- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, ++ { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"), ++ { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} + }; + + static const char *const iwmmxt_wwnames[] = +@@ -3208,7 +3242,7 @@ static const char *const iwmmxt_cregname + /* Default to GCC register name set. */ + static unsigned int regname_selected = 1; + +-#define NUM_ARM_REGNAMES NUM_ELEM (regnames) ++#define NUM_ARM_REGNAMES ARRAY_SIZE (regnames) + #define arm_regnames regnames[regname_selected].reg_names + + static bfd_boolean force_thumb = FALSE; +@@ -3227,31 +3261,6 @@ static bfd_vma ifthen_address; + + + /* Functions. */ +-int +-get_arm_regname_num_options (void) +-{ +- return NUM_ARM_REGNAMES; +-} +- +-int +-set_arm_regname_option (int option) +-{ +- int old = regname_selected; +- regname_selected = option; +- return old; +-} +- +-int +-get_arm_regnames (int option, +- const char **setname, +- const char **setdescription, +- const char *const **register_names) +-{ +- *setname = regnames[option].name; +- *setdescription = regnames[option].description; +- *register_names = regnames[option].reg_names; +- return 16; +-} + + /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. + Returns pointer to following character of the format string and +@@ -3669,10 +3678,15 @@ print_insn_coprocessor (bfd_vma pc, + } + func (stream, "%s", arm_regnames[value]); + break; ++ case 'V': ++ if (given & (1 << 6)) ++ goto Q; ++ /* FALLTHROUGH */ + case 'D': + func (stream, "d%ld", value); + break; + case 'Q': ++ Q: + if (value & 1) + func (stream, "", value >> 1); + else +@@ -4686,6 +4700,7 @@ print_insn_arm (bfd_vma pc, struct disas + + case 'S': + allow_unpredictable = TRUE; ++ /* Fall through. */ + case 's': + if ((given & 0x004f0000) == 0x004f0000) + { +@@ -5427,22 +5442,31 @@ psr_name (int regno) + { + switch (regno) + { +- case 0: return "APSR"; +- case 1: return "IAPSR"; +- case 2: return "EAPSR"; +- case 3: return "PSR"; +- case 5: return "IPSR"; +- case 6: return "EPSR"; +- case 7: return "IEPSR"; +- case 8: return "MSP"; +- case 9: return "PSP"; +- case 16: return "PRIMASK"; +- case 17: return "BASEPRI"; +- case 18: return "BASEPRI_MAX"; +- case 19: return "FAULTMASK"; +- case 20: return "CONTROL"; ++ case 0x0: return "APSR"; ++ case 0x1: return "IAPSR"; ++ case 0x2: return "EAPSR"; ++ case 0x3: return "PSR"; ++ case 0x5: return "IPSR"; ++ case 0x6: return "EPSR"; ++ case 0x7: return "IEPSR"; ++ case 0x8: return "MSP"; ++ case 0x9: return "PSP"; ++ case 0xa: return "MSPLIM"; ++ case 0xb: return "PSPLIM"; ++ case 0x10: return "PRIMASK"; ++ case 0x11: return "BASEPRI"; ++ case 0x12: return "BASEPRI_MAX"; ++ case 0x13: return "FAULTMASK"; ++ case 0x14: return "CONTROL"; + case 0x88: return "MSP_NS"; + case 0x89: return "PSP_NS"; ++ case 0x8a: return "MSPLIM_NS"; ++ case 0x8b: return "PSPLIM_NS"; ++ case 0x90: return "PRIMASK_NS"; ++ case 0x91: return "BASEPRI_NS"; ++ case 0x93: return "FAULTMASK_NS"; ++ case 0x94: return "CONTROL_NS"; ++ case 0x98: return "SP_NS"; + default: return ""; + } + } +@@ -5717,7 +5741,7 @@ print_insn_thumb32 (bfd_vma pc, struct d + if (off || !U) + { + func (stream, ", #%c%u", U ? '+' : '-', off * 4); +- value_in_comment = off * 4 * U ? 1 : -1; ++ value_in_comment = off * 4 * (U ? 1 : -1); + } + func (stream, "]"); + if (W) +@@ -5729,7 +5753,7 @@ print_insn_thumb32 (bfd_vma pc, struct d + if (W) + { + func (stream, "#%c%u", U ? '+' : '-', off * 4); +- value_in_comment = off * 4 * U ? 1 : -1; ++ value_in_comment = off * 4 * (U ? 1 : -1); + } + else + { +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,2 @@ ++#as: -march=armv8.3-a+fp ++#error-output: armv8_3-a-fp-bad.l +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,7 @@ ++[^:]+: Assembler messages: ++[^:]+:3: Error: operand types can't be inferred -- `vjcvt s0,d1' ++[^:]+:4: Error: VFP single precision register expected -- `vjcvt\.s32\.f64 r0,d1' ++[^:]+:5: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f64 s0,s1' ++[^:]+:6: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f32 s0,s1' ++[^:]+:7: Error: bad type in Neon instruction -- `vjcvt\.s32\.f32 s0,d1' ++[^:]+:8: Error: bad type in Neon instruction -- `vjcvt\.f32\.f64 s0,d1' +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,8 @@ ++ .text ++ .arm ++ vjcvt s0, d1 ++ vjcvt.s32.f64 r0, d1 ++ vjcvt.s32.f64 s0, s1 ++ vjcvt.s32.f32 s0, s1 ++ vjcvt.s32.f32 s0, d1 ++ vjcvt.f32.f64 s0, d1 +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp.d binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp.d +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp.d 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,15 @@ ++#as: -march=armv8.3-a+fp ++#objdump: -dr ++#skip: *-*-pe *-wince-* *-*-coff ++ ++.*: +file format .*arm.* ++ ++Disassembly of section .text: ++ ++[0-9a-f]+ <.*>: ++ [0-9a-f]+: eef90bc7 vjcvt.s32.f64 s1, d7 ++ [0-9a-f]+: eef90bc7 vjcvt.s32.f64 s1, d7 ++ ++[0-9a-f]+ <.*>: ++ [0-9a-f]+: eef9 0bc7 vjcvt.s32.f64 s1, d7 ++ +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp.s binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp.s +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp.s 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,8 @@ ++ .text ++A1: ++ .arm ++ vjcvt.s32.f64 s1, d7 ++ vjcvtal.s32.f64 s1, d7 ++T1: ++ .thumb ++ vjcvt.s32.f64 s1, d7 +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,2 @@ ++#as: -march=armv8.3-a+fp16+simd ++#error-output: armv8_3-a-simd-bad.l +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,39 @@ ++[^:]+: Assembler messages: ++[^:]+:6: Error: operand types can't be inferred -- `vcadd d0,d1,d2,#90' ++[^:]+:7: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0' ++[^:]+:8: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180' ++[^:]+:9: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90' ++[^:]+:10: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90' ++[^:]+:11: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90' ++[^:]+:13: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90' ++[^:]+:14: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90' ++[^:]+:15: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120' ++[^:]+:16: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360' ++[^:]+:17: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90' ++[^:]+:18: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90' ++[^:]+:19: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90' ++[^:]+:21: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90' ++[^:]+:22: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90' ++[^:]+:23: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90' ++[^:]+:24: Error: scalar out of range -- `vcmla\.f16 q0,q1,d2\[2\],#90' ++[^:]+:25: Error: scalar out of range -- `vcmla\.f16 q0,q1,d16\[1\],#90' ++[^:]+:26: Error: scalar out of range -- `vcmla\.f32 q0,q1,d2\[1\],#90' ++[^:]+:31: Error: operand types can't be inferred -- `vcadd d0,d1,d2,#90' ++[^:]+:32: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0' ++[^:]+:33: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180' ++[^:]+:34: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90' ++[^:]+:35: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90' ++[^:]+:36: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90' ++[^:]+:38: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90' ++[^:]+:39: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90' ++[^:]+:40: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120' ++[^:]+:41: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360' ++[^:]+:42: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90' ++[^:]+:43: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90' ++[^:]+:44: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90' ++[^:]+:46: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90' ++[^:]+:47: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90' ++[^:]+:48: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90' ++[^:]+:49: Error: scalar out of range -- `vcmla\.f16 q0,q1,d2\[2\],#90' ++[^:]+:50: Error: scalar out of range -- `vcmla\.f16 q0,q1,d16\[1\],#90' ++[^:]+:51: Error: scalar out of range -- `vcmla\.f32 q0,q1,d2\[1\],#90' +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,51 @@ ++ .text ++ ++A1: ++ .arm ++ ++ vcadd d0,d1,d2,#90 ++ vcadd.f32 q0,q1,q2,#0 ++ vcadd.f32 q0,q1,q2,#180 ++ vcadd.f16 s0,s1,s2,#90 ++ vcadd.f64 d0,d1,d2,#90 ++ vcadd.f64 q0,q1,q2,#90 ++ ++ vcmla d0,d1,d2,#90 ++ vcmla.f32 q0,q1,q2,#-90 ++ vcmla.f32 q0,q1,q2,#120 ++ vcmla.f32 q0,q1,q2,#360 ++ vcmla.f16 s0,s1,s2,#90 ++ vcmla.f64 d0,d1,d2,#90 ++ vcmla.f64 q0,q1,q2,#90 ++ ++ vcmla.f16 q0,q1,q2[0],#90 ++ vcmla.f32 q0,q1,q2[0],#90 ++ vcmla.f16 d0,d1,d2[2],#90 ++ vcmla.f16 q0,q1,d2[2],#90 ++ vcmla.f16 q0,q1,d16[1],#90 ++ vcmla.f32 q0,q1,d2[1],#90 ++ ++T1: ++ .thumb ++ ++ vcadd d0,d1,d2,#90 ++ vcadd.f32 q0,q1,q2,#0 ++ vcadd.f32 q0,q1,q2,#180 ++ vcadd.f16 s0,s1,s2,#90 ++ vcadd.f64 d0,d1,d2,#90 ++ vcadd.f64 q0,q1,q2,#90 ++ ++ vcmla d0,d1,d2,#90 ++ vcmla.f32 q0,q1,q2,#-90 ++ vcmla.f32 q0,q1,q2,#120 ++ vcmla.f32 q0,q1,q2,#360 ++ vcmla.f16 s0,s1,s2,#90 ++ vcmla.f64 d0,d1,d2,#90 ++ vcmla.f64 q0,q1,q2,#90 ++ ++ vcmla.f16 q0,q1,q2[0],#90 ++ vcmla.f32 q0,q1,q2[0],#90 ++ vcmla.f16 d0,d1,d2[2],#90 ++ vcmla.f16 q0,q1,d2[2],#90 ++ vcmla.f16 q0,q1,d16[1],#90 ++ vcmla.f32 q0,q1,d2[1],#90 +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd.d binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd.d +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd.d 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,59 @@ ++#as: -march=armv8.3-a+fp16+simd ++#objdump: -dr ++#skip: *-*-pe *-wince-* *-*-coff ++ ++.*: +file format .*arm.* ++ ++Disassembly of section .text: ++ ++[0-9a-f]+ <.*>: ++ +[0-9a-f]+: fc942846 vcadd.f32 q1, q2, q3, #90 ++ +[0-9a-f]+: fd942846 vcadd.f32 q1, q2, q3, #270 ++ +[0-9a-f]+: fcc658a7 vcadd.f16 d21, d22, d23, #90 ++ +[0-9a-f]+: fc842846 vcadd.f16 q1, q2, q3, #90 ++ +[0-9a-f]+: fcd658a7 vcadd.f32 d21, d22, d23, #90 ++ +[0-9a-f]+: fc342846 vcmla.f32 q1, q2, q3, #0 ++ +[0-9a-f]+: fcb42846 vcmla.f32 q1, q2, q3, #90 ++ +[0-9a-f]+: fd342846 vcmla.f32 q1, q2, q3, #180 ++ +[0-9a-f]+: fdb42846 vcmla.f32 q1, q2, q3, #270 ++ +[0-9a-f]+: fce658a7 vcmla.f16 d21, d22, d23, #90 ++ +[0-9a-f]+: fca42846 vcmla.f16 q1, q2, q3, #90 ++ +[0-9a-f]+: fcf658a7 vcmla.f32 d21, d22, d23, #90 ++ +[0-9a-f]+: fe565883 vcmla.f16 d21, d22, d3\[0\], #90 ++ +[0-9a-f]+: fe5658a3 vcmla.f16 d21, d22, d3\[1\], #90 ++ +[0-9a-f]+: fe142843 vcmla.f16 q1, q2, d3\[0\], #90 ++ +[0-9a-f]+: fe142863 vcmla.f16 q1, q2, d3\[1\], #90 ++ +[0-9a-f]+: fed658a7 vcmla.f32 d21, d22, d23\[0\], #90 ++ +[0-9a-f]+: fe942867 vcmla.f32 q1, q2, d23\[0\], #90 ++ +[0-9a-f]+: fe042863 vcmla.f16 q1, q2, d3\[1\], #0 ++ +[0-9a-f]+: fe242863 vcmla.f16 q1, q2, d3\[1\], #180 ++ +[0-9a-f]+: fe342863 vcmla.f16 q1, q2, d3\[1\], #270 ++ +[0-9a-f]+: fe842843 vcmla.f32 q1, q2, d3\[0\], #0 ++ +[0-9a-f]+: fea42843 vcmla.f32 q1, q2, d3\[0\], #180 ++ +[0-9a-f]+: feb42843 vcmla.f32 q1, q2, d3\[0\], #270 ++ ++[0-9a-f]+ <.*>: ++ +[0-9a-f]+: fc94 2846 vcadd.f32 q1, q2, q3, #90 ++ +[0-9a-f]+: fd94 2846 vcadd.f32 q1, q2, q3, #270 ++ +[0-9a-f]+: fcc6 58a7 vcadd.f16 d21, d22, d23, #90 ++ +[0-9a-f]+: fc84 2846 vcadd.f16 q1, q2, q3, #90 ++ +[0-9a-f]+: fcd6 58a7 vcadd.f32 d21, d22, d23, #90 ++ +[0-9a-f]+: fc34 2846 vcmla.f32 q1, q2, q3, #0 ++ +[0-9a-f]+: fcb4 2846 vcmla.f32 q1, q2, q3, #90 ++ +[0-9a-f]+: fd34 2846 vcmla.f32 q1, q2, q3, #180 ++ +[0-9a-f]+: fdb4 2846 vcmla.f32 q1, q2, q3, #270 ++ +[0-9a-f]+: fce6 58a7 vcmla.f16 d21, d22, d23, #90 ++ +[0-9a-f]+: fca4 2846 vcmla.f16 q1, q2, q3, #90 ++ +[0-9a-f]+: fcf6 58a7 vcmla.f32 d21, d22, d23, #90 ++ +[0-9a-f]+: fe56 5883 vcmla.f16 d21, d22, d3\[0\], #90 ++ +[0-9a-f]+: fe56 58a3 vcmla.f16 d21, d22, d3\[1\], #90 ++ +[0-9a-f]+: fe14 2843 vcmla.f16 q1, q2, d3\[0\], #90 ++ +[0-9a-f]+: fe14 2863 vcmla.f16 q1, q2, d3\[1\], #90 ++ +[0-9a-f]+: fed6 58a7 vcmla.f32 d21, d22, d23\[0\], #90 ++ +[0-9a-f]+: fe94 2867 vcmla.f32 q1, q2, d23\[0\], #90 ++ +[0-9a-f]+: fe04 2863 vcmla.f16 q1, q2, d3\[1\], #0 ++ +[0-9a-f]+: fe24 2863 vcmla.f16 q1, q2, d3\[1\], #180 ++ +[0-9a-f]+: fe34 2863 vcmla.f16 q1, q2, d3\[1\], #270 ++ +[0-9a-f]+: fe84 2843 vcmla.f32 q1, q2, d3\[0\], #0 ++ +[0-9a-f]+: fea4 2843 vcmla.f32 q1, q2, d3\[0\], #180 ++ +[0-9a-f]+: feb4 2843 vcmla.f32 q1, q2, d3\[0\], #270 +diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd.s binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd.s +--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd.s 2017-08-09 12:10:22.428965485 +0100 +@@ -0,0 +1,63 @@ ++ .text ++ ++A1: ++ .arm ++ ++ vcadd.f32 q1,q2,q3,#90 ++ vcadd.f32 q1,q2,q3,#270 ++ vcadd.f16 d21,d22,d23,#90 ++ vcadd.f16 q1,q2,q3,#90 ++ vcadd.f32 d21,d22,d23,#90 ++ ++ vcmla.f32 q1,q2,q3,#0 ++ vcmla.f32 q1,q2,q3,#90 ++ vcmla.f32 q1,q2,q3,#180 ++ vcmla.f32 q1,q2,q3,#270 ++ vcmla.f16 d21,d22,d23,#90 ++ vcmla.f16 q1,q2,q3,#90 ++ vcmla.f32 d21,d22,d23,#90 ++ ++ vcmla.f16 d21,d22,d3[0],#90 ++ vcmla.f16 d21,d22,d3[1],#90 ++ vcmla.f16 q1,q2,d3[0],#90 ++ vcmla.f16 q1,q2,d3[1],#90 ++ vcmla.f32 d21,d22,d23[0],#90 ++ vcmla.f32 q1,q2,d23[0],#90 ++ ++ vcmla.f16 q1,q2,d3[1],#0 ++ vcmla.f16 q1,q2,d3[1],#180 ++ vcmla.f16 q1,q2,d3[1],#270 ++ vcmla.f32 q1,q2,d3[0],#0 ++ vcmla.f32 q1,q2,d3[0],#180 ++ vcmla.f32 q1,q2,d3[0],#270 ++ ++T1: ++ .thumb ++ ++ vcadd.f32 q1,q2,q3,#90 ++ vcadd.f32 q1,q2,q3,#270 ++ vcadd.f16 d21,d22,d23,#90 ++ vcadd.f16 q1,q2,q3,#90 ++ vcadd.f32 d21,d22,d23,#90 ++ ++ vcmla.f32 q1,q2,q3,#0 ++ vcmla.f32 q1,q2,q3,#90 ++ vcmla.f32 q1,q2,q3,#180 ++ vcmla.f32 q1,q2,q3,#270 ++ vcmla.f16 d21,d22,d23,#90 ++ vcmla.f16 q1,q2,q3,#90 ++ vcmla.f32 d21,d22,d23,#90 ++ ++ vcmla.f16 d21,d22,d3[0],#90 ++ vcmla.f16 d21,d22,d3[1],#90 ++ vcmla.f16 q1,q2,d3[0],#90 ++ vcmla.f16 q1,q2,d3[1],#90 ++ vcmla.f32 d21,d22,d23[0],#90 ++ vcmla.f32 q1,q2,d23[0],#90 ++ ++ vcmla.f16 q1,q2,d3[1],#0 ++ vcmla.f16 q1,q2,d3[1],#180 ++ vcmla.f16 q1,q2,d3[1],#270 ++ vcmla.f32 q1,q2,d3[0],#0 ++ vcmla.f32 q1,q2,d3[0],#180 ++ vcmla.f32 q1,q2,d3[0],#270 diff --git a/SOURCES/binutils-2.27-DW_AT_export_symbols.patch b/SOURCES/binutils-2.27-DW_AT_export_symbols.patch new file mode 100644 index 0000000..5994f60 --- /dev/null +++ b/SOURCES/binutils-2.27-DW_AT_export_symbols.patch @@ -0,0 +1,10 @@ +--- binutils.orig/include/dwarf2.def 2017-08-08 17:40:39.295382994 +0100 ++++ binutils-2.27/include/dwarf2.def 2017-08-08 17:44:03.672045965 +0100 +@@ -310,6 +310,7 @@ DW_AT (DW_AT_enum_class, 0x6d) + DW_AT (DW_AT_linkage_name, 0x6e) + /* DWARF 5. */ + DW_AT (DW_AT_noreturn, 0x87) ++DW_AT (DW_AT_export_symbols, 0x89) + + DW_AT_DUP (DW_AT_lo_user, 0x2000) /* Implementation-defined range start. */ + DW_AT_DUP (DW_AT_hi_user, 0x3fff) /* Implementation-defined range end. */ diff --git a/SOURCES/binutils-2.27-aarch64-copy-relocs.patch b/SOURCES/binutils-2.27-aarch64-copy-relocs.patch new file mode 100644 index 0000000..b8102b2 --- /dev/null +++ b/SOURCES/binutils-2.27-aarch64-copy-relocs.patch @@ -0,0 +1,367 @@ +diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c +index 1edf2a0..e27f067 100644 (file) +--- a/bfd/elfnn-aarch64.c ++++ b/bfd/elfnn-aarch64.c +@@ -6869,6 +6889,31 @@ elfNN_aarch64_gc_sweep_hook (bfd *abfd, + return TRUE; + } + ++/* Return true if we need copy relocation against EH. */ ++ ++static bfd_boolean ++need_copy_relocation_p (struct elf_aarch64_link_hash_entry *eh) ++{ ++ struct elf_dyn_relocs *p; ++ asection *s; ++ ++ for (p = eh->dyn_relocs; p != NULL; p = p->next) ++ { ++ /* If there is any pc-relative reference, we need to keep copy relocation ++ to avoid propagating the relocation into runtime that current glibc ++ does not support. */ ++ if (p->pc_count) ++ return TRUE; ++ ++ s = p->sec->output_section; ++ /* Need copy relocation if it's against read-only section. */ ++ if (s != NULL && (s->flags & SEC_READONLY) != 0) ++ return TRUE; ++ } ++ ++ return FALSE; ++} ++ + /* Adjust a symbol defined by a dynamic object and referenced by a + regular object. The current definition is in some section of the + dynamic object, but we're not including those sections. We have to +@@ -6942,6 +6987,19 @@ elfNN_aarch64_adjust_dynamic_symbol (struct bfd_link_info *info, + return TRUE; + } + ++ if (ELIMINATE_COPY_RELOCS) ++ { ++ struct elf_aarch64_link_hash_entry *eh; ++ /* If we didn't find any dynamic relocs in read-only sections, then ++ we'll be keeping the dynamic relocs and avoiding the copy reloc. */ ++ eh = (struct elf_aarch64_link_hash_entry *) h; ++ if (!need_copy_relocation_p (eh)) ++ { ++ h->non_got_ref = 0; ++ return TRUE; ++ } ++ } ++ + /* We must allocate the symbol in our .dynbss section, which will + become part of the .bss section of the executable. There will be + an entry for this symbol in the .dynsym section. The dynamic +diff --git a/ld/testsuite/ld-aarch64/copy-reloc-2.d b/ld/testsuite/ld-aarch64/copy-reloc-2.d +new file mode 100644 (file) +index 0000000..87ddccd +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/copy-reloc-2.d +@@ -0,0 +1,7 @@ ++.* ++DYNAMIC RELOCATION RECORDS ++OFFSET.*TYPE.*VALUE.* ++.*R_AARCH64_COPY.*global_[abcd] ++.*R_AARCH64_COPY.*global_[abcd] ++.*R_AARCH64_COPY.*global_[abcd] ++.*R_AARCH64_COPY.*global_[abcd] +diff --git a/ld/testsuite/ld-aarch64/copy-reloc-eliminate.d b/ld/testsuite/ld-aarch64/copy-reloc-eliminate.d +new file mode 100644 (file) +index 0000000..9657d65 +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/copy-reloc-eliminate.d +@@ -0,0 +1,4 @@ ++.* ++DYNAMIC RELOCATION RECORDS ++OFFSET.*TYPE.*VALUE.* ++.*R_AARCH64_ABS64.*global_a +diff --git a/ld/testsuite/ld-aarch64/copy-reloc-exe-2.s b/ld/testsuite/ld-aarch64/copy-reloc-exe-2.s +new file mode 100644 (file) +index 0000000..d83658c +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/copy-reloc-exe-2.s +@@ -0,0 +1,32 @@ ++ # expect copy relocation for all these scenarios. ++ .global p ++ .global q ++ .global r ++ .section .data.rel.ro,"aw",%progbits ++ .align 3 ++ .type p, %object ++ .size p, 8 ++p: ++ .xword global_a ++ ++ .type q, %object ++ .size q, 8 ++q: ++ .xword global_b ++ ++ .type r, %object ++ .size r, 8 ++r: ++ # Any pc-rel relocation as no dynamic linker support on AArch64. ++ .xword global_c - . ++ ++ .text ++ .global main ++main: ++ # Symbols are referenced by any other relocation against read-only ++ # section. ++ movz x0, :abs_g0_nc:global_a ++ adrp x1, global_b ++ # pc-rel. ++ adrp x2, global_d ++ add x2, x2, #:lo12:global_c +diff --git a/ld/testsuite/ld-aarch64/copy-reloc-exe-eliminate.s b/ld/testsuite/ld-aarch64/copy-reloc-exe-eliminate.s +new file mode 100644 (file) +index 0000000..33227aa +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/copy-reloc-exe-eliminate.s +@@ -0,0 +1,7 @@ ++ .global p ++ .section .data.rel.ro,"aw",%progbits ++ .align 3 ++ .type p, %object ++ .size p, 8 ++p: ++ .xword global_a +--- binutils.orig/ld/testsuite/ld-aarch64/copy-reloc-so.s 2017-10-10 16:56:06.347550451 +0100 ++++ binutils-2.27/ld/testsuite/ld-aarch64/copy-reloc-so.s 2017-10-10 16:56:25.926321182 +0100 +@@ -1,6 +1,25 @@ + .global global_a + .type global_a, %object + .size global_a, 4 ++ ++ .global global_b ++ .type global_b, %object ++ .size global_b, 4 ++ ++ .global global_c ++ .type global_c, %object ++ .size global_c, 4 ++ ++ .global global_d ++ .type global_d, %object ++ .size global_d, 4 ++ + .data + global_a: + .word 0xcafedead ++global_b: ++ .word 0xcafecafe ++global_c: ++ .word 0xdeadcafe ++global_d: ++ .word 0xdeaddead +--- binutils.orig/ld/testsuite/ld-aarch64/aarch64-elf.exp 2017-10-10 16:56:06.347550451 +0100 ++++ binutils-2.27/ld/testsuite/ld-aarch64/aarch64-elf.exp 2017-10-10 16:58:19.629989701 +0100 +@@ -292,6 +292,10 @@ set aarch64elflinktests { + {} "copy-reloc-so.so"} + {"ld-aarch64/exe with copy relocation" "-e0 tmpdir/copy-reloc-so.so" "" "" + {copy-reloc-exe.s} {{objdump -R copy-reloc.d}} "copy-reloc"} ++ {"ld-aarch64/exe with copy relocation 2" "-e0 tmpdir/copy-reloc-so.so" "" "" ++ {copy-reloc-exe-2.s} {{objdump -R copy-reloc-2.d}} "copy-reloc-2"} ++ {"ld-aarch64/exe with copy relocation elimination" "-e0 tmpdir/copy-reloc-so.so" "" "" ++ {copy-reloc-exe-eliminate.s} {{objdump -R copy-reloc-eliminate.d}} "copy-reloc-elimination"} + } + + run_ld_link_tests $aarch64elflinktests +--- binutils.orig/bfd/elfnn-aarch64.c 2017-10-10 16:56:05.783557056 +0100 ++++ binutils-2.27/bfd/elfnn-aarch64.c 2017-10-10 17:15:02.559298576 +0100 +@@ -246,7 +246,7 @@ + || (R_TYPE) == BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC \ + || (R_TYPE) == BFD_RELOC_AARCH64_TLSDESC_OFF_G1) + +-#define ELIMINATE_COPY_RELOCS 0 ++#define ELIMINATE_COPY_RELOCS 1 + + /* Return size of a relocation entry. HTAB is the bfd's + elf_aarch64_link_hash_entry. */ +@@ -5154,12 +5154,25 @@ elfNN_aarch64_final_link_relocate (reloc + /* When generating a shared object or relocatable executable, these + relocations are copied into the output file to be resolved at + run time. */ +- if (((bfd_link_pic (info) == TRUE) +- || globals->root.is_relocatable_executable) +- && (input_section->flags & SEC_ALLOC) +- && (h == NULL +- || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT +- || h->root.type != bfd_link_hash_undefweak)) ++ if ((((bfd_link_pic (info) == TRUE) ++ || globals->root.is_relocatable_executable) ++ && (input_section->flags & SEC_ALLOC) ++ && (h == NULL ++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT ++ || h->root.type != bfd_link_hash_undefweak)) ++ /* Or we are creating an executable, we may need to keep relocations ++ for symbols satisfied by a dynamic library if we manage to avoid ++ copy relocs for the symbol. */ ++ || (ELIMINATE_COPY_RELOCS ++ && !bfd_link_pic (info) ++ && h != NULL ++ && (input_section->flags & SEC_ALLOC) ++ && h->dynindx != -1 ++ && !h->non_got_ref ++ && ((h->def_dynamic ++ && !h->def_regular) ++ || h->root.type == bfd_link_hash_undefweak ++ || h->root.type == bfd_link_hash_undefined))) + { + Elf_Internal_Rela outrel; + bfd_byte *loc; +@@ -6777,15 +6790,22 @@ elfNN_aarch64_gc_sweep_hook (bfd *abfd, + h->plt.refcount -= 1; + break; + ++ case BFD_RELOC_AARCH64_ADD_LO12: + case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: + case BFD_RELOC_AARCH64_ADR_HI21_PCREL: + case BFD_RELOC_AARCH64_ADR_LO21_PCREL: ++ case BFD_RELOC_AARCH64_LDST128_LO12: ++ case BFD_RELOC_AARCH64_LDST16_LO12: ++ case BFD_RELOC_AARCH64_LDST32_LO12: ++ case BFD_RELOC_AARCH64_LDST64_LO12: ++ case BFD_RELOC_AARCH64_LDST8_LO12: ++ case BFD_RELOC_AARCH64_LD_LO19_PCREL: + case BFD_RELOC_AARCH64_MOVW_G0_NC: + case BFD_RELOC_AARCH64_MOVW_G1_NC: + case BFD_RELOC_AARCH64_MOVW_G2_NC: + case BFD_RELOC_AARCH64_MOVW_G3: + case BFD_RELOC_AARCH64_NN: +- if (h != NULL && bfd_link_executable (info)) ++ if (h != NULL && bfd_link_pic (info)) + { + if (h->plt.refcount > 0) + h->plt.refcount -= 1; +@@ -7158,6 +7178,41 @@ elfNN_aarch64_check_relocs (bfd *abfd, s + + switch (bfd_r_type) + { ++ case BFD_RELOC_AARCH64_MOVW_G0_NC: ++ case BFD_RELOC_AARCH64_MOVW_G1_NC: ++ case BFD_RELOC_AARCH64_MOVW_G2_NC: ++ case BFD_RELOC_AARCH64_MOVW_G3: ++ if (bfd_link_pic (info)) ++ { ++ int howto_index = bfd_r_type - BFD_RELOC_AARCH64_RELOC_START; ++ _bfd_error_handler ++ /* xgettext:c-format */ ++ (_("%B: relocation %s against `%s' can not be used when making " ++ "a shared object; recompile with -fPIC"), ++ abfd, elfNN_aarch64_howto_table[howto_index].name, ++ (h) ? h->root.root.string : "a local symbol"); ++ bfd_set_error (bfd_error_bad_value); ++ return FALSE; ++ } ++ /* Fall through. */ ++ ++ case BFD_RELOC_AARCH64_16_PCREL: ++ case BFD_RELOC_AARCH64_32_PCREL: ++ case BFD_RELOC_AARCH64_64_PCREL: ++ case BFD_RELOC_AARCH64_ADD_LO12: ++ case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: ++ case BFD_RELOC_AARCH64_ADR_HI21_PCREL: ++ case BFD_RELOC_AARCH64_ADR_LO21_PCREL: ++ case BFD_RELOC_AARCH64_LDST128_LO12: ++ case BFD_RELOC_AARCH64_LDST16_LO12: ++ case BFD_RELOC_AARCH64_LDST32_LO12: ++ case BFD_RELOC_AARCH64_LDST64_LO12: ++ case BFD_RELOC_AARCH64_LDST8_LO12: ++ case BFD_RELOC_AARCH64_LD_LO19_PCREL: ++ if (h == NULL || bfd_link_pic (info)) ++ break; ++ /* Fall through. */ ++ + case BFD_RELOC_AARCH64_NN: + + /* We don't need to handle relocs into sections not going into +@@ -7176,12 +7231,32 @@ elfNN_aarch64_check_relocs (bfd *abfd, s + + /* No need to do anything if we're not creating a shared + object. */ +- if (! bfd_link_pic (info)) +- break; ++ if (!(bfd_link_pic (info) ++ /* If on the other hand, we are creating an executable, we ++ may need to keep relocations for symbols satisfied by a ++ dynamic library if we manage to avoid copy relocs for the ++ symbol. ++ ++ NOTE: Currently, there is no support of copy relocs ++ elimination on pc-relative relocation types, because there is ++ no dynamic relocation support for them in glibc. We still ++ record the dynamic symbol reference for them. This is ++ because one symbol may be referenced by both absolute ++ relocation (for example, BFD_RELOC_AARCH64_NN) and ++ pc-relative relocation. We need full symbol reference ++ information to make correct decision later in ++ elfNN_aarch64_adjust_dynamic_symbol. */ ++ || (ELIMINATE_COPY_RELOCS ++ && !bfd_link_pic (info) ++ && h != NULL ++ && (h->root.type == bfd_link_hash_defweak ++ || !h->def_regular)))) ++ break; + + { + struct elf_dyn_relocs *p; + struct elf_dyn_relocs **head; ++ int howto_index = bfd_r_type - BFD_RELOC_AARCH64_RELOC_START; + + /* We must copy these reloc types into the output file. + Create a reloc section in dynobj and make room for +@@ -7245,6 +7320,8 @@ elfNN_aarch64_check_relocs (bfd *abfd, s + + p->count += 1; + ++ if (elfNN_aarch64_howto_table[howto_index].pc_relative) ++ p->pc_count += 1; + } + break; + +@@ -7348,42 +7425,6 @@ elfNN_aarch64_check_relocs (bfd *abfd, s + break; + } + +- case BFD_RELOC_AARCH64_MOVW_G0_NC: +- case BFD_RELOC_AARCH64_MOVW_G1_NC: +- case BFD_RELOC_AARCH64_MOVW_G2_NC: +- case BFD_RELOC_AARCH64_MOVW_G3: +- if (bfd_link_pic (info)) +- { +- int howto_index = bfd_r_type - BFD_RELOC_AARCH64_RELOC_START; +- (*_bfd_error_handler) +- (_("%B: relocation %s against `%s' can not be used when making " +- "a shared object; recompile with -fPIC"), +- abfd, elfNN_aarch64_howto_table[howto_index].name, +- (h) ? h->root.root.string : "a local symbol"); +- bfd_set_error (bfd_error_bad_value); +- return FALSE; +- } +- +- case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: +- case BFD_RELOC_AARCH64_ADR_HI21_PCREL: +- case BFD_RELOC_AARCH64_ADR_LO21_PCREL: +- if (h != NULL && bfd_link_executable (info)) +- { +- /* If this reloc is in a read-only section, we might +- need a copy reloc. We can't check reliably at this +- stage whether the section is read-only, as input +- sections have not yet been mapped to output sections. +- Tentatively set the flag for now, and correct in +- adjust_dynamic_symbol. */ +- h->non_got_ref = 1; +- h->plt.refcount += 1; +- h->pointer_equality_needed = 1; +- } +- /* FIXME:: RR need to handle these in shared libraries +- and essentially bomb out as these being non-PIC +- relocations in shared libraries. */ +- break; +- + case BFD_RELOC_AARCH64_CALL26: + case BFD_RELOC_AARCH64_JUMP26: + /* If this is a local symbol then we resolve it diff --git a/SOURCES/binutils-2.27-cve-bugs.patch b/SOURCES/binutils-2.27-cve-bugs.patch new file mode 100644 index 0000000..f835e1e --- /dev/null +++ b/SOURCES/binutils-2.27-cve-bugs.patch @@ -0,0 +1,2317 @@ +diff -rup binutils.orig/bfd/aoutx.h binutils-2.27/bfd/aoutx.h +--- binutils.orig/bfd/aoutx.h 2017-03-24 13:50:55.358188013 +0000 ++++ binutils-2.27/bfd/aoutx.h 2017-03-24 14:26:38.438542134 +0000 +@@ -2807,9 +2807,17 @@ NAME (aout, find_nearest_line) (bfd *abf + *filename_ptr = main_file_name; + else + { +- sprintf (buf, "%s%s", directory_name, main_file_name); +- *filename_ptr = buf; +- buf += filelen + 1; ++ if (buf == NULL) ++ /* PR binutils/20891: In a corrupt input file both ++ main_file_name and directory_name can be empty... */ ++ * filename_ptr = NULL; ++ else ++ { ++ snprintf (buf, filelen + 1, "%s%s", directory_name, ++ main_file_name); ++ *filename_ptr = buf; ++ buf += filelen + 1; ++ } + } + } + +@@ -2818,6 +2826,13 @@ NAME (aout, find_nearest_line) (bfd *abf + const char *function = func->name; + char *colon; + ++ if (buf == NULL) ++ { ++ /* PR binutils/20892: In a corrupt input file func can be empty. */ ++ * functionname_ptr = NULL; ++ return TRUE; ++ } ++ + /* The caller expects a symbol name. We actually have a + function name, without the leading underscore. Put the + underscore back in, so that the caller gets a symbol name. */ +diff -rup binutils.orig/bfd/compress.c binutils-2.27/bfd/compress.c +--- binutils.orig/bfd/compress.c 2017-03-24 13:50:55.362187961 +0000 ++++ binutils-2.27/bfd/compress.c 2017-03-24 14:17:49.075366778 +0000 +@@ -292,7 +292,7 @@ bfd_get_full_section_contents (bfd *abfd + SHF_COMPRESSED section. */ + compression_header_size = 12; + if (!decompress_contents (compressed_buffer + compression_header_size, +- sec->compressed_size, p, sz)) ++ sec->compressed_size - compression_header_size, p, sz)) + { + bfd_set_error (bfd_error_bad_value); + if (p != *ptr) +diff -rup binutils.orig/bfd/peicode.h binutils-2.27/bfd/peicode.h +--- binutils.orig/bfd/peicode.h 2017-03-24 13:50:55.374187806 +0000 ++++ binutils-2.27/bfd/peicode.h 2017-03-24 14:22:36.326663483 +0000 +@@ -1264,7 +1264,8 @@ pe_ILF_object_p (bfd * abfd) + } + + symbol_name = (char *) ptr; +- source_dll = symbol_name + strlen (symbol_name) + 1; ++ /* See PR 20905 for an example of where the strnlen is necessary. */ ++ source_dll = symbol_name + strnlen (symbol_name, size - 1) + 1; + + /* Verify that the strings are null terminated. */ + if (ptr[size - 1] != 0 +diff -rup binutils.orig/binutils/dwarf.c binutils-2.27/binutils/dwarf.c +--- binutils.orig/binutils/dwarf.c 2017-03-24 13:50:55.381187716 +0000 ++++ binutils-2.27/binutils/dwarf.c 2017-03-24 13:58:05.061648769 +0000 +@@ -76,7 +76,6 @@ int dwarf_check = 0; + as a zero-terminated list of section indexes comprising one set of debug + sections from a .dwo file. */ + +-static int cu_tu_indexes_read = 0; + static unsigned int *shndx_pool = NULL; + static unsigned int shndx_pool_size = 0; + static unsigned int shndx_pool_used = 0; +@@ -99,7 +98,7 @@ static int tu_count = 0; + static struct cu_tu_set *cu_sets = NULL; + static struct cu_tu_set *tu_sets = NULL; + +-static void load_cu_tu_indexes (void *file); ++static bfd_boolean load_cu_tu_indexes (void *); + + /* Values for do_debug_lines. */ + #define FLAG_DEBUG_LINES_RAW 1 +@@ -2713,7 +2712,7 @@ load_debug_info (void * file) + return num_debug_info_entries; + + /* If this is a DWARF package file, load the CU and TU indexes. */ +- load_cu_tu_indexes (file); ++ (void) load_cu_tu_indexes (file); + + if (load_debug_section (info, file) + && process_debug_info (&debug_displays [info].section, file, abbrev, 1, 0)) +@@ -7302,21 +7301,27 @@ process_cu_tu_index (struct dwarf_sectio + section sets that we can use to associate a .debug_info.dwo section + with its associated .debug_abbrev.dwo section in a .dwp file. */ + +-static void ++static bfd_boolean + load_cu_tu_indexes (void *file) + { ++ static int cu_tu_indexes_read = -1; /* Tri-state variable. */ ++ + /* If we have already loaded (or tried to load) the CU and TU indexes + then do not bother to repeat the task. */ +- if (cu_tu_indexes_read) +- return; +- +- if (load_debug_section (dwp_cu_index, file)) +- process_cu_tu_index (&debug_displays [dwp_cu_index].section, 0); ++ if (cu_tu_indexes_read == -1) ++ { ++ cu_tu_indexes_read = TRUE; ++ ++ if (load_debug_section (dwp_cu_index, file)) ++ if (! process_cu_tu_index (&debug_displays [dwp_cu_index].section, 0)) ++ cu_tu_indexes_read = FALSE; + +- if (load_debug_section (dwp_tu_index, file)) +- process_cu_tu_index (&debug_displays [dwp_tu_index].section, 0); ++ if (load_debug_section (dwp_tu_index, file)) ++ if (! process_cu_tu_index (&debug_displays [dwp_tu_index].section, 0)) ++ cu_tu_indexes_read = FALSE; ++ } + +- cu_tu_indexes_read = 1; ++ return (bfd_boolean) cu_tu_indexes_read; + } + + /* Find the set of sections that includes section SHNDX. */ +@@ -7326,7 +7331,8 @@ find_cu_tu_set (void *file, unsigned int + { + unsigned int i; + +- load_cu_tu_indexes (file); ++ if (! load_cu_tu_indexes (file)) ++ return NULL; + + /* Find SHNDX in the shndx pool. */ + for (i = 0; i < shndx_pool_used; i++) +diff -rup binutils.orig/binutils/readelf.c binutils-2.27/binutils/readelf.c +--- binutils.orig/binutils/readelf.c 2017-03-24 13:50:55.390187599 +0000 ++++ binutils-2.27/binutils/readelf.c 2017-03-24 14:16:39.008271196 +0000 +@@ -674,8 +674,14 @@ find_section_in_set (const char * name, + if (set != NULL) + { + while ((i = *set++) > 0) +- if (streq (SECTION_NAME (section_headers + i), name)) +- return section_headers + i; ++ { ++ /* See PR 21156 for a reproducer. */ ++ if (i >= elf_header.e_shnum) ++ continue; /* FIXME: Should we issue an error message ? */ ++ ++ if (streq (SECTION_NAME (section_headers + i), name)) ++ return section_headers + i; ++ } + } + + return find_section (name); +@@ -11342,16 +11348,32 @@ process_syminfo (FILE * file ATTRIBUTE_U + return 1; + } + ++#define IN_RANGE(START,END,ADDR,OFF) \ ++ (((ADDR) >= (START)) && ((ADDR) + (OFF) < (END))) ++ + /* Check to see if the given reloc needs to be handled in a target specific + manner. If so then process the reloc and return TRUE otherwise return +- FALSE. */ ++ FALSE. ++ ++ If called with reloc == NULL, then this is a signal that reloc processing ++ for the current section has finished, and any saved state should be ++ discarded. */ + + static bfd_boolean + target_specific_reloc_handling (Elf_Internal_Rela * reloc, + unsigned char * start, +- Elf_Internal_Sym * symtab) ++ unsigned char * end, ++ Elf_Internal_Sym * symtab, ++ unsigned long num_syms) + { +- unsigned int reloc_type = get_reloc_type (reloc->r_info); ++ unsigned int reloc_type = 0; ++ unsigned long sym_index = 0; ++ ++ if (reloc) ++ { ++ reloc_type = get_reloc_type (reloc->r_info); ++ sym_index = get_reloc_symindex (reloc->r_info); ++ } + + switch (elf_header.e_machine) + { +@@ -11360,13 +11382,25 @@ target_specific_reloc_handling (Elf_Inte + { + static Elf_Internal_Sym * saved_sym = NULL; + ++ if (reloc == NULL) ++ { ++ saved_sym = NULL; ++ return TRUE; ++ } ++ + switch (reloc_type) + { + case 10: /* R_MSP430_SYM_DIFF */ + if (uses_msp430x_relocs ()) + break; ++ /* Fall through. */ + case 21: /* R_MSP430X_SYM_DIFF */ +- saved_sym = symtab + get_reloc_symindex (reloc->r_info); ++ /* PR 21139. */ ++ if (sym_index >= num_syms) ++ error (_("MSP430 SYM_DIFF reloc contains invalid symbol index %lu\n"), ++ sym_index); ++ else ++ saved_sym = symtab + sym_index; + return TRUE; + + case 1: /* R_MSP430_32 or R_MSP430_ABS32 */ +@@ -11388,13 +11422,24 @@ target_specific_reloc_handling (Elf_Inte + handle_sym_diff: + if (saved_sym != NULL) + { ++ int reloc_size = reloc_type == 1 ? 4 : 2; + bfd_vma value; + +- value = reloc->r_addend +- + (symtab[get_reloc_symindex (reloc->r_info)].st_value +- - saved_sym->st_value); ++ if (sym_index >= num_syms) ++ error (_("MSP430 reloc contains invalid symbol index %lu\n"), ++ sym_index); ++ else ++ { ++ value = reloc->r_addend + (symtab[sym_index].st_value ++ - saved_sym->st_value); + +- byte_put (start + reloc->r_offset, value, reloc_type == 1 ? 4 : 2); ++ if (IN_RANGE (start, end, start + reloc->r_offset, reloc_size)) ++ byte_put (start + reloc->r_offset, value, reloc_size); ++ else ++ /* PR 21137 */ ++ error (_("MSP430 sym diff reloc contains invalid offset: 0x%lx\n"), ++ (long) reloc->r_offset); ++ } + + saved_sym = NULL; + return TRUE; +@@ -11414,24 +11459,46 @@ target_specific_reloc_handling (Elf_Inte + { + static Elf_Internal_Sym * saved_sym = NULL; + ++ if (reloc == NULL) ++ { ++ saved_sym = NULL; ++ return TRUE; ++ } ++ + switch (reloc_type) + { + case 34: /* R_MN10300_ALIGN */ + return TRUE; ++ + case 33: /* R_MN10300_SYM_DIFF */ +- saved_sym = symtab + get_reloc_symindex (reloc->r_info); ++ if (sym_index >= num_syms) ++ error (_("MN10300_SYM_DIFF reloc contains invalid symbol index %lu\n"), ++ sym_index); ++ else ++ saved_sym = symtab + sym_index; + return TRUE; ++ + case 1: /* R_MN10300_32 */ + case 2: /* R_MN10300_16 */ + if (saved_sym != NULL) + { ++ int reloc_size = reloc_type == 1 ? 4 : 2; + bfd_vma value; + +- value = reloc->r_addend +- + (symtab[get_reloc_symindex (reloc->r_info)].st_value +- - saved_sym->st_value); ++ if (sym_index >= num_syms) ++ error (_("MN10300 reloc contains invalid symbol index %lu\n"), ++ sym_index); ++ else ++ { ++ value = reloc->r_addend + (symtab[sym_index].st_value ++ - saved_sym->st_value); + +- byte_put (start + reloc->r_offset, value, reloc_type == 1 ? 4 : 2); ++ if (IN_RANGE (start, end, start + reloc->r_offset, reloc_size)) ++ byte_put (start + reloc->r_offset, value, reloc_size); ++ else ++ error (_("MN10300 sym diff reloc contains invalid offset: 0x%lx\n"), ++ (long) reloc->r_offset); ++ } + + saved_sym = NULL; + return TRUE; +@@ -11451,12 +11518,24 @@ target_specific_reloc_handling (Elf_Inte + static bfd_vma saved_sym2 = 0; + static bfd_vma value; + ++ if (reloc == NULL) ++ { ++ saved_sym1 = saved_sym2 = 0; ++ return TRUE; ++ } ++ + switch (reloc_type) + { + case 0x80: /* R_RL78_SYM. */ + saved_sym1 = saved_sym2; +- saved_sym2 = symtab[get_reloc_symindex (reloc->r_info)].st_value; +- saved_sym2 += reloc->r_addend; ++ if (sym_index >= num_syms) ++ error (_("RL78_SYM reloc contains invalid symbol index %lu\n"), ++ sym_index); ++ else ++ { ++ saved_sym2 = symtab[sym_index].st_value; ++ saved_sym2 += reloc->r_addend; ++ } + return TRUE; + + case 0x83: /* R_RL78_OPsub. */ +@@ -11466,12 +11545,20 @@ target_specific_reloc_handling (Elf_Inte + break; + + case 0x41: /* R_RL78_ABS32. */ +- byte_put (start + reloc->r_offset, value, 4); ++ if (IN_RANGE (start, end, start + reloc->r_offset, 4)) ++ byte_put (start + reloc->r_offset, value, 4); ++ else ++ error (_("RL78 sym diff reloc contains invalid offset: 0x%lx\n"), ++ (long) reloc->r_offset); + value = 0; + return TRUE; + + case 0x43: /* R_RL78_ABS16. */ +- byte_put (start + reloc->r_offset, value, 2); ++ if (IN_RANGE (start, end, start + reloc->r_offset, 2)) ++ byte_put (start + reloc->r_offset, value, 2); ++ else ++ error (_("RL78 sym diff reloc contains invalid offset: 0x%lx\n"), ++ (long) reloc->r_offset); + value = 0; + return TRUE; + +@@ -12078,7 +12165,7 @@ apply_relocations (void * + + reloc_type = get_reloc_type (rp->r_info); + +- if (target_specific_reloc_handling (rp, start, symtab)) ++ if (target_specific_reloc_handling (rp, start, end, symtab, num_syms)) + continue; + else if (is_none_reloc (reloc_type)) + continue; +@@ -12174,6 +12261,9 @@ apply_relocations (void * + } + + free (symtab); ++ /* Let the target specific reloc processing code know that ++ we have finished with these relocs. */ ++ target_specific_reloc_handling (NULL, NULL, NULL, NULL, 0); + + if (relocs_return) + { +@@ -12471,10 +12561,18 @@ dump_section_as_bytes (Elf_Internal_Shdr + new_size -= 12; + } + +- if (uncompressed_size +- && uncompress_section_contents (& start, uncompressed_size, +- & new_size)) +- section_size = new_size; ++ if (uncompressed_size) ++ { ++ if (uncompress_section_contents (& start, uncompressed_size, ++ & new_size)) ++ section_size = new_size; ++ else ++ { ++ error (_("Unable to decompress section %s\n"), ++ printable_section_name (section)); ++ return; ++ } ++ } + } + + if (relocate) +diff -rup binutils.orig/binutils/stabs.c binutils-2.27/binutils/stabs.c +--- binutils.orig/binutils/stabs.c 2017-03-24 13:50:55.386187651 +0000 ++++ binutils-2.27/binutils/stabs.c 2017-03-24 14:14:20.823055085 +0000 +@@ -232,6 +232,10 @@ parse_number (const char **pp, bfd_boole + + orig = *pp; + ++ /* Stop early if we are passed an empty string. */ ++ if (*orig == 0) ++ return (bfd_vma) 0; ++ + errno = 0; + ul = strtoul (*pp, (char **) pp, 0); + if (ul + 1 != 0 || errno == 0) +@@ -1975,9 +1979,17 @@ parse_stab_enum_type (void *dhandle, con + bfd_signed_vma val; + + p = *pp; +- while (*p != ':') ++ while (*p != ':' && *p != 0) + ++p; + ++ if (*p == 0) ++ { ++ bad_stab (orig); ++ free (names); ++ free (values); ++ return DEBUG_TYPE_NULL; ++ } ++ + name = savestring (*pp, p - *pp); + + *pp = p + 1; +diff -rup binutils.orig/gas/app.c binutils-2.27/gas/app.c +--- binutils.orig/gas/app.c 2017-03-24 13:50:55.395187534 +0000 ++++ binutils-2.27/gas/app.c 2017-03-24 13:52:02.141327121 +0000 +@@ -1187,7 +1187,7 @@ do_scrub_chars (size_t (*get) (char *, s + state = -2; + break; + } +- else ++ else if (ch2 != EOF) + { + UNGET (ch2); + } +diff -rup binutils.orig/ld/ldlex.c binutils-2.27/ld/ldlex.c +--- binutils.orig/ld/ldlex.c 2017-03-24 13:50:55.613184724 +0000 ++++ binutils-2.27/ld/ldlex.c 2017-03-24 14:20:47.319068827 +0000 +@@ -1,5 +1,5 @@ + +-#line 3 "ldlex.c" ++#line 3 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.c" + + #define YY_INT_ALIGNED short int + +@@ -7,8 +7,8 @@ + + #define FLEX_SCANNER + #define YY_FLEX_MAJOR_VERSION 2 +-#define YY_FLEX_MINOR_VERSION 5 +-#define YY_FLEX_SUBMINOR_VERSION 35 ++#define YY_FLEX_MINOR_VERSION 6 ++#define YY_FLEX_SUBMINOR_VERSION 0 + #if YY_FLEX_SUBMINOR_VERSION > 0 + #define FLEX_BETA + #endif +@@ -46,7 +46,6 @@ typedef int16_t flex_int16_t; + typedef uint16_t flex_uint16_t; + typedef int32_t flex_int32_t; + typedef uint32_t flex_uint32_t; +-typedef uint64_t flex_uint64_t; + #else + typedef signed char flex_int8_t; + typedef short int flex_int16_t; +@@ -54,7 +53,6 @@ typedef int flex_int32_t; + typedef unsigned char flex_uint8_t; + typedef unsigned short int flex_uint16_t; + typedef unsigned int flex_uint32_t; +-#endif /* ! C99 */ + + /* Limits of integral types. */ + #ifndef INT8_MIN +@@ -85,6 +83,8 @@ typedef unsigned int flex_uint32_t; + #define UINT32_MAX (4294967295U) + #endif + ++#endif /* ! C99 */ ++ + #endif /* ! FLEXINT_H */ + + #ifdef __cplusplus +@@ -141,7 +141,15 @@ typedef unsigned int flex_uint32_t; + + /* Size of default input buffer. */ + #ifndef YY_BUF_SIZE ++#ifdef __ia64__ ++/* On IA-64, the buffer size is 16k, not 8k. ++ * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case. ++ * Ditto for the __ia64__ case accordingly. ++ */ ++#define YY_BUF_SIZE 32768 ++#else + #define YY_BUF_SIZE 16384 ++#endif /* __ia64__ */ + #endif + + /* The state buf must be large enough to hold one state per character in the main buffer. +@@ -167,13 +175,14 @@ extern FILE *yyin, *yyout; + #define EOB_ACT_LAST_MATCH 2 + + #define YY_LESS_LINENO(n) ++ #define YY_LINENO_REWIND_TO(ptr) + + /* Return all but the first "n" matched characters back to the input stream. */ + #define yyless(n) \ + do \ + { \ + /* Undo effects of setting up yytext. */ \ +- int yyless_macro_arg = (n); \ ++ yy_size_t yyless_macro_arg = (n); \ + YY_LESS_LINENO(yyless_macro_arg);\ + *yy_cp = (yy_hold_char); \ + YY_RESTORE_YY_MORE_OFFSET \ +@@ -343,11 +352,17 @@ extern int yylineno; + int yylineno = 1; + + extern char *yytext; ++#ifdef yytext_ptr ++#undef yytext_ptr ++#endif + #define yytext_ptr yytext + + static yy_state_type yy_get_previous_state (void ); + static yy_state_type yy_try_NUL_trans (yy_state_type current_state ); + static int yy_get_next_buffer (void ); ++#if defined(__GNUC__) && __GNUC__ >= 3 ++__attribute__((__noreturn__)) ++#endif + static void yy_fatal_error (yyconst char msg[] ); + + /* Done after the current pattern has been matched and before the +@@ -355,7 +370,7 @@ static void yy_fatal_error (yyconst char + */ + #define YY_DO_BEFORE_ACTION \ + (yytext_ptr) = yy_bp; \ +- yyleng = (yy_size_t) (yy_cp - yy_bp); \ ++ yyleng = (size_t) (yy_cp - yy_bp); \ + (yy_hold_char) = *yy_cp; \ + *yy_cp = '\0'; \ + (yy_c_buf_p) = yy_cp; +@@ -568,7 +583,7 @@ static yyconst flex_int16_t yy_accept[17 + 174, 84, 84, 0 + } ; + +-static yyconst flex_int32_t yy_ec[256] = ++static yyconst YY_CHAR yy_ec[256] = + { 0, + 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, + 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, +@@ -600,7 +615,7 @@ static yyconst flex_int32_t yy_ec[256] = + 1, 1, 1, 1, 1 + } ; + +-static yyconst flex_int32_t yy_meta[83] = ++static yyconst YY_CHAR yy_meta[83] = + { 0, + 1, 1, 2, 3, 1, 1, 4, 1, 1, 1, + 1, 3, 5, 6, 7, 8, 9, 10, 10, 10, +@@ -613,7 +628,7 @@ static yyconst flex_int32_t yy_meta[83] + 1, 9 + } ; + +-static yyconst flex_int16_t yy_base[1807] = ++static yyconst flex_uint16_t yy_base[1807] = + { 0, + 0, 0, 0, 0, 82, 163, 244, 0, 326, 0, + 408, 489, 570, 0, 112, 114, 652, 734, 816, 898, +@@ -1019,7 +1034,7 @@ static yyconst flex_int16_t yy_def[1807] + 1774, 1774, 1774, 1774, 1774, 1774 + } ; + +-static yyconst flex_int16_t yy_nxt[2940] = ++static yyconst flex_uint16_t yy_nxt[2940] = + { 0, + 23, 24, 25, 26, 27, 23, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, 40, 40, +@@ -1687,8 +1702,8 @@ int yy_flex_debug = 0; + #define YY_MORE_ADJ 0 + #define YY_RESTORE_YY_MORE_OFFSET + char *yytext; +-#line 1 "ldlex.l" +-#line 4 "ldlex.l" ++#line 1 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" ++#line 4 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + + /* Copyright (C) 1991-2016 Free Software Foundation, Inc. + Written by Steve Chamberlain of Cygnus Support. +@@ -1788,7 +1803,7 @@ int yywrap (void) { return 1; } + + + +-#line 1792 "ldlex.c" ++#line 1807 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.c" + + #define INITIAL 0 + #define SCRIPT 1 +@@ -1830,11 +1845,11 @@ void yyset_extra (YY_EXTRA_TYPE user_def + + FILE *yyget_in (void ); + +-void yyset_in (FILE * in_str ); ++void yyset_in (FILE * _in_str ); + + FILE *yyget_out (void ); + +-void yyset_out (FILE * out_str ); ++void yyset_out (FILE * _out_str ); + + yy_size_t yyget_leng (void ); + +@@ -1842,7 +1857,7 @@ char *yyget_text (void ); + + int yyget_lineno (void ); + +-void yyset_lineno (int line_number ); ++void yyset_lineno (int _line_number ); + + /* Macros after this point can all be overridden by user definitions in + * section 1. +@@ -1856,6 +1871,10 @@ extern int yywrap (void ); + #endif + #endif + ++#ifndef YY_NO_UNPUT ++ ++#endif ++ + #ifndef yytext_ptr + static void yy_flex_strncpy (char *,yyconst char *,int ); + #endif +@@ -1876,7 +1895,12 @@ static int input (void ); + + /* Amount of stuff to slurp up with each read. */ + #ifndef YY_READ_BUF_SIZE ++#ifdef __ia64__ ++/* On IA-64, the buffer size is 16k, not 8k */ ++#define YY_READ_BUF_SIZE 16384 ++#else + #define YY_READ_BUF_SIZE 8192 ++#endif /* __ia64__ */ + #endif + + /* Copy whatever the last rule matched to the standard output. */ +@@ -1884,7 +1908,7 @@ static int input (void ); + /* This used to be an fputs(), but since the string might contain NUL's, + * we now use fwrite(). + */ +-#define ECHO fwrite( yytext, yyleng, 1, yyout ) ++#define ECHO do { if (fwrite( yytext, yyleng, 1, yyout )) {} } while (0) + #endif + + /* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, +@@ -1895,7 +1919,7 @@ static int input (void ); + if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ + { \ + int c = '*'; \ +- yy_size_t n; \ ++ size_t n; \ + for ( n = 0; n < max_size && \ + (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ + buf[n] = (char) c; \ +@@ -1963,7 +1987,7 @@ extern int yylex (void); + + /* Code executed at the end of each rule. */ + #ifndef YY_BREAK +-#define YY_BREAK break; ++#define YY_BREAK /*LINTED*/break; + #endif + + #define YY_RULE_SETUP \ +@@ -1973,31 +1997,10 @@ extern int yylex (void); + */ + YY_DECL + { +- register yy_state_type yy_current_state; +- register char *yy_cp, *yy_bp; +- register int yy_act; ++ yy_state_type yy_current_state; ++ char *yy_cp, *yy_bp; ++ int yy_act; + +-#line 121 "ldlex.l" +- +- +- if (parser_input != input_selected) +- { +- /* The first token of the input determines the initial parser state. */ +- input_type t = parser_input; +- parser_input = input_selected; +- switch (t) +- { +- case input_script: return INPUT_SCRIPT; break; +- case input_mri_script: return INPUT_MRI_SCRIPT; break; +- case input_version_script: return INPUT_VERSION_SCRIPT; break; +- case input_dynamic_list: return INPUT_DYNAMIC_LIST; break; +- case input_defsym: return INPUT_DEFSYM; break; +- default: abort (); +- } +- } +- +-#line 2000 "ldlex.c" +- + if ( !(yy_init) ) + { + (yy_init) = 1; +@@ -2024,7 +2027,29 @@ YY_DECL + yy_load_buffer_state( ); + } + +- while ( 1 ) /* loops until end-of-file is reached */ ++ { ++#line 121 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" ++ ++ ++ if (parser_input != input_selected) ++ { ++ /* The first token of the input determines the initial parser state. */ ++ input_type t = parser_input; ++ parser_input = input_selected; ++ switch (t) ++ { ++ case input_script: return INPUT_SCRIPT; break; ++ case input_mri_script: return INPUT_MRI_SCRIPT; break; ++ case input_version_script: return INPUT_VERSION_SCRIPT; break; ++ case input_dynamic_list: return INPUT_DYNAMIC_LIST; break; ++ case input_defsym: return INPUT_DEFSYM; break; ++ default: abort (); ++ } ++ } ++ ++#line 2051 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.c" ++ ++ while ( /*CONSTCOND*/1 ) /* loops until end-of-file is reached */ + { + yy_cp = (yy_c_buf_p); + +@@ -2040,7 +2065,7 @@ YY_DECL + yy_match: + do + { +- register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)]; ++ YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)] ; + if ( yy_accept[yy_current_state] ) + { + (yy_last_accepting_state) = yy_current_state; +@@ -2081,32 +2106,32 @@ do_action: /* This label is used only to + + case 1: + YY_RULE_SETUP +-#line 139 "ldlex.l" ++#line 139 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { comment (); } + YY_BREAK + case 2: + YY_RULE_SETUP +-#line 142 "ldlex.l" ++#line 142 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('-');} + YY_BREAK + case 3: + YY_RULE_SETUP +-#line 143 "ldlex.l" ++#line 143 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('+');} + YY_BREAK + case 4: + YY_RULE_SETUP +-#line 144 "ldlex.l" ++#line 144 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { yylval.name = xstrdup (yytext); return NAME; } + YY_BREAK + case 5: + YY_RULE_SETUP +-#line 145 "ldlex.l" ++#line 145 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('='); } + YY_BREAK + case 6: + YY_RULE_SETUP +-#line 147 "ldlex.l" ++#line 147 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + yylval.integer = bfd_scan_vma (yytext + 1, 0, 16); + yylval.bigint.str = NULL; +@@ -2115,7 +2140,7 @@ YY_RULE_SETUP + YY_BREAK + case 7: + YY_RULE_SETUP +-#line 153 "ldlex.l" ++#line 153 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + int ibase ; + switch (yytext[yyleng - 1]) { +@@ -2144,7 +2169,7 @@ YY_RULE_SETUP + YY_BREAK + case 8: + YY_RULE_SETUP +-#line 178 "ldlex.l" ++#line 178 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + char *s = yytext; + int ibase = 0; +@@ -2177,829 +2202,829 @@ YY_RULE_SETUP + YY_BREAK + case 9: + YY_RULE_SETUP +-#line 207 "ldlex.l" ++#line 207 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(']');} + YY_BREAK + case 10: + YY_RULE_SETUP +-#line 208 "ldlex.l" ++#line 208 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('[');} + YY_BREAK + case 11: + YY_RULE_SETUP +-#line 209 "ldlex.l" ++#line 209 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LSHIFTEQ);} + YY_BREAK + case 12: + YY_RULE_SETUP +-#line 210 "ldlex.l" ++#line 210 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(RSHIFTEQ);} + YY_BREAK + case 13: + YY_RULE_SETUP +-#line 211 "ldlex.l" ++#line 211 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(OROR);} + YY_BREAK + case 14: + YY_RULE_SETUP +-#line 212 "ldlex.l" ++#line 212 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(EQ);} + YY_BREAK + case 15: + YY_RULE_SETUP +-#line 213 "ldlex.l" ++#line 213 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(NE);} + YY_BREAK + case 16: + YY_RULE_SETUP +-#line 214 "ldlex.l" ++#line 214 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(GE);} + YY_BREAK + case 17: + YY_RULE_SETUP +-#line 215 "ldlex.l" ++#line 215 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LE);} + YY_BREAK + case 18: + YY_RULE_SETUP +-#line 216 "ldlex.l" ++#line 216 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LSHIFT);} + YY_BREAK + case 19: + YY_RULE_SETUP +-#line 217 "ldlex.l" ++#line 217 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(RSHIFT);} + YY_BREAK + case 20: + YY_RULE_SETUP +-#line 218 "ldlex.l" ++#line 218 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(PLUSEQ);} + YY_BREAK + case 21: + YY_RULE_SETUP +-#line 219 "ldlex.l" ++#line 219 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(MINUSEQ);} + YY_BREAK + case 22: + YY_RULE_SETUP +-#line 220 "ldlex.l" ++#line 220 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(MULTEQ);} + YY_BREAK + case 23: + YY_RULE_SETUP +-#line 221 "ldlex.l" ++#line 221 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(DIVEQ);} + YY_BREAK + case 24: + YY_RULE_SETUP +-#line 222 "ldlex.l" ++#line 222 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ANDEQ);} + YY_BREAK + case 25: + YY_RULE_SETUP +-#line 223 "ldlex.l" ++#line 223 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(OREQ);} + YY_BREAK + case 26: + YY_RULE_SETUP +-#line 224 "ldlex.l" ++#line 224 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ANDAND);} + YY_BREAK + case 27: + YY_RULE_SETUP +-#line 225 "ldlex.l" ++#line 225 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('>');} + YY_BREAK + case 28: + YY_RULE_SETUP +-#line 226 "ldlex.l" ++#line 226 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(',');} + YY_BREAK + case 29: + YY_RULE_SETUP +-#line 227 "ldlex.l" ++#line 227 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('&');} + YY_BREAK + case 30: + YY_RULE_SETUP +-#line 228 "ldlex.l" ++#line 228 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('|');} + YY_BREAK + case 31: + YY_RULE_SETUP +-#line 229 "ldlex.l" ++#line 229 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('~');} + YY_BREAK + case 32: + YY_RULE_SETUP +-#line 230 "ldlex.l" ++#line 230 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('!');} + YY_BREAK + case 33: + YY_RULE_SETUP +-#line 231 "ldlex.l" ++#line 231 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('?');} + YY_BREAK + case 34: + YY_RULE_SETUP +-#line 232 "ldlex.l" ++#line 232 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('*');} + YY_BREAK + case 35: + YY_RULE_SETUP +-#line 233 "ldlex.l" ++#line 233 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('+');} + YY_BREAK + case 36: + YY_RULE_SETUP +-#line 234 "ldlex.l" ++#line 234 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('-');} + YY_BREAK + case 37: + YY_RULE_SETUP +-#line 235 "ldlex.l" ++#line 235 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('/');} + YY_BREAK + case 38: + YY_RULE_SETUP +-#line 236 "ldlex.l" ++#line 236 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('%');} + YY_BREAK + case 39: + YY_RULE_SETUP +-#line 237 "ldlex.l" ++#line 237 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('<');} + YY_BREAK + case 40: + YY_RULE_SETUP +-#line 238 "ldlex.l" ++#line 238 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('=');} + YY_BREAK + case 41: + YY_RULE_SETUP +-#line 239 "ldlex.l" ++#line 239 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('}') ; } + YY_BREAK + case 42: + YY_RULE_SETUP +-#line 240 "ldlex.l" ++#line 240 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('{'); } + YY_BREAK + case 43: + YY_RULE_SETUP +-#line 241 "ldlex.l" ++#line 241 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(')');} + YY_BREAK + case 44: + YY_RULE_SETUP +-#line 242 "ldlex.l" ++#line 242 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN('(');} + YY_BREAK + case 45: + YY_RULE_SETUP +-#line 243 "ldlex.l" ++#line 243 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(':'); } + YY_BREAK + case 46: + YY_RULE_SETUP +-#line 244 "ldlex.l" ++#line 244 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(';');} + YY_BREAK + case 47: + YY_RULE_SETUP +-#line 245 "ldlex.l" ++#line 245 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(MEMORY);} + YY_BREAK + case 48: + YY_RULE_SETUP +-#line 246 "ldlex.l" ++#line 246 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(REGION_ALIAS);} + YY_BREAK + case 49: + YY_RULE_SETUP +-#line 247 "ldlex.l" ++#line 247 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LD_FEATURE);} + YY_BREAK + case 50: + YY_RULE_SETUP +-#line 248 "ldlex.l" ++#line 248 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ORIGIN);} + YY_BREAK + case 51: + YY_RULE_SETUP +-#line 249 "ldlex.l" ++#line 249 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(VERSIONK);} + YY_BREAK + case 52: + YY_RULE_SETUP +-#line 250 "ldlex.l" ++#line 250 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(BLOCK);} + YY_BREAK + case 53: + YY_RULE_SETUP +-#line 251 "ldlex.l" ++#line 251 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(BIND);} + YY_BREAK + case 54: + YY_RULE_SETUP +-#line 252 "ldlex.l" ++#line 252 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LENGTH);} + YY_BREAK + case 55: + YY_RULE_SETUP +-#line 253 "ldlex.l" ++#line 253 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ALIGN_K);} + YY_BREAK + case 56: + YY_RULE_SETUP +-#line 254 "ldlex.l" ++#line 254 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(DATA_SEGMENT_ALIGN);} + YY_BREAK + case 57: + YY_RULE_SETUP +-#line 255 "ldlex.l" ++#line 255 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(DATA_SEGMENT_RELRO_END);} + YY_BREAK + case 58: + YY_RULE_SETUP +-#line 256 "ldlex.l" ++#line 256 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(DATA_SEGMENT_END);} + YY_BREAK + case 59: + YY_RULE_SETUP +-#line 257 "ldlex.l" ++#line 257 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ADDR);} + YY_BREAK + case 60: + YY_RULE_SETUP +-#line 258 "ldlex.l" ++#line 258 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LOADADDR);} + YY_BREAK + case 61: + YY_RULE_SETUP +-#line 259 "ldlex.l" ++#line 259 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ALIGNOF); } + YY_BREAK + case 62: + YY_RULE_SETUP +-#line 260 "ldlex.l" ++#line 260 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(MAX_K); } + YY_BREAK + case 63: + YY_RULE_SETUP +-#line 261 "ldlex.l" ++#line 261 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(MIN_K); } + YY_BREAK + case 64: + YY_RULE_SETUP +-#line 262 "ldlex.l" ++#line 262 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LOG2CEIL); } + YY_BREAK + case 65: + YY_RULE_SETUP +-#line 263 "ldlex.l" ++#line 263 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ASSERT_K); } + YY_BREAK + case 66: + YY_RULE_SETUP +-#line 264 "ldlex.l" ++#line 264 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ENTRY);} + YY_BREAK + case 67: + YY_RULE_SETUP +-#line 265 "ldlex.l" ++#line 265 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(EXTERN);} + YY_BREAK + case 68: + YY_RULE_SETUP +-#line 266 "ldlex.l" ++#line 266 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(NEXT);} + YY_BREAK + case 69: + YY_RULE_SETUP +-#line 267 "ldlex.l" ++#line 267 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SIZEOF_HEADERS);} + YY_BREAK + case 70: + YY_RULE_SETUP +-#line 268 "ldlex.l" ++#line 268 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SIZEOF_HEADERS);} + YY_BREAK + case 71: + YY_RULE_SETUP +-#line 269 "ldlex.l" ++#line 269 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SEGMENT_START);} + YY_BREAK + case 72: + YY_RULE_SETUP +-#line 270 "ldlex.l" ++#line 270 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(MAP);} + YY_BREAK + case 73: + YY_RULE_SETUP +-#line 271 "ldlex.l" ++#line 271 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SIZEOF);} + YY_BREAK + case 74: + YY_RULE_SETUP +-#line 272 "ldlex.l" ++#line 272 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(TARGET_K);} + YY_BREAK + case 75: + YY_RULE_SETUP +-#line 273 "ldlex.l" ++#line 273 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SEARCH_DIR);} + YY_BREAK + case 76: + YY_RULE_SETUP +-#line 274 "ldlex.l" ++#line 274 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(OUTPUT);} + YY_BREAK + case 77: + YY_RULE_SETUP +-#line 275 "ldlex.l" ++#line 275 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(INPUT);} + YY_BREAK + case 78: + YY_RULE_SETUP +-#line 276 "ldlex.l" ++#line 276 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(GROUP);} + YY_BREAK + case 79: + YY_RULE_SETUP +-#line 277 "ldlex.l" ++#line 277 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(AS_NEEDED);} + YY_BREAK + case 80: + YY_RULE_SETUP +-#line 278 "ldlex.l" ++#line 278 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(DEFINED);} + YY_BREAK + case 81: + YY_RULE_SETUP +-#line 279 "ldlex.l" ++#line 279 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(CREATE_OBJECT_SYMBOLS);} + YY_BREAK + case 82: + YY_RULE_SETUP +-#line 280 "ldlex.l" ++#line 280 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN( CONSTRUCTORS);} + YY_BREAK + case 83: + YY_RULE_SETUP +-#line 281 "ldlex.l" ++#line 281 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(FORCE_COMMON_ALLOCATION);} + YY_BREAK + case 84: + YY_RULE_SETUP +-#line 282 "ldlex.l" ++#line 282 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(INHIBIT_COMMON_ALLOCATION);} + YY_BREAK + case 85: + YY_RULE_SETUP +-#line 283 "ldlex.l" ++#line 283 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SECTIONS);} + YY_BREAK + case 86: + YY_RULE_SETUP +-#line 284 "ldlex.l" ++#line 284 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(INSERT_K);} + YY_BREAK + case 87: + YY_RULE_SETUP +-#line 285 "ldlex.l" ++#line 285 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(AFTER);} + YY_BREAK + case 88: + YY_RULE_SETUP +-#line 286 "ldlex.l" ++#line 286 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(BEFORE);} + YY_BREAK + case 89: + YY_RULE_SETUP +-#line 287 "ldlex.l" ++#line 287 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(FILL);} + YY_BREAK + case 90: + YY_RULE_SETUP +-#line 288 "ldlex.l" ++#line 288 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(STARTUP);} + YY_BREAK + case 91: + YY_RULE_SETUP +-#line 289 "ldlex.l" ++#line 289 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(OUTPUT_FORMAT);} + YY_BREAK + case 92: + YY_RULE_SETUP +-#line 290 "ldlex.l" ++#line 290 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN( OUTPUT_ARCH);} + YY_BREAK + case 93: + YY_RULE_SETUP +-#line 291 "ldlex.l" ++#line 291 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(HLL);} + YY_BREAK + case 94: + YY_RULE_SETUP +-#line 292 "ldlex.l" ++#line 292 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SYSLIB);} + YY_BREAK + case 95: + YY_RULE_SETUP +-#line 293 "ldlex.l" ++#line 293 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(FLOAT);} + YY_BREAK + case 96: + YY_RULE_SETUP +-#line 294 "ldlex.l" ++#line 294 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN( QUAD);} + YY_BREAK + case 97: + YY_RULE_SETUP +-#line 295 "ldlex.l" ++#line 295 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN( SQUAD);} + YY_BREAK + case 98: + YY_RULE_SETUP +-#line 296 "ldlex.l" ++#line 296 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN( LONG);} + YY_BREAK + case 99: + YY_RULE_SETUP +-#line 297 "ldlex.l" ++#line 297 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN( SHORT);} + YY_BREAK + case 100: + YY_RULE_SETUP +-#line 298 "ldlex.l" ++#line 298 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN( BYTE);} + YY_BREAK + case 101: + YY_RULE_SETUP +-#line 299 "ldlex.l" ++#line 299 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(NOFLOAT);} + YY_BREAK + case 102: + YY_RULE_SETUP +-#line 300 "ldlex.l" ++#line 300 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(NOCROSSREFS);} + YY_BREAK + case 103: + YY_RULE_SETUP +-#line 301 "ldlex.l" ++#line 301 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(NOCROSSREFS_TO);} + YY_BREAK + case 104: + YY_RULE_SETUP +-#line 302 "ldlex.l" ++#line 302 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(OVERLAY); } + YY_BREAK + case 105: + YY_RULE_SETUP +-#line 303 "ldlex.l" ++#line 303 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SORT_BY_NAME); } + YY_BREAK + case 106: + YY_RULE_SETUP +-#line 304 "ldlex.l" ++#line 304 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SORT_BY_ALIGNMENT); } + YY_BREAK + case 107: + YY_RULE_SETUP +-#line 305 "ldlex.l" ++#line 305 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SORT_BY_NAME); } + YY_BREAK + case 108: + YY_RULE_SETUP +-#line 306 "ldlex.l" ++#line 306 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SORT_BY_INIT_PRIORITY); } + YY_BREAK + case 109: + YY_RULE_SETUP +-#line 307 "ldlex.l" ++#line 307 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SORT_NONE); } + YY_BREAK + case 110: + YY_RULE_SETUP +-#line 308 "ldlex.l" ++#line 308 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(NOLOAD);} + YY_BREAK + case 111: + YY_RULE_SETUP +-#line 309 "ldlex.l" ++#line 309 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(DSECT);} + YY_BREAK + case 112: + YY_RULE_SETUP +-#line 310 "ldlex.l" ++#line 310 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(COPY);} + YY_BREAK + case 113: + YY_RULE_SETUP +-#line 311 "ldlex.l" ++#line 311 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(INFO);} + YY_BREAK + case 114: + YY_RULE_SETUP +-#line 312 "ldlex.l" ++#line 312 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(OVERLAY);} + YY_BREAK + case 115: + YY_RULE_SETUP +-#line 313 "ldlex.l" ++#line 313 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ONLY_IF_RO); } + YY_BREAK + case 116: + YY_RULE_SETUP +-#line 314 "ldlex.l" ++#line 314 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ONLY_IF_RW); } + YY_BREAK + case 117: + YY_RULE_SETUP +-#line 315 "ldlex.l" ++#line 315 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SPECIAL); } + YY_BREAK + case 118: + YY_RULE_SETUP +-#line 316 "ldlex.l" ++#line 316 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ORIGIN);} + YY_BREAK + case 119: + YY_RULE_SETUP +-#line 317 "ldlex.l" ++#line 317 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ORIGIN);} + YY_BREAK + case 120: + YY_RULE_SETUP +-#line 318 "ldlex.l" ++#line 318 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN( LENGTH);} + YY_BREAK + case 121: + YY_RULE_SETUP +-#line 319 "ldlex.l" ++#line 319 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN( LENGTH);} + YY_BREAK + case 122: + YY_RULE_SETUP +-#line 320 "ldlex.l" ++#line 320 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(INPUT_SECTION_FLAGS); } + YY_BREAK + case 123: + YY_RULE_SETUP +-#line 321 "ldlex.l" ++#line 321 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(INCLUDE);} + YY_BREAK + case 124: + YY_RULE_SETUP +-#line 322 "ldlex.l" ++#line 322 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN (PHDRS); } + YY_BREAK + case 125: + YY_RULE_SETUP +-#line 323 "ldlex.l" ++#line 323 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(AT);} + YY_BREAK + case 126: + YY_RULE_SETUP +-#line 324 "ldlex.l" ++#line 324 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ALIGN_WITH_INPUT);} + YY_BREAK + case 127: + YY_RULE_SETUP +-#line 325 "ldlex.l" ++#line 325 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SUBALIGN);} + YY_BREAK + case 128: + YY_RULE_SETUP +-#line 326 "ldlex.l" ++#line 326 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(HIDDEN); } + YY_BREAK + case 129: + YY_RULE_SETUP +-#line 327 "ldlex.l" ++#line 327 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(PROVIDE); } + YY_BREAK + case 130: + YY_RULE_SETUP +-#line 328 "ldlex.l" ++#line 328 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(PROVIDE_HIDDEN); } + YY_BREAK + case 131: + YY_RULE_SETUP +-#line 329 "ldlex.l" ++#line 329 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(KEEP); } + YY_BREAK + case 132: + YY_RULE_SETUP +-#line 330 "ldlex.l" ++#line 330 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(EXCLUDE_FILE); } + YY_BREAK + case 133: + YY_RULE_SETUP +-#line 331 "ldlex.l" ++#line 331 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(CONSTANT);} + YY_BREAK + case 134: + /* rule 134 can match eol */ + YY_RULE_SETUP +-#line 332 "ldlex.l" ++#line 332 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { ++ lineno; } + YY_BREAK + case 135: + /* rule 135 can match eol */ + YY_RULE_SETUP +-#line 333 "ldlex.l" ++#line 333 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { ++ lineno; RTOKEN(NEWLINE); } + YY_BREAK + case 136: + YY_RULE_SETUP +-#line 334 "ldlex.l" ++#line 334 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { /* Mri comment line */ } + YY_BREAK + case 137: + YY_RULE_SETUP +-#line 335 "ldlex.l" ++#line 335 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { /* Mri comment line */ } + YY_BREAK + case 138: + YY_RULE_SETUP +-#line 336 "ldlex.l" ++#line 336 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ENDWORD); } + YY_BREAK + case 139: + YY_RULE_SETUP +-#line 337 "ldlex.l" ++#line 337 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ALIGNMOD);} + YY_BREAK + case 140: + YY_RULE_SETUP +-#line 338 "ldlex.l" ++#line 338 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ALIGN_K);} + YY_BREAK + case 141: + YY_RULE_SETUP +-#line 339 "ldlex.l" ++#line 339 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(CHIP); } + YY_BREAK + case 142: + YY_RULE_SETUP +-#line 340 "ldlex.l" ++#line 340 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(BASE); } + YY_BREAK + case 143: + YY_RULE_SETUP +-#line 341 "ldlex.l" ++#line 341 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ALIAS); } + YY_BREAK + case 144: + YY_RULE_SETUP +-#line 342 "ldlex.l" ++#line 342 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(TRUNCATE); } + YY_BREAK + case 145: + YY_RULE_SETUP +-#line 343 "ldlex.l" ++#line 343 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LOAD); } + YY_BREAK + case 146: + YY_RULE_SETUP +-#line 344 "ldlex.l" ++#line 344 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(PUBLIC); } + YY_BREAK + case 147: + YY_RULE_SETUP +-#line 345 "ldlex.l" ++#line 345 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ORDER); } + YY_BREAK + case 148: + YY_RULE_SETUP +-#line 346 "ldlex.l" ++#line 346 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(NAMEWORD); } + YY_BREAK + case 149: + YY_RULE_SETUP +-#line 347 "ldlex.l" ++#line 347 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(FORMAT); } + YY_BREAK + case 150: + YY_RULE_SETUP +-#line 348 "ldlex.l" ++#line 348 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(CASE); } + YY_BREAK + case 151: + YY_RULE_SETUP +-#line 349 "ldlex.l" ++#line 349 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(START); } + YY_BREAK + case 152: + YY_RULE_SETUP +-#line 350 "ldlex.l" ++#line 350 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LIST); /* LIST and ignore to end of line */ } + YY_BREAK + case 153: + YY_RULE_SETUP +-#line 351 "ldlex.l" ++#line 351 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SECT); } + YY_BREAK + case 154: + YY_RULE_SETUP +-#line 352 "ldlex.l" ++#line 352 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ABSOLUTE); } + YY_BREAK + case 155: + YY_RULE_SETUP +-#line 353 "ldlex.l" ++#line 353 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ENDWORD); } + YY_BREAK + case 156: + YY_RULE_SETUP +-#line 354 "ldlex.l" ++#line 354 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ALIGNMOD);} + YY_BREAK + case 157: + YY_RULE_SETUP +-#line 355 "ldlex.l" ++#line 355 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ALIGN_K);} + YY_BREAK + case 158: + YY_RULE_SETUP +-#line 356 "ldlex.l" ++#line 356 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(CHIP); } + YY_BREAK + case 159: + YY_RULE_SETUP +-#line 357 "ldlex.l" ++#line 357 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(BASE); } + YY_BREAK + case 160: + YY_RULE_SETUP +-#line 358 "ldlex.l" ++#line 358 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ALIAS); } + YY_BREAK + case 161: + YY_RULE_SETUP +-#line 359 "ldlex.l" ++#line 359 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(TRUNCATE); } + YY_BREAK + case 162: + YY_RULE_SETUP +-#line 360 "ldlex.l" ++#line 360 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LOAD); } + YY_BREAK + case 163: + YY_RULE_SETUP +-#line 361 "ldlex.l" ++#line 361 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(PUBLIC); } + YY_BREAK + case 164: + YY_RULE_SETUP +-#line 362 "ldlex.l" ++#line 362 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ORDER); } + YY_BREAK + case 165: + YY_RULE_SETUP +-#line 363 "ldlex.l" ++#line 363 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(NAMEWORD); } + YY_BREAK + case 166: + YY_RULE_SETUP +-#line 364 "ldlex.l" ++#line 364 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(FORMAT); } + YY_BREAK + case 167: + YY_RULE_SETUP +-#line 365 "ldlex.l" ++#line 365 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(CASE); } + YY_BREAK + case 168: + YY_RULE_SETUP +-#line 366 "ldlex.l" ++#line 366 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(EXTERN); } + YY_BREAK + case 169: + YY_RULE_SETUP +-#line 367 "ldlex.l" ++#line 367 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(START); } + YY_BREAK + case 170: + YY_RULE_SETUP +-#line 368 "ldlex.l" ++#line 368 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LIST); /* LIST and ignore to end of line */ } + YY_BREAK + case 171: + YY_RULE_SETUP +-#line 369 "ldlex.l" ++#line 369 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(SECT); } + YY_BREAK + case 172: + YY_RULE_SETUP +-#line 370 "ldlex.l" ++#line 370 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(ABSOLUTE); } + YY_BREAK + case 173: + YY_RULE_SETUP +-#line 372 "ldlex.l" ++#line 372 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + /* Filename without commas, needed to parse mri stuff */ + yylval.name = xstrdup (yytext); +@@ -3008,7 +3033,7 @@ YY_RULE_SETUP + YY_BREAK + case 174: + YY_RULE_SETUP +-#line 379 "ldlex.l" ++#line 379 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + yylval.name = xstrdup (yytext); + return NAME; +@@ -3016,7 +3041,7 @@ YY_RULE_SETUP + YY_BREAK + case 175: + YY_RULE_SETUP +-#line 383 "ldlex.l" ++#line 383 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + /* Filename to be prefixed by --sysroot or when non-sysrooted, nothing. */ + yylval.name = xstrdup (yytext); +@@ -3025,7 +3050,7 @@ YY_RULE_SETUP + YY_BREAK + case 176: + YY_RULE_SETUP +-#line 388 "ldlex.l" ++#line 388 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + yylval.name = xstrdup (yytext + 2); + return LNAME; +@@ -3033,7 +3058,7 @@ YY_RULE_SETUP + YY_BREAK + case 177: + YY_RULE_SETUP +-#line 392 "ldlex.l" ++#line 392 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + yylval.name = xstrdup (yytext); + return NAME; +@@ -3041,7 +3066,7 @@ YY_RULE_SETUP + YY_BREAK + case 178: + YY_RULE_SETUP +-#line 396 "ldlex.l" ++#line 396 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + yylval.name = xstrdup (yytext + 2); + return LNAME; +@@ -3049,7 +3074,7 @@ YY_RULE_SETUP + YY_BREAK + case 179: + YY_RULE_SETUP +-#line 400 "ldlex.l" ++#line 400 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + /* Annoyingly, this pattern can match comments, and we have + longest match issues to consider. So if the first two +@@ -3070,66 +3095,72 @@ YY_RULE_SETUP + case 180: + /* rule 180 can match eol */ + YY_RULE_SETUP +-#line 417 "ldlex.l" ++#line 417 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + /* No matter the state, quotes +- give what's inside */ ++ give what's inside. */ ++ bfd_size_type len; + yylval.name = xstrdup (yytext + 1); +- yylval.name[yyleng - 2] = 0; ++ /* PR ld/20906. A corrupt input file ++ can contain bogus strings. */ ++ len = strlen (yylval.name); ++ if (len > yyleng - 2) ++ len = yyleng - 2; ++ yylval.name[len] = 0; + return NAME; + } + YY_BREAK + case 181: + /* rule 181 can match eol */ + YY_RULE_SETUP +-#line 424 "ldlex.l" ++#line 430 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { lineno++;} + YY_BREAK + case 182: + YY_RULE_SETUP +-#line 425 "ldlex.l" ++#line 431 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { } + YY_BREAK + case 183: + YY_RULE_SETUP +-#line 427 "ldlex.l" ++#line 433 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { return *yytext; } + YY_BREAK + case 184: + YY_RULE_SETUP +-#line 429 "ldlex.l" ++#line 435 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(GLOBAL); } + YY_BREAK + case 185: + YY_RULE_SETUP +-#line 431 "ldlex.l" ++#line 437 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(LOCAL); } + YY_BREAK + case 186: + YY_RULE_SETUP +-#line 433 "ldlex.l" ++#line 439 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { RTOKEN(EXTERN); } + YY_BREAK + case 187: + YY_RULE_SETUP +-#line 435 "ldlex.l" ++#line 441 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { yylval.name = xstrdup (yytext); + return VERS_IDENTIFIER; } + YY_BREAK + case 188: + YY_RULE_SETUP +-#line 438 "ldlex.l" ++#line 444 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { yylval.name = xstrdup (yytext); + return VERS_TAG; } + YY_BREAK + case 189: + YY_RULE_SETUP +-#line 441 "ldlex.l" ++#line 447 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { BEGIN(VERS_SCRIPT); return *yytext; } + YY_BREAK + case 190: + YY_RULE_SETUP +-#line 443 "ldlex.l" ++#line 449 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { BEGIN(VERS_NODE); + vers_node_nesting = 0; + return *yytext; +@@ -3137,17 +3168,17 @@ YY_RULE_SETUP + YY_BREAK + case 191: + YY_RULE_SETUP +-#line 447 "ldlex.l" ++#line 453 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { return *yytext; } + YY_BREAK + case 192: + YY_RULE_SETUP +-#line 448 "ldlex.l" ++#line 454 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { vers_node_nesting++; return *yytext; } + YY_BREAK + case 193: + YY_RULE_SETUP +-#line 449 "ldlex.l" ++#line 455 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { if (--vers_node_nesting < 0) + BEGIN(VERS_SCRIPT); + return *yytext; +@@ -3156,17 +3187,17 @@ YY_RULE_SETUP + case 194: + /* rule 194 can match eol */ + YY_RULE_SETUP +-#line 454 "ldlex.l" ++#line 460 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { lineno++; } + YY_BREAK + case 195: + YY_RULE_SETUP +-#line 456 "ldlex.l" ++#line 462 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { /* Eat up comments */ } + YY_BREAK + case 196: + YY_RULE_SETUP +-#line 458 "ldlex.l" ++#line 464 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { /* Eat up whitespace */ } + YY_BREAK + case YY_STATE_EOF(INITIAL): +@@ -3179,7 +3210,7 @@ case YY_STATE_EOF(MRI): + case YY_STATE_EOF(VERS_START): + case YY_STATE_EOF(VERS_SCRIPT): + case YY_STATE_EOF(VERS_NODE): +-#line 460 "ldlex.l" ++#line 466 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + { + include_stack_ptr--; + if (include_stack_ptr == 0) +@@ -3195,20 +3226,20 @@ case YY_STATE_EOF(VERS_NODE): + YY_BREAK + case 197: + YY_RULE_SETUP +-#line 473 "ldlex.l" ++#line 479 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + lex_warn_invalid (" in script", yytext); + YY_BREAK + case 198: + YY_RULE_SETUP +-#line 474 "ldlex.l" ++#line 480 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + lex_warn_invalid (" in expression", yytext); + YY_BREAK + case 199: + YY_RULE_SETUP +-#line 476 "ldlex.l" ++#line 482 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + ECHO; + YY_BREAK +-#line 3212 "ldlex.c" ++#line 3243 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.c" + + case YY_END_OF_BUFFER: + { +@@ -3337,6 +3368,7 @@ ECHO; + "fatal flex scanner internal error--no action found" ); + } /* end of action switch */ + } /* end of scanning one token */ ++ } /* end of user's declarations */ + } /* end of yylex */ + + /* yy_get_next_buffer - try to read in a new buffer +@@ -3348,9 +3380,9 @@ ECHO; + */ + static int yy_get_next_buffer (void) + { +- register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; +- register char *source = (yytext_ptr); +- register int number_to_move, i; ++ char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; ++ char *source = (yytext_ptr); ++ yy_size_t number_to_move, i; + int ret_val; + + if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) +@@ -3379,7 +3411,7 @@ static int yy_get_next_buffer (void) + /* Try to read more data. */ + + /* First move last chars to start of buffer. */ +- number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1; ++ number_to_move = (yy_size_t) ((yy_c_buf_p) - (yytext_ptr)) - 1; + + for ( i = 0; i < number_to_move; ++i ) + *(dest++) = *(source++); +@@ -3392,14 +3424,14 @@ static int yy_get_next_buffer (void) + + else + { +- yy_size_t num_to_read = ++ int num_to_read = + YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; + + while ( num_to_read <= 0 ) + { /* Not enough room in the buffer - grow it. */ + + /* just a shorter name for the current buffer */ +- YY_BUFFER_STATE b = YY_CURRENT_BUFFER; ++ YY_BUFFER_STATE b = YY_CURRENT_BUFFER_LVALUE; + + int yy_c_buf_p_offset = + (int) ((yy_c_buf_p) - b->yy_ch_buf); +@@ -3482,14 +3514,14 @@ static int yy_get_next_buffer (void) + + static yy_state_type yy_get_previous_state (void) + { +- register yy_state_type yy_current_state; +- register char *yy_cp; ++ yy_state_type yy_current_state; ++ char *yy_cp; + + yy_current_state = (yy_start); + + for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp ) + { +- register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1); ++ YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1); + if ( yy_accept[yy_current_state] ) + { + (yy_last_accepting_state) = yy_current_state; +@@ -3514,10 +3546,10 @@ static int yy_get_next_buffer (void) + */ + static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state ) + { +- register int yy_is_jam; +- register char *yy_cp = (yy_c_buf_p); ++ int yy_is_jam; ++ char *yy_cp = (yy_c_buf_p); + +- register YY_CHAR yy_c = 1; ++ YY_CHAR yy_c = 1; + if ( yy_accept[yy_current_state] ) + { + (yy_last_accepting_state) = yy_current_state; +@@ -3532,9 +3564,13 @@ static int yy_get_next_buffer (void) + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; + yy_is_jam = (yy_current_state == 1774); + +- return yy_is_jam ? 0 : yy_current_state; ++ return yy_is_jam ? 0 : yy_current_state; + } + ++#ifndef YY_NO_UNPUT ++ ++#endif ++ + #ifndef YY_NO_INPUT + #ifdef __cplusplus + static int yyinput (void) +@@ -3583,7 +3619,7 @@ static int yy_get_next_buffer (void) + case EOB_ACT_END_OF_FILE: + { + if ( yywrap( ) ) +- return 0; ++ return EOF; + + if ( ! (yy_did_buffer_switch_on_eof) ) + YY_NEW_FILE; +@@ -3684,7 +3720,7 @@ static void yy_load_buffer_state (void) + if ( ! b ) + YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); + +- b->yy_buf_size = size; ++ b->yy_buf_size = (yy_size_t)size; + + /* yy_ch_buf has to be 2 characters longer than the size given because + * we need to put in 2 end-of-buffer characters. +@@ -3719,10 +3755,6 @@ static void yy_load_buffer_state (void) + yyfree((void *) b ); + } + +-#ifndef __cplusplus +-extern int isatty (int ); +-#endif /* __cplusplus */ +- + /* Initializes or reinitializes a buffer. + * This function is sometimes called more than once on the same buffer, + * such as during a yyrestart() or at EOF. +@@ -3843,7 +3875,7 @@ static void yyensure_buffer_stack (void) + * scanner will even need a stack. We use 2 instead of 1 to avoid an + * immediate realloc on the next call. + */ +- num_to_alloc = 1; ++ num_to_alloc = 1; /* After all that talk, this was set to 1 anyways... */ + (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc + (num_to_alloc * sizeof(struct yy_buffer_state*) + ); +@@ -3860,7 +3892,7 @@ static void yyensure_buffer_stack (void) + if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){ + + /* Increase the buffer to prepare for a possible push. */ +- int grow_size = 8 /* arbitrary grow size */; ++ yy_size_t grow_size = 8 /* arbitrary grow size */; + + num_to_alloc = (yy_buffer_stack_max) + grow_size; + (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc +@@ -3927,8 +3959,8 @@ YY_BUFFER_STATE yy_scan_string (yyconst + + /** Setup the input buffer state to scan the given bytes. The next call to yylex() will + * scan from a @e copy of @a bytes. +- * @param bytes the byte buffer to scan +- * @param len the number of bytes in the buffer pointed to by @a bytes. ++ * @param yybytes the byte buffer to scan ++ * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes. + * + * @return the newly allocated buffer state object. + */ +@@ -3936,7 +3968,8 @@ YY_BUFFER_STATE yy_scan_bytes (yyconst + { + YY_BUFFER_STATE b; + char *buf; +- yy_size_t n, i; ++ yy_size_t n; ++ yy_size_t i; + + /* Get memory for full buffer, including space for trailing EOB's. */ + n = _yybytes_len + 2; +@@ -3967,7 +4000,7 @@ YY_BUFFER_STATE yy_scan_bytes (yyconst + + static void yy_fatal_error (yyconst char* msg ) + { +- (void) fprintf( stderr, "%s\n", msg ); ++ (void) fprintf( stderr, "%s\n", msg ); + exit( YY_EXIT_FAILURE ); + } + +@@ -3978,7 +4011,7 @@ static void yy_fatal_error (yyconst char + do \ + { \ + /* Undo effects of setting up yytext. */ \ +- int yyless_macro_arg = (n); \ ++ yy_size_t yyless_macro_arg = (n); \ + YY_LESS_LINENO(yyless_macro_arg);\ + yytext[yyleng] = (yy_hold_char); \ + (yy_c_buf_p) = yytext + yyless_macro_arg; \ +@@ -4033,29 +4066,29 @@ char *yyget_text (void) + } + + /** Set the current line number. +- * @param line_number ++ * @param _line_number line number + * + */ +-void yyset_lineno (int line_number ) ++void yyset_lineno (int _line_number ) + { + +- yylineno = line_number; ++ yylineno = _line_number; + } + + /** Set the input stream. This does not discard the current + * input buffer. +- * @param in_str A readable stream. ++ * @param _in_str A readable stream. + * + * @see yy_switch_to_buffer + */ +-void yyset_in (FILE * in_str ) ++void yyset_in (FILE * _in_str ) + { +- yyin = in_str ; ++ yyin = _in_str ; + } + +-void yyset_out (FILE * out_str ) ++void yyset_out (FILE * _out_str ) + { +- yyout = out_str ; ++ yyout = _out_str ; + } + + int yyget_debug (void) +@@ -4063,9 +4096,9 @@ int yyget_debug (void) + return yy_flex_debug; + } + +-void yyset_debug (int bdebug ) ++void yyset_debug (int _bdebug ) + { +- yy_flex_debug = bdebug ; ++ yy_flex_debug = _bdebug ; + } + + static int yy_init_globals (void) +@@ -4125,7 +4158,8 @@ int yylex_destroy (void) + #ifndef yytext_ptr + static void yy_flex_strncpy (char* s1, yyconst char * s2, int n ) + { +- register int i; ++ ++ int i; + for ( i = 0; i < n; ++i ) + s1[i] = s2[i]; + } +@@ -4134,7 +4168,7 @@ static void yy_flex_strncpy (char* s1, y + #ifdef YY_NEED_STRLEN + static int yy_flex_strlen (yyconst char * s ) + { +- register int n; ++ int n; + for ( n = 0; s[n]; ++n ) + ; + +@@ -4144,11 +4178,12 @@ static int yy_flex_strlen (yyconst char + + void *yyalloc (yy_size_t size ) + { +- return (void *) malloc( size ); ++ return (void *) malloc( size ); + } + + void *yyrealloc (void * ptr, yy_size_t size ) + { ++ + /* The cast to (char *) in the following accommodates both + * implementations that use char* generic pointers, and those + * that use void* generic pointers. It works with the latter +@@ -4161,12 +4196,12 @@ void *yyrealloc (void * ptr, yy_size_t + + void yyfree (void * ptr ) + { +- free( (char *) ptr ); /* see yyrealloc() for (char *) cast */ ++ free( (char *) ptr ); /* see yyrealloc() for (char *) cast */ + } + + #define YYTABLES_NAME "yytables" + +-#line 476 "ldlex.l" ++#line 482 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l" + + + +diff -rup binutils.orig/ld/ldlex.l binutils-2.27/ld/ldlex.l +--- binutils.orig/ld/ldlex.l 2017-03-24 13:50:55.613184724 +0000 ++++ binutils-2.27/ld/ldlex.l 2017-03-24 14:20:35.039227142 +0000 +@@ -416,9 +416,15 @@ V_IDENTIFIER [*?.$_a-zA-Z\[\]\-\!\^\\]([ + + "\""[^\"]*"\"" { + /* No matter the state, quotes +- give what's inside */ ++ give what's inside. */ ++ bfd_size_type len; + yylval.name = xstrdup (yytext + 1); +- yylval.name[yyleng - 2] = 0; ++ /* PR ld/20906. A corrupt input file ++ can contain bogus strings. */ ++ len = strlen (yylval.name); ++ if (len > yyleng - 2) ++ len = yyleng - 2; ++ yylval.name[len] = 0; + return NAME; + } + "\n" { lineno++;} diff --git a/SOURCES/binutils-2.27-ppc64-discarded-plt-sections.patch b/SOURCES/binutils-2.27-ppc64-discarded-plt-sections.patch new file mode 100644 index 0000000..dc40f0e --- /dev/null +++ b/SOURCES/binutils-2.27-ppc64-discarded-plt-sections.patch @@ -0,0 +1,79 @@ +diff -rup binutils.orig/bfd/elf64-ppc.c binutils-2.27/bfd/elf64-ppc.c +--- binutils.orig/bfd/elf64-ppc.c 2017-11-16 10:35:34.873666405 +0000 ++++ binutils-2.27/bfd/elf64-ppc.c 2017-11-16 10:39:54.037530964 +0000 +@@ -10105,6 +10105,10 @@ ppc64_elf_size_dynamic_sections (bfd *ou + continue; + } + ++ if (bfd_is_abs_section (s->output_section)) ++ _bfd_error_handler (_("warning: discarding dynamic section %s"), ++ s->name); ++ + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + +@@ -10875,7 +10879,7 @@ ppc_build_one_stub (struct bfd_hash_entr + + htab->brlt->output_section->vma); + + off = (dest +- - elf_gp (htab->brlt->output_section->owner) ++ - elf_gp (info->output_bfd) + - htab->sec_info[stub_entry->group->link_sec->id].toc_off); + + if (off + 0x80008000 > 0xffffffff || (off & 7) != 0) +@@ -11025,7 +11029,7 @@ ppc_build_one_stub (struct bfd_hash_entr + } + + off = (dest +- - elf_gp (plt->output_section->owner) ++ - elf_gp (info->output_bfd) + - htab->sec_info[stub_entry->group->link_sec->id].toc_off); + + if (off + 0x80008000 > 0xffffffff || (off & 7) != 0) +@@ -11172,7 +11176,7 @@ ppc_size_one_stub (struct bfd_hash_entry + plt = htab->elf.iplt; + off += (plt->output_offset + + plt->output_section->vma +- - elf_gp (plt->output_section->owner) ++ - elf_gp (info->output_bfd) + - htab->sec_info[stub_entry->group->link_sec->id].toc_off); + + size = plt_stub_size (htab, stub_entry, off); +@@ -11266,7 +11270,7 @@ ppc_size_one_stub (struct bfd_hash_entry + off = (br_entry->offset + + htab->brlt->output_offset + + htab->brlt->output_section->vma +- - elf_gp (htab->brlt->output_section->owner) ++ - elf_gp (info->output_bfd) + - htab->sec_info[stub_entry->group->link_sec->id].toc_off); + + if (info->emitrelocations) +@@ -11386,7 +11390,7 @@ ppc64_elf_next_toc_section (struct bfd_l + output toc base plus 0x8000. Making the input elf_gp an + offset allows us to move the toc as a whole without + recalculating input elf_gp. */ +- off = htab->toc_curr - elf_gp (isec->output_section->owner); ++ off = htab->toc_curr - elf_gp (info->output_bfd); + off += TOC_BASE_OFF; + + /* Die if someone uses a linker script that doesn't keep input +@@ -11415,7 +11419,7 @@ ppc64_elf_next_toc_section (struct bfd_l + } + addr = (htab->toc_first_sec->output_offset + + htab->toc_first_sec->output_section->vma); +- off = addr - elf_gp (isec->output_section->owner) + TOC_BASE_OFF; ++ off = addr - elf_gp (info->output_bfd) + TOC_BASE_OFF; + elf_gp (isec->owner) = off; + + return TRUE; +diff -rup binutils.orig/ld/testsuite/ld-elf/note-3.t binutils-2.27/ld/testsuite/ld-elf/note-3.t +--- binutils.orig/ld/testsuite/ld-elf/note-3.t 2017-11-16 10:35:35.670656893 +0000 ++++ binutils-2.27/ld/testsuite/ld-elf/note-3.t 2017-11-16 10:59:06.352286215 +0000 +@@ -17,6 +17,7 @@ SECTIONS + + .dynstr : { *(.dynstr) } + .dynsym : { *(.dynsym) } ++ .got : { *(.got .toc) *(.igot) } + .got.plt : { *(.got.plt) *(.igot.plt) } + /DISCARD/ : { *(*) } + } diff --git a/SOURCES/binutils-2.27-remove-dwarf2-minmax.patch b/SOURCES/binutils-2.27-remove-dwarf2-minmax.patch new file mode 100644 index 0000000..c65dbe2 --- /dev/null +++ b/SOURCES/binutils-2.27-remove-dwarf2-minmax.patch @@ -0,0 +1,41 @@ +--- binutils.orig/bfd/dwarf2.c 2017-08-08 17:40:39.084385407 +0100 ++++ binutils-2.27/bfd/dwarf2.c 2017-08-08 17:41:34.237754733 +0100 +@@ -215,9 +215,6 @@ struct comp_unit + /* Linked list of the low and high address ranges contained in this + compilation unit as specified in the compilation unit header. */ + struct arange arange; +- /* A single arange containing the lowest and highest +- addresses covered by the compilation unit. */ +- struct arange minmax; + + /* The DW_AT_name attribute (for error messages). */ + char *name; +@@ -1540,16 +1537,11 @@ arange_add (struct comp_unit *unit, stru + /* If the first arange is empty, use it. */ + if (first_arange->high == 0) + { +- unit->minmax.low = first_arange->low = low_pc; +- unit->minmax.high = first_arange->high = high_pc; ++ first_arange->low = low_pc; ++ first_arange->high = high_pc; + return TRUE; + } + +- if (unit->minmax.low > low_pc) +- unit->minmax.low = low_pc; +- if (unit->minmax.high < high_pc) +- unit->minmax.high = high_pc; +- + /* Next see if we can cheaply extend an existing range. */ + arange = first_arange; + do +@@ -3151,9 +3143,6 @@ comp_unit_contains_address (struct comp_ + if (unit->error) + return FALSE; + +- if (unit->minmax.high < addr || unit->minmax.low > addr) +- return FALSE; +- + /* We know that the address *might* be contained within this comp + unit, but we cannot be sure until we check the specific ranges. */ + arange = &unit->arange; diff --git a/SOURCES/binutils-2.27-s390-pgste-marker.patch b/SOURCES/binutils-2.27-s390-pgste-marker.patch new file mode 100644 index 0000000..e864c39 --- /dev/null +++ b/SOURCES/binutils-2.27-s390-pgste-marker.patch @@ -0,0 +1,354 @@ +diff -rup binutils.orig/bfd/elf64-s390.c binutils-2.27/bfd/elf64-s390.c +--- binutils.orig/bfd/elf64-s390.c 2017-08-29 13:09:44.135143399 +0100 ++++ binutils-2.27/bfd/elf64-s390.c 2017-08-29 13:10:37.272554164 +0100 +@@ -25,6 +25,7 @@ + #include "libbfd.h" + #include "elf-bfd.h" + #include "elf/s390.h" ++#include "elf-s390.h" + + /* In case we're on a 32-bit machine, construct a 64-bit "-1" value + from smaller values. Start with zero, widen, *then* decrement. */ +@@ -660,6 +661,9 @@ struct elf_s390_link_hash_table + + /* Small local sym cache. */ + struct sym_cache sym_cache; ++ ++ /* Options passed from the linker. */ ++ struct s390_elf_params *params; + }; + + /* Get the s390 ELF linker hash table from a link_info structure. */ +@@ -3883,6 +3887,70 @@ elf64_s390_merge_private_bfd_data (bfd * + return TRUE; + } + ++/* We may add a PT_S390_PGSTE program header. */ ++ ++static int ++elf_s390_additional_program_headers (bfd *abfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info *info) ++{ ++ struct elf_s390_link_hash_table *htab; ++ ++ htab = elf_s390_hash_table (info); ++ return htab->params->pgste; ++} ++ ++ ++/* Add the PT_S390_PGSTE program header. */ ++ ++static bfd_boolean ++elf_s390_modify_segment_map (bfd *abfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info *info) ++{ ++ struct elf_s390_link_hash_table *htab; ++ struct elf_segment_map *m, *pm = NULL; ++ ++ htab = elf_s390_hash_table (info); ++ if (!htab->params->pgste) ++ return TRUE; ++ ++ /* If there is already a PT_S390_PGSTE header, avoid adding ++ another. */ ++ m = elf_seg_map (abfd); ++ while (m && m->p_type != PT_S390_PGSTE) ++ { ++ pm = m; ++ m = m->next; ++ } ++ ++ if (m) ++ return TRUE; ++ ++ m = (struct elf_segment_map *) ++ bfd_zalloc (abfd, sizeof (struct elf_segment_map)); ++ if (m == NULL) ++ return FALSE; ++ m->p_type = PT_S390_PGSTE; ++ m->count = 0; ++ m->next = NULL; ++ if (pm) ++ pm->next = m; ++ ++ return TRUE; ++} ++ ++bfd_boolean ++bfd_elf_s390_set_options (struct bfd_link_info *info, ++ struct s390_elf_params *params) ++{ ++ struct elf_s390_link_hash_table *htab; ++ ++ htab = elf_s390_hash_table (info); ++ htab->params = params; ++ ++ return TRUE; ++} ++ ++ + /* Why was the hash table entry size definition changed from + ARCH_SIZE/8 to 4? This breaks the 64 bit dynamic linker and + this is the only reason for the s390_elf64_size_info structure. */ +@@ -3959,6 +4027,8 @@ const struct elf_size_info s390_elf64_si + #define elf_backend_plt_sym_val elf_s390_plt_sym_val + #define elf_backend_add_symbol_hook elf_s390_add_symbol_hook + #define elf_backend_sort_relocs_p elf_s390_elf_sort_relocs_p ++#define elf_backend_additional_program_headers elf_s390_additional_program_headers ++#define elf_backend_modify_segment_map elf_s390_modify_segment_map + + #define bfd_elf64_mkobject elf_s390_mkobject + #define elf_backend_object_p elf_s390_object_p +diff -rup binutils.orig/binutils/readelf.c binutils-2.27/binutils/readelf.c +--- binutils.orig/binutils/readelf.c 2017-08-29 13:09:44.138143366 +0100 ++++ binutils-2.27/binutils/readelf.c 2017-08-29 13:09:53.384040839 +0100 +@@ -3610,6 +3610,16 @@ get_arm_segment_type (unsigned long type + } + + static const char * ++get_s390_segment_type (unsigned long type) ++{ ++ switch (type) ++ { ++ case PT_S390_PGSTE: return "S390_PGSTE"; ++ default: return NULL; ++ } ++} ++ ++static const char * + get_mips_segment_type (unsigned long type) + { + switch (type) +@@ -3755,6 +3765,10 @@ get_segment_type (unsigned long p_type) + case EM_TI_C6000: + result = get_tic6x_segment_type (p_type); + break; ++ case EM_S390: ++ case EM_S390_OLD: ++ result = get_s390_segment_type (p_type); ++ break; + default: + result = NULL; + break; +diff -rup binutils.orig/elfcpp/elfcpp.h binutils-2.27/elfcpp/elfcpp.h +--- binutils.orig/elfcpp/elfcpp.h 2017-08-29 13:09:44.182142878 +0100 ++++ binutils-2.27/elfcpp/elfcpp.h 2017-08-29 13:09:53.385040828 +0100 +@@ -514,7 +514,9 @@ enum PT + // Platform architecture compatibility information + PT_AARCH64_ARCHEXT = 0x70000000, + // Exception unwind tables +- PT_AARCH64_UNWIND = 0x70000001 ++ PT_AARCH64_UNWIND = 0x70000001, ++ // 4k page table size ++ PT_S390_PGSTE = 0x70000000, + }; + + // The valid bit flags found in the Phdr p_flags field. +diff -rup binutils.orig/include/elf/s390.h binutils-2.27/include/elf/s390.h +--- binutils.orig/include/elf/s390.h 2017-08-29 13:09:44.434140083 +0100 ++++ binutils-2.27/include/elf/s390.h 2017-08-29 13:09:53.385040828 +0100 +@@ -37,6 +37,9 @@ + + #define EF_S390_HIGH_GPRS 0x00000001 + ++/* Request 4k page table size. */ ++#define PT_S390_PGSTE (PT_LOPROC + 0) ++ + /* Relocation types. */ + + START_RELOC_NUMBERS (elf_s390_reloc_type) +diff -rup binutils.orig/ld/emulparams/elf64_s390.sh binutils-2.27/ld/emulparams/elf64_s390.sh +--- binutils.orig/ld/emulparams/elf64_s390.sh 2017-08-29 13:09:44.441140006 +0100 ++++ binutils-2.27/ld/emulparams/elf64_s390.sh 2017-08-29 13:09:53.385040828 +0100 +@@ -12,6 +12,7 @@ TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + GENERATE_PIE_SCRIPT=yes + NO_SMALL_DATA=yes ++EXTRA_EM_FILE=s390 + IREL_IN_PLT= + + # Treat a host that matches the target with the possible exception of "x" +diff -rup binutils.orig/ld/gen-doc.texi binutils-2.27/ld/gen-doc.texi +--- binutils.orig/ld/gen-doc.texi 2017-08-29 13:09:44.445139961 +0100 ++++ binutils-2.27/ld/gen-doc.texi 2017-08-29 13:09:53.385040828 +0100 +@@ -21,6 +21,7 @@ + @set POWERPC + @set POWERPC64 + @set Renesas ++@set S/390 + @set SPU + @set TICOFF + @set WIN32 +diff -rup binutils.orig/ld/ld.texinfo binutils-2.27/ld/ld.texinfo +--- binutils.orig/ld/ld.texinfo 2017-08-29 13:09:44.445139961 +0100 ++++ binutils-2.27/ld/ld.texinfo 2017-08-29 13:09:53.385040828 +0100 +@@ -34,6 +34,7 @@ + @set POWERPC + @set POWERPC64 + @set Renesas ++@set S/390 + @set SPU + @set TICOFF + @set WIN32 +@@ -158,6 +159,9 @@ in the section entitled ``GNU Free Docum + @ifset POWERPC64 + * PowerPC64 ELF64:: ld and PowerPC64 64-bit ELF Support + @end ifset ++@ifset S/390 ++* S/390 ELF:: ld and S/390 ELF Support ++@end ifset + @ifset SPU + * SPU ELF:: ld and SPU ELF Support + @end ifset +@@ -6380,6 +6384,9 @@ functionality are not listed. + @ifset POWERPC64 + * PowerPC64 ELF64:: @command{ld} and PowerPC64 64-bit ELF Support + @end ifset ++@ifset S/390 ++* S/390 ELF:: @command{ld} and S/390 ELF Support ++@end ifset + @ifset SPU + * SPU ELF:: @command{ld} and SPU ELF Support + @end ifset +@@ -7373,6 +7380,30 @@ default behaviour. + @end table + + @ifclear GENERIC ++@lowersections ++@end ifclear ++@end ifset ++ ++@ifset S/390 ++@ifclear GENERIC ++@raisesections ++@end ifclear ++ ++@node S/390 ELF ++@section @command{ld} and S/390 ELF Support ++ ++@cindex S/390 ELF options ++@table @option ++ ++@cindex S/390 ++@kindex --s390-pgste ++@item --s390-pgste ++This option marks the result file with a @code{PT_S390_PGSTE} ++segment. The Linux kernel is supposed to allocate 4k page tables for ++binaries marked that way. ++@end table ++ ++@ifclear GENERIC + @lowersections + @end ifclear + @end ifset +diff -rup binutils.orig/ld/Makefile.in binutils-2.27/ld/Makefile.in +--- binutils.orig/ld/Makefile.in 2017-08-29 13:09:44.446139950 +0100 ++++ binutils-2.27/ld/Makefile.in 2017-08-29 13:09:53.385040828 +0100 +@@ -3490,6 +3490,7 @@ eelf64_ia64_vms.c: $(srcdir)/emulparams/ + $(srcdir)/scripttempl/ia64vms.sc ${GEN_DEPENDS} + + eelf64_s390.c: $(srcdir)/emulparams/elf64_s390.sh \ ++ $(srcdir)/emultempl/s390.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + + eelf64_sparc.c: $(srcdir)/emulparams/elf64_sparc.sh \ + +--- /dev/null 2017-08-29 08:03:33.387685165 +0100 ++++ binutils-2.27/bfd/elf-s390.h 2017-08-29 13:19:31.705627899 +0100 +@@ -0,0 +1,29 @@ ++/* S/390-specific support for ELF. ++ Copyright (C) 2017 Free Software Foundation, Inc. ++ ++ This file is part of BFD, the Binary File Descriptor library. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++ MA 02110-1301, USA. */ ++ ++/* Used to pass info between ld and bfd. */ ++struct s390_elf_params ++{ ++ /* Tell the kernel to allocate 4k page tables. */ ++ int pgste; ++}; ++ ++bfd_boolean bfd_elf_s390_set_options (struct bfd_link_info *info, ++ struct s390_elf_params *params); +--- /dev/null 2017-08-29 08:03:33.387685165 +0100 ++++ binutils-2.27/ld/emultempl/s390.em 2017-08-29 13:26:01.797302217 +0100 +@@ -0,0 +1,64 @@ ++# This shell script emits a C file. -*- C -*- ++# Copyright (C) 2017 Free Software Foundation, Inc. ++# ++# This file is part of the GNU Binutils. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the license, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; see the file COPYING3. If not, ++# see . ++# ++ ++# This file is sourced from elf-generic.em, and defines S/390 ++# specific routines. ++# ++fragment <: ++.*: e7 f1 40 00 06 85 [ ]*vbperm %v15,%v17,%v20 ++.*: e7 f6 9f a0 60 04 [ ]*vllezlf %v15,4000\(%r6,%r9\) ++.*: e7 f1 4d c0 87 b8 [ ]*vmsl %v15,%v17,%v20,%v24,13,12 ++.*: e7 f1 43 d0 87 b8 [ ]*vmslg %v15,%v17,%v20,%v24,13 ++.*: e7 f1 40 00 06 6c [ ]*vnx %v15,%v17,%v20 ++.*: e7 f1 40 00 06 6e [ ]*vnn %v15,%v17,%v20 ++.*: e7 f1 40 00 06 6f [ ]*voc %v15,%v17,%v20 ++.*: e7 f1 00 00 04 50 [ ]*vpopctb %v15,%v17 ++.*: e7 f1 00 00 14 50 [ ]*vpopcth %v15,%v17 ++.*: e7 f1 00 00 24 50 [ ]*vpopctf %v15,%v17 ++.*: e7 f1 00 00 34 50 [ ]*vpopctg %v15,%v17 ++.*: e7 f1 40 00 26 e3 [ ]*vfasb %v15,%v17,%v20 ++.*: e7 f1 40 08 26 e3 [ ]*wfasb %v15,%v17,%v20 ++.*: e7 f1 40 08 46 e3 [ ]*wfaxb %v15,%v17,%v20 ++.*: e7 f1 00 00 24 cb [ ]*wfcsb %v15,%v17 ++.*: e7 f1 00 00 44 cb [ ]*wfcxb %v15,%v17 ++.*: e7 f1 00 00 24 ca [ ]*wfksb %v15,%v17 ++.*: e7 f1 00 00 44 ca [ ]*wfkxb %v15,%v17 ++.*: e7 f1 40 00 26 e8 [ ]*vfcesb %v15,%v17,%v20 ++.*: e7 f1 40 10 26 e8 [ ]*vfcesbs %v15,%v17,%v20 ++.*: e7 f1 40 08 26 e8 [ ]*wfcesb %v15,%v17,%v20 ++.*: e7 f1 40 18 26 e8 [ ]*wfcesbs %v15,%v17,%v20 ++.*: e7 f1 40 08 46 e8 [ ]*wfcexb %v15,%v17,%v20 ++.*: e7 f1 40 18 46 e8 [ ]*wfcexbs %v15,%v17,%v20 ++.*: e7 f1 40 04 26 e8 [ ]*vfkesb %v15,%v17,%v20 ++.*: e7 f1 40 14 26 e8 [ ]*vfkesbs %v15,%v17,%v20 ++.*: e7 f1 40 0c 26 e8 [ ]*wfkesb %v15,%v17,%v20 ++.*: e7 f1 40 1c 26 e8 [ ]*wfkesbs %v15,%v17,%v20 ++.*: e7 f1 40 04 36 e8 [ ]*vfkedb %v15,%v17,%v20 ++.*: e7 f1 40 14 36 e8 [ ]*vfkedbs %v15,%v17,%v20 ++.*: e7 f1 40 0c 36 e8 [ ]*wfkedb %v15,%v17,%v20 ++.*: e7 f1 40 1c 36 e8 [ ]*wfkedbs %v15,%v17,%v20 ++.*: e7 f1 40 0c 46 e8 [ ]*wfkexb %v15,%v17,%v20 ++.*: e7 f1 40 1c 46 e8 [ ]*wfkexbs %v15,%v17,%v20 ++.*: e7 f1 40 00 26 eb [ ]*vfchsb %v15,%v17,%v20 ++.*: e7 f1 40 10 26 eb [ ]*vfchsbs %v15,%v17,%v20 ++.*: e7 f1 40 08 26 eb [ ]*wfchsb %v15,%v17,%v20 ++.*: e7 f1 40 18 26 eb [ ]*wfchsbs %v15,%v17,%v20 ++.*: e7 f1 40 08 46 eb [ ]*wfchxb %v15,%v17,%v20 ++.*: e7 f1 40 18 46 eb [ ]*wfchxbs %v15,%v17,%v20 ++.*: e7 f1 40 04 26 eb [ ]*vfkhsb %v15,%v17,%v20 ++.*: e7 f1 40 14 26 eb [ ]*vfkhsbs %v15,%v17,%v20 ++.*: e7 f1 40 0c 26 eb [ ]*wfkhsb %v15,%v17,%v20 ++.*: e7 f1 40 1c 26 eb [ ]*wfkhsbs %v15,%v17,%v20 ++.*: e7 f1 40 04 36 eb [ ]*vfkhdb %v15,%v17,%v20 ++.*: e7 f1 40 14 36 eb [ ]*vfkhdbs %v15,%v17,%v20 ++.*: e7 f1 40 0c 36 eb [ ]*wfkhdb %v15,%v17,%v20 ++.*: e7 f1 40 1c 36 eb [ ]*wfkhdbs %v15,%v17,%v20 ++.*: e7 f1 40 0c 46 eb [ ]*wfkhxb %v15,%v17,%v20 ++.*: e7 f1 40 1c 46 eb [ ]*wfkhxbs %v15,%v17,%v20 ++.*: e7 f1 40 00 26 ea [ ]*vfchesb %v15,%v17,%v20 ++.*: e7 f1 40 10 26 ea [ ]*vfchesbs %v15,%v17,%v20 ++.*: e7 f1 40 08 26 ea [ ]*wfchesb %v15,%v17,%v20 ++.*: e7 f1 40 18 26 ea [ ]*wfchesbs %v15,%v17,%v20 ++.*: e7 f1 40 08 46 ea [ ]*wfchexb %v15,%v17,%v20 ++.*: e7 f1 40 18 46 ea [ ]*wfchexbs %v15,%v17,%v20 ++.*: e7 f1 40 04 26 ea [ ]*vfkhesb %v15,%v17,%v20 ++.*: e7 f1 40 14 26 ea [ ]*vfkhesbs %v15,%v17,%v20 ++.*: e7 f1 40 0c 26 ea [ ]*wfkhesb %v15,%v17,%v20 ++.*: e7 f1 40 1c 26 ea [ ]*wfkhesbs %v15,%v17,%v20 ++.*: e7 f1 40 04 36 ea [ ]*vfkhedb %v15,%v17,%v20 ++.*: e7 f1 40 14 36 ea [ ]*vfkhedbs %v15,%v17,%v20 ++.*: e7 f1 40 0c 36 ea [ ]*wfkhedb %v15,%v17,%v20 ++.*: e7 f1 40 1c 36 ea [ ]*wfkhedbs %v15,%v17,%v20 ++.*: e7 f1 40 0c 46 ea [ ]*wfkhexb %v15,%v17,%v20 ++.*: e7 f1 40 1c 46 ea [ ]*wfkhexbs %v15,%v17,%v20 ++.*: e7 f1 40 00 26 e5 [ ]*vfdsb %v15,%v17,%v20 ++.*: e7 f1 40 08 26 e5 [ ]*wfdsb %v15,%v17,%v20 ++.*: e7 f1 40 08 46 e5 [ ]*wfdxb %v15,%v17,%v20 ++.*: e7 f1 00 cd 24 c7 [ ]*wfisb %v15,%v17,5,12 ++.*: e7 f1 00 cd 24 c7 [ ]*wfisb %v15,%v17,5,12 ++.*: e7 f1 00 cd 44 c7 [ ]*wfixb %v15,%v17,5,12 ++.*: e7 f1 00 0c d4 c4 [ ]*vfll %v15,%v17,13,12 ++.*: e7 f1 00 00 24 c4 [ ]*vflls %v15,%v17 ++.*: e7 f1 00 08 24 c4 [ ]*wflls %v15,%v17 ++.*: e7 f1 00 08 34 c4 [ ]*wflld %v15,%v17 ++.*: e7 f1 00 bc d4 c5 [ ]*vflr %v15,%v17,13,12,11 ++.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12 ++.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12 ++.*: e7 f1 00 cd 44 c5 [ ]*wflrx %v15,%v17,5,12 ++.*: e7 f1 40 bc d6 ef [ ]*vfmax %v15,%v17,%v20,13,12,11 ++.*: e7 f1 40 d0 26 ef [ ]*vfmaxsb %v15,%v17,%v20,13 ++.*: e7 f1 40 d0 36 ef [ ]*vfmaxdb %v15,%v17,%v20,13 ++.*: e7 f1 40 d8 26 ef [ ]*wfmaxsb %v15,%v17,%v20,13 ++.*: e7 f1 40 d8 36 ef [ ]*wfmaxdb %v15,%v17,%v20,13 ++.*: e7 f1 40 d8 46 ef [ ]*wfmaxxb %v15,%v17,%v20,13 ++.*: e7 f1 40 bc d6 ee [ ]*vfmin %v15,%v17,%v20,13,12,11 ++.*: e7 f1 40 d0 26 ee [ ]*vfminsb %v15,%v17,%v20,13 ++.*: e7 f1 40 d0 36 ee [ ]*vfmindb %v15,%v17,%v20,13 ++.*: e7 f1 40 d8 26 ee [ ]*wfminsb %v15,%v17,%v20,13 ++.*: e7 f1 40 d8 36 ee [ ]*wfmindb %v15,%v17,%v20,13 ++.*: e7 f1 40 d8 46 ee [ ]*wfminxb %v15,%v17,%v20,13 ++.*: e7 f1 40 00 26 e7 [ ]*vfmsb %v15,%v17,%v20 ++.*: e7 f1 40 08 26 e7 [ ]*wfmsb %v15,%v17,%v20 ++.*: e7 f1 40 08 46 e7 [ ]*wfmxb %v15,%v17,%v20 ++.*: e7 f1 42 00 87 8f [ ]*vfmasb %v15,%v17,%v20,%v24 ++.*: e7 f1 42 08 87 8f [ ]*wfmasb %v15,%v17,%v20,%v24 ++.*: e7 f1 44 08 87 8f [ ]*wfmaxb %v15,%v17,%v20,%v24 ++.*: e7 f1 42 00 87 8e [ ]*vfmssb %v15,%v17,%v20,%v24 ++.*: e7 f1 42 08 87 8e [ ]*wfmssb %v15,%v17,%v20,%v24 ++.*: e7 f1 44 08 87 8e [ ]*wfmsxb %v15,%v17,%v20,%v24 ++.*: e7 f1 4c 0d 87 9f [ ]*vfnma %v15,%v17,%v20,%v24,13,12 ++.*: e7 f1 42 00 87 9f [ ]*vfnmasb %v15,%v17,%v20,%v24 ++.*: e7 f1 42 08 87 9f [ ]*wfnmasb %v15,%v17,%v20,%v24 ++.*: e7 f1 43 00 87 9f [ ]*vfnmadb %v15,%v17,%v20,%v24 ++.*: e7 f1 43 08 87 9f [ ]*wfnmadb %v15,%v17,%v20,%v24 ++.*: e7 f1 44 08 87 9f [ ]*wfnmaxb %v15,%v17,%v20,%v24 ++.*: e7 f1 4c 0d 87 9e [ ]*vfnms %v15,%v17,%v20,%v24,13,12 ++.*: e7 f1 42 00 87 9e [ ]*vfnmssb %v15,%v17,%v20,%v24 ++.*: e7 f1 42 08 87 9e [ ]*wfnmssb %v15,%v17,%v20,%v24 ++.*: e7 f1 43 00 87 9e [ ]*vfnmsdb %v15,%v17,%v20,%v24 ++.*: e7 f1 43 08 87 9e [ ]*wfnmsdb %v15,%v17,%v20,%v24 ++.*: e7 f1 44 08 87 9e [ ]*wfnmsxb %v15,%v17,%v20,%v24 ++.*: e7 f1 00 d0 24 cc [ ]*vfpsosb %v15,%v17,13 ++.*: e7 f1 00 d8 24 cc [ ]*wfpsosb %v15,%v17,13 ++.*: e7 f1 00 00 24 cc [ ]*vflcsb %v15,%v17 ++.*: e7 f1 00 08 24 cc [ ]*wflcsb %v15,%v17 ++.*: e7 f1 00 10 24 cc [ ]*vflnsb %v15,%v17 ++.*: e7 f1 00 18 24 cc [ ]*wflnsb %v15,%v17 ++.*: e7 f1 00 20 24 cc [ ]*vflpsb %v15,%v17 ++.*: e7 f1 00 28 24 cc [ ]*wflpsb %v15,%v17 ++.*: e7 f1 00 d8 44 cc [ ]*wfpsoxb %v15,%v17,13 ++.*: e7 f1 00 08 44 cc [ ]*wflcxb %v15,%v17 ++.*: e7 f1 00 18 44 cc [ ]*wflnxb %v15,%v17 ++.*: e7 f1 00 28 44 cc [ ]*wflpxb %v15,%v17 ++.*: e7 f1 00 00 24 ce [ ]*vfsqsb %v15,%v17 ++.*: e7 f1 00 08 24 ce [ ]*wfsqsb %v15,%v17 ++.*: e7 f1 00 08 44 ce [ ]*wfsqxb %v15,%v17 ++.*: e7 f1 40 00 26 e2 [ ]*vfssb %v15,%v17,%v20 ++.*: e7 f1 40 08 26 e2 [ ]*wfssb %v15,%v17,%v20 ++.*: e7 f1 40 08 46 e2 [ ]*wfsxb %v15,%v17,%v20 ++.*: e7 f1 ff d0 24 4a [ ]*vftcisb %v15,%v17,4093 ++.*: e7 f1 ff d8 24 4a [ ]*wftcisb %v15,%v17,4093 ++.*: e7 f1 ff d8 44 4a [ ]*wftcixb %v15,%v17,4093 ++.*: e3 69 b8 f0 fd 38 [ ]*agh %r6,-10000\(%r9,%r11\) ++.*: e3 d6 98 f0 fd 47 [ ]*binh -10000\(%r6,%r9\) ++.*: e3 f6 98 f0 fd 47 [ ]*bi -10000\(%r6,%r9\) ++.*: e3 16 98 f0 fd 47 [ ]*bio -10000\(%r6,%r9\) ++.*: e3 26 98 f0 fd 47 [ ]*bih -10000\(%r6,%r9\) ++.*: e3 26 98 f0 fd 47 [ ]*bih -10000\(%r6,%r9\) ++.*: e3 36 98 f0 fd 47 [ ]*binle -10000\(%r6,%r9\) ++.*: e3 46 98 f0 fd 47 [ ]*bil -10000\(%r6,%r9\) ++.*: e3 46 98 f0 fd 47 [ ]*bil -10000\(%r6,%r9\) ++.*: e3 56 98 f0 fd 47 [ ]*binhe -10000\(%r6,%r9\) ++.*: e3 66 98 f0 fd 47 [ ]*bilh -10000\(%r6,%r9\) ++.*: e3 76 98 f0 fd 47 [ ]*bine -10000\(%r6,%r9\) ++.*: e3 76 98 f0 fd 47 [ ]*bine -10000\(%r6,%r9\) ++.*: e3 86 98 f0 fd 47 [ ]*bie -10000\(%r6,%r9\) ++.*: e3 86 98 f0 fd 47 [ ]*bie -10000\(%r6,%r9\) ++.*: e3 96 98 f0 fd 47 [ ]*binlh -10000\(%r6,%r9\) ++.*: e3 a6 98 f0 fd 47 [ ]*bihe -10000\(%r6,%r9\) ++.*: e3 b6 98 f0 fd 47 [ ]*binl -10000\(%r6,%r9\) ++.*: e3 b6 98 f0 fd 47 [ ]*binl -10000\(%r6,%r9\) ++.*: e3 c6 98 f0 fd 47 [ ]*bile -10000\(%r6,%r9\) ++.*: e3 d6 98 f0 fd 47 [ ]*binh -10000\(%r6,%r9\) ++.*: e3 d6 98 f0 fd 47 [ ]*binh -10000\(%r6,%r9\) ++.*: e3 e6 98 f0 fd 47 [ ]*bino -10000\(%r6,%r9\) ++.*: b9 ec b0 69 [ ]*mgrk %r6,%r9,%r11 ++.*: e3 69 b8 f0 fd 84 [ ]*mg %r6,-10000\(%r9,%r11\) ++.*: e3 69 b8 f0 fd 3c [ ]*mgh %r6,-10000\(%r9,%r11\) ++.*: b9 fd b0 69 [ ]*msrkc %r6,%r9,%r11 ++.*: b9 ed b0 69 [ ]*msgrkc %r6,%r9,%r11 ++.*: e3 69 b8 f0 fd 53 [ ]*msc %r6,-10000\(%r9,%r11\) ++.*: e3 69 b8 f0 fd 83 [ ]*msgc %r6,-10000\(%r9,%r11\) ++.*: e3 69 b8 f0 fd 39 [ ]*sgh %r6,-10000\(%r9,%r11\) ++.*: e6 06 9f a0 f0 37 [ ]*vlrlr %v15,%r6,4000\(%r9\) ++.*: e6 fd 6f a0 f0 35 [ ]*vlrl %v15,4000\(%r6\),253 ++.*: e6 06 9f a0 f0 3f [ ]*vstrlr %v15,%r6,4000\(%r9\) ++.*: e6 fd 6f a0 f0 3d [ ]*vstrl %v15,4000\(%r6\),253 ++.*: e6 f1 40 cf d6 71 [ ]*vap %v15,%v17,%v20,253,12 ++.*: e6 0f 10 d0 02 77 [ ]*vcp %v15,%v17,13 ++.*: e6 6f 00 d0 00 50 [ ]*vcvb %r6,%v15,13 ++.*: e6 6f 00 d0 00 52 [ ]*vcvbg %r6,%v15,13 ++.*: e6 f6 00 cf d0 58 [ ]*vcvd %v15,%r6,253,12 ++.*: e6 f6 00 cf d0 5a [ ]*vcvdg %v15,%r6,253,12 ++.*: e6 f1 40 cf d6 7a [ ]*vdp %v15,%v17,%v20,253,12 ++.*: e6 f0 ff fd c0 49 [ ]*vlip %v15,65533,12 ++.*: e6 f1 40 cf d6 78 [ ]*vmp %v15,%v17,%v20,253,12 ++.*: e6 f1 40 cf d6 79 [ ]*vmsp %v15,%v17,%v20,253,12 ++.*: e6 fd 6f a0 f0 34 [ ]*vpkz %v15,4000\(%r6\),253 ++.*: e6 f1 fc bf d4 5b [ ]*vpsop %v15,%v17,253,252,11 ++.*: e6 f1 40 cf d6 7b [ ]*vrp %v15,%v17,%v20,253,12 ++.*: e6 f1 40 cf d6 7e [ ]*vsdp %v15,%v17,%v20,253,12 ++.*: e6 f1 fc bf d4 59 [ ]*vsrp %v15,%v17,253,252,11 ++.*: e6 f1 40 cf d6 73 [ ]*vsp %v15,%v17,%v20,253,12 ++.*: e6 0f 00 00 00 5f [ ]*vtp %v15 ++.*: e6 fd 6f a0 f0 3c [ ]*vupkz %v15,4000\(%r6\),253 ++.*: e3 69 b8 f0 fd 4c [ ]*lgg %r6,-10000\(%r9,%r11\) ++.*: e3 69 b8 f0 fd 48 [ ]*llgfsg %r6,-10000\(%r9,%r11\) ++.*: e3 69 b8 f0 fd 4d [ ]*lgsc %r6,-10000\(%r9,%r11\) ++.*: e3 69 b8 f0 fd 49 [ ]*stgsc %r6,-10000\(%r9,%r11\) ++.*: b9 29 90 6b [ ]*kma %r6,%r9,%r11 +diff --git a/gas/testsuite/gas/s390/zarch-arch12.s b/gas/testsuite/gas/s390/zarch-arch12.s +new file mode 100644 +index 0000000..6ebd2fd +--- /dev/null ++++ b/gas/testsuite/gas/s390/zarch-arch12.s +@@ -0,0 +1,194 @@ ++.text ++foo: ++ vbperm %v15,%v17,%v20 ++ vllezlf %v15,4000(%r6,%r9) ++ vmsl %v15,%v17,%v20,%v24,13,12 ++ vmslg %v15,%v17,%v20,%v24,13 ++ vnx %v15,%v17,%v20 ++ vnn %v15,%v17,%v20 ++ voc %v15,%v17,%v20 ++ vpopctb %v15,%v17 ++ vpopcth %v15,%v17 ++ vpopctf %v15,%v17 ++ vpopctg %v15,%v17 ++ vfasb %v15,%v17,%v20 ++ wfasb %v15,%v17,%v20 ++ wfaxb %v15,%v17,%v20 ++ wfcsb %v15,%v17 ++ wfcxb %v15,%v17 ++ wfksb %v15,%v17 ++ wfkxb %v15,%v17 ++ vfcesb %v15,%v17,%v20 ++ vfcesbs %v15,%v17,%v20 ++ wfcesb %v15,%v17,%v20 ++ wfcesbs %v15,%v17,%v20 ++ wfcexb %v15,%v17,%v20 ++ wfcexbs %v15,%v17,%v20 ++ vfkesb %v15,%v17,%v20 ++ vfkesbs %v15,%v17,%v20 ++ wfkesb %v15,%v17,%v20 ++ wfkesbs %v15,%v17,%v20 ++ vfkedb %v15,%v17,%v20 ++ vfkedbs %v15,%v17,%v20 ++ wfkedb %v15,%v17,%v20 ++ wfkedbs %v15,%v17,%v20 ++ wfkexb %v15,%v17,%v20 ++ wfkexbs %v15,%v17,%v20 ++ vfchsb %v15,%v17,%v20 ++ vfchsbs %v15,%v17,%v20 ++ wfchsb %v15,%v17,%v20 ++ wfchsbs %v15,%v17,%v20 ++ wfchxb %v15,%v17,%v20 ++ wfchxbs %v15,%v17,%v20 ++ vfkhsb %v15,%v17,%v20 ++ vfkhsbs %v15,%v17,%v20 ++ wfkhsb %v15,%v17,%v20 ++ wfkhsbs %v15,%v17,%v20 ++ vfkhdb %v15,%v17,%v20 ++ vfkhdbs %v15,%v17,%v20 ++ wfkhdb %v15,%v17,%v20 ++ wfkhdbs %v15,%v17,%v20 ++ wfkhxb %v15,%v17,%v20 ++ wfkhxbs %v15,%v17,%v20 ++ vfchesb %v15,%v17,%v20 ++ vfchesbs %v15,%v17,%v20 ++ wfchesb %v15,%v17,%v20 ++ wfchesbs %v15,%v17,%v20 ++ wfchexb %v15,%v17,%v20 ++ wfchexbs %v15,%v17,%v20 ++ vfkhesb %v15,%v17,%v20 ++ vfkhesbs %v15,%v17,%v20 ++ wfkhesb %v15,%v17,%v20 ++ wfkhesbs %v15,%v17,%v20 ++ vfkhedb %v15,%v17,%v20 ++ vfkhedbs %v15,%v17,%v20 ++ wfkhedb %v15,%v17,%v20 ++ wfkhedbs %v15,%v17,%v20 ++ wfkhexb %v15,%v17,%v20 ++ wfkhexbs %v15,%v17,%v20 ++ vfdsb %v15,%v17,%v20 ++ wfdsb %v15,%v17,%v20 ++ wfdxb %v15,%v17,%v20 ++ vfisb %v15,%v17,13,12 ++ wfisb %v15,%v17,13,12 ++ wfixb %v15,%v17,13,12 ++ vfll %v15,%v17,13,12 ++ vflls %v15,%v17 ++ wflls %v15,%v17 ++ wflld %v15,%v17 ++ vflr %v15,%v17,13,12,11 ++ vflrd %v15,%v17,13,12 ++ wflrd %v15,%v17,13,12 ++ wflrx %v15,%v17,13,12 ++ vfmax %v15,%v17,%v20,13,12,11 ++ vfmaxsb %v15,%v17,%v20,13 ++ vfmaxdb %v15,%v17,%v20,13 ++ wfmaxsb %v15,%v17,%v20,13 ++ wfmaxdb %v15,%v17,%v20,13 ++ wfmaxxb %v15,%v17,%v20,13 ++ vfmin %v15,%v17,%v20,13,12,11 ++ vfminsb %v15,%v17,%v20,13 ++ vfmindb %v15,%v17,%v20,13 ++ wfminsb %v15,%v17,%v20,13 ++ wfmindb %v15,%v17,%v20,13 ++ wfminxb %v15,%v17,%v20,13 ++ vfmsb %v15,%v17,%v20 ++ wfmsb %v15,%v17,%v20 ++ wfmxb %v15,%v17,%v20 ++ vfmasb %v15,%v17,%v20,%v24 ++ wfmasb %v15,%v17,%v20,%v24 ++ wfmaxb %v15,%v17,%v20,%v24 ++ vfmssb %v15,%v17,%v20,%v24 ++ wfmssb %v15,%v17,%v20,%v24 ++ wfmsxb %v15,%v17,%v20,%v24 ++ vfnma %v15,%v17,%v20,%v24,13,12 ++ vfnmasb %v15,%v17,%v20,%v24 ++ wfnmasb %v15,%v17,%v20,%v24 ++ vfnmadb %v15,%v17,%v20,%v24 ++ wfnmadb %v15,%v17,%v20,%v24 ++ wfnmaxb %v15,%v17,%v20,%v24 ++ vfnms %v15,%v17,%v20,%v24,13,12 ++ vfnmssb %v15,%v17,%v20,%v24 ++ wfnmssb %v15,%v17,%v20,%v24 ++ vfnmsdb %v15,%v17,%v20,%v24 ++ wfnmsdb %v15,%v17,%v20,%v24 ++ wfnmsxb %v15,%v17,%v20,%v24 ++ vfpsosb %v15,%v17,13 ++ wfpsosb %v15,%v17,13 ++ vflcsb %v15,%v17 ++ wflcsb %v15,%v17 ++ vflnsb %v15,%v17 ++ wflnsb %v15,%v17 ++ vflpsb %v15,%v17 ++ wflpsb %v15,%v17 ++ wfpsoxb %v15,%v17,13 ++ wflcxb %v15,%v17 ++ wflnxb %v15,%v17 ++ wflpxb %v15,%v17 ++ vfsqsb %v15,%v17 ++ wfsqsb %v15,%v17 ++ wfsqxb %v15,%v17 ++ vfssb %v15,%v17,%v20 ++ wfssb %v15,%v17,%v20 ++ wfsxb %v15,%v17,%v20 ++ vftcisb %v15,%v17,4093 ++ wftcisb %v15,%v17,4093 ++ wftcixb %v15,%v17,4093 ++ agh %r6,-10000(%r9,%r11) ++ bic 13,-10000(%r6,%r9) ++ bi -10000(%r6,%r9) ++ bio -10000(%r6,%r9) ++ bih -10000(%r6,%r9) ++ bip -10000(%r6,%r9) ++ binle -10000(%r6,%r9) ++ bil -10000(%r6,%r9) ++ bim -10000(%r6,%r9) ++ binhe -10000(%r6,%r9) ++ bilh -10000(%r6,%r9) ++ bine -10000(%r6,%r9) ++ binz -10000(%r6,%r9) ++ bie -10000(%r6,%r9) ++ biz -10000(%r6,%r9) ++ binlh -10000(%r6,%r9) ++ bihe -10000(%r6,%r9) ++ binl -10000(%r6,%r9) ++ binm -10000(%r6,%r9) ++ bile -10000(%r6,%r9) ++ binh -10000(%r6,%r9) ++ binp -10000(%r6,%r9) ++ bino -10000(%r6,%r9) ++ mgrk %r6,%r9,%r11 ++ mg %r6,-10000(%r9,%r11) ++ mgh %r6,-10000(%r9,%r11) ++ msrkc %r6,%r9,%r11 ++ msgrkc %r6,%r9,%r11 ++ msc %r6,-10000(%r9,%r11) ++ msgc %r6,-10000(%r9,%r11) ++ sgh %r6,-10000(%r9,%r11) ++ vlrlr %v15,%r6,4000(%r9) ++ vlrl %v15,4000(%r6),253 ++ vstrlr %v15,%r6,4000(%r9) ++ vstrl %v15,4000(%r6),253 ++ vap %v15,%v17,%v20,253,12 ++ vcp %v15,%v17,13 ++ vcvb %r6,%v15,13 ++ vcvbg %r6,%v15,13 ++ vcvd %v15,%r6,253,12 ++ vcvdg %v15,%r6,253,12 ++ vdp %v15,%v17,%v20,253,12 ++ vlip %v15,65533,12 ++ vmp %v15,%v17,%v20,253,12 ++ vmsp %v15,%v17,%v20,253,12 ++ vpkz %v15,4000(%r6),253 ++ vpsop %v15,%v17,253,252,11 ++ vrp %v15,%v17,%v20,253,12 ++ vsdp %v15,%v17,%v20,253,12 ++ vsrp %v15,%v17,253,252,11 ++ vsp %v15,%v17,%v20,253,12 ++ vtp %v15 ++ vupkz %v15,4000(%r6),253 ++ lgg %r6,-10000(%r9,%r11) ++ llgfsg %r6,-10000(%r9,%r11) ++ lgsc %r6,-10000(%r9,%r11) ++ stgsc %r6,-10000(%r9,%r11) ++ kma %r6,%r9,%r11 +diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-z13.d binutils-2.27/gas/testsuite/gas/s390/zarch-z13.d +--- binutils.orig/gas/testsuite/gas/s390/zarch-z13.d 2017-03-24 14:50:54.052789212 +0000 ++++ binutils-2.27/gas/testsuite/gas/s390/zarch-z13.d 2017-03-24 14:54:05.065330554 +0000 +@@ -513,12 +513,12 @@ Disassembly of section .text: + .*: e7 f1 00 bc d4 c7 [ ]*vfi %v15,%v17,13,12,11 + .*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 + .*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 +-.*: e7 f1 00 0c d4 c4 [ ]*vlde %v15,%v17,13,12 +-.*: e7 f1 00 00 24 c4 [ ]*vldeb %v15,%v17 +-.*: e7 f1 00 08 24 c4 [ ]*wldeb %v15,%v17 +-.*: e7 f1 00 bc d4 c5 [ ]*vled %v15,%v17,13,12,11 +-.*: e7 f1 00 cd 34 c5 [ ]*wledb %v15,%v17,5,12 +-.*: e7 f1 00 cd 34 c5 [ ]*wledb %v15,%v17,5,12 ++.*: e7 f1 00 0c d4 c4 [ ]*vfll %v15,%v17,13,12 ++.*: e7 f1 00 00 24 c4 [ ]*vflls %v15,%v17 ++.*: e7 f1 00 08 24 c4 [ ]*wflls %v15,%v17 ++.*: e7 f1 00 bc d4 c5 [ ]*vflr %v15,%v17,13,12,11 ++.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12 ++.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12 + .*: e7 f1 40 0c d6 e7 [ ]*vfm %v15,%v17,%v20,13,12 + .*: e7 f1 40 00 36 e7 [ ]*vfmdb %v15,%v17,%v20 + .*: e7 f1 40 08 36 e7 [ ]*wfmdb %v15,%v17,%v20 +diff -rup binutils.orig/include/opcode/s390.h binutils-2.27/include/opcode/s390.h +--- binutils.orig/include/opcode/s390.h 2017-03-24 14:51:01.896688195 +0000 ++++ binutils-2.27/include/opcode/s390.h 2017-03-24 14:54:05.065330554 +0000 +@@ -42,14 +42,17 @@ enum s390_opcode_cpu_val + S390_OPCODE_Z196, + S390_OPCODE_ZEC12, + S390_OPCODE_Z13, ++ S390_OPCODE_ARCH12, + S390_OPCODE_MAXCPU + }; + + /* Instruction specific flags. */ + #define S390_INSTR_FLAG_OPTPARM 0x1 ++ + #define S390_INSTR_FLAG_HTM 0x2 + #define S390_INSTR_FLAG_VX 0x4 +-#define S390_INSTR_FLAG_FACILITY_MASK 0x6 ++#define S390_INSTR_FLAG_VX2 0x8 ++#define S390_INSTR_FLAG_FACILITY_MASK 0xe + + /* The opcode table is an array of struct s390_opcode. */ + +diff -rup binutils.orig/opcodes/s390-mkopc.c binutils-2.27/opcodes/s390-mkopc.c +--- binutils.orig/opcodes/s390-mkopc.c 2017-03-24 14:50:54.849778948 +0000 ++++ binutils-2.27/opcodes/s390-mkopc.c 2017-03-24 14:54:05.065330554 +0000 +@@ -366,6 +366,8 @@ main (void) + min_cpu = S390_OPCODE_ZEC12; + else if (strcmp (cpu_string, "z13") == 0) + min_cpu = S390_OPCODE_Z13; ++ else if (strcmp (cpu_string, "arch12") == 0) ++ min_cpu = S390_OPCODE_ARCH12; + else { + fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); + exit (1); +@@ -409,6 +411,10 @@ main (void) + && (str[2] == 0 || str[2] == ',')) { + flag_bits |= S390_INSTR_FLAG_VX; + str += 2; ++ } else if (strncmp (str, "vx2", 3) == 0 ++ && (str[3] == 0 || str[3] == ',')) { ++ flag_bits |= S390_INSTR_FLAG_VX2; ++ str += 3; + } else { + fprintf (stderr, "Couldn't parse flags string %s\n", + flags_string); +diff -rup binutils.orig/opcodes/s390-opc.c binutils-2.27/opcodes/s390-opc.c +--- binutils.orig/opcodes/s390-opc.c 2017-03-24 14:50:54.850778935 +0000 ++++ binutils-2.27/opcodes/s390-opc.c 2017-03-24 14:54:05.065330554 +0000 +@@ -220,28 +220,30 @@ const struct s390_operand s390_operands[ + { 8, 16, 0 }, + #define U8_24 69 /* 8 bit unsigned value starting at 24 */ + { 8, 24, 0 }, +-#define U8_32 70 /* 8 bit unsigned value starting at 32 */ ++#define U8_28 70 /* 8 bit unsigned value starting at 28 */ ++ { 8, 28, 0 }, ++#define U8_32 71 /* 8 bit unsigned value starting at 32 */ + { 8, 32, 0 }, +-#define U12_16 71 /* 12 bit unsigned value starting at 16 */ ++#define U12_16 72 /* 12 bit unsigned value starting at 16 */ + { 12, 16, 0 }, +-#define U16_16 72 /* 16 bit unsigned value starting at 16 */ ++#define U16_16 73 /* 16 bit unsigned value starting at 16 */ + { 16, 16, 0 }, +-#define U16_32 73 /* 16 bit unsigned value starting at 32 */ ++#define U16_32 74 /* 16 bit unsigned value starting at 32 */ + { 16, 32, 0 }, +-#define U32_16 74 /* 32 bit unsigned value starting at 16 */ ++#define U32_16 75 /* 32 bit unsigned value starting at 16 */ + { 32, 16, 0 }, + + /* PC-relative address operands. */ + +-#define J12_12 75 /* 12 bit PC relative offset at 12 */ ++#define J12_12 76 /* 12 bit PC relative offset at 12 */ + { 12, 12, S390_OPERAND_PCREL }, +-#define J16_16 76 /* 16 bit PC relative offset at 16 */ ++#define J16_16 77 /* 16 bit PC relative offset at 16 */ + { 16, 16, S390_OPERAND_PCREL }, +-#define J16_32 77 /* 16 bit PC relative offset at 32 */ ++#define J16_32 78 /* 16 bit PC relative offset at 32 */ + { 16, 32, S390_OPERAND_PCREL }, +-#define J24_24 78 /* 24 bit PC relative offset at 24 */ ++#define J24_24 79 /* 24 bit PC relative offset at 24 */ + { 24, 24, S390_OPERAND_PCREL }, +-#define J32_16 79 /* 32 bit PC relative offset at 16 */ ++#define J32_16 80 /* 32 bit PC relative offset at 16 */ + { 32, 16, S390_OPERAND_PCREL }, + + }; +@@ -425,6 +427,7 @@ const struct s390_operand s390_operands[ + #define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ + #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ + #define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ ++#define INSTR_RXY_0RRD 6, { D20_20,X_12,B_16,0,0 } /* e.g. bic */ + #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ + #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ + #define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ +@@ -454,23 +457,29 @@ const struct s390_operand s390_operands[ + #define INSTR_VRI_V 6, { V_8,0,0,0,0,0 } /* e.g. vzero */ + #define INSTR_VRI_V0UUU 6, { V_8,U8_16,U8_24,U4_32,0,0 } /* e.g. vgm */ + #define INSTR_VRI_V0UU 6, { V_8,U8_16,U8_24,0,0,0 } /* e.g. vgmb */ ++#define INSTR_VRI_V0UU2 6, { V_8,U16_16,U4_32,0,0,0 } /* e.g. vlip */ + #define INSTR_VRI_VVUU 6, { V_8,V_12,U16_16,U4_32,0,0 } /* e.g. vrep */ + #define INSTR_VRI_VVU 6, { V_8,V_12,U16_16,0,0,0 } /* e.g. vrepb */ + #define INSTR_VRI_VVU2 6, { V_8,V_12,U12_16,0,0,0 } /* e.g. vftcidb */ + #define INSTR_VRI_V0IU 6, { V_8,I16_16,U4_32,0,0,0 } /* e.g. vrepi */ + #define INSTR_VRI_V0I 6, { V_8,I16_16,0,0,0,0 } /* e.g. vrepib */ + #define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ ++#define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */ + #define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ + #define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ ++#define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */ ++#define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */ + #define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ + #define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ +-#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrp */ ++#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */ + #define INSTR_VRS_RVRDU 6, { R_8,V_12,D_20,B_16,U4_32,0 } /* e.g. vlgv */ + #define INSTR_VRS_RVRD 6, { R_8,V_12,D_20,B_16,0,0 } /* e.g. vlgvb */ + #define INSTR_VRS_VVRDU 6, { V_8,V_12,D_20,B_16,U4_32,0 } /* e.g. verll */ + #define INSTR_VRS_VVRD 6, { V_8,V_12,D_20,B_16,0,0 } /* e.g. vlm */ + #define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ + #define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ ++#define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */ ++#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */ + #define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ + #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ + #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ +@@ -499,6 +508,9 @@ const struct s390_operand s390_operands[ + #define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ + #define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ + #define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ ++#define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */ ++#define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */ ++#define INSTR_VSI_URDV 6, { V_32,D_20,B_16,U8_8,0,0 } /* e.g. vlrl */ + + #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + #define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +@@ -631,6 +643,7 @@ const struct s390_operand s390_operands[ + #define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RXY_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } + #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +@@ -660,14 +673,18 @@ const struct s390_operand s390_operands[ + #define MASK_VRI_V { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff } + #define MASK_VRI_V0UUU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } + #define MASK_VRI_V0UU { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRI_V0UU2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } + #define MASK_VRI_VVUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + #define MASK_VRI_VVU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } + #define MASK_VRI_VVU2 { 0xff, 0x00, 0x00, 0x0f, 0xf0, 0xff } + #define MASK_VRI_V0IU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } + #define MASK_VRI_V0I { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } + #define MASK_VRI_VVV0UU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } ++#define MASK_VRI_VVV0UU2 { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } + #define MASK_VRI_VVV0U { 0xff, 0x00, 0x0f, 0x00, 0xf0, 0xff } + #define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } + #define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } + #define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } + #define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +@@ -677,6 +694,8 @@ const struct s390_operand s390_operands[ + #define MASK_VRS_VVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } + #define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + #define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff } + #define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } + #define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } + #define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } +@@ -705,36 +724,46 @@ const struct s390_operand s390_operands[ + #define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } + #define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } + #define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } ++#define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff } ++#define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } ++#define MASK_VSI_URDV { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++ + + /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ + + const struct s390_opcode s390_opformats[] = + { +- { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 }, +- { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 }, +- { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 }, +- { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 }, +- { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 }, +- { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 ,0 }, +- { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 }, +- { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 }, +- { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 }, +- { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 ,0 }, +- { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 }, +- { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 }, +- { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 }, +- { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 }, +- { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 }, +- { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 }, +- { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 ,0 }, +- { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 }, +- { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 }, +- { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 }, +- { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 }, +- { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 }, +- { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 ,0 }, +- { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 }, +- { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 ,0 }, ++ { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 }, ++ { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 }, ++ { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 }, ++ { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 }, ++ { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 }, ++ { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6 ,0 }, ++ { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 }, ++ { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 }, ++ { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 }, ++ { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6 ,0 }, ++ { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 }, ++ { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 }, ++ { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 }, ++ { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 }, ++ { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 }, ++ { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 }, ++ { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0 ,0 }, ++ { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 }, ++ { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 }, ++ { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 }, ++ { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 }, ++ { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 }, ++ { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0 ,0 }, ++ { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 }, ++ { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0 ,0 }, ++ { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9 ,0 }, ++ { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9 ,0 }, ++ { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9 ,0 }, ++ { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9 ,0 }, ++ { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9 ,0 }, ++ { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10 ,0 }, + }; + + const int s390_num_opformats = +diff -rup binutils.orig/opcodes/s390-opc.txt binutils-2.27/opcodes/s390-opc.txt +--- binutils.orig/opcodes/s390-opc.txt 2017-03-24 14:50:54.851778922 +0000 ++++ binutils-2.27/opcodes/s390-opc.txt 2017-03-24 14:54:05.066330541 +0000 +@@ -630,7 +630,7 @@ eb0000000051 tmy SIY_URD "test under mas + # 'old' instructions extended to long displacement + # these instructions are entered into the opcode table twice. + e30000000003 lrag RXY_RRRD "load real address with long offset 64" z990 zarch +-e30000000004 lg RXY_RRRD " load 64" z990 zarch ++e30000000004 lg RXY_RRRD "load 64" z990 zarch + e30000000008 ag RXY_RRRD "add with long offset 64" z990 zarch + e30000000009 sg RXY_RRRD "subtract with long offset 64" z990 zarch + e3000000000a alg RXY_RRRD "add logical with long offset 64" z990 zarch +@@ -1584,27 +1584,27 @@ e7000230008a vstrczfs VRR_VVVU0VB3 "vect + + # Chapter 24 + e700000000e3 vfa VRR_VVV0UU "vector fp add" z13 zarch vx +-e700000030e3 vfadb VRR_VVV "vector fp add" z13 zarch vx +-e700000830e3 wfadb VRR_VVV "vector fp add" z13 zarch vx ++e700000030e3 vfadb VRR_VVV "vector fp add long" z13 zarch vx ++e700000830e3 wfadb VRR_VVV "vector fp add long" z13 zarch vx + e700000000cb wfc VRR_VV0UU2 "vector fp compare scalar" z13 zarch vx +-e700000030cb wfcdb VRR_VV "vector fp compare scalar" z13 zarch vx ++e700000030cb wfcdb VRR_VV "vector fp compare scalar long" z13 zarch vx + e700000000ca wfk VRR_VV0UU2 "vector fp compare and signal scalar" z13 zarch vx +-e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar" z13 zarch vx ++e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar long" z13 zarch vx + e700000000e8 vfce VRR_VVV0UUU "vector fp compare equal" z13 zarch vx +-e700000030e8 vfcedb VRR_VVV "vector fp compare equal" z13 zarch vx +-e700001030e8 vfcedbs VRR_VVV "vector fp compare equal" z13 zarch vx +-e700000830e8 wfcedb VRR_VVV "vector fp compare equal" z13 zarch vx +-e700001830e8 wfcedbs VRR_VVV "vector fp compare equal" z13 zarch vx ++e700000030e8 vfcedb VRR_VVV "vector fp compare equal long" z13 zarch vx ++e700001030e8 vfcedbs VRR_VVV "vector fp compare equal long" z13 zarch vx ++e700000830e8 wfcedb VRR_VVV "vector fp compare equal long" z13 zarch vx ++e700001830e8 wfcedbs VRR_VVV "vector fp compare equal long" z13 zarch vx + e700000000eb vfch VRR_VVV0UUU "vector fp compare high" z13 zarch vx +-e700000030eb vfchdb VRR_VVV "vector fp compare high" z13 zarch vx +-e700001030eb vfchdbs VRR_VVV "vector fp compare high" z13 zarch vx +-e700000830eb wfchdb VRR_VVV "vector fp compare high" z13 zarch vx +-e700001830eb wfchdbs VRR_VVV "vector fp compare high" z13 zarch vx ++e700000030eb vfchdb VRR_VVV "vector fp compare high long" z13 zarch vx ++e700001030eb vfchdbs VRR_VVV "vector fp compare high long" z13 zarch vx ++e700000830eb wfchdb VRR_VVV "vector fp compare high long" z13 zarch vx ++e700001830eb wfchdbs VRR_VVV "vector fp compare high long" z13 zarch vx + e700000000ea vfche VRR_VVV0UUU "vector fp compare high or equal" z13 zarch vx +-e700000030ea vfchedb VRR_VVV "vector fp compare high or equal" z13 zarch vx +-e700001030ea vfchedbs VRR_VVV "vector fp compare high or equal" z13 zarch vx +-e700000830ea wfchedb VRR_VVV "vector fp compare high or equal" z13 zarch vx +-e700001830ea wfchedbs VRR_VVV "vector fp compare high or equal" z13 zarch vx ++e700000030ea vfchedb VRR_VVV "vector fp compare high or equal long" z13 zarch vx ++e700001030ea vfchedbs VRR_VVV "vector fp compare high or equal long" z13 zarch vx ++e700000830ea wfchedb VRR_VVV "vector fp compare high or equal long" z13 zarch vx ++e700001830ea wfchedbs VRR_VVV "vector fp compare high or equal long" z13 zarch vx + e700000000c3 vcdg VRR_VV0UUU "vector fp convert from fixed 64 bit" z13 zarch vx + e700000030c3 vcdgb VRR_VV0UU "vector fp convert from fixed 64 bit" z13 zarch vx + e700000830c3 wcdgb VRR_VV0UU8 "vector fp convert from fixed 64 bit" z13 zarch vx +@@ -1618,41 +1618,41 @@ e700000000c0 vclgd VRR_VV0UUU "vector fp + e700000030c0 vclgdb VRR_VV0UU "vector fp convert to logical 64 bit" z13 zarch vx + e700000830c0 wclgdb VRR_VV0UU8 "vector fp convert to logical 64 bit" z13 zarch vx + e700000000e5 vfd VRR_VVV0UU "vector fp divide" z13 zarch vx +-e700000030e5 vfddb VRR_VVV "vector fp divide" z13 zarch vx +-e700000830e5 wfddb VRR_VVV "vector fp divide" z13 zarch vx ++e700000030e5 vfddb VRR_VVV "vector fp divide long" z13 zarch vx ++e700000830e5 wfddb VRR_VVV "vector fp divide long" z13 zarch vx + e700000000c7 vfi VRR_VV0UUU "vector load fp integer" z13 zarch vx +-e700000030c7 vfidb VRR_VV0UU "vector load fp integer" z13 zarch vx +-e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer" z13 zarch vx ++e700000030c7 vfidb VRR_VV0UU "vector load fp integer long" z13 zarch vx ++e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer long" z13 zarch vx + e700000000c4 vlde VRR_VV0UU2 "vector fp load lengthened" z13 zarch vx +-e700000020c4 vldeb VRR_VV "vector fp load lengthened" z13 zarch vx +-e700000820c4 wldeb VRR_VV "vector fp load lengthened" z13 zarch vx ++e700000020c4 vldeb VRR_VV "vector fp load lengthened short to long" z13 zarch vx ++e700000820c4 wldeb VRR_VV "vector fp load lengthened short to long" z13 zarch vx + e700000000c5 vled VRR_VV0UUU "vector fp load rounded" z13 zarch vx +-e700000030c5 vledb VRR_VV0UU "vector fp load rounded" z13 zarch vx +-e700000830c5 wledb VRR_VV0UU8 "vector fp load rounded" z13 zarch vx ++e700000030c5 vledb VRR_VV0UU "vector fp load rounded long to short" z13 zarch vx ++e700000830c5 wledb VRR_VV0UU8 "vector fp load rounded long to short" z13 zarch vx + e700000000e7 vfm VRR_VVV0UU "vector fp multiply" z13 zarch vx +-e700000030e7 vfmdb VRR_VVV "vector fp multiply" z13 zarch vx +-e700000830e7 wfmdb VRR_VVV "vector fp multiply" z13 zarch vx ++e700000030e7 vfmdb VRR_VVV "vector fp multiply long" z13 zarch vx ++e700000830e7 wfmdb VRR_VVV "vector fp multiply long" z13 zarch vx + e7000000008f vfma VRR_VVVU0UV "vector fp multiply and add" z13 zarch vx +-e7000300008f vfmadb VRR_VVVV "vector fp multiply and add" z13 zarch vx +-e7000308008f wfmadb VRR_VVVV "vector fp multiply and add" z13 zarch vx ++e7000300008f vfmadb VRR_VVVV "vector fp multiply and add long" z13 zarch vx ++e7000308008f wfmadb VRR_VVVV "vector fp multiply and add long" z13 zarch vx + e7000000008e vfms VRR_VVVU0UV "vector fp multiply and subtract" z13 zarch vx +-e7000300008e vfmsdb VRR_VVVV "vector fp multiply and subtract" z13 zarch vx +-e7000308008e wfmsdb VRR_VVVV "vector fp multiply and subtract" z13 zarch vx ++e7000300008e vfmsdb VRR_VVVV "vector fp multiply and subtract long" z13 zarch vx ++e7000308008e wfmsdb VRR_VVVV "vector fp multiply and subtract long" z13 zarch vx + e700000000cc vfpso VRR_VV0UUU "vector fp perform sign operation" z13 zarch vx +-e700000030cc vfpsodb VRR_VV0U2 "vector fp perform sign operation" z13 zarch vx +-e700000830cc wfpsodb VRR_VV0U2 "vector fp perform sign operation" z13 zarch vx +-e700000030cc vflcdb VRR_VV "vector fp perform sign operation" z13 zarch vx +-e700000830cc wflcdb VRR_VV "vector fp perform sign operation" z13 zarch vx +-e700001030cc vflndb VRR_VV "vector fp perform sign operation" z13 zarch vx +-e700001830cc wflndb VRR_VV "vector fp perform sign operation" z13 zarch vx +-e700002030cc vflpdb VRR_VV "vector fp perform sign operation" z13 zarch vx +-e700002830cc wflpdb VRR_VV "vector fp perform sign operation" z13 zarch vx ++e700000030cc vfpsodb VRR_VV0U2 "vector fp perform sign operation long" z13 zarch vx ++e700000830cc wfpsodb VRR_VV0U2 "vector fp perform sign operation long" z13 zarch vx ++e700000030cc vflcdb VRR_VV "vector fp perform sign operation long" z13 zarch vx ++e700000830cc wflcdb VRR_VV "vector fp perform sign operation long" z13 zarch vx ++e700001030cc vflndb VRR_VV "vector fp perform sign operation long" z13 zarch vx ++e700001830cc wflndb VRR_VV "vector fp perform sign operation long" z13 zarch vx ++e700002030cc vflpdb VRR_VV "vector fp perform sign operation long" z13 zarch vx ++e700002830cc wflpdb VRR_VV "vector fp perform sign operation long" z13 zarch vx + e700000000ce vfsq VRR_VV0UU2 "vector fp square root" z13 zarch vx +-e700000030ce vfsqdb VRR_VV "vector fp square root" z13 zarch vx +-e700000830ce wfsqdb VRR_VV "vector fp square root" z13 zarch vx ++e700000030ce vfsqdb VRR_VV "vector fp square root long" z13 zarch vx ++e700000830ce wfsqdb VRR_VV "vector fp square root long" z13 zarch vx + e700000000e2 vfs VRR_VVV0UU "vector fp subtract" z13 zarch vx +-e700000030e2 vfsdb VRR_VVV "vector fp subtract" z13 zarch vx +-e700000830e2 wfsdb VRR_VVV "vector fp subtract" z13 zarch vx ++e700000030e2 vfsdb VRR_VVV "vector fp subtract long" z13 zarch vx ++e700000830e2 wfsdb VRR_VVV "vector fp subtract long" z13 zarch vx + e7000000004a vftci VRI_VVUUU "vector fp test data class immediate" z13 zarch vx + e7000000304a vftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch vx + e7000008304a wftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch vx +@@ -1679,3 +1679,200 @@ e3000000003a llzrgf RXY_RRRD "load logic + e3000000003b lzrf RXY_RRRD "load and zero rightmost byte 32->32" z13 zarch + e3000000002a lzrg RXY_RRRD "load and zero rightmost byte 64->64" z13 zarch + b93c ppno RRE_RR "perform pseudorandom number operation" z13 zarch ++ ++# arch12 instructions ++ ++# Vector Enhancements Facility 1 ++ ++e70000000085 vbperm VRR_VVV "vector bit permute" arch12 zarch ++e70000006004 vllezlf VRX_VRRD "vector load logical word element and zero - left aligned" arch12 zarch vx2 ++e700000000b8 vmsl VRR_VVVUU0V "vector multiply sum logical" arch12 zarch vx2 ++e700030000b8 vmslg VRR_VVVU0VB "vector multiply sum logical double word" arch12 zarch vx2 ++e7000000006c vnx VRR_VVV "vector not exclusive or" arch12 zarch vx2 ++e7000000006e vnn VRR_VVV "vector nand" arch12 zarch ++e7000000006f voc VRR_VVV "vector or with complement" arch12 zarch vx2 ++e70000000050 vpopctb VRR_VV "vector population count byte" arch12 zarch vx2 ++e70000001050 vpopcth VRR_VV "vector population count halfword" arch12 zarch vx2 ++e70000002050 vpopctf VRR_VV "vector population count word" arch12 zarch vx2 ++e70000003050 vpopctg VRR_VV "vector population count double word" arch12 zarch vx2 ++e700000020e3 vfasb VRR_VVV "vector fp add short" arch12 zarch vx2 ++e700000820e3 wfasb VRR_VVV "scalar vector fp add scalar short" arch12 zarch vx2 ++e700000840e3 wfaxb VRR_VVV "scalar vector fp add scalar extended" arch12 zarch vx2 ++e700000020cb wfcsb VRR_VV "scalar vector fp compare scalar short" arch12 zarch vx2 ++e700000040cb wfcxb VRR_VV "scalar vector fp compare scalar extended" arch12 zarch vx2 ++e700000020ca wfksb VRR_VV "scalar vector fp compare and signal scalar short" arch12 zarch vx2 ++e700000040ca wfkxb VRR_VV "scalar vector fp compare and signal scalar extended" arch12 zarch vx2 ++ ++e700000020e8 vfcesb VRR_VVV "vector fp compare equal short" arch12 zarch vx2 ++e700001020e8 vfcesbs VRR_VVV "vector fp compare equal short" arch12 zarch vx2 ++e700000820e8 wfcesb VRR_VVV "scalar vector fp compare equal scalar short" arch12 zarch vx2 ++e700001820e8 wfcesbs VRR_VVV "scalar fp compare equal scalar short" arch12 zarch vx2 ++e700000840e8 wfcexb VRR_VVV "scalar vector fp compare equal scalar extended" arch12 zarch vx2 ++e700001840e8 wfcexbs VRR_VVV "scalar vector fp compare equal scalar extended" arch12 zarch vx2 ++ ++e700000420e8 vfkesb VRR_VVV "vector fp compare and signal equal short" arch12 zarch vx2 ++e700001420e8 vfkesbs VRR_VVV "vector fp compare and signal equal short" arch12 zarch vx2 ++e700000c20e8 wfkesb VRR_VVV "scalar vector fp compare and signal equal scalar short" arch12 zarch vx2 ++e700001c20e8 wfkesbs VRR_VVV "scalar fp compare and signal equal scalar short" arch12 zarch vx2 ++e700000430e8 vfkedb VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx ++e700001430e8 vfkedbs VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx ++e700000c30e8 wfkedb VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx ++e700001c30e8 wfkedbs VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx ++e700000c40e8 wfkexb VRR_VVV "scalar vector fp compare and signal equal scalar extended" arch12 zarch vx2 ++e700001c40e8 wfkexbs VRR_VVV "scalar vector fp compare and signal equal scalar extended" arch12 zarch vx2 ++ ++e700000020eb vfchsb VRR_VVV "vector fp compare high short" arch12 zarch vx2 ++e700001020eb vfchsbs VRR_VVV "vector fp compare high short" arch12 zarch vx2 ++e700000820eb wfchsb VRR_VVV "scalar vector fp compare high scalar short" arch12 zarch vx2 ++e700001820eb wfchsbs VRR_VVV "scalar vector fp compare high scalar short" arch12 zarch vx2 ++e700000840eb wfchxb VRR_VVV "scalar vector fp compare high scalar extended" arch12 zarch vx2 ++e700001840eb wfchxbs VRR_VVV "scalar vector fp compare high scalar extended" arch12 zarch vx2 ++ ++e700000420eb vfkhsb VRR_VVV "vector fp compare and signal high short" arch12 zarch vx2 ++e700001420eb vfkhsbs VRR_VVV "vector fp compare and signal high short" arch12 zarch vx2 ++e700000c20eb wfkhsb VRR_VVV "scalar vector fp compare and signal high scalar short" arch12 zarch vx2 ++e700001c20eb wfkhsbs VRR_VVV "scalar vector fp compare and signal high scalar short" arch12 zarch vx2 ++e700000430eb vfkhdb VRR_VVV "vector fp compare and signal high long" arch12 zarch vx ++e700001430eb vfkhdbs VRR_VVV "vector fp compare and signal high long" arch12 zarch vx ++e700000c30eb wfkhdb VRR_VVV "vector fp compare and signal high long" arch12 zarch vx ++e700001c30eb wfkhdbs VRR_VVV "vector fp compare and signal high long" arch12 zarch vx ++e700000c40eb wfkhxb VRR_VVV "scalar vector fp compare and signal high scalar extended" arch12 zarch vx2 ++e700001c40eb wfkhxbs VRR_VVV "scalar vector fp compare and signal high scalar extended" arch12 zarch vx2 ++ ++e700000020ea vfchesb VRR_VVV "vector fp compare high or equal short" arch12 zarch vx2 ++e700001020ea vfchesbs VRR_VVV "vector fp compare high or equal short" arch12 zarch vx2 ++e700000820ea wfchesb VRR_VVV "scalar vector fp compare high or equal scalar short" arch12 zarch vx2 ++e700001820ea wfchesbs VRR_VVV "scalar vector fp compare high or equal scalar short" arch12 zarch vx2 ++e700000840ea wfchexb VRR_VVV "scalar vector fp compare high or equal scalar extended" arch12 zarch vx2 ++e700001840ea wfchexbs VRR_VVV "scalar vector fp compare high or equal scalar extended" arch12 zarch vx2 ++ ++e700000420ea vfkhesb VRR_VVV "vector fp compare and signal high or equal short" arch12 zarch vx2 ++e700001420ea vfkhesbs VRR_VVV "vector fp compare and signal high or equal short" arch12 zarch vx2 ++e700000c20ea wfkhesb VRR_VVV "scalar vector fp compare and signal high or equal scalar short" arch12 zarch vx2 ++e700001c20ea wfkhesbs VRR_VVV "scalar vector fp compare and signal high or equal scalar short" arch12 zarch vx2 ++e700000430ea vfkhedb VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx ++e700001430ea vfkhedbs VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx ++e700000c30ea wfkhedb VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx ++e700001c30ea wfkhedbs VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx ++e700000c40ea wfkhexb VRR_VVV "scalar vector fp compare and signal high or equal scalar extended" arch12 zarch vx2 ++e700001c40ea wfkhexbs VRR_VVV "scalar vector fp compare and signal high or equal scalar extended" arch12 zarch vx2 ++ ++e700000020e5 vfdsb VRR_VVV "vector fp divide short" arch12 zarch vx2 ++e700000820e5 wfdsb VRR_VVV "scalar vector fp divide scalar short" arch12 zarch vx2 ++e700000840e5 wfdxb VRR_VVV "scalar vector fp divide scalar extended" arch12 zarch vx2 ++e700000020c7 vfisb VRR_VV0UU "vector load fp integer short" arch12 zarch vx2 ++e700000820c7 wfisb VRR_VV0UU8 "scalar vector load fp integer scalar short" arch12 zarch vx2 ++e700000840c7 wfixb VRR_VV0UU8 "scalar vector load fp integer scalar extended" arch12 zarch vx2 ++e700000000c4 vfll VRR_VV0UU2 "vector fp load lengthened" arch12 zarch vx2 ++e700000020c4 vflls VRR_VV "vector fp load lengthened" arch12 zarch vx2 ++e700000820c4 wflls VRR_VV "scalar vector fp load lengthened short" arch12 zarch vx2 ++e700000830c4 wflld VRR_VV "scalar vector fp load lengthened long" arch12 zarch vx2 ++e700000000c5 vflr VRR_VV0UUU "vector fp load rounded" arch12 zarch vx2 ++e700000030c5 vflrd VRR_VV0UU "vector fp load rounded long" arch12 zarch vx2 ++e700000830c5 wflrd VRR_VV0UU8 "scalar vector fp load rounded long" arch12 zarch vx2 ++e700000840c5 wflrx VRR_VV0UU8 "scalar vector fp load rounded extended" arch12 zarch vx2 ++e700000000ef vfmax VRR_VVV0UUU "vector fp maximum" arch12 zarch vx2 ++e700000020ef vfmaxsb VRR_VVV0U0 "vector fp maximum short" arch12 zarch vx2 ++e700000030ef vfmaxdb VRR_VVV0U0 "vector fp maximum long" arch12 zarch vx2 ++e700000820ef wfmaxsb VRR_VVV0U0 "scalar fp maximum scalar short" arch12 zarch vx2 ++e700000830ef wfmaxdb VRR_VVV0U0 "scalar fp maximum scalar long" arch12 zarch vx2 ++e700000840ef wfmaxxb VRR_VVV0U0 "scalar fp maximum scalar extended" arch12 zarch vx2 ++e700000000ee vfmin VRR_VVV0UUU "vector fp minimum" arch12 zarch vx2 ++e700000020ee vfminsb VRR_VVV0U0 "vector fp minimum short" arch12 zarch vx2 ++e700000030ee vfmindb VRR_VVV0U0 "vector fp minimum long" arch12 zarch vx2 ++e700000820ee wfminsb VRR_VVV0U0 "scalar fp minimum scalar short" arch12 zarch vx2 ++e700000830ee wfmindb VRR_VVV0U0 "scalar fp minimum scalar long" arch12 zarch vx2 ++e700000840ee wfminxb VRR_VVV0U0 "scalar fp minimum scalar extended" arch12 zarch vx2 ++e700000020e7 vfmsb VRR_VVV "vector fp multiply short" arch12 zarch vx2 ++e700000820e7 wfmsb VRR_VVV "scalar vector fp multiply scalar short" arch12 zarch vx2 ++e700000840e7 wfmxb VRR_VVV "scalar vector fp multiply scalar extended" arch12 zarch vx2 ++e7000200008f vfmasb VRR_VVVV "vector fp multiply and add short" arch12 zarch vx2 ++e7000208008f wfmasb VRR_VVVV "scalar vector fp multiply and add scalar short" arch12 zarch vx2 ++e7000408008f wfmaxb VRR_VVVV "scalar vector fp multiply and add scalar extended" arch12 zarch vx2 ++e7000200008e vfmssb VRR_VVVV "vector fp multiply and subtract short" arch12 zarch vx2 ++e7000208008e wfmssb VRR_VVVV "scalar vector fp multiply and subtract scalar short" arch12 zarch vx2 ++e7000408008e wfmsxb VRR_VVVV "scalar vector fp multiply and subtract scalar extended" arch12 zarch vx2 ++e7000000009f vfnma VRR_VVVU0UV "vector fp negative multiply and add" arch12 zarch vx2 ++e7000200009f vfnmasb VRR_VVVV "vector fp negative multiply and add short" arch12 zarch vx2 ++e7000208009f wfnmasb VRR_VVVV "scalar vector fp negative multiply and add scalar short" arch12 zarch vx2 ++e7000300009f vfnmadb VRR_VVVV "vector fp negative multiply and add long" arch12 zarch vx2 ++e7000308009f wfnmadb VRR_VVVV "scalar vector fp negative multiply and add scalar long" arch12 zarch vx2 ++e7000408009f wfnmaxb VRR_VVVV "scalar vector fp negative multiply and add scalar extended" arch12 zarch vx2 ++e7000000009e vfnms VRR_VVVU0UV "vector fp negative multiply and subtract" arch12 zarch vx2 ++e7000200009e vfnmssb VRR_VVVV "vector fp negative multiply and subtract short" arch12 zarch vx2 ++e7000208009e wfnmssb VRR_VVVV "scalar vector fp negative multiply and subtract scalar short" arch12 zarch vx2 ++e7000300009e vfnmsdb VRR_VVVV "vector fp negative multiply and subtract long" arch12 zarch vx2 ++e7000308009e wfnmsdb VRR_VVVV "scalar vector fp negative multiply and subtract scalar long" arch12 zarch vx2 ++e7000408009e wfnmsxb VRR_VVVV "scalar vector fp negative multiply and subtract scalar extended" arch12 zarch vx2 ++e700000020cc vfpsosb VRR_VV0U2 "vector fp perform sign operation short" arch12 zarch vx2 ++e700000820cc wfpsosb VRR_VV0U2 "scalar vector fp perform sign operation scalar short" arch12 zarch vx2 ++e700000020cc vflcsb VRR_VV "vector fp perform sign operation short" arch12 zarch vx2 ++e700000820cc wflcsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch vx2 ++e700001020cc vflnsb VRR_VV "vector fp perform sign operation short" arch12 zarch vx2 ++e700001820cc wflnsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch vx2 ++e700002020cc vflpsb VRR_VV "vector fp perform sign operation short" arch12 zarch vx2 ++e700002820cc wflpsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch vx2 ++e700000840cc wfpsoxb VRR_VV0U2 "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2 ++e700000840cc wflcxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2 ++e700001840cc wflnxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2 ++e700002840cc wflpxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2 ++e700000020ce vfsqsb VRR_VV "vector fp square root short" arch12 zarch vx2 ++e700000820ce wfsqsb VRR_VV "scalar vector fp square root scalar short" arch12 zarch vx2 ++e700000840ce wfsqxb VRR_VV "scalar vector fp square root scalar extended" arch12 zarch vx2 ++e700000020e2 vfssb VRR_VVV "vector fp subtract short" arch12 zarch vx2 ++e700000820e2 wfssb VRR_VVV "scalar vector fp subtract scalar short" arch12 zarch vx2 ++e700000840e2 wfsxb VRR_VVV "scalar vector fp subtract scalar extended" arch12 zarch vx2 ++e7000000204a vftcisb VRI_VVU2 "vector fp test data class immediate short" arch12 zarch vx2 ++e7000008204a wftcisb VRI_VVU2 "scalar vector fp test data class immediate scalar short" arch12 zarch vx2 ++e7000008404a wftcixb VRI_VVU2 "scalar vector fp test data class immediate scalar extended" arch12 zarch vx2 ++ ++# Miscellaneous Instruction Extensions Facility 2 ++ ++e30000000038 agh RXY_RRRD "add halfword to 64 bit value" arch12 zarch ++e30000000047 bic RXY_URRD "branch indirect on condition" arch12 zarch ++e3f000000047 bi RXY_0RRD "unconditional indirect branch" arch12 zarch ++e30000000047 bi*8 RXY_0RRD "branch indirect on condition" arch12 zarch ++b9ec mgrk RRF_R0RR2 "multiply 64x64reg -> 128" arch12 zarch ++e30000000084 mg RXY_RRRD "multiply 64x64mem -> 128" arch12 zarch ++e3000000003c mgh RXY_RRRD "multiply halfword 64x16mem -> 64" arch12 zarch ++b9fd msrkc RRF_R0RR2 "multiply single 32x32 -> 32" arch12 zarch ++b9ed msgrkc RRF_R0RR2 "multiply single 64x64 -> 64" arch12 zarch ++e30000000053 msc RXY_RRRD "multiply single 32x32mem -> 32" arch12 zarch ++e30000000083 msgc RXY_RRRD "multiply single 64x64mem -> 64" arch12 zarch ++e30000000039 sgh RXY_RRRD "subtract halfword from 64 bit value" arch12 zarch ++ ++# Vector packed decimal facility ++ ++e60000000037 vlrlr VRS_RRDV "vector load rightmost with length" arch12 zarch vx2 ++e60000000035 vlrl VSI_URDV "vector load rightmost with immediate length" arch12 zarch vx2 ++e6000000003f vstrlr VRS_RRDV "vector store rightmost with length" arch12 zarch vx2 ++e6000000003d vstrl VSI_URDV "vector store rightmost with immediate length" arch12 zarch vx2 ++e60000000071 vap VRI_VVV0UU2 "vector add decimal" arch12 zarch vx2 ++e60000000077 vcp VRR_0VV0U "vector compare decimal" arch12 zarch vx2 ++e60000000050 vcvb VRR_RV0U "vector convert to binary 32 bit" arch12 zarch vx2 ++e60000000052 vcvbg VRR_RV0U "vector convert to binary 64 bit" arch12 zarch vx2 ++e60000000058 vcvd VRI_VR0UU "vector convert to decimal 32 bit" arch12 zarch vx2 ++e6000000005a vcvdg VRI_VR0UU "vector convert to decimal 64 bit" arch12 zarch vx2 ++e6000000007a vdp VRI_VVV0UU2 "vector divide decimal" arch12 zarch vx2 ++e60000000049 vlip VRI_V0UU2 "vector load immediate decimal" arch12 zarch vx2 ++e60000000078 vmp VRI_VVV0UU2 "vector multiply decimal" arch12 zarch vx2 ++e60000000079 vmsp VRI_VVV0UU2 "vector multiply and shift decimal" arch12 zarch vx2 ++e60000000034 vpkz VSI_URDV "vector pack zoned" arch12 zarch vx2 ++e6000000005b vpsop VRI_VVUUU2 "vector perform sign operation decimal" arch12 zarch vx2 ++e6000000007b vrp VRI_VVV0UU2 "vector remainder decimal" arch12 zarch vx2 ++e6000000007e vsdp VRI_VVV0UU2 "vector shift and divide decimal" arch12 zarch vx2 ++e60000000059 vsrp VRI_VVUUU2 "vector shift and round decimal" arch12 zarch vx2 ++e60000000073 vsp VRI_VVV0UU2 "vector subtract decimal" arch12 zarch vx2 ++e6000000005f vtp VRR_0V "vector test decimal" arch12 zarch vx2 ++e6000000003c vupkz VSI_URDV "vector unpack zoned" arch12 zarch vx2 ++ ++# Guarded storage facility ++ ++e3000000004c lgg RXY_RRRD "load guarded 64 bit" arch12 zarch ++e30000000048 llgfsg RXY_RRRD "load logical and shift guarded 64 bit" arch12 zarch ++e3000000004d lgsc RXY_RRRD "load guarded storage controls" arch12 zarch ++e30000000049 stgsc RXY_RRRD "store guarded storage controls" arch12 zarch ++ ++# Message-Security-Assist Extension 8 ++ ++b929 kma RRF_R0RR "cipher message with galois counter mode" arch12 zarch + diff --git a/SOURCES/binutils-2.27-s390x-check-for-NULL-pointers.patch b/SOURCES/binutils-2.27-s390x-check-for-NULL-pointers.patch new file mode 100644 index 0000000..bcc7d22 --- /dev/null +++ b/SOURCES/binutils-2.27-s390x-check-for-NULL-pointers.patch @@ -0,0 +1,43 @@ +--- binutils.orig/bfd/elf64-s390.c 2017-09-06 09:03:23.142216202 +0100 ++++ binutils-2.27/bfd/elf64-s390.c 2017-09-06 09:11:05.209080947 +0100 +@@ -3895,8 +3895,13 @@ elf_s390_additional_program_headers (bfd + { + struct elf_s390_link_hash_table *htab; + +- htab = elf_s390_hash_table (info); +- return htab->params->pgste; ++ if (info) ++ { ++ htab = elf_s390_hash_table (info); ++ if (htab) ++ return htab->params->pgste; ++ } ++ return 0; + } + + +@@ -3909,6 +3914,9 @@ elf_s390_modify_segment_map (bfd *abfd A + struct elf_s390_link_hash_table *htab; + struct elf_segment_map *m, *pm = NULL; + ++ if (!abfd || !info) ++ return TRUE; ++ + htab = elf_s390_hash_table (info); + if (!htab->params->pgste) + return TRUE; +@@ -3944,8 +3952,12 @@ bfd_elf_s390_set_options (struct bfd_lin + { + struct elf_s390_link_hash_table *htab; + +- htab = elf_s390_hash_table (info); +- htab->params = params; ++ if (info) ++ { ++ htab = elf_s390_hash_table (info); ++ if (htab) ++ htab->params = params; ++ } + + return TRUE; + } diff --git a/SOURCES/binutils-2.27-s390x-complain-missing-fPIC.patch b/SOURCES/binutils-2.27-s390x-complain-missing-fPIC.patch new file mode 100644 index 0000000..373391b --- /dev/null +++ b/SOURCES/binutils-2.27-s390x-complain-missing-fPIC.patch @@ -0,0 +1,22 @@ +--- binutils.orig/bfd/elf64-s390.c 2017-08-11 11:09:23.264667227 +0000 ++++ binutils-2.27/bfd/elf64-s390.c 2017-08-11 11:15:07.510029088 +0000 +@@ -2745,6 +2745,19 @@ elf_s390_relocate_section (bfd *output_b + case R_390_PC32: + case R_390_PC32DBL: + case R_390_PC64: ++ if (h != NULL ++ && bfd_link_pie (info) ++ && !h->def_regular) ++ { ++ _bfd_error_handler (_("%B: `%s' non-PLT reloc for symbol defined " ++ "in shared library and accessed " ++ "from executable " ++ "(rebuild file with -fPIC ?)"), ++ input_bfd, h->root.root.string); ++ bfd_set_error (bfd_error_bad_value); ++ return FALSE; ++ } ++ + /* The target of these relocs are instruction operands + residing in read-only sections. We cannot emit a runtime + reloc for it. */ diff --git a/SOURCES/binutils-2.27-suppress-R_X86_64_GOTPCRELX.patch b/SOURCES/binutils-2.27-suppress-R_X86_64_GOTPCRELX.patch new file mode 100644 index 0000000..434c4ac --- /dev/null +++ b/SOURCES/binutils-2.27-suppress-R_X86_64_GOTPCRELX.patch @@ -0,0 +1,1515 @@ +--- binutils.orig/gas/config/tc-i386.c 2017-10-25 12:52:19.977290474 +0100 ++++ binutils-2.27/gas/config/tc-i386.c 2017-10-25 15:09:15.572415126 +0100 +@@ -10655,14 +10655,7 @@ i386_validate_fix (fixS *fixp) + { + if (!object_64bit) + abort (); +-#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) +- if (fixp->fx_tcbit2) +- fixp->fx_r_type = (fixp->fx_tcbit +- ? BFD_RELOC_X86_64_REX_GOTPCRELX +- : BFD_RELOC_X86_64_GOTPCRELX); +- else +-#endif +- fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; ++ fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; + } + else + { +@@ -10674,14 +10667,6 @@ i386_validate_fix (fixS *fixp) + fixp->fx_subsy = 0; + } + } +-#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) +- else if (!object_64bit) +- { +- if (fixp->fx_r_type == BFD_RELOC_386_GOT32 +- && fixp->fx_tcbit2) +- fixp->fx_r_type = BFD_RELOC_386_GOT32X; +- } +-#endif + } + + arelent * +diff -rup binutils.orig/gas/testsuite/gas/i386/got.d binutils-2.27/gas/testsuite/gas/i386/got.d +--- binutils.orig/gas/testsuite/gas/i386/got.d 2017-10-25 12:52:20.045289685 +0100 ++++ binutils-2.27/gas/testsuite/gas/i386/got.d 2017-10-25 15:19:02.458621604 +0100 +@@ -8,23 +8,23 @@ Disassembly of section .text: + + 0+ <_start>: + [ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 1: R_386_GOT32 foo +-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32X foo +-[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax d: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax d: R_386_GOT32 foo + [ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 12: R_386_GOT32 foo +-[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32X foo +-[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 1e: R_386_GOT32X foo +-[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32X foo +-[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 2a: R_386_GOT32X foo +-[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32X foo +-[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 36: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 1e: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 2a: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 36: R_386_GOT32 foo + [ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 3b: R_386_GOT32 foo +-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32X foo +-[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax 47: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax 47: R_386_GOT32 foo + [ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 4c: R_386_GOT32 foo +-[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32X foo +-[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 58: R_386_GOT32X foo +-[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 5e: R_386_GOT32X foo +-[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32X foo +-[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 6a: R_386_GOT32X foo +-[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32 foo ++[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 58: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 5e: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 6a: R_386_GOT32 foo ++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32 foo + #pass +diff -rup binutils.orig/gas/testsuite/gas/i386/got-no-relax.d binutils-2.27/gas/testsuite/gas/i386/got-no-relax.d +--- binutils.orig/gas/testsuite/gas/i386/got-no-relax.d 2017-10-25 12:52:20.045289685 +0100 ++++ binutils-2.27/gas/testsuite/gas/i386/got-no-relax.d 2017-10-25 15:18:30.398991961 +0100 +@@ -9,23 +9,23 @@ Disassembly of section .text: + + 0+ <_start>: + [ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 1: R_386_GOT32 foo +-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32 foo + [ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax d: R_386_GOT32 foo + [ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 12: R_386_GOT32 foo +-[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32 foo + [ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 1e: R_386_GOT32 foo +-[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32X foo ++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32 foo + [ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 2a: R_386_GOT32 foo +-[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32X foo ++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32 foo + [ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 36: R_386_GOT32 foo + [ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 3b: R_386_GOT32 foo +-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32 foo + [ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax 47: R_386_GOT32 foo + [ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 4c: R_386_GOT32 foo +-[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32X foo ++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32 foo + [ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 58: R_386_GOT32 foo + [ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 5e: R_386_GOT32 foo +-[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32X foo ++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32 foo + [ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 6a: R_386_GOT32 foo +-[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32X foo ++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32 foo + #pass +diff -rup binutils.orig/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d binutils-2.27/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d +--- binutils.orig/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d 2017-10-25 12:52:20.047289662 +0100 ++++ binutils-2.27/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d 2017-10-25 15:12:35.549099037 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #objdump: -dwr + #name: x86-64 (ILP32) gotpcrel ++#skip: *-*-* ++# SKIPed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d binutils-2.27/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d +--- binutils.orig/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d 2017-10-25 12:52:20.047289662 +0100 ++++ binutils-2.27/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d 2017-10-25 15:12:35.549099037 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #readelf: -rsW + #name: x86-64 (ILP32) local PIC ++#skip: *-*-* ++# SKIPed because generation of the R_X86_64_REX_GOTPCRELX reloc is currently suppressed. + + Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 1 entries: + +Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend +diff -rup binutils.orig/gas/testsuite/gas/i386/localpic.d binutils-2.27/gas/testsuite/gas/i386/localpic.d +--- binutils.orig/gas/testsuite/gas/i386/localpic.d 2017-10-25 12:52:20.049289639 +0100 ++++ binutils-2.27/gas/testsuite/gas/i386/localpic.d 2017-10-25 15:18:13.799183724 +0100 +@@ -4,7 +4,7 @@ + + Relocation section '.rel.text' at offset 0x[0-9a-f]+ contains 1 entries: + Offset Info Type Sym.Value Sym. Name +-[0-9a-f]+ +[0-9a-f]+ R_386_GOT32X +[0-9a-f]+ +foo ++[0-9a-f]+ +[0-9a-f]+ R_386_GOT32 +[0-9a-f]+ +foo + #... + +[0-9]+: +[0-9a-f]+ +[0-9a-f]+ +NOTYPE +LOCAL +DEFAULT +[0-9]+ +foo + #pass +diff -rup binutils.orig/gas/testsuite/gas/i386/mixed-mode-reloc32.d binutils-2.27/gas/testsuite/gas/i386/mixed-mode-reloc32.d +--- binutils.orig/gas/testsuite/gas/i386/mixed-mode-reloc32.d 2017-10-25 12:52:20.050289627 +0100 ++++ binutils-2.27/gas/testsuite/gas/i386/mixed-mode-reloc32.d 2017-10-25 15:18:02.186317878 +0100 +@@ -7,9 +7,9 @@ + + RELOCATION RECORDS FOR \[.text\]: + OFFSET[ ]+TYPE[ ]+VALUE[ ]* +-[0-9a-f]+[ ]+R_386_GOT32X[ ]+xtrn[ ]* ++[0-9a-f]+[ ]+R_386_GOT32[ ]+xtrn[ ]* + [0-9a-f]+[ ]+R_386_PLT32[ ]+xtrn[ ]* +-[0-9a-f]+[ ]+R_386_GOT32X[ ]+xtrn[ ]* ++[0-9a-f]+[ ]+R_386_GOT32[ ]+xtrn[ ]* + [0-9a-f]+[ ]+R_386_PLT32[ ]+xtrn[ ]* +-[0-9a-f]+[ ]+R_386_GOT32X[ ]+xtrn[ ]* ++[0-9a-f]+[ ]+R_386_GOT32[ ]+xtrn[ ]* + [0-9a-f]+[ ]+R_386_PLT32[ ]+xtrn[ ]* +diff -rup binutils.orig/gas/testsuite/gas/i386/reloc32.d binutils-2.27/gas/testsuite/gas/i386/reloc32.d +--- binutils.orig/gas/testsuite/gas/i386/reloc32.d 2017-10-25 12:52:20.052289604 +0100 ++++ binutils-2.27/gas/testsuite/gas/i386/reloc32.d 2017-10-25 15:16:06.161659763 +0100 +@@ -19,7 +19,7 @@ Disassembly of section \.text: + .*[ ]+R_386_PC32[ ]+xtrn + .*[ ]+R_386_PC8[ ]+xtrn + .*[ ]+R_386_GOT32[ ]+xtrn +-.*[ ]+R_386_GOT32X[ ]+xtrn ++.*[ ]+R_386_GOT32[ ]+xtrn + .*[ ]+R_386_GOTOFF[ ]+xtrn + .*[ ]+R_386_GOTOFF[ ]+xtrn + .*[ ]+R_386_GOTPC[ ]+_GLOBAL_OFFSET_TABLE_ +diff -rup binutils.orig/gas/testsuite/gas/i386/x86-64-gotpcrel.d binutils-2.27/gas/testsuite/gas/i386/x86-64-gotpcrel.d +--- binutils.orig/gas/testsuite/gas/i386/x86-64-gotpcrel.d 2017-10-25 12:52:20.063289476 +0100 ++++ binutils-2.27/gas/testsuite/gas/i386/x86-64-gotpcrel.d 2017-10-25 15:12:35.549099037 +0100 +@@ -1,5 +1,7 @@ + #as: -mrelax-relocations=yes + #objdump: -dwr ++#skip: *-*-* ++# SKIPed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/gas/testsuite/gas/i386/x86-64-localpic.d binutils-2.27/gas/testsuite/gas/i386/x86-64-localpic.d +--- binutils.orig/gas/testsuite/gas/i386/x86-64-localpic.d 2017-10-25 12:52:20.064289465 +0100 ++++ binutils-2.27/gas/testsuite/gas/i386/x86-64-localpic.d 2017-10-25 15:12:35.549099037 +0100 +@@ -1,6 +1,8 @@ + #as: -mrelax-relocations=yes + #readelf: -rsW + #name: x86-64 local PIC ++#skip: *-*-* ++# SKIPed because generation of the R_X86_64_REX_GOTPCRELX reloc is currently suppressed. + + Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 1 entries: + +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend +diff -rup binutils.orig/ld/testsuite/ld-cdtest/cdtest-foo.cc binutils-2.27/ld/testsuite/ld-cdtest/cdtest-foo.cc +--- binutils.orig/ld/testsuite/ld-cdtest/cdtest-foo.cc 2017-10-25 12:52:20.549283841 +0100 ++++ binutils-2.27/ld/testsuite/ld-cdtest/cdtest-foo.cc 2017-10-25 15:12:35.549099037 +0100 +@@ -8,7 +8,7 @@ + #if (__GNUG__ == 2) + typedef __SIZE_TYPE__ size_t; + #else +-typedef unsigned int size_t; ++typedef unsigned long size_t; + #endif + + extern "C" { +diff -rup binutils.orig/ld/testsuite/ld-elf/shared.exp binutils-2.27/ld/testsuite/ld-elf/shared.exp +--- binutils.orig/ld/testsuite/ld-elf/shared.exp 2017-10-25 12:52:20.578283504 +0100 ++++ binutils-2.27/ld/testsuite/ld-elf/shared.exp 2017-10-25 15:45:58.374968233 +0100 +@@ -483,10 +483,10 @@ set build_cxx_tests { + "-shared -Wl,--dynamic-list-cpp-typeinfo" "-fPIC" + {dl3.cc} {} "libdl3c.so" "c++"} + {"Build libdnew1a.so with --Bsymbolic-functions --dynamic-list-cpp-new" +- "-shared -Wl,-Bsymbolic-functions,--dynamic-list-cpp-new" "-fPIC" ++ "-shared -Wl,-Bsymbolic-functions,--dynamic-list-cpp-new" "-fPIC -ansi" + {del.cc new.cc} {} "libnew1a.so" "c++"} + {"Build libdnew1b.so with --dynamic-list-data --dynamic-list-cpp-new" +- "-shared -Wl,--dynamic-list-data,--dynamic-list-cpp-new" "-fPIC" ++ "-shared -Wl,--dynamic-list-data,--dynamic-list-cpp-new" "-fPIC -ansi" + {del.cc new.cc} {} "libnew1b.so" "c++"} + } + +@@ -503,10 +503,10 @@ set run_cxx_tests { + {dl3main.cc} "dl3c" "dl3a.out" "" "c++"} + {"Run with libnew1a.so" + "tmpdir/libnew1a.so" "" +- {dl5.cc} "dl5a" "dl5.out" "" "c++"} ++ {dl5.cc} "dl5a" "dl5.out" "-ansi" "c++"} + {"Run with libnew1b.so" + "tmpdir/libnew1b.so" "" +- {dl5.cc} "dl5b" "dl5.out" "" "c++"} ++ {dl5.cc} "dl5b" "dl5.out" "-ansi" "c++"} + } + + run_cc_link_tests $build_cxx_tests +diff -rup binutils.orig/ld/testsuite/ld-i386/branch1.d binutils-2.27/ld/testsuite/ld-i386/branch1.d +--- binutils.orig/ld/testsuite/ld-i386/branch1.d 2017-10-25 12:52:20.657282588 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/branch1.d 2017-10-25 15:26:26.015497567 +0100 +@@ -1,6 +1,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/call1.d binutils-2.27/ld/testsuite/ld-i386/call1.d +--- binutils.orig/ld/testsuite/ld-i386/call1.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call1.d 2017-10-25 15:26:33.407412174 +0100 +@@ -1,3 +1,5 @@ + #as: --32 -mrelax-relocations=yes + #ld: -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-i386/call2.d binutils-2.27/ld/testsuite/ld-i386/call2.d +--- binutils.orig/ld/testsuite/ld-i386/call2.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call2.d 2017-10-25 15:26:43.024301080 +0100 +@@ -1,3 +1,5 @@ + #as: --32 -mrelax-relocations=yes + #ld: -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-i386/call3a.d binutils-2.27/ld/testsuite/ld-i386/call3a.d +--- binutils.orig/ld/testsuite/ld-i386/call3a.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call3a.d 2017-10-25 15:29:17.042521838 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/call3b.d binutils-2.27/ld/testsuite/ld-i386/call3b.d +--- binutils.orig/ld/testsuite/ld-i386/call3b.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call3b.d 2017-10-25 15:29:21.756467382 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=prefix-addr + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/call3c.d binutils-2.27/ld/testsuite/ld-i386/call3c.d +--- binutils.orig/ld/testsuite/ld-i386/call3c.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call3c.d 2017-10-25 15:29:26.457413076 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=prefix-nop + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/call3d.d binutils-2.27/ld/testsuite/ld-i386/call3d.d +--- binutils.orig/ld/testsuite/ld-i386/call3d.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call3d.d 2017-10-25 15:29:30.925361461 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=suffix-nop + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/call3e.d binutils-2.27/ld/testsuite/ld-i386/call3e.d +--- binutils.orig/ld/testsuite/ld-i386/call3e.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call3e.d 2017-10-25 15:29:38.894269403 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=prefix-0x67 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/call3f.d binutils-2.27/ld/testsuite/ld-i386/call3f.d +--- binutils.orig/ld/testsuite/ld-i386/call3f.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call3f.d 2017-10-25 15:29:47.134174215 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=prefix-0x90 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/call3g.d binutils-2.27/ld/testsuite/ld-i386/call3g.d +--- binutils.orig/ld/testsuite/ld-i386/call3g.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call3g.d 2017-10-25 15:29:52.341114063 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=suffix-0x90 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/call3h.d binutils-2.27/ld/testsuite/ld-i386/call3h.d +--- binutils.orig/ld/testsuite/ld-i386/call3h.d 2017-10-25 12:52:20.658282576 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/call3h.d 2017-10-25 15:29:57.237057504 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -z call-nop=suffix-144 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/i386.exp binutils-2.27/ld/testsuite/ld-i386/i386.exp +--- binutils.orig/ld/testsuite/ld-i386/i386.exp 2017-10-25 12:52:20.661282542 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/i386.exp 2017-10-25 15:42:06.083647050 +0100 +@@ -133,13 +133,6 @@ set i386tests { + {{readelf -Ssrl tlspic.rd} {objdump -drj.text tlspic.dd} + {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}} + "libtlspic.so"} +- {"TLS -fpic -shared transitions without PLT" +- "-shared -melf_i386 --no-ld-generated-unwind-info" "" +- "-mrelax-relocations=yes --32" +- {tlspic3.s tlspic2.s} +- {{readelf -Ssrl tlspic2.rd} {objdump -drj.text tlspic2.dd} +- {objdump -sj.got tlspic2.sd} {objdump -sj.tdata tlspic2.td}} +- "libtlspic2.so"} + {"TLS descriptor -fpic -shared transitions" + "-shared -melf_i386 --no-ld-generated-unwind-info" "" + "--32" {tlsdesc.s tlspic2.s} +@@ -154,13 +147,6 @@ set i386tests { + {{readelf -Ssrl tlsbin.rd} {objdump -drj.text tlsbin.dd} + {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}} + "tlsbin"} +- {"TLS -fpic and -fno-pic exec transitions without PLT" +- "-melf_i386 tmpdir/libtlslib.so --no-ld-generated-unwind-info" "" +- "-mrelax-relocations=yes --32" +- {tlsbinpic2.s tlsbin.s} +- {{readelf -Ssrl tlsbin2.rd} {objdump -drj.text tlsbin2.dd} +- {objdump -sj.got tlsbin2.sd} {objdump -sj.tdata tlsbin2.td}} +- "tlsbin2"} + {"TLS descriptor -fpic and -fno-pic exec transitions" + "-melf_i386 tmpdir/libtlslib.so --no-ld-generated-unwind-info" "" + "--32" {tlsbindesc.s tlsbin.s} +@@ -191,17 +177,9 @@ set i386tests { + {"TLS GD->LE transition" "-melf_i386" "" + "--32" {tlsgd1.s} + {{objdump -dwr tlsgd1.dd}} "tlsgd1"} +- {"TLS GD->LE transition without PLT" "-melf_i386" "" +- "-mrelax-relocations=yes --32" +- {tlsgd3.s} +- {{objdump -dwr tlsgd3.dd}} "tlsgd3"} + {"TLS LD->LE transition" "-melf_i386" "" + "--32" {tlsld1.s} + {{objdump -dwr tlsld1.dd}} "tlsld1"} +- {"TLS LD->LE transition without PLT" "-melf_i386" "" +- "-mrelax-relocations=yes --32" +- {tlsld2.s} +- {{objdump -dwr tlsld2.dd}} "tlsld2"} + {"TLS IE->LE transition" "-melf_i386" "" + "--32" {tlsie1.s} + {{objdump -dwr tlsie1.dd}} "tlsie1"} +diff -rup binutils.orig/ld/testsuite/ld-i386/jmp1.d binutils-2.27/ld/testsuite/ld-i386/jmp1.d +--- binutils.orig/ld/testsuite/ld-i386/jmp1.d 2017-10-25 12:52:20.661282542 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/jmp1.d 2017-10-25 15:30:06.805946963 +0100 +@@ -1,3 +1,5 @@ + #as: --32 -mrelax-relocations=yes + #ld: -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-i386/jmp2.d binutils-2.27/ld/testsuite/ld-i386/jmp2.d +--- binutils.orig/ld/testsuite/ld-i386/jmp2.d 2017-10-25 12:52:20.662282530 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/jmp2.d 2017-10-25 15:30:14.181861755 +0100 +@@ -1,3 +1,5 @@ + #as: --32 -mrelax-relocations=yes + #ld: -shared -melf_i386 + #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-i386/lea1a.d binutils-2.27/ld/testsuite/ld-i386/lea1a.d +--- binutils.orig/ld/testsuite/ld-i386/lea1a.d 2017-10-25 12:52:20.662282530 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/lea1a.d 2017-10-25 15:25:33.592103171 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -Bsymbolic -shared -melf_i386 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/lea1b.d binutils-2.27/ld/testsuite/ld-i386/lea1b.d +--- binutils.orig/ld/testsuite/ld-i386/lea1b.d 2017-10-25 12:52:20.662282530 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/lea1b.d 2017-10-25 15:25:39.289037359 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -pie -melf_i386 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/lea1c.d binutils-2.27/ld/testsuite/ld-i386/lea1c.d +--- binutils.orig/ld/testsuite/ld-i386/lea1c.d 2017-10-25 12:52:20.662282530 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/lea1c.d 2017-10-25 15:25:46.777950846 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/lea1d.d binutils-2.27/ld/testsuite/ld-i386/lea1d.d +--- binutils.orig/ld/testsuite/ld-i386/lea1d.d 2017-10-25 12:52:20.662282530 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/lea1d.d 2017-10-25 15:25:55.802846589 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -Bsymbolic -shared -melf_i386 + #readelf: -Sw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + #failif + #... +diff -rup binutils.orig/ld/testsuite/ld-i386/lea1e.d binutils-2.27/ld/testsuite/ld-i386/lea1e.d +--- binutils.orig/ld/testsuite/ld-i386/lea1e.d 2017-10-25 12:52:20.662282530 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/lea1e.d 2017-10-25 15:26:03.115762109 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -pie -melf_i386 + #readelf: -Sw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + #failif + #... +diff -rup binutils.orig/ld/testsuite/ld-i386/lea1f.d binutils-2.27/ld/testsuite/ld-i386/lea1f.d +--- binutils.orig/ld/testsuite/ld-i386/lea1f.d 2017-10-25 12:52:20.662282530 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/lea1f.d 2017-10-25 15:26:09.485688523 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #readelf: -Sw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + #failif + #... +diff -rup binutils.orig/ld/testsuite/ld-i386/load1.d binutils-2.27/ld/testsuite/ld-i386/load1.d +--- binutils.orig/ld/testsuite/ld-i386/load1.d 2017-10-25 12:52:20.662282530 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/load1.d 2017-10-25 15:30:23.543753605 +0100 +@@ -2,6 +2,8 @@ + #ld: -melf_i386 + #objdump: -dw --sym + #notarget: i?86-*-nacl* x86_64-*-nacl* ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/load2.d binutils-2.27/ld/testsuite/ld-i386/load2.d +--- binutils.orig/ld/testsuite/ld-i386/load2.d 2017-10-25 12:52:20.662282530 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/load2.d 2017-10-25 15:31:10.090215894 +0100 +@@ -1,3 +1,3 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -shared +-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object ++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object +diff -rup binutils.orig/ld/testsuite/ld-i386/load3.d binutils-2.27/ld/testsuite/ld-i386/load3.d +--- binutils.orig/ld/testsuite/ld-i386/load3.d 2017-10-25 12:52:20.663282518 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/load3.d 2017-10-25 15:31:24.220052664 +0100 +@@ -1,3 +1,3 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -shared +-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object ++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object +diff -rup binutils.orig/ld/testsuite/ld-i386/load4a.d binutils-2.27/ld/testsuite/ld-i386/load4a.d +--- binutils.orig/ld/testsuite/ld-i386/load4a.d 2017-10-25 12:52:20.663282518 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/load4a.d 2017-10-25 15:31:33.802941960 +0100 +@@ -1,4 +1,4 @@ + #source: load4.s + #as: --32 -mrelax-relocations=yes + #ld: -Bsymbolic -shared -melf_i386 +-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object ++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object +diff -rup binutils.orig/ld/testsuite/ld-i386/load4b.d binutils-2.27/ld/testsuite/ld-i386/load4b.d +--- binutils.orig/ld/testsuite/ld-i386/load4b.d 2017-10-25 12:52:20.663282518 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/load4b.d 2017-10-25 15:31:50.701746743 +0100 +@@ -2,6 +2,8 @@ + #as: --32 + #ld: -melf_i386 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/load5a.d binutils-2.27/ld/testsuite/ld-i386/load5a.d +--- binutils.orig/ld/testsuite/ld-i386/load5a.d 2017-10-25 12:52:20.663282518 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/load5a.d 2017-10-25 15:31:59.182648770 +0100 +@@ -1,4 +1,4 @@ + #source: load5.s + #as: --32 -mrelax-relocations=yes + #ld: -Bsymbolic -shared -melf_i386 +-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object ++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object +diff -rup binutils.orig/ld/testsuite/ld-i386/load5b.d binutils-2.27/ld/testsuite/ld-i386/load5b.d +--- binutils.orig/ld/testsuite/ld-i386/load5b.d 2017-10-25 12:52:20.663282518 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/load5b.d 2017-10-25 15:32:05.614574468 +0100 +@@ -2,6 +2,8 @@ + #as: --32 + #ld: -melf_i386 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/load7.d binutils-2.27/ld/testsuite/ld-i386/load7.d +--- binutils.orig/ld/testsuite/ld-i386/load7.d 2017-10-25 12:52:20.663282518 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/load7.d 2017-10-25 15:32:15.231463372 +0100 +@@ -1,6 +1,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -shared -melf_i386 --version-script load7.map + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/mov1b.d binutils-2.27/ld/testsuite/ld-i386/mov1b.d +--- binutils.orig/ld/testsuite/ld-i386/mov1b.d 2017-10-25 12:52:20.664282507 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/mov1b.d 2017-10-25 15:26:17.582594986 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -pie -melf_i386 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/pr19175.d binutils-2.27/ld/testsuite/ld-i386/pr19175.d +--- binutils.orig/ld/testsuite/ld-i386/pr19175.d 2017-10-25 12:52:20.671282426 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr19175.d 2017-10-25 15:34:05.638187937 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -Bsymbolic -shared -melf_i386 -T pr19175.t + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1a.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1a.d +--- binutils.orig/ld/testsuite/ld-i386/pr19609-1a.d 2017-10-25 12:52:20.672282414 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1a.d 2017-10-25 15:34:17.143055031 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1b.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1b.d +--- binutils.orig/ld/testsuite/ld-i386/pr19609-1b.d 2017-10-25 12:52:20.672282414 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1b.d 2017-10-25 15:34:25.735955848 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -pie -melf_i386 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1d.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1d.d +--- binutils.orig/ld/testsuite/ld-i386/pr19609-1d.d 2017-10-25 12:52:20.673282403 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1d.d 2017-10-25 15:35:05.258500067 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -E -melf_i386 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1f.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1f.d +--- binutils.orig/ld/testsuite/ld-i386/pr19609-1f.d 2017-10-25 12:52:20.673282403 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1f.d 2017-10-25 15:35:18.620345975 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -pie --dynamic-list-data -melf_i386 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1g.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1g.d +--- binutils.orig/ld/testsuite/ld-i386/pr19609-1g.d 2017-10-25 12:52:20.673282403 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1g.d 2017-10-25 15:35:26.379256499 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -pie -E -melf_i386 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1h.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1h.d +--- binutils.orig/ld/testsuite/ld-i386/pr19609-1h.d 2017-10-25 12:52:20.673282403 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1h.d 2017-10-25 15:35:33.308176593 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -pie -E -Bsymbolic-functions -melf_i386 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-2a.d binutils-2.27/ld/testsuite/ld-i386/pr19609-2a.d +--- binutils.orig/ld/testsuite/ld-i386/pr19609-2a.d 2017-10-25 12:52:20.673282403 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-2a.d 2017-10-25 15:35:46.253027313 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/pr20244-2d.d binutils-2.27/ld/testsuite/ld-i386/pr20244-2d.d +--- binutils.orig/ld/testsuite/ld-i386/pr20244-2d.d 2017-10-25 12:52:20.677282356 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr20244-2d.d 2017-10-25 15:38:34.521086821 +0100 +@@ -1,4 +1,4 @@ + #source: pr20244-2.s + #as: --32 + #ld: -pie -m elf_i386 +-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object ++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object +diff -rup binutils.orig/ld/testsuite/ld-i386/pr20253-4b.d binutils-2.27/ld/testsuite/ld-i386/pr20253-4b.d +--- binutils.orig/ld/testsuite/ld-i386/pr20253-4b.d 2017-10-25 12:52:20.678282345 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/pr20253-4b.d 2017-10-25 15:36:45.185347695 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -pie -melf_i386 + #readelf: -r --wide ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 1 entries: + +Offset +Info +Type +Sym.* Value +Symbol's Name +diff -rup binutils.orig/ld/testsuite/ld-i386/tlspie3a.d binutils-2.27/ld/testsuite/ld-i386/tlspie3a.d +--- binutils.orig/ld/testsuite/ld-i386/tlspie3a.d 2017-10-25 12:52:20.682282298 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/tlspie3a.d 2017-10-25 15:25:02.726459735 +0100 +@@ -2,5 +2,7 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -pie + #readelf: -r ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + There are no relocations in this file. +diff -rup binutils.orig/ld/testsuite/ld-i386/tlspie3b.d binutils-2.27/ld/testsuite/ld-i386/tlspie3b.d +--- binutils.orig/ld/testsuite/ld-i386/tlspie3b.d 2017-10-25 12:52:20.682282298 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/tlspie3b.d 2017-10-25 15:25:10.854365839 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -pie + #objdump: -dwr ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-i386/tlspie3c.d binutils-2.27/ld/testsuite/ld-i386/tlspie3c.d +--- binutils.orig/ld/testsuite/ld-i386/tlspie3c.d 2017-10-25 12:52:20.682282298 +0100 ++++ binutils-2.27/ld/testsuite/ld-i386/tlspie3c.d 2017-10-25 15:25:21.319244949 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #ld: -melf_i386 -pie -z call-nop=suffix-nop + #objdump: -dwr ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-13-i386.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-13-i386.d +--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-13-i386.d 2017-10-25 12:52:20.686282252 +0100 ++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-13-i386.d 2017-10-25 15:22:29.230232946 +0100 +@@ -4,6 +4,8 @@ + #as: --32 -mrelax-relocations=yes + #readelf: -r --wide + #target: x86_64-*-* i?86-*-* ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + Relocation section '.rel.ifunc' at offset 0x[0-9a-f]+ contains 1 entries: + [ ]+Offset[ ]+Info[ ]+Type[ ]+.* +diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-21-i386.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-21-i386.d +--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-21-i386.d 2017-10-25 12:52:20.688282229 +0100 ++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-21-i386.d 2017-10-25 15:23:08.637777705 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #objdump: -dw + #target: x86_64-*-* i?86-*-* ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d +--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d 2017-10-25 12:52:20.690282205 +0100 ++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d 2017-10-25 15:12:35.549099037 +0100 +@@ -2,6 +2,8 @@ + #ld: -melf_x86_64 + #objdump: -dw + #target: x86_64-*-* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-22-i386.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-22-i386.d +--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-22-i386.d 2017-10-25 12:52:20.688282229 +0100 ++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-22-i386.d 2017-10-25 15:23:00.698869415 +0100 +@@ -2,6 +2,8 @@ + #as: --32 -mrelax-relocations=yes + #objdump: -dw + #target: x86_64-*-* i?86-*-* ++#xfail: *-*-* ++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d +--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d 2017-10-25 12:52:20.690282205 +0100 ++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d 2017-10-25 15:12:35.549099037 +0100 +@@ -2,6 +2,8 @@ + #ld: -melf_x86_64 + #objdump: -dw + #target: x86_64-*-* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d +--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d 2017-10-25 12:52:20.689282217 +0100 ++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d 2017-10-25 15:12:35.549099037 +0100 +@@ -3,6 +3,8 @@ + #ld: -r -melf_x86_64 + #readelf: -r --wide + #target: x86_64-*-* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + Relocation section '.rela.text' at .* + [ ]+Offset[ ]+Info[ ]+Type[ ]+.* +diff -rup binutils.orig/ld/testsuite/ld-selective/selective.exp binutils-2.27/ld/testsuite/ld-selective/selective.exp +--- binutils.orig/ld/testsuite/ld-selective/selective.exp 2017-10-25 12:52:20.872280095 +0100 ++++ binutils-2.27/ld/testsuite/ld-selective/selective.exp 2017-10-25 15:21:30.397912586 +0100 +@@ -102,7 +102,7 @@ foreach testitem $seltests { + # the functionality we try to test for cannot be expected to work. + set version [remote_exec host "$CXX -dumpversion"] + set version [lindex $version 1] +- if [regexp "^(\[1-9\]\[0-9\]+|\[4-9\]|3.(\[1-9\]\[0-9\]+|\[4-9\]))\\." $version] { ++ if [regexp "^(\[1-9\]\[0-9\]+|\[4-9\]|3.(\[1-9\]\[0-9\]+|\[4-9\]))" $version] { + set testflags "$cflags $cxxflags" + setup_xfail {*-*-*} + } else { +diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1a.d binutils-2.27/ld/testsuite/ld-x86-64/call1a.d +--- binutils.orig/ld/testsuite/ld-x86-64/call1a.d 2017-10-25 12:52:21.010278494 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/call1a.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1b.d binutils-2.27/ld/testsuite/ld-x86-64/call1b.d +--- binutils.orig/ld/testsuite/ld-x86-64/call1b.d 2017-10-25 12:52:21.010278494 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/call1b.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=prefix-addr + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1c.d binutils-2.27/ld/testsuite/ld-x86-64/call1c.d +--- binutils.orig/ld/testsuite/ld-x86-64/call1c.d 2017-10-25 12:52:21.010278494 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/call1c.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=prefix-nop + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1d.d binutils-2.27/ld/testsuite/ld-x86-64/call1d.d +--- binutils.orig/ld/testsuite/ld-x86-64/call1d.d 2017-10-25 12:52:21.011278483 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/call1d.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=suffix-nop + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1e.d binutils-2.27/ld/testsuite/ld-x86-64/call1e.d +--- binutils.orig/ld/testsuite/ld-x86-64/call1e.d 2017-10-25 12:52:21.011278483 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/call1e.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=prefix-0x67 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1f.d binutils-2.27/ld/testsuite/ld-x86-64/call1f.d +--- binutils.orig/ld/testsuite/ld-x86-64/call1f.d 2017-10-25 12:52:21.011278483 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/call1f.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=prefix-0x90 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1g.d binutils-2.27/ld/testsuite/ld-x86-64/call1g.d +--- binutils.orig/ld/testsuite/ld-x86-64/call1g.d 2017-10-25 12:52:21.011278483 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/call1g.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=suffix-0x90 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1h.d binutils-2.27/ld/testsuite/ld-x86-64/call1h.d +--- binutils.orig/ld/testsuite/ld-x86-64/call1h.d 2017-10-25 12:52:21.011278483 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/call1h.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -z call-nop=suffix-144 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1i.d binutils-2.27/ld/testsuite/ld-x86-64/call1i.d +--- binutils.orig/ld/testsuite/ld-x86-64/call1i.d 2017-10-25 12:52:21.011278483 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/call1i.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 -z call-nop=suffix-0x90 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/lea1c.d binutils-2.27/ld/testsuite/ld-x86-64/lea1c.d +--- binutils.orig/ld/testsuite/ld-x86-64/lea1c.d 2017-10-25 12:52:21.015278436 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/lea1c.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/lea1f.d binutils-2.27/ld/testsuite/ld-x86-64/lea1f.d +--- binutils.orig/ld/testsuite/ld-x86-64/lea1f.d 2017-10-25 12:52:21.016278425 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/lea1f.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/load1a.d binutils-2.27/ld/testsuite/ld-x86-64/load1a.d +--- binutils.orig/ld/testsuite/ld-x86-64/load1a.d 2017-10-25 12:52:21.016278425 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/load1a.d 2017-10-25 15:12:35.550099025 +0100 +@@ -3,6 +3,8 @@ + #ld: -melf_x86_64 + #objdump: -dw --sym + #notarget: x86_64-*-nacl* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/load1b.d binutils-2.27/ld/testsuite/ld-x86-64/load1b.d +--- binutils.orig/ld/testsuite/ld-x86-64/load1b.d 2017-10-25 12:52:21.017278414 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/load1b.d 2017-10-25 15:12:35.550099025 +0100 +@@ -3,6 +3,8 @@ + #ld: -melf32_x86_64 + #objdump: -dw --sym + #notarget: x86_64-*-nacl* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/mov1b.d binutils-2.27/ld/testsuite/ld-x86-64/mov1b.d +--- binutils.orig/ld/testsuite/ld-x86-64/mov1b.d 2017-10-25 12:52:21.041278135 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/mov1b.d 2017-10-25 15:12:35.550099025 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -pie -melf_x86_64 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/mov1d.d binutils-2.27/ld/testsuite/ld-x86-64/mov1d.d +--- binutils.orig/ld/testsuite/ld-x86-64/mov1d.d 2017-10-25 12:52:21.041278135 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/mov1d.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -pie -melf32_x86_64 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/no-plt.exp binutils-2.27/ld/testsuite/ld-x86-64/no-plt.exp +--- binutils.orig/ld/testsuite/ld-x86-64/no-plt.exp 2017-10-25 12:52:21.020278378 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/no-plt.exp 2017-10-25 15:12:35.551099013 +0100 +@@ -70,15 +70,6 @@ run_cc_link_tests [list \ + "libno-plt-1b.so" \ + ] \ + [list \ +- "No PLT (dynamic 1a)" \ +- "tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \ +- tmpdir/no-plt-func1.o tmpdir/no-plt-extern1.o" \ +- "" \ +- {dummy.s} \ +- {{readelf -Wr no-plt-1a.rd} {objdump -dwrj.text no-plt-1a.dd}} \ +- "no-plt-1a" \ +- ] \ +- [list \ + "No PLT (dynamic 1b)" \ + "tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \ + tmpdir/libno-plt-1a.so tmpdir/libno-plt-1b.so" \ +@@ -88,33 +79,6 @@ run_cc_link_tests [list \ + "no-plt-1b" \ + ] \ + [list \ +- "No PLT (dynamic 1c)" \ +- "tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \ +- tmpdir/no-plt-func1.o tmpdir/libno-plt-1b.so" \ +- "" \ +- {dummy.s} \ +- {{readelf -Wr no-plt-1c.rd} {objdump -dwrj.text no-plt-1c.dd}} \ +- "no-plt-1c" \ +- ] \ +- [list \ +- "No PLT (static 1d)" \ +- "-static tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \ +- tmpdir/no-plt-func1.o tmpdir/no-plt-extern1.o" \ +- "" \ +- {dummy.s} \ +- {{readelf -Wr no-plt-1d.rd} {objdump -dwrj.text no-plt-1d.dd}} \ +- "no-plt-1d" \ +- ] \ +- [list \ +- "No PLT (PIE 1e)" \ +- "-pie tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \ +- tmpdir/no-plt-func1.o tmpdir/no-plt-extern1.o" \ +- "" \ +- {dummy.s} \ +- {{readelf -Wr no-plt-1e.rd} {objdump -dwrj.text no-plt-1e.dd}} \ +- "no-plt-1e" \ +- ] \ +- [list \ + "No PLT (PIE 1f)" \ + "-pie tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \ + tmpdir/libno-plt-1a.so tmpdir/libno-plt-1b.so" \ +@@ -123,15 +87,6 @@ run_cc_link_tests [list \ + {{readelf -Wr no-plt-1f.rd} {objdump -dwrj.text no-plt-1f.dd}} \ + "no-plt-1f" \ + ] \ +- [list \ +- "No PLT (PIE 1g)" \ +- "-pie tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \ +- tmpdir/no-plt-func1.o tmpdir/libno-plt-1b.so" \ +- "" \ +- { dummy.s } \ +- {{readelf -Wr no-plt-1g.rd} {objdump -dwrj.text no-plt-1g.dd}} \ +- "no-plt-1g" \ +- ] \ + ] + + run_ld_link_exec_tests [] [list \ +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1a.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1a.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1a.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 --no-relax + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1b.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1b.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1b.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1b.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -pie -melf_x86_64 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1d.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1d.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1d.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1d.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -E -melf_x86_64 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1f.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1f.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1f.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1f.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -pie --dynamic-list-data -melf_x86_64 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1g.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1g.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1g.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1g.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -pie -E -melf_x86_64 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1h.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1h.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1h.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1h.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 --no-relax + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1i.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1i.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1i.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1i.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -pie -melf32_x86_64 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1k.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1k.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1k.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1k.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -pie -E -Bsymbolic-functions -melf_x86_64 --no-dynamic-linker + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-2a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-2a.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-2a.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-2a.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,3 +2,5 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000 + #error: .*relocation truncated to fit: R_X86_64_32S .* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-2b.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-2b.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-2b.d 2017-10-25 12:52:21.029278274 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-2b.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,3 +2,5 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000 + #error: .*relocation truncated to fit: R_X86_64_32S .* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-3a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-3a.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-3a.d 2017-10-25 12:52:21.030278263 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-3a.d 2017-10-25 15:12:35.551099013 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-3b.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-3b.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-3b.d 2017-10-25 12:52:21.030278263 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-3b.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-4a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4a.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-4a.d 2017-10-25 12:52:21.030278263 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4a.d 2017-10-25 15:12:35.552099002 +0100 +@@ -3,3 +3,5 @@ + #ld: -melf_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000 + #error: .*relocation truncated to fit: R_X86_64_32S .* + #error: .*relocation truncated to fit: R_X86_64_32S .* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-4b.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4b.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-4b.d 2017-10-25 12:52:21.030278263 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4b.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-4c.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4c.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-4c.d 2017-10-25 12:52:21.030278263 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4c.d 2017-10-25 15:12:35.552099002 +0100 +@@ -3,3 +3,5 @@ + #ld: -melf_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000 + #error: .*relocation truncated to fit: R_X86_64_32S .* + #error: .*relocation truncated to fit: R_X86_64_32S .* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-4d.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4d.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-4d.d 2017-10-25 12:52:21.030278263 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4d.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-5a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-5a.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-5a.d 2017-10-25 12:52:21.030278263 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-5a.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-5d.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-5d.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-5d.d 2017-10-25 12:52:21.030278263 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-5d.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,3 +2,5 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -Ttext=0x80000000 + #error: .*relocation truncated to fit: R_X86_64_PC32 .* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-6a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6a.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-6a.d 2017-10-25 12:52:21.031278251 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6a.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,3 +2,5 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 --defsym foobar=0x80000000 + #error: .*relocation truncated to fit: R_X86_64_32S .* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-6c.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6c.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-6c.d 2017-10-25 12:52:21.031278251 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6c.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 --defsym foobar=0x70000000 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-6d.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6d.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-6d.d 2017-10-25 12:52:21.031278251 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6d.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,6 +2,8 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 --defsym foobar=0x80000000 + #objdump: -dw ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-7a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-7a.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-7a.d 2017-10-25 12:52:21.031278251 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-7a.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,3 +2,5 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -Ttext=0x80000000 + #error: .*relocation truncated to fit: R_X86_64_PC32 .* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-7c.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-7c.d +--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-7c.d 2017-10-25 12:52:21.031278251 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-7c.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,3 +2,5 @@ + #as: --x32 -mrelax-relocations=yes + #ld: -melf32_x86_64 -Ttext=0x80000000 + #error: .*relocation truncated to fit: R_X86_64_PC32 .* ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. +diff -rup binutils.orig/ld/testsuite/ld-x86-64/tls.exp binutils-2.27/ld/testsuite/ld-x86-64/tls.exp +--- binutils.orig/ld/testsuite/ld-x86-64/tls.exp 2017-10-25 12:52:21.036278193 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/tls.exp 2017-10-25 15:12:35.552099002 +0100 +@@ -69,42 +69,6 @@ run_cc_link_tests [list \ + + run_ld_link_exec_tests [] [list \ + [list \ +- "TLS GD/LD -> LE transition without PLT (dynamic)" \ +- "tmpdir/tls-def1.o tmpdir/tls-main1.o tmpdir/tls-gd1.o \ +- tmpdir/tls-ld1.o" \ +- "" \ +- { dummy.s } \ +- "tls-1a" \ +- "pass.out" \ +- ] \ +- [list \ +- "TLS GD/LD -> LE transition without PLT (PIE)" \ +- "-pie tmpdir/tls-def1.o tmpdir/tls-main1.o tmpdir/tls-gd1.o \ +- tmpdir/tls-ld1.o" \ +- "" \ +- { dummy.s } \ +- "tls-1b" \ +- "pass.out" \ +- ] \ +- [list \ +- "TLS GD/LD -> LE transition without PLT (static)" \ +- "-static tmpdir/tls-def1.o tmpdir/tls-main1.o tmpdir/tls-gd1.o \ +- tmpdir/tls-ld1.o" \ +- "" \ +- { dummy.s } \ +- "tls-1c" \ +- "pass.out" \ +- ] \ +- [list \ +- "TLS GD/LD -> IE transition without PLT" \ +- "tmpdir/tls-main1.o tmpdir/tls-gd1.o tmpdir/tls-ld1.o \ +- tmpdir/libtls-1a.so -R tmpdir" \ +- "" \ +- { dummy.s } \ +- "tls-1d" \ +- "pass.out" \ +- ] \ +- [list \ + "TLS without PLT (1)" \ + "tmpdir/tls-main1.o \ + tmpdir/libtls-1a.so tmpdir/libtls-1b.so -R tmpdir" \ +diff -rup binutils.orig/ld/testsuite/ld-x86-64/tlspie2a.d binutils-2.27/ld/testsuite/ld-x86-64/tlspie2a.d +--- binutils.orig/ld/testsuite/ld-x86-64/tlspie2a.d 2017-10-25 12:52:21.039278158 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/tlspie2a.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,5 +2,7 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -pie + #readelf: -r ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + There are no relocations in this file. +diff -rup binutils.orig/ld/testsuite/ld-x86-64/tlspie2b.d binutils-2.27/ld/testsuite/ld-x86-64/tlspie2b.d +--- binutils.orig/ld/testsuite/ld-x86-64/tlspie2b.d 2017-10-25 12:52:21.039278158 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/tlspie2b.d 2017-10-25 15:12:35.552099002 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -pie + #objdump: -dwr ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/tlspie2c.d binutils-2.27/ld/testsuite/ld-x86-64/tlspie2c.d +--- binutils.orig/ld/testsuite/ld-x86-64/tlspie2c.d 2017-10-25 12:52:21.039278158 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/tlspie2c.d 2017-10-25 15:12:35.553098990 +0100 +@@ -2,6 +2,8 @@ + #as: --64 -mrelax-relocations=yes + #ld: -melf_x86_64 -pie -z call-nop=suffix-nop + #objdump: -dwr ++#xfail: *-*-* ++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed. + + .*: +file format .* + +diff -rup binutils.orig/ld/testsuite/ld-x86-64/x86-64.exp binutils-2.27/ld/testsuite/ld-x86-64/x86-64.exp +--- binutils.orig/ld/testsuite/ld-x86-64/x86-64.exp 2017-10-25 12:52:21.040278147 +0100 ++++ binutils-2.27/ld/testsuite/ld-x86-64/x86-64.exp 2017-10-25 15:12:35.553098990 +0100 +@@ -55,13 +55,6 @@ set x86_64tests { + {{readelf -WSsrl tlspic.rd} {objdump -drj.text\ -Mintel64 tlspic.dd} + {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}} + "libtlspic.so"} +- {"TLS -fpic -shared transitions with r15 as GOT base" +- "-shared -melf_x86_64 --no-ld-generated-unwind-info" "" +- "--64 -mrelax-relocations=yes" +- {tlspic3.s tlspic2.s} +- {{readelf -WSsrl tlspic2.rd} {objdump -drj.text\ -Mintel64 tlspic2.dd} +- {objdump -sj.got tlspic2.sd} {objdump -sj.tdata tlspic2.td}} +- "libtlspic2.so"} + {"TLS descriptor -fpic -shared transitions" + "-shared -melf_x86_64 --no-ld-generated-unwind-info" "" + "--64" {tlsdesc.s tlspic2.s} +@@ -76,12 +69,6 @@ set x86_64tests { + {{readelf -WSsrl tlsbin.rd} {objdump -drj.text tlsbin.dd} + {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}} + "tlsbin"} +- {"TLS -fpic and -fno-pic exec transitions without PLT" +- "-melf_x86_64 tmpdir/libtlslib.so --no-ld-generated-unwind-info" "" +- "-mrelax-relocations=yes --64" {tlsbinpic2.s tlsbin.s} +- {{readelf -WSsrl tlsbin2.rd} {objdump -drj.text tlsbin2.dd} +- {objdump -sj.got tlsbin2.sd} {objdump -sj.tdata tlsbin2.td}} +- "tlsbin2"} + {"TLS descriptor -fpic and -fno-pic exec transitions" + "-melf_x86_64 tmpdir/libtlslib.so --no-ld-generated-unwind-info" "" + "--64" {tlsbindesc.s tlsbin.s} +@@ -128,19 +115,11 @@ set x86_64tests { + {"TLS GD->IE transition" "-melf_x86_64 tmpdir/libtlsgd5.so" "" + "--64" {tlsgd5a.s} + {{objdump -dwr tlsgd5.dd}} "tlsgd5a"} +- {"TLS GD->IE transition without PLT" +- "-melf_x86_64 tmpdir/libtlsgd5.so" "" +- "-mrelax-relocations=yes --64" {tlsgd5c.s} +- {{objdump -dwr tlsgd5.dd}} "tlsgd5b"} + {"Helper TLS X32 GD->IE transition DSO" "-shared -melf32_x86_64" "" + "--x32" {tlsgd6b.s} {} "libtlsgd6.so"} + {"TLS X32 GD->IE transition" "-melf32_x86_64 tmpdir/libtlsgd6.so" "" + "--x32" {tlsgd6a.s} + {{objdump -dwr tlsgd6.dd}} "tlsgd6a"} +- {"TLS X32 GD->IE transition without PLT" +- "-melf32_x86_64 tmpdir/libtlsgd6.so" "" +- "-mrelax-relocations=yes --x32" {tlsgd6c.s} +- {{objdump -dwr tlsgd6.dd}} "tlsgd6b"} + {"TLS X32 LD->LE transition" "-melf32_x86_64" "" + "--x32" {tlsld2.s} + {{objdump -dwr tlsld2.dd}} "tlsld2"} +@@ -154,15 +133,6 @@ set x86_64tests { + "-melf_x86_64" "" + "--64" {tlsld4.s} + {{objdump -dwr tlsld4.dd}} "tlsld4"} +- {"TLS LD->LE transition without PLT" +- "-melf_x86_64" "" +- "--64 -mrelax-relocations=yes" +- {tlsld5.s} +- {{objdump -dwr tlsld5.dd}} "tlsld5"} +- {"TLS X32 LD->LE transition without PLT" "-melf32_x86_64" "" +- "--x32 -mrelax-relocations=yes" +- {tlsld6.s} +- {{objdump -dwr tlsld6.dd}} "tlsld6"} + {"TLS -mcmodel=large GD->IE transition" "-melf_x86_64 tmpdir/libtlsgd5.so" "" + "--64" {tlsgd8.s} + {{objdump -dwrj.text tlsgd8.dd}} "tlsgd8"} +@@ -620,7 +590,7 @@ if { [isnative] && [which $CC] != 0 } { + "" \ + "-fPIC -Wa,-mrelax-relocations=yes" \ + { plt-main1.c } \ +- {{readelf {-Wr} plt-main1.rd}} \ ++ {} \ + "libplt-main1.a" \ + ] \ + [list \ +@@ -644,7 +614,7 @@ if { [isnative] && [which $CC] != 0 } { + "" \ + "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \ + { plt-main4.c } \ +- {{readelf {-Wr} plt-main4.rd}} \ ++ {} \ + "libplt-main4.a" \ + ] \ + [list \ +@@ -799,14 +769,6 @@ if { [isnative] && [which $CC] != 0 } { + { gotpcrel1a.S gotpcrel1b.c gotpcrel1c.c } \ + ] \ + [list \ +- "Build gotpcrel1" \ +- "-Wl,--as-needed tmpdir/gotpcrel1a.o tmpdir/gotpcrel1b.o tmpdir/gotpcrel1c.o tmpdir/gotpcrel1d.so" \ +- { dummy.s } \ +- "" \ +- {{objdump {-dw} gotpcrel1.dd}} \ +- "gotpcrel1" \ +- ] \ +- [list \ + "Build pr19319.so" \ + "-shared" \ + "" \ diff --git a/SPECS/binutils.spec b/SPECS/binutils.spec index e646b6e..693e829 100644 --- a/SPECS/binutils.spec +++ b/SPECS/binutils.spec @@ -17,6 +17,7 @@ %define isnative 0 %define enable_shared 0 %endif + # Provide a way to enable deterministic archives. # But do not do this by default. %define enable_deterministic_archives 0 @@ -24,6 +25,8 @@ %define enable_lto 1 # Disable the default generation of compressed debug sections. %define default_compress_debug 0 +# Default to read-only-relocations (relro) in shared binaries. +%define default_relro 1 # Default: Not bootstrapping. %bcond_with bootstrap @@ -43,94 +46,274 @@ %undefine with_testsuite %endif +#--------------------------------------------------------------------------------- + Summary: A GNU collection of binary utilities Name: %{?cross}binutils%{?_with_debug:-debug} Version: 2.27 -# Note: The Release string *must* be different from that used by any of the +# Note: The Release string *must* be different from that used by any of the # devtoolset binutils associated with this release. That is why ".base" # has been appended here. See BZ 1337617 for more details. -Release: 11.base%{?dist} +Release: 27.base%{?dist} License: GPLv3+ Group: Development/Tools URL: http://sources.redhat.com/binutils +# Note - the Linux Kernel binutils releases are too unstable and contain +# too many controversial patches so we stick with the official FSF version +# instead. + Source: http://ftp.gnu.org/gnu/binutils/binutils-%{version}.tar.bz2 Source2: binutils-2.19.50.0.1-output-format.sed +%if %{with docs} +# Strictly speaking this next file is not part of the binutils distribution. +# But the emacs info system expects it to be present on any system where +# emacs is installed, and old binutils distributions used to include it by +# mistake. Since there is no suitable 'documentation files' component to +# current RHEL releases, it is included here, but to save time and complexity +# it is stored as a pre-built, compressed, info file. +# The upstream version of the original source file can be found here: +# http://git.savannah.gnu.org/gitweb/?p=gnulib.git;a=blob_plain;f=doc/standards.texi;hb=HEAD +# For more information see: https://bugzilla.redhat.com/show_bug.cgi?id=1467390 +Source3: standards.info.gz +%endif + +#----------------------Patches---------------------------------------------------- +# Purpose: Use /lib64 and /usr/lib64 instead of /lib and /usr/lib in the +# default library search path of 64-bit targets. +# Lifetime: Permanent, but it should not be. This is a bug in the libtool +# sources used in both binutils and gcc, (specifically the +# libtool.m4 file). These are based on a version released in 2009 +# (2.2.6?) rather than the latest version. (Definitely fixed in +# libtool version 2.4.6). Patch01: binutils-2.20.51.0.2-libtool-lib64.patch + +# Purpose: Prevents the generation of a spurious relocation in PPC64 PEI +# executables. +# Lifetime: Redundant - should be deleted. Patch02: binutils-2.20.51.0.10-ppc64-pie.patch + +# Purpose: Appends a RHEL or Fedora release string to the generic binutils +# version string. +# Lifetime: Permanent. This is a RHEL/Fedora specific patch. Patch03: binutils-2.25-version.patch + +# Purpose: Use the "unsigned long long" type for pointers on hosts where +# long is a 32-bit type but pointers are a 64-bit type. +# Lifetime: Redundant - should be deleted. Patch04: binutils-2.25-set-long-long.patch + +# Purpose: Prevent a seg-fault when attempting to pad a section with a NULL +# padding pointer. +# Lifetime: Fixed in 2.30. Patch05: binutils-2.20.51.0.10-sec-merge-emit.patch -# Enable -zrelro by default: BZ #621983 -Patch06: binutils-2.22.52.0.1-relro-on-by-default.patch -# Local patch - export demangle.h with the binutils-devel rpm. + +# Purpose: Exports the demangle.h header file (associated with the libiberty +# sources) with the binutils-devel rpm. +# Lifetime: Permanent. This is a RHEL/Fedora specific patch. Patch07: binutils-2.22.52.0.1-export-demangle.h.patch -# Disable checks that config.h has been included before system headers. BZ #845084 + +# Purpose: Disables the check in the BFD library's header file that config.h +# has been included before the bfd.h header. See BZ #845084 for +# more details. +# Lifetime: Permanent - but it should not be. The bfd.h header defines +# various types that are dependent upon configuration options, so +# the order of inclusion is important. +# FIXME: It would be better if the packages using the BFD header were +# fixed so that they do include the header files in the correct +# order. It may also be necessary to add a way for a package to +# tell the bfd.h header that this check is not necessary. Patch08: binutils-2.22.52.0.4-no-config-h-check.patch -# Enable RELRO on AArch64 + +# Purpose: Enables RELRO by default for AArch64 and ARM targets. +# See BZ 1203449. +# Lifetime: Fixed in FSF binutils 2.28. Patch09: binutils-rh1203449.patch -# Ignore duplicate FDE entries + +# Purpose: Stops the linker from issuing a warning message when it +# encounters an FDE entry that duplicates another FDE entry. These +# can be generated by linker garbage collection eliminating a +# section but not its FDE data. See BZ 1300603 for more details. +# Lifetime: Permanent - for now. Ideally the linker should be improved so +# that these duplicate entries are eliminated at an earlier stage +# of the link process. Patch10: binutils-rh1300603.patch -# Fix linker testsuite failures for PPC64. + +# Purpose: Fix linker testsuite failures for PPC64. +# Lifetime: Redundant. These failures should be fixed in the upstream +# sources now. +# FIXME: Need to test that failures are fixed and then remove this patch. Patch11: binutils-rh1312876.patch -# Enhance the location of separate debug info files + +# Purpose: Add /usr/lib/debug to the list of directories searched for +# separate debug info files. +# Lifetime: Fixed in 2.28. Patch12: binutils-2.23.52.0.1-find-separate-debug-file.patch -# # Make linking fail when PIE and non-PIE S390 binaries are combined. -# Patch13: binutils-rh1406430.patch -# Speed up combining source code listings with disassembly output. + +# Purpose: Speed up combining source code listings with disassembly output. +# Lifetime: Fixed in 2.28. Patch14: binutils-2.25.1-objdump-speedup.patch -# Fix computation of sh_info field for .dynsym sections + +# Purpose: Fix computation of sh_info field for .dynsym sections +# Lifetime: Fixed in 2.28. Patch15: binutils-2.27-local-dynsym-count.patch -# Put sections in a monotonically increasing order of file offset. + +# Purpose: Ensure that sections are placed in a monotonically increasing +# order of file offset. +# Lifetime: Fixed in 2.28. Patch16: binutils-2.27-monotonic-section-offsets.patch -# Skip PR14918 linker test for ARM native targets. + +# Purpose: Skip PR14918 linker test for ARM native targets. +# Lifetime: Fixed in 2.30. Patch17: binutils-2.27-skip-rp14918-test-for-arm.patch -# Fix GOLD for ARM/AARCH64. + +# Purpose: Fixes compile time errors building GOLD for the AArch64 and ARM +# targets. +# Lifetime: Fixed in 2.28. Patch18: binutils-2.27-gold.patch -# Improve objdump's disassembly of dynamic executables. + +# Purpose: Improve objdump's disassembly of dynamic executables. +# Lifetime: Fixed in 2.28. +# FIXME: Contains a bug. See entry for +# binutils-2.27-remove-dwarf2-minmax.patch Patch19: binutils-2.27-objdump-improvements.patch -# Include the filename concerned in readelf error messages. + +# Purpose: Include the filename concerned in readelf error messages. +# Lifetime: Permanent. This patch changes the format of readelf's output, +# making it better (IMHO) but also potentially breaking tools that +# depend upon readelf's current format. Hence it remains a local +# patch. Patch20: binutils-2.27-filename-in-error-messages.patch -# Add support for the Power9 architecture + +# Purpose: Add support for the Power9 architecture. +# Lifetime: Fixed in 2.28. Patch21: binutils-2.27-power9.patch -# And some Power9 bug fixes. + +# Purpose: And some Power9 bug fixes. +# Lifetime: Fixed in 2.28. Patch22: binutils-2.27-power9.2.patch -# Fix up errors detected by Coverty + +# Purpose: Fix up errors detected by Coverty. +# Lifetime: Fixed in 2.29. Patch23: binutils-coverty-fixes.patch -# Do not create PLT entries for AARCh64 IFUNC symbols referenced in debug sections. + +# Purpose: Do not create PLT entries for AARCH64 IFUNC symbols referenced in +# debug sections. +# Lifetime: Permanent. +# FIXME: Find related bug. Decide on permanency. Patch24: binutils-2.27-aarch64-ifunc.patch -# Skip ifunc exec tests for AArch64. + +# Purpose: Skip ifunc exec tests for AArch64. +# Lifetime: Fixed in 2.28. Patch25: binutils-2.27-skip-ld-aarch64-ifunc-exec-tests.patch -# Expect linker test PR19719 to fail for the S390. + +# Purpose: Expect linker test PR19719 to fail for the S390. +# Lifetime: Permanent. +# FIXME: Check to see if this test still fails, and delete patch when it +# passes. Patch26: binutils-2.27-s390-pr19719.patch -# Delete linker tests for PR 19784. + +# Purpose: Delete linker tests for PR 19784. +# Lifetime: Fixed in 2.28. Patch27: binutils-2.27-remove-pr19784-test.patch -# Fix computing stub sizes on PowerPC. + +# Purpose: Fix computing stub sizes on PowerPC. +# Lifetime: Fixed in 2.28. Patch28: binutils-2.27-ppc-stubs.patch -# Fix s390 PLT entry allocation. + +# Purpose: Fix s390 PLT entry allocation. +# Lifetime: Fixed in 2.29. Patch29: binutils-2.27-s390-plt.patch -# Revert H.J/s PLT elision patch. + +# Purpose: Revert H.J/s PLT elision patch. +# Lifetime: Permanent. +# FIXME: We should add a configure time option to enable/disable this +# optimization. Patch30: binutils-2.27-revert-PLT-elision.patch -# Add SCV, RFSCV and LNIA instructions for Power9. -Patch31: binutils-2.27-power9.3.patch -# A *temporary* patch to disable checking for valid PowerPC64 TLBIE -# instructions. This allows the PPC kernel to be built. See: -# https://sourceware.org/ml/binutils/2015-05/msg00133.html +# Purpose: Add support for new DWARF5 tag: DW_AT_export_symbols. +# Lifetime: Fixed in 2.29. +Patch31: binutils-2.27-DW_AT_export_symbols.patch + +# Purpose: Fixes a bug in binutils-2.25.1-objdump-speedup.patch that +# prevents address to function name lookup from working properly +# in some circumstances. +# Lifetime: Retire when binutils-2.25.1-objdump-speedup.ptch is retired. +# Ie when rebasing to 2.28. +Patch32: binutils-2.27-remove-dwarf2-minmax.patch + +# Purpose: Add support for the arch12 s390x ISA extensions. +# Lifetime: Fixed in 2.28. +Patch33: binutils-2.27-s390x-arch12.patch + +# Purpose: Fix various minor CVE bugs. +# Lifetime: Fixed in 2.28. +Patch34: binutils-2.27-cve-bugs.patch + +# Purpose: Add support for ARMv8.2a and ARMv8.3 ISA extensions. +# Lifetime: Fixewd in 2.29. +Patch35: binutils-2.27-ARMv8.2.patch + +# Purpose: Fix generation of COPY relocs on AArch64. +# Lifetime: Fixed in 2.29. +Patch36: binutils-2.27-aarch64-copy-relocs.patch + +# Purpose: Generate an error when attempting to link non-PIC s390 objects in +# PIE mode. +# Lifetime: Fixed in 2.28. +Patch37: binutils-2.27-s390x-complain-missing-fPIC.patch + +# Purpose: Add support for creating an PT_S390_PGSTE segment in s390 +# binaries. +# Lifetime: Fixed in 2.29. +Patch38: binutils-2.27-s390-pgste-marker.patch + +# Purpose: Fix seg-faults when stripping s390x binaries. +# Lifetime: Fixed in 2.29. +Patch39: binutils-2.27-s390x-check-for-NULL-pointers.patch + +# Purpose: Add support for the LNIA, SCV and RFSCV instructions in Power9 +# Lifetime: Fixed in 2.28. +Patch40: binutils-2.27-power9.3.patch + +# Purpose: Fix a seg-fault in the PowerPC linker when discarding .plt +# sections when -pie is used and undefined weak symbols are +# present. See PR 22431. +# Lifetime: Fixed in 2.30. +Patch41: binutils-2.27-ppc64-discarded-plt-sections.patch + +# Purpose: A *temporary* patch to disable the generation of +# R_X86_64_GOTPCRELX and R_X86_64_REX_GETPCRELX relocations by the +# x86_64 assembler and the generations of the R_386_GOT32X +# relocation by the x86 assembler. This is because these +# relocations are unknown to the 2.25 version of the linker, and so +# static libraries and object files built with the 2.27 assembler +# (and without this patch) are incompatible. Unfortunately we need +# to maintain backwards compatibility to the 2.25 linker for the +# RHEL 7 product. See BZ 1506004 for more defails. +# Lifetime: Keep in RHEL 7, discard for RHEL 8. +Patch998: binutils-2.27-suppress-R_X86_64_GOTPCRELX.patch + +# Purpose: A *temporary* patch to disable checking for valid PowerPC64 TLBIE +# instructions. This allows the PPC kernel to be built. See: +# https://sourceware.org/ml/binutils/2015-05/msg00133.html +# Lifetime: Delete in NEXT release. Patch999: binutils-SUPPRESS-PPC-TLBIE-CHECK.patch +#--------------------------------------------------------------------------------- + Provides: bundled(libiberty) %define gold_arches %ix86 x86_64 %arm aarch64 %if %{with bootstrap} -%define build_gold no +%define build_gold no %else %ifarch %gold_arches -%define build_gold both +%define build_gold both %else -%define build_gold no +%define build_gold no %endif %endif @@ -143,7 +326,6 @@ Provides: bundled(libiberty) Buildroot: %(mktemp -ud %{_tmppath}/%{name}-%{version}-%{release}-XXXXXX) - BuildRequires: gcc # Gold needs bison in order to build gold/yyscript.c. @@ -178,8 +360,8 @@ BuildRequires: libstdc++-static Conflicts: gcc-c++ < 4.0.0 # The higher of these two numbers determines the default ld. -%{!?ld_bfd_priority: %global ld_bfd_priority 50} -%{!?ld_gold_priority:%global ld_gold_priority 30} +%{!?ld_bfd_priority: %global ld_bfd_priority 50} +%{!?ld_gold_priority:%global ld_gold_priority 30} %if "%{build_gold}" == "both" Requires(post): coreutils @@ -193,6 +375,8 @@ Requires(preun): %{_sbindir}/alternatives %define _gnu %{nil} %endif +#--------------------------------------------------------------------------------- + %description Binutils is a collection of binary utilities, including ar (for creating, modifying and extracting from archives), as (a family of GNU @@ -206,6 +390,8 @@ of an object or archive file), strings (for listing printable strings from files), strip (for discarding symbols), and addr2line (for converting addresses to file and line). +#--------------------------------------------------------------------------------- + %package devel Summary: BFD and opcodes static and dynamic libraries and header files Group: System Environment/Libraries @@ -232,23 +418,22 @@ dynamic libraries. Developers starting new projects are strongly encouraged to consider using libelf instead of BFD. +#--------------------------------------------------------------------------------- + %prep %setup -q -n binutils-%{version} -%patch01 -p0 -b .libtool-lib64~ -%patch02 -p0 -b .ppc64-pie~ -%patch03 -p1 -b .version~ -%patch04 -p1 -b .set-long-long~ -%patch05 -p1 -b .sec-merge-emit~ -%if 0%{?fedora} >= 18 || 0%{?rhel} >= 7 -%patch06 -p1 -b .relro~ -%endif -%patch07 -p1 -b .export-demangle-h~ -%patch08 -p0 -b .no-config-h-check~ -%patch09 -p0 -b .aarch64relro~ +%patch01 -p0 +%patch02 -p0 +%patch03 -p1 +%patch04 -p1 +%patch05 -p1 +%patch07 -p1 +%patch08 -p0 +%patch09 -p0 %patch10 -p1 %patch11 -p1 %patch12 -p1 -# %patch13 -p1 + %patch14 -p1 %patch15 -p1 %patch16 -p1 @@ -267,8 +452,19 @@ using libelf instead of BFD. %patch29 -p1 %patch30 -p1 %patch31 -p1 - -# TEMPORARY patch. +%patch32 -p1 +%patch33 -p1 +%patch34 -p1 +%patch35 -p1 +%patch36 -p1 +%patch37 -p1 +%patch38 -p1 +%patch39 -p1 +%patch40 -p1 +%patch41 -p1 + +# TEMPORARY patches. +%patch998 -p1 %patch999 -p1 # We cannot run autotools as there is an exact requirement of autoconf-2.59. @@ -307,9 +503,12 @@ touch */configure %define _target_platform %{_arch}-%{_vendor}-%{_host_os} %endif +#--------------------------------------------------------------------------------- + %build echo target is %{binutils_target} export CFLAGS="$RPM_OPT_FLAGS" + CARGS= case %{binutils_target} in i?86*|sparc*|ppc*|s390*|sh*|arm*|aarch64*) @@ -328,10 +527,16 @@ case %{binutils_target} in ppc*|ppc64*) esac case %{binutils_target} in ppc64le*) - CARGS="$CARGS --enable-targets=spu,powerpc-linux" - ;; + CARGS="$CARGS --enable-targets=spu,powerpc-linux" + ;; esac +%if %{default_relro} + CARGS="$CARGS --enable-relro=yes" +%else + CARGS="$CARGS --enable-relro=no" +%endif + %if 0%{?_with_debug:1} CFLAGS="$CFLAGS -O0 -ggdb2 -Wno-error -D_FORTIFY_SOURCE=0" %define enable_shared 0 @@ -340,6 +545,7 @@ CFLAGS="$CFLAGS -O0 -ggdb2 -Wno-error -D_FORTIFY_SOURCE=0" # We could optimize the cross builds size by --enable-shared but the produced # binaries may be less convenient in the embedded environment. %configure \ + --quiet \ --build=%{_target_platform} --host=%{_target_platform} \ --target=%{binutils_target} \ %ifarch %gold_arches @@ -363,7 +569,7 @@ CFLAGS="$CFLAGS -O0 -ggdb2 -Wno-error -D_FORTIFY_SOURCE=0" %endif %if %{enable_deterministic_archives} --enable-deterministic-archives \ -%else +%else --enable-deterministic-archives=no \ %endif %if %{enable_lto} @@ -378,7 +584,7 @@ CFLAGS="$CFLAGS -O0 -ggdb2 -Wno-error -D_FORTIFY_SOURCE=0" --enable-plugins \ --with-bugurl=http://bugzilla.redhat.com/bugzilla/ -%if %{with docs} +%if %{with docs} make %{_smp_mflags} tooldir=%{_prefix} all make %{_smp_mflags} tooldir=%{_prefix} info %else @@ -403,17 +609,20 @@ uuencode binutils-%{_target_platform}.tar.bz2 binutils-%{_target_platform}.tar.b rm -f binutils-%{_target_platform}.tar.bz2 binutils-%{_target_platform}-*.{sum,log} %endif +#--------------------------------------------------------------------------------- + %install rm -rf %{buildroot} -%if %{with docs} +%if %{with docs} make install DESTDIR=%{buildroot} %else make install DESTDIR=%{buildroot} MAKEINFO=true %endif %if %{isnative} -%if %{with info} +%if %{with docs} make prefix=%{buildroot}%{_prefix} infodir=%{buildroot}%{_infodir} install-info +cp %{SOURCE3} %{buildroot}%{_infodir} %endif # Rebuild libiberty.a with -fPIC. @@ -437,10 +646,14 @@ install -m 644 include/libiberty.h %{buildroot}%{_prefix}/include install -m 644 opcodes/libopcodes.a %{buildroot}%{_libdir} # Remove Windows/Novell only man pages rm -f %{buildroot}%{_mandir}/man1/{dlltool,nlmconv,windres,windmc}* +%if %{without docs} +rm -f %{buildroot}%{_mandir}/man1/{addr2line,ar,as,c++filt,elfedit,gprof,ld,nm,objcopy,objdump,ranlib,readelf,size,strings,strip}* +rm -f %{buildroot}%{_infodir}/{as,bfd,binutils,gprof,ld}* +%endif %if %{enable_shared} chmod +x %{buildroot}%{_libdir}/lib*.so* -%endif +%endif # isnative # Prevent programs from linking against libbfd and libopcodes # dynamically, as they are change far too often. @@ -493,14 +706,14 @@ $OUTPUT_FORMAT INPUT ( %{_libdir}/libopcodes.a -lbfd ) EOH -%else # !%{isnative} +%else # !isnative # For cross-binutils we drop the documentation. rm -rf %{buildroot}%{_infodir} # We keep these as one can have native + cross binutils of different versions. -#rm -rf %{buildroot}%{_prefix}/share/locale -#rm -rf %{buildroot}%{_mandir} +#rm -rf {buildroot}{_prefix}/share/locale +#rm -rf {buildroot}{_mandir} rm -rf %{buildroot}%{_libdir}/libiberty.a -%endif # !%{isnative} +%endif # !isnative # This one comes from gcc rm -f %{buildroot}%{_infodir}/dir @@ -525,9 +738,13 @@ if [ -x gold/ld-new ]; then cat %{?cross}gold.lang >> %{?cross}binutils.lang fi +#--------------------------------------------------------------------------------- + %clean rm -rf %{buildroot} +#--------------------------------------------------------------------------------- + %post %if "%{build_gold}" == "both" %__rm -f %{_bindir}/%{?cross}ld @@ -535,26 +752,33 @@ rm -rf %{buildroot} %{_bindir}/%{?cross}ld.bfd %{ld_bfd_priority} %{_sbindir}/alternatives --install %{_bindir}/%{?cross}ld %{?cross}ld \ %{_bindir}/%{?cross}ld.gold %{ld_gold_priority} -%{_sbindir}/alternatives --auto %{?cross}ld -%endif +%{_sbindir}/alternatives --auto %{?cross}ld +%endif # both ld.gold and ld.bfd + %if %{isnative} /sbin/ldconfig + %if %{with docs} /sbin/install-info --info-dir=%{_infodir} %{_infodir}/as.info.gz /sbin/install-info --info-dir=%{_infodir} %{_infodir}/binutils.info.gz /sbin/install-info --info-dir=%{_infodir} %{_infodir}/gprof.info.gz /sbin/install-info --info-dir=%{_infodir} %{_infodir}/ld.info.gz + /sbin/install-info --info-dir=%{_infodir} %{_infodir}/standards.info.gz %endif # with docs -%endif # %{isnative} +%endif # isnative + exit 0 +#--------------------------------------------------------------------------------- + %preun %if "%{build_gold}" == "both" if [ $1 = 0 ]; then %{_sbindir}/alternatives --remove %{?cross}ld %{_bindir}/%{?cross}ld.bfd %{_sbindir}/alternatives --remove %{?cross}ld %{_bindir}/%{?cross}ld.gold fi -%endif +%endif # both ld.gold and ld.bfd + %if %{isnative} if [ $1 = 0 ]; then if [ -e %{_infodir}/binutils.info.gz ] @@ -564,13 +788,21 @@ if [ $1 = 0 ]; then /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/gprof.info.gz /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/ld.info.gz fi + if [ -e %{_infodir}/standards.info.gz ] + then + /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/standards.info.gz + fi fi -%endif +%endif # isnative + exit 0 +#--------------------------------------------------------------------------------- + %if %{isnative} %postun /sbin/ldconfig + if [ -e %{_infodir}/binutils.info.gz ] then /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/as.info.gz @@ -578,30 +810,44 @@ exit 0 /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/gprof.info.gz /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/ld.info.gz fi -%endif # %{isnative} + if [ -e %{_infodir}/standards.info.gz ] + then + /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/standards.info.gz + fi +%endif # isnative + +#--------------------------------------------------------------------------------- %files -f %{?cross}binutils.lang %defattr(-,root,root,-) +%license COPYING COPYING3 COPYING3.LIB COPYING.LIB %doc README %{_bindir}/%{?cross}[!l]* + %if "%{build_gold}" == "both" %{_bindir}/%{?cross}ld.* %ghost %{_bindir}/%{?cross}ld %else %{_bindir}/%{?cross}ld* -%endif +%endif # both ld.gold and ld.bfd + +%if %{with docs} %{_mandir}/man1/* %{_infodir}/as.info.gz %{_infodir}/binutils.info.gz %{_infodir}/gprof.info.gz %{_infodir}/ld.info.gz +%{_infodir}/standards.info.gz +%endif # with docs + %if %{enable_shared} %{_libdir}/lib*.so %exclude %{_libdir}/libbfd.so %exclude %{_libdir}/libopcodes.so -%endif +%endif # enable_shared %if %{isnative} + %if %{with docs} %{_infodir}/[^b]*info* %{_infodir}/binutils*info* @@ -613,55 +859,81 @@ exit 0 %{_libdir}/lib*.a %{_libdir}/libbfd.so %{_libdir}/libopcodes.so + %if %{with docs} %{_infodir}/bfd*info* %endif # with docs -%endif # %{isnative} +%endif # isnative + +#--------------------------------------------------------------------------------- %changelog -* Wed Sep 13 2017 Nick Clifton 2.27-11.base -- Add SCV, RFSCV amd LNIA instructions to Power9 port of gas. - (#1449585) - -* Thu May 18 2017 Nick Clifton - 2.27-9.base -- Revert H.J.Lu PLT elision patch. - (#1445781) - -* Fri May 12 2017 Nick Clifton - 2.27-8.base -- Restore rebase to 2.27. - (#1449585) - (#1449586) -- Disable patch for BZ 1406430 - it prevents building correct s390 binaries. - (#1406430) - (#1447209) -- Fix generation of PLT entries for s390 binaries. - (#1440168) +* Thu Jan 11 2018 Nick Clifton 2.27-27.base +- Do enable relro by default for the PowerPC64 architecture. + (#1523946) -* Wed Mar 08 2017 Nick Clifton 2.27-7.base -- Import fix for PR 20886 - corrects the sizing of PowerPC stubs. - (#1406498) +* Thu Jan 04 2018 Nick Clifton 2.27-26.base +- Fix thinko in post-uninstall section. + (#1520899) + +* Tue Jan 02 2018 Nick Clifton 2.27-25.base +- Remove man and info files not needed when building without documentation. + (#1530339) + +* Tue Jan 02 2018 Nick Clifton 2.27-24.base +- Check for the existance of standards.info.gz before attempting to uninstall it. + (#1520899) + +* Tue Dec 19 2017 Nick Clifton 2.27-23.base +- Do not complain if the standards.info.gz file does not exist when uninstalling. + (#1520899) + +* Mon Dec 11 2017 Nick Clifton 2.27-22.base +- Do not enable relro by default for the PowerPC64 architecture. + (#1523946) + +* Thu Nov 16 2017 Nick Clifton 2.27-21.base +- Prevent the PowerPC64 linker from triggering a seg-fault when discarding dynamic sections. + (#1513014) -* Tue Feb 21 2017 Nick Clifton 2.27-6.base -- Delete linker tests for PR 19784. - (#1424707) +* Thu Nov 02 2017 Nick Clifton 2.27-20.base +- Bump NVR so that the binutils rpms will be rebuilt, since they also have files that contain the offending relocs. + (#1508954) -* Tue Feb 21 2017 Nick Clifton 2.27-5.base -- Expect linker test PR19719 to fail for S390 architectures. - (#1424706) +* Wed Oct 25 2017 Nick Clifton 2.27-19.base +- Suppress the generation of R_X86_64_GOTPCRELX, R_X86_64_REX_GETPCRELX and R_386_GOT32X relocations. + (#1506004) -* Tue Feb 21 2017 Nick Clifton 2.27-4.base -- Skip the ifunc exec tests for AArch64. - (#1424705) +* Tue Oct 10 2017 Nick Clifton 2.27-18.base +- Update AArch64 copy reloc patch. + (#1430743) -* Tue Feb 21 2017 Nick Clifton 2.27-3.base -- Fix error in linker testsuite for AArch64 target. - (#1424704) +* Mon Sep 18 2017 Nick Clifton 2.27-17.base +- Add LNIA, SCV and RFSCV instructions from Power9. + (#1356856) + +* Wed Sep 06 2017 Nick Clifton 2.27-16.base +- Fix seg-fault when stripping s390x binaries. + (#14888890) -* Tue Feb 14 2017 Nick Clifton 2.27-2.base -- Fix errors detected by Coverty. +* Wed Aug 30 2017 Nick Clifton 2.27-15.base +- Add support for creating a PT_S390_PGSTE segment in s390 binaries. + (#1485398) -* Tue Jan 17 2017 Nick Clifton 2.27-1.base -- Rebase on FSF binutils 2.27 +* Wed Aug 30 2017 Nick Clifton 2.27-14.base +- Add standards.info file to documentation distributed with the binutils package. + (#1467390) + +* Fri Aug 11 2017 Nick Clifton 2.27-12.base +- Generate an error when attempting to link non-PIC s390 objects in PIE mode. + (#1406430) + +* Fri Aug 11 2017 Nick Clifton 2.27-11.base +- Fix generation of dynamic COPY relocs for the AArch64. + (#1452170) + +* Wed Aug 09 2017 Nick Clifton 2.27-10.base +- Rebase to binutils 2.27 + Retire: binutils-2.20.51.0.2-ia64-lib64.patch + Retire: binutils-2.20.51.0.10-copy-osabi.patch + Retire: binutils-rh1260158.patch @@ -677,59 +949,85 @@ exit 0 + Retire: binutils-2.25.1-aarch64-arch-extension.patch + Retire: binutils-2.25.1-s390-z13.patch + Retire: binutils-2.25.1-gold-resolving-to-hidden-symbols.patch -- Import Power9 bug fixes from FSF mainline. - (#1356856) - -* Mon Jan 16 2017 Nick Clifton 2.25.1-26.base +- Sync with Pegas 1.1 binutils. +- Import patch to add support for DWARF5 tags. + (#1472955) +- Import patch to fix converting addresses into function names. + (#1465318)(#1452170) +- Add support for ARMv8.2 ISA extensions. + (#1385959) + +* Tue Jul 25 2017 Nick Clifton 2.25.1-33.base +- Add support for new tags defined by version 5 of the DWARF standard. + (#1472955) + +* Tue Jul 25 2017 Nick Clifton 2.25.1-32.base +- Remove the minmax part of the objdump speedup patch. + (#1465318) + +* Tue May 09 2017 Nick Clifton 2.25.1-31.base +- Fix generation of PLT entries for s390 binaries. + (#1440168) + +* Thu May 04 2017 Nick Clifton 2.25.1-28-base +- Disable fix for 1406430. It breaks building real s390 executables. + (#1447209) + (#1406430) + +* Thu Apr 27 2017 Nick Clifton 2.25.1-27-base +- Fix infnite loop in linker when counting PowerPC stubs. + (#1406498) + +* Mon Jan 16 2017 Nick Clifton 2.25.1-26-base - Speed up displaying disassembly when mixed with source code. - (#1366052) - -* Mon Jan 16 2017 Nick Clifton 2.25.1-25.base + (#1311352) + +* Mon Jan 16 2017 Nick Clifton 2.25.1-25-base - Fix GOLD so that it will not warn about references to hidden symbols in shared objects. (#1326710) -* Fri Jan 06 2017 Nick Clifton 2.25.1-24.base +* Fri Jan 06 2017 Nick Clifton 2.25.1-24-base - Fix thinko in previous patch. (#1406430) -* Fri Jan 06 2017 Nick Clifton 2.25.1-23.base +* Fri Jan 06 2017 Nick Clifton 2.25.1-23-base - Add code to detect attempts to link PIE and non-PIE S390 binaries. (#1406430) -* Mon Aug 08 2016 Nick Clifton 2.25.1-22.base +* Mon Aug 08 2016 Nick Clifton 2.25.1-22-base - Fix date format bug in changelog which was preventing package build. -* Mon Aug 08 2016 Nick Clifton 2.25.1-21.base +* Mon Aug 08 2016 Nick Clifton 2.25.1-21-base - Add support for Z13 extensions to IBMs s390 architecture. (#1364516) -* Fri Jun 24 2016 Nick Clifton 2.25.1-20.base +* Fri Jun 24 2016 Nick Clifton 2.25.1-20-base - Import new PPC ISA 3.0 patch from FSF binutils. (#1341730) -* Mon Jun 13 2016 Nick Clifton 2.25.1-19.base +* Mon Jun 13 2016 Nick Clifton 2.25.1-19-base - Add support for the .arch_extension pseudo-op to the AArch64 port of GAS. (#1276755) -* Mon Jun 13 2016 Nick Clifton 2.25.1-18.base +* Mon Jun 13 2016 Nick Clifton 2.25.1-18-base - Update patch to fix AArch64 stub generation. (#1243559) -* Thu Jun 02 2016 Nick Clifton 2.25.1-17.base +* Thu Jun 02 2016 Nick Clifton 2.25.1-17-base - Close memory leak in "ar" archiver program. (#1162655) - Retire the copy-osabi patch. (#1252066) -* Thu Jun 02 2016 Nick Clifton 2.25.1-16.base +* Thu Jun 02 2016 Nick Clifton 2.25.1-16-base - Version bump to allow adding 1300543 to the errata. (#1300543) - -* Wed Jun 01 2016 Nick Clifton 2.25.1-15.base + +* Wed Jun 01 2016 Nick Clifton 2.25.1-15-base - Extend Power9 patch to add new ISA 3.0 instructions. (#1341730) - -* Wed May 25 2016 Nick Clifton 2.25.1-14.base + +* Wed May 25 2016 Nick Clifton 2.25.1-14-base - Extend Release string to include ".base" thus ensuring that it will not collide with a DTS release which might otherwise have the same name. @@ -907,7 +1205,7 @@ exit 0 (#1140375) * Wed Aug 27 2014 Jeff Law - 2.23.52.0.1-25.9 - Revert this change (handled elsewhere): + Revert this change (handled elsewhere): - Additional patch from Alan to fix problems with ld --defsym. (#1132732) @@ -1115,10 +1413,8 @@ exit 0 * Fri Apr 27 2012 Nick Clifton - 2.22.52.0.1-12 - Include demangle.h in the devel rpm. -%if 0%{?rhel} >= 7 * Tue Apr 03 2012 Nick Clifton - 2.22.52.0.1-11 - Enable -zrelro by default for RHEL 7+. (#807831) -%endif * Fri Mar 16 2012 Jakub Jelinek - 2.22.52.0.1-10 - Fix up handling of hidden ifunc relocs on i?86 @@ -1130,10 +1426,8 @@ exit 0 - Fix up handling of hidden ifunc relocs on x86_64 - Add Intel TSX support -%if 0%{?fedora} >= 18 * Tue Mar 06 2012 Nick Clifton - 2.22.52.0.1-7 - Enable -zrelro by default. (#621983 #807831) -%endif * Mon Feb 27 2012 Jeff Law - 2.22.52.0.1-6 - Fix c++filt docs (#797752) @@ -1155,7 +1449,7 @@ exit 0 - Remove build-id.patch and gold-casts.patch as they are included in the 2.22.52 sources. * Fri Jan 13 2012 Nick Clifton - 2.22-4 -- Fix bug in GOLD sources parsing signed integers in command line options. +- Fix bug in GOLD sources parsing signed integers in command line options. * Fri Jan 13 2012 Nick Clifton - 2.22-3 - Add casts for building gold with 4.7 version of gcc. @@ -1248,7 +1542,7 @@ exit 0 * Tue Aug 10 2010 Nick Clifton - 2.20.51.0.10-1 - Rebase on 2.20.51.0.10 tarball. -- Import GOLD sources from binutils mainline as of 10 Aug 2010. +- Import GOLD sources from binutils mainline as of 10 Aug 2010. * Wed Jun 30 2010 Nick Clifton - 2.20.51.0.7-5 - Rename the binutils-static package to binutils-devel in line with the Fedora packaging guidelines.