From d570a8a31067a51dfe112eb4009de0cb42e06d7d Mon Sep 17 00:00:00 2001 From: CentOS Sources Date: Nov 19 2015 03:33:40 +0000 Subject: import binutils-2.23.52.0.1-55.el7 --- diff --git a/SOURCES/bfd-ppc64le.patch b/SOURCES/bfd-ppc64le.patch new file mode 100644 index 0000000..cbf5500 --- /dev/null +++ b/SOURCES/bfd-ppc64le.patch @@ -0,0 +1,65 @@ +--- a/bfd/elf-bfd.h 2015-01-20 14:18:26.027084406 -0700 ++++ b/bfd/elf-bfd.h 2015-01-20 14:29:25.280023651 -0700 +@@ -1130,8 +1130,13 @@ + (char *); + + /* This function returns class of a reloc type. */ ++#if __PPC__ + enum elf_reloc_type_class (*elf_backend_reloc_type_class) + (const struct bfd_link_info *, const asection *, const Elf_Internal_Rela *); ++#else ++ enum elf_reloc_type_class (*elf_backend_reloc_type_class) ++ (const Elf_Internal_Rela *); ++#endif + + /* This function, if defined, removes information about discarded functions + from other sections which mention them. */ +@@ -1789,8 +1794,13 @@ + (bfd *input_bfd, struct bfd_link_info *info, asection *eh_frame_section); + + extern enum elf_reloc_type_class _bfd_elf_reloc_type_class ++#if __PPC__ + (const struct bfd_link_info *, const asection *, + const Elf_Internal_Rela *); ++#else ++ (const Elf_Internal_Rela *); ++#endif ++ + extern bfd_vma _bfd_elf_rela_local_sym + (bfd *, Elf_Internal_Sym *, asection **, Elf_Internal_Rela *); + extern bfd_vma _bfd_elf_rel_local_sym +--- a/bfd/elflink.c 2015-01-20 14:18:26.053084125 -0700 ++++ b/bfd/elflink.c 2015-01-20 14:32:18.350170081 -0700 +@@ -8496,7 +8496,11 @@ + struct elf_link_sort_rela *s = (struct elf_link_sort_rela *) p; + + (*swap_in) (abfd, erel, s->rela); ++#if __PPC__ + s->type = (*bed->elf_backend_reloc_type_class) (info, o, s->rela); ++#else ++ s->type = (*bed->elf_backend_reloc_type_class) (s->rela); ++#endif + s->u.sym_mask = r_sym_mask; + p += sort_elt; + erel += ext_size; +--- binutils-2.23.52.0.1/bfd/elf.c 2015-01-29 10:25:53.120250272 -0700 ++++ srcroot/bfd/elf.c 2015-01-29 15:53:56.300896880 -0700 +@@ -9876,10 +9876,14 @@ + return num_phdrs; + } + +-enum elf_reloc_type_class +-_bfd_elf_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED, +- const asection *rel_sec ATTRIBUTE_UNUSED, +- const Elf_Internal_Rela *rela ATTRIBUTE_UNUSED) ++extern enum elf_reloc_type_class _bfd_elf_reloc_type_class ++#if __PPC__ ++ (const struct bfd_link_info *info ATTRIBUTE_UNUSED, ++ const asection *rel_sec ATTRIBUTE_UNUSED, ++ const Elf_Internal_Rela *rela ATTRIBUTE_UNUSED) ++#else ++ (const Elf_Internal_Rela *rela ATTRIBUTE_UNUSED) ++#endif + { + return reloc_class_normal; + } diff --git a/SOURCES/binutils-2.23.52.0.1-aarch64-local-GOT-entries.patch b/SOURCES/binutils-2.23.52.0.1-aarch64-local-GOT-entries.patch new file mode 100644 index 0000000..ae0ea5e --- /dev/null +++ b/SOURCES/binutils-2.23.52.0.1-aarch64-local-GOT-entries.patch @@ -0,0 +1,114 @@ +--- binutils-2.23.52.0.1.orig/bfd/elf64-aarch64.c 2015-07-29 15:17:32.056365096 +0100 ++++ binutils-2.23.52.0.1/bfd/elf64-aarch64.c 2015-07-29 16:37:17.550432586 +0100 +@@ -3932,10 +3932,11 @@ elf64_aarch64_final_link_relocate (reloc + unsigned int r_type = howto->type; + unsigned long r_symndx; + bfd_byte *hit_data = contents + rel->r_offset; +- bfd_vma place; ++ bfd_vma place, off; + bfd_signed_vma signed_addend; + struct elf64_aarch64_link_hash_table *globals; + bfd_boolean weak_undef_p; ++ asection *base_got; + + globals = elf64_aarch64_hash_table (info); + +@@ -3971,8 +3972,6 @@ elf64_aarch64_final_link_relocate (reloc + { + asection *plt; + const char *name; +- asection *base_got; +- bfd_vma off; + + if ((input_section->flags & SEC_ALLOC) == 0 + || h->plt.offset == (bfd_vma) -1) +@@ -4326,6 +4325,58 @@ elf64_aarch64_final_link_relocate (reloc + value = aarch64_resolve_relocation (r_type, place, value, + 0, weak_undef_p); + } ++ else ++ { ++ struct elf_aarch64_local_symbol *locals ++ = elf64_aarch64_locals (input_bfd); ++ ++ if (locals == NULL) ++ { ++ (*_bfd_error_handler) ++ (_("%B: Local symbol descriptor table be NULL when applying " ++ "relocation against local symbol"), ++ input_bfd); ++ abort (); ++ } ++ ++ off = symbol_got_offset (input_bfd, h, r_symndx); ++ base_got = globals->root.sgot; ++ bfd_vma got_entry_addr = (base_got->output_section->vma ++ + base_got->output_offset + off); ++ ++ if (!symbol_got_offset_mark_p (input_bfd, h, r_symndx)) ++ { ++ bfd_put_64 (output_bfd, value, base_got->contents + off); ++ ++ if (info->shared) ++ { ++ asection *s; ++ Elf_Internal_Rela outrel; ++ ++ /* For local symbol, we have done absolute relocation in static ++ linking stageh. While for share library, we need to update ++ the content of GOT entry according to the share objects ++ loading base address. So we need to generate a ++ R_AARCH64_RELATIVE reloc for dynamic linker. */ ++ s = globals->root.srelgot; ++ if (s == NULL) ++ abort (); ++ ++ outrel.r_offset = got_entry_addr; ++ outrel.r_info = ELF64_R_INFO (0, R_AARCH64_RELATIVE); ++ outrel.r_addend = value; ++ elf_append_rela (output_bfd, s, &outrel); ++ } ++ ++ symbol_got_offset_mark (input_bfd, h, r_symndx); ++ } ++ ++ /* Update the relocation value to GOT entry addr as we have transformed ++ the direct data access into indirect data access through GOT. */ ++ value = got_entry_addr; ++ value = aarch64_resolve_relocation (r_type, place, value, ++ 0, weak_undef_p); ++ } + break; + + case R_AARCH64_TLSGD_ADR_PAGE21: +@@ -7032,7 +7083,8 @@ elf64_aarch64_size_dynamic_sections (bfd + htab->root.sgot->size += GOT_ENTRY_SIZE * 2; + } + +- if (got_type & GOT_TLS_IE) ++ if (got_type & GOT_TLS_IE ++ || got_type & GOT_NORMAL) + { + locals[i].got_offset = htab->root.sgot->size; + htab->root.sgot->size += GOT_ENTRY_SIZE; +@@ -7042,10 +7094,6 @@ elf64_aarch64_size_dynamic_sections (bfd + { + } + +- if (got_type == GOT_NORMAL) +- { +- } +- + if (info->shared) + { + if (got_type & GOT_TLSDESC_GD) +@@ -7058,7 +7106,8 @@ elf64_aarch64_size_dynamic_sections (bfd + if (got_type & GOT_TLS_GD) + htab->root.srelgot->size += RELOC_SIZE (htab) * 2; + +- if (got_type & GOT_TLS_IE) ++ if (got_type & GOT_TLS_IE ++ || got_type & GOT_NORMAL) + htab->root.srelgot->size += RELOC_SIZE (htab); + } + } diff --git a/SOURCES/binutils-ppc64le-1.1.patch b/SOURCES/binutils-ppc64le-1.1.patch new file mode 100644 index 0000000..f2eafd9 --- /dev/null +++ b/SOURCES/binutils-ppc64le-1.1.patch @@ -0,0 +1,598 @@ +--- a/gold/powerpc.cc 2015-01-09 12:22:41.336190605 -0700 ++++ b/gold/powerpc.cc 2015-01-09 12:25:12.129711802 -0700 +@@ -72,19 +72,12 @@ public: + const typename elfcpp::Ehdr& ehdr) + : Sized_relobj_file(name, input_file, offset, ehdr), + special_(0), has_small_toc_reloc_(false), opd_valid_(false), +- opd_ent_(), access_from_map_(), has14_(), stub_table_(), +- e_flags_(ehdr.get_e_flags()), st_other_() +- { +- this->set_abiversion(0); +- } ++ opd_ent_(), access_from_map_(), has14_(), stub_table_() ++ { } + + ~Powerpc_relobj() + { } + +- // Read the symbols then set up st_other vector. +- void +- do_read_symbols(Read_symbols_data*); +- + // The .got2 section shndx. + unsigned int + got2_shndx() const +@@ -270,22 +263,6 @@ public: + return NULL; + } + +- int +- abiversion() const +- { return this->e_flags_ & elfcpp::EF_PPC64_ABI; } +- +- // Set ABI version for input and output +- void +- set_abiversion(int ver); +- +- unsigned int +- ppc64_local_entry_offset(const Symbol* sym) const +- { return elfcpp::ppc64_decode_local_entry(sym->nonvis() >> 3); } +- +- unsigned int +- ppc64_local_entry_offset(unsigned int symndx) const +- { return elfcpp::ppc64_decode_local_entry(this->st_other_[symndx] >> 5); } +- + private: + struct Opd_ent + { +@@ -339,12 +316,6 @@ private: + + // The stub table to use for a given input section. + std::vector*> stub_table_; +- +- // Header e_flags +- elfcpp::Elf_Word e_flags_; +- +- // ELF st_other field for local symbols. +- std::vector st_other_; + }; + + template +@@ -1334,14 +1305,6 @@ public: + STATUS_OVERFLOW + }; + +- int +- abiversion() const +- { return this->e_flags_ & elfcpp::EF_PPC64_ABI; } +- +- // Set ABI version for input and output. +- void +- set_abiversion(int ver); +- + private: + typedef Powerpc_relocate_functions This; + typedef typename elfcpp::Elf_types::Elf_Addr Address; +@@ -1967,24 +1930,6 @@ class Stub_control + output_section() + { return output_section_; } + +- int +- abiversion () const +- { return this->processor_specific_flags() & elfcpp::EF_PPC64_ABI; } +- +- void +- set_abiversion (int ver) +- { +- elfcpp::Elf_Word flags = this->processor_specific_flags(); +- flags &= ~elfcpp::EF_PPC64_ABI; +- flags |= ver & elfcpp::EF_PPC64_ABI; +- this->set_processor_specific_flags(flags); +- } +- +- // Offset to to save stack slot +- int +- stk_toc () const +- { return this->abiversion() < 2 ? 40 : 24; } +- + private: + typedef enum + { +@@ -3660,26 +3605,6 @@ Stub_table::do_write(O + } + } + } +- else +- { +- // Define .TOC. as for 32-bit _GLOBAL_OFFSET_TABLE_ +- Symbol *gotsym = symtab->lookup(".TOC.", NULL); +- if (gotsym != NULL && gotsym->is_undefined()) +- { +- Target_powerpc* target = +- static_cast*>( +- parameters->sized_target()); +- Output_data_got_powerpc* got +- = target->got_section(symtab, layout); +- symtab->define_in_output_data(".TOC.", NULL, +- Symbol_table::PREDEFINED, +- got, 0x8000, 0, +- elfcpp::STT_OBJECT, +- elfcpp::STB_LOCAL, +- elfcpp::STV_HIDDEN, 0, +- false, false); +- } +- } + } + + // Write out .glink. +@@ -3707,34 +3632,16 @@ Output_data_glink::do_ + + elfcpp::Swap<64, big_endian>::writeval(p, pltoff), p += 8; + +- if (this->targ_->abiversion() < 2) +- { +- write_insn(p, mflr_12), p += 4; +- write_insn(p, bcl_20_31), p += 4; +- write_insn(p, mflr_11), p += 4; +- write_insn(p, ld_2_11 + l(-16)), p += 4; +- write_insn(p, mtlr_12), p += 4; +- write_insn(p, add_11_2_11), p += 4; +- write_insn(p, ld_12_11 + 0), p += 4; +- write_insn(p, ld_2_11 + 8), p += 4; +- write_insn(p, mtctr_12), p += 4; +- write_insn(p, ld_11_11 + 16), p += 4; +- } +- else +- { +- write_insn(p, mflr_0), p += 4; +- write_insn(p, bcl_20_31), p += 4; +- write_insn(p, mflr_11), p += 4; +- write_insn(p, ld_2_11 + l(-16)), p += 4; +- write_insn(p, mtlr_0), p += 4; +- write_insn(p, sub_12_12_11), p += 4; +- write_insn(p, add_11_2_11), p += 4; +- write_insn(p, addi_0_12 + l(-48)), p += 4; +- write_insn(p, ld_12_11 + 0), p += 4; +- write_insn(p, srdi_0_0_2), p += 4; +- write_insn(p, mtctr_12), p += 4; +- write_insn(p, ld_11_11 + 8), p += 4; +- } ++ write_insn(p, mflr_12), p += 4; ++ write_insn(p, bcl_20_31), p += 4; ++ write_insn(p, mflr_11), p += 4; ++ write_insn(p, ld_2_11 + l(-16)), p += 4; ++ write_insn(p, mtlr_12), p += 4; ++ write_insn(p, add_12_2_11), p += 4; ++ write_insn(p, ld_11_12 + 0), p += 4; ++ write_insn(p, ld_2_12 + 8), p += 4; ++ write_insn(p, mtctr_11), p += 4; ++ write_insn(p, ld_11_12 + 16), p += 4; + write_insn(p, bctr), p += 4; + while (p < oview + this->pltresolve_size) + write_insn(p, nop), p += 4; +@@ -3743,17 +3650,14 @@ Output_data_glink::do_ + uint32_t indx = 0; + while (p < oview + oview_size) + { +- if (this->targ_->abiversion() < 2) ++ if (indx < 0x8000) + { +- if (indx < 0x8000) +- { +- write_insn(p, li_0_0 + indx), p += 4; +- } +- else +- { +- write_insn(p, lis_0_0 + hi(indx)), p += 4; +- write_insn(p, ori_0_0_0 + l(indx)), p += 4; +- } ++ write_insn(p, li_0_0 + indx), p += 4; ++ } ++ else ++ { ++ write_insn(p, lis_0_0 + hi(indx)), p += 4; ++ write_insn(p, ori_0_0_0 + l(indx)), p += 4; + } + uint32_t branch_off = 8 - (p - oview); + write_insn(p, b + (branch_off & 0x3fffffc)), p += 4; +@@ -4240,6 +4144,24 @@ Target_powerpc::plt_en + return count; + } + ++// Return the offset of the first non-reserved PLT entry. ++ ++template ++unsigned int ++Target_powerpc::first_plt_entry_offset() const ++{ ++ return this->plt_->first_plt_entry_offset(); ++} ++ ++// Return the size of each PLT entry. ++ ++template ++unsigned int ++Target_powerpc::plt_entry_size() const ++{ ++ return Output_data_plt_powerpc::get_plt_entry_size(); ++} ++ + // Create a GOT entry for local dynamic __tls_get_addr calls. + + template +@@ -4267,12 +4189,8 @@ Target_powerpc::tlsld_ + + template + int +-Target_powerpc::Scan::get_reference_flags( +- unsigned int r_type, +- const Target_powerpc* target) ++Target_powerpc::Scan::get_reference_flags(unsigned int r_type) + { +- int ref = 0; +- + switch (r_type) + { + case elfcpp::R_POWERPC_NONE: +@@ -4280,7 +4198,7 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_GNU_VTENTRY: + case elfcpp::R_PPC64_TOC: + // No symbol reference. +- break; ++ return 0; + + case elfcpp::R_PPC64_ADDR64: + case elfcpp::R_PPC64_UADDR64: +@@ -4291,15 +4209,13 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_ADDR16_LO: + case elfcpp::R_POWERPC_ADDR16_HI: + case elfcpp::R_POWERPC_ADDR16_HA: +- ref = Symbol::ABSOLUTE_REF; +- break; ++ return Symbol::ABSOLUTE_REF; + + case elfcpp::R_POWERPC_ADDR24: + case elfcpp::R_POWERPC_ADDR14: + case elfcpp::R_POWERPC_ADDR14_BRTAKEN: + case elfcpp::R_POWERPC_ADDR14_BRNTAKEN: +- ref = Symbol::FUNCTION_CALL | Symbol::ABSOLUTE_REF; +- break; ++ return Symbol::FUNCTION_CALL | Symbol::ABSOLUTE_REF; + + case elfcpp::R_PPC64_REL64: + case elfcpp::R_POWERPC_REL32: +@@ -4308,16 +4224,14 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_REL16_LO: + case elfcpp::R_POWERPC_REL16_HI: + case elfcpp::R_POWERPC_REL16_HA: +- ref = Symbol::RELATIVE_REF; +- break; ++ return Symbol::RELATIVE_REF; + + case elfcpp::R_POWERPC_REL24: + case elfcpp::R_PPC_PLTREL24: + case elfcpp::R_POWERPC_REL14: + case elfcpp::R_POWERPC_REL14_BRTAKEN: + case elfcpp::R_POWERPC_REL14_BRNTAKEN: +- ref = Symbol::FUNCTION_CALL | Symbol::RELATIVE_REF; +- break; ++ return Symbol::FUNCTION_CALL | Symbol::RELATIVE_REF; + + case elfcpp::R_POWERPC_GOT16: + case elfcpp::R_POWERPC_GOT16_LO: +@@ -4332,13 +4246,11 @@ Target_powerpc::Scan:: + case elfcpp::R_PPC64_TOC16_DS: + case elfcpp::R_PPC64_TOC16_LO_DS: + // Absolute in GOT. +- ref = Symbol::ABSOLUTE_REF; +- break; ++ return Symbol::ABSOLUTE_REF; + + case elfcpp::R_POWERPC_GOT_TPREL16: + case elfcpp::R_POWERPC_TLS: +- ref = Symbol::TLS_REF; +- break; ++ return Symbol::TLS_REF; + + case elfcpp::R_POWERPC_COPY: + case elfcpp::R_POWERPC_GLOB_DAT: +@@ -4347,12 +4259,8 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_DTPMOD: + default: + // Not expected. We will give an error later. +- break; ++ return 0; + } +- +- if (size == 64 && target->abiversion() < 2) +- ref |= Symbol::FUNC_DESC_ABI; +- return ref; + } + + // Report an unsupported relocation against a local symbol. +@@ -4423,8 +4331,6 @@ Target_powerpc::Scan:: + case elfcpp::R_PPC64_JMP_IREL: + case elfcpp::R_PPC64_ADDR16_DS: + case elfcpp::R_PPC64_ADDR16_LO_DS: +- case elfcpp::R_PPC64_ADDR16_HIGH: +- case elfcpp::R_PPC64_ADDR16_HIGHA: + case elfcpp::R_PPC64_ADDR16_HIGHER: + case elfcpp::R_PPC64_ADDR16_HIGHEST: + case elfcpp::R_PPC64_ADDR16_HIGHERA: +@@ -4433,8 +4339,6 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_ADDR30: + case elfcpp::R_PPC64_TPREL16_DS: + case elfcpp::R_PPC64_TPREL16_LO_DS: +- case elfcpp::R_PPC64_TPREL16_HIGH: +- case elfcpp::R_PPC64_TPREL16_HIGHA: + case elfcpp::R_PPC64_TPREL16_HIGHER: + case elfcpp::R_PPC64_TPREL16_HIGHEST: + case elfcpp::R_PPC64_TPREL16_HIGHERA: +@@ -4605,6 +4509,7 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_GNU_VTINHERIT: + case elfcpp::R_POWERPC_GNU_VTENTRY: + case elfcpp::R_PPC64_TOCSAVE: ++ case elfcpp::R_PPC_EMB_MRKREF: + case elfcpp::R_POWERPC_TLS: + break; + +@@ -4641,8 +4546,6 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_ADDR16_HI: + case elfcpp::R_POWERPC_ADDR16_HA: + case elfcpp::R_POWERPC_UADDR16: +- case elfcpp::R_PPC64_ADDR16_HIGH: +- case elfcpp::R_PPC64_ADDR16_HIGHA: + case elfcpp::R_PPC64_ADDR16_HIGHER: + case elfcpp::R_PPC64_ADDR16_HIGHERA: + case elfcpp::R_PPC64_ADDR16_HIGHEST: +@@ -4709,35 +4612,31 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_REL16_HI: + case elfcpp::R_POWERPC_REL16_HA: + case elfcpp::R_POWERPC_SECTOFF: +- case elfcpp::R_POWERPC_SECTOFF_LO: +- case elfcpp::R_POWERPC_SECTOFF_HI: +- case elfcpp::R_POWERPC_SECTOFF_HA: +- case elfcpp::R_PPC64_SECTOFF_DS: +- case elfcpp::R_PPC64_SECTOFF_LO_DS: + case elfcpp::R_POWERPC_TPREL16: ++ case elfcpp::R_POWERPC_DTPREL16: ++ case elfcpp::R_POWERPC_SECTOFF_LO: + case elfcpp::R_POWERPC_TPREL16_LO: ++ case elfcpp::R_POWERPC_DTPREL16_LO: ++ case elfcpp::R_POWERPC_SECTOFF_HI: + case elfcpp::R_POWERPC_TPREL16_HI: ++ case elfcpp::R_POWERPC_DTPREL16_HI: ++ case elfcpp::R_POWERPC_SECTOFF_HA: + case elfcpp::R_POWERPC_TPREL16_HA: +- case elfcpp::R_PPC64_TPREL16_DS: +- case elfcpp::R_PPC64_TPREL16_LO_DS: +- case elfcpp::R_PPC64_TPREL16_HIGH: +- case elfcpp::R_PPC64_TPREL16_HIGHA: ++ case elfcpp::R_POWERPC_DTPREL16_HA: ++ case elfcpp::R_PPC64_DTPREL16_HIGHER: + case elfcpp::R_PPC64_TPREL16_HIGHER: ++ case elfcpp::R_PPC64_DTPREL16_HIGHERA: + case elfcpp::R_PPC64_TPREL16_HIGHERA: ++ case elfcpp::R_PPC64_DTPREL16_HIGHEST: + case elfcpp::R_PPC64_TPREL16_HIGHEST: ++ case elfcpp::R_PPC64_DTPREL16_HIGHESTA: + case elfcpp::R_PPC64_TPREL16_HIGHESTA: +- case elfcpp::R_POWERPC_DTPREL16: +- case elfcpp::R_POWERPC_DTPREL16_LO: +- case elfcpp::R_POWERPC_DTPREL16_HI: +- case elfcpp::R_POWERPC_DTPREL16_HA: ++ case elfcpp::R_PPC64_TPREL16_DS: ++ case elfcpp::R_PPC64_TPREL16_LO_DS: + case elfcpp::R_PPC64_DTPREL16_DS: + case elfcpp::R_PPC64_DTPREL16_LO_DS: +- case elfcpp::R_PPC64_DTPREL16_HIGH: +- case elfcpp::R_PPC64_DTPREL16_HIGHA: +- case elfcpp::R_PPC64_DTPREL16_HIGHER: +- case elfcpp::R_PPC64_DTPREL16_HIGHERA: +- case elfcpp::R_PPC64_DTPREL16_HIGHEST: +- case elfcpp::R_PPC64_DTPREL16_HIGHESTA: ++ case elfcpp::R_PPC64_SECTOFF_DS: ++ case elfcpp::R_PPC64_SECTOFF_LO_DS: + case elfcpp::R_PPC64_TLSGD: + case elfcpp::R_PPC64_TLSLD: + break; +@@ -4971,6 +4870,7 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_GNU_VTINHERIT: + case elfcpp::R_POWERPC_GNU_VTENTRY: + case elfcpp::R_PPC_LOCAL24PC: ++ case elfcpp::R_PPC_EMB_MRKREF: + case elfcpp::R_POWERPC_TLS: + break; + +@@ -5019,8 +4919,6 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_ADDR16_HI: + case elfcpp::R_POWERPC_ADDR16_HA: + case elfcpp::R_POWERPC_UADDR16: +- case elfcpp::R_PPC64_ADDR16_HIGH: +- case elfcpp::R_PPC64_ADDR16_HIGHA: + case elfcpp::R_PPC64_ADDR16_HIGHER: + case elfcpp::R_PPC64_ADDR16_HIGHERA: + case elfcpp::R_PPC64_ADDR16_HIGHEST: +@@ -5107,7 +5005,7 @@ Target_powerpc::Scan:: + case elfcpp::R_PPC64_REL64: + case elfcpp::R_POWERPC_REL32: + // Make a dynamic relocation if necessary. +- if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type, target))) ++ if (needs_dynamic_reloc(gsym, Scan::get_reference_flags(r_type))) + { + if (gsym->may_need_copy_reloc()) + { +@@ -5139,35 +5037,31 @@ Target_powerpc::Scan:: + case elfcpp::R_POWERPC_REL16_HI: + case elfcpp::R_POWERPC_REL16_HA: + case elfcpp::R_POWERPC_SECTOFF: +- case elfcpp::R_POWERPC_SECTOFF_LO: +- case elfcpp::R_POWERPC_SECTOFF_HI: +- case elfcpp::R_POWERPC_SECTOFF_HA: +- case elfcpp::R_PPC64_SECTOFF_DS: +- case elfcpp::R_PPC64_SECTOFF_LO_DS: + case elfcpp::R_POWERPC_TPREL16: ++ case elfcpp::R_POWERPC_DTPREL16: ++ case elfcpp::R_POWERPC_SECTOFF_LO: + case elfcpp::R_POWERPC_TPREL16_LO: ++ case elfcpp::R_POWERPC_DTPREL16_LO: ++ case elfcpp::R_POWERPC_SECTOFF_HI: + case elfcpp::R_POWERPC_TPREL16_HI: ++ case elfcpp::R_POWERPC_DTPREL16_HI: ++ case elfcpp::R_POWERPC_SECTOFF_HA: + case elfcpp::R_POWERPC_TPREL16_HA: +- case elfcpp::R_PPC64_TPREL16_DS: +- case elfcpp::R_PPC64_TPREL16_LO_DS: +- case elfcpp::R_PPC64_TPREL16_HIGH: +- case elfcpp::R_PPC64_TPREL16_HIGHA: ++ case elfcpp::R_POWERPC_DTPREL16_HA: ++ case elfcpp::R_PPC64_DTPREL16_HIGHER: + case elfcpp::R_PPC64_TPREL16_HIGHER: ++ case elfcpp::R_PPC64_DTPREL16_HIGHERA: + case elfcpp::R_PPC64_TPREL16_HIGHERA: ++ case elfcpp::R_PPC64_DTPREL16_HIGHEST: + case elfcpp::R_PPC64_TPREL16_HIGHEST: ++ case elfcpp::R_PPC64_DTPREL16_HIGHESTA: + case elfcpp::R_PPC64_TPREL16_HIGHESTA: +- case elfcpp::R_POWERPC_DTPREL16: +- case elfcpp::R_POWERPC_DTPREL16_LO: +- case elfcpp::R_POWERPC_DTPREL16_HI: +- case elfcpp::R_POWERPC_DTPREL16_HA: ++ case elfcpp::R_PPC64_TPREL16_DS: ++ case elfcpp::R_PPC64_TPREL16_LO_DS: + case elfcpp::R_PPC64_DTPREL16_DS: + case elfcpp::R_PPC64_DTPREL16_LO_DS: +- case elfcpp::R_PPC64_DTPREL16_HIGH: +- case elfcpp::R_PPC64_DTPREL16_HIGHA: +- case elfcpp::R_PPC64_DTPREL16_HIGHER: +- case elfcpp::R_PPC64_DTPREL16_HIGHERA: +- case elfcpp::R_PPC64_DTPREL16_HIGHEST: +- case elfcpp::R_PPC64_DTPREL16_HIGHESTA: ++ case elfcpp::R_PPC64_SECTOFF_DS: ++ case elfcpp::R_PPC64_SECTOFF_LO_DS: + case elfcpp::R_PPC64_TLSGD: + case elfcpp::R_PPC64_TLSLD: + break; +@@ -5900,8 +5794,7 @@ Target_powerpc::Reloca + && (insn2 == nop + || insn2 == cror_15_15_15 || insn2 == cror_31_31_31)) + { +- elfcpp::Swap<32, big_endian>:: +- writeval(wv + 1, ld_2_1 + target->stk_toc()); ++ elfcpp::Swap<32, big_endian>::writeval(wv + 1, ld_2_1 + 40); + can_plt_call = true; + } + } +@@ -6190,10 +6083,6 @@ Target_powerpc::Reloca + if (r_type != elfcpp::R_PPC_PLTREL24) + addend = rela.get_r_addend(); + value = psymval->value(object, addend); +- if (gsym != NULL) +- value += object->ppc64_local_entry_offset(gsym); +- else +- value += object->ppc64_local_entry_offset(r_sym); + if (size == 64 && is_branch_reloc(r_type)) + value = target->symval_for_branch(value, gsym, object, &dest_shndx); + unsigned int max_branch_offset = 0; +@@ -6257,10 +6146,8 @@ Target_powerpc::Reloca + + case elfcpp::R_PPC64_TPREL16_DS: + case elfcpp::R_PPC64_TPREL16_LO_DS: +- case elfcpp::R_PPC64_TPREL16_HIGH: +- case elfcpp::R_PPC64_TPREL16_HIGHA: + if (size != 64) +- // R_PPC_TLSGD, R_PPC_TLSLD, R_PPC_EMB_RELST_LO, R_PPC_EMB_RELST_HI ++ // R_PPC_TLSGD and R_PPC_TLSLD + break; + case elfcpp::R_POWERPC_TPREL16: + case elfcpp::R_POWERPC_TPREL16_LO: +@@ -6290,8 +6177,6 @@ Target_powerpc::Reloca + case elfcpp::R_POWERPC_DTPREL16_HI: + case elfcpp::R_POWERPC_DTPREL16_HA: + case elfcpp::R_POWERPC_DTPREL: +- case elfcpp::R_PPC64_DTPREL16_HIGH: +- case elfcpp::R_PPC64_DTPREL16_HIGHA: + // tls symbol values are relative to tls_segment()->vaddr() + value -= dtp_offset; + break; +@@ -6432,34 +6317,6 @@ Target_powerpc::Reloca + overflow = Reloc::CHECK_BITFIELD; + break; + +- case elfcpp::R_POWERPC_ADDR16_HI: +- case elfcpp::R_POWERPC_ADDR16_HA: +- case elfcpp::R_POWERPC_GOT16_HI: +- case elfcpp::R_POWERPC_GOT16_HA: +- case elfcpp::R_POWERPC_PLT16_HI: +- case elfcpp::R_POWERPC_PLT16_HA: +- case elfcpp::R_POWERPC_SECTOFF_HI: +- case elfcpp::R_POWERPC_SECTOFF_HA: +- case elfcpp::R_PPC64_TOC16_HI: +- case elfcpp::R_PPC64_TOC16_HA: +- case elfcpp::R_PPC64_PLTGOT16_HI: +- case elfcpp::R_PPC64_PLTGOT16_HA: +- case elfcpp::R_POWERPC_TPREL16_HI: +- case elfcpp::R_POWERPC_TPREL16_HA: +- case elfcpp::R_POWERPC_DTPREL16_HI: +- case elfcpp::R_POWERPC_DTPREL16_HA: +- case elfcpp::R_POWERPC_GOT_TLSGD16_HI: +- case elfcpp::R_POWERPC_GOT_TLSGD16_HA: +- case elfcpp::R_POWERPC_GOT_TLSLD16_HI: +- case elfcpp::R_POWERPC_GOT_TLSLD16_HA: +- case elfcpp::R_POWERPC_GOT_TPREL16_HI: +- case elfcpp::R_POWERPC_GOT_TPREL16_HA: +- case elfcpp::R_POWERPC_GOT_DTPREL16_HI: +- case elfcpp::R_POWERPC_GOT_DTPREL16_HA: +- case elfcpp::R_POWERPC_REL16_HI: +- case elfcpp::R_POWERPC_REL16_HA: +- if (size == 32) +- break; + case elfcpp::R_POWERPC_REL24: + case elfcpp::R_PPC_PLTREL24: + case elfcpp::R_PPC_LOCAL24PC: +@@ -6493,6 +6350,7 @@ Target_powerpc::Reloca + case elfcpp::R_POWERPC_TLS: + case elfcpp::R_POWERPC_GNU_VTINHERIT: + case elfcpp::R_POWERPC_GNU_VTENTRY: ++ case elfcpp::R_PPC_EMB_MRKREF: + break; + + case elfcpp::R_PPC64_ADDR64: +@@ -6563,12 +6421,6 @@ Target_powerpc::Reloca + status = Reloc::addr16_u(view, value, overflow); + break; + +- case elfcpp::R_PPC64_ADDR16_HIGH: +- case elfcpp::R_PPC64_TPREL16_HIGH: +- case elfcpp::R_PPC64_DTPREL16_HIGH: +- if (size == 32) +- // R_PPC_EMB_MRKREF, R_PPC_EMB_RELST_LO, R_PPC_EMB_RELST_HA +- goto unsupp; + case elfcpp::R_POWERPC_ADDR16_HI: + case elfcpp::R_POWERPC_REL16_HI: + case elfcpp::R_PPC64_TOC16_HI: +@@ -6583,12 +6435,6 @@ Target_powerpc::Reloca + Reloc::addr16_hi(view, value); + break; + +- case elfcpp::R_PPC64_ADDR16_HIGHA: +- case elfcpp::R_PPC64_TPREL16_HIGHA: +- case elfcpp::R_PPC64_DTPREL16_HIGHA: +- if (size == 32) +- // R_PPC_EMB_RELSEC16, R_PPC_EMB_RELST_HI, R_PPC_EMB_BIT_FLD +- goto unsupp; + case elfcpp::R_POWERPC_ADDR16_HA: + case elfcpp::R_POWERPC_REL16_HA: + case elfcpp::R_PPC64_TOC16_HA: +@@ -6713,6 +6559,11 @@ Target_powerpc::Reloca + case elfcpp::R_PPC64_PLT16_LO_DS: + case elfcpp::R_PPC64_PLTGOT16_DS: + case elfcpp::R_PPC64_PLTGOT16_LO_DS: ++ case elfcpp::R_PPC_EMB_RELSEC16: ++ case elfcpp::R_PPC_EMB_RELST_LO: ++ case elfcpp::R_PPC_EMB_RELST_HI: ++ case elfcpp::R_PPC_EMB_RELST_HA: ++ case elfcpp::R_PPC_EMB_BIT_FLD: + case elfcpp::R_PPC_EMB_RELSDA: + case elfcpp::R_PPC_TOC16: + default: diff --git a/SOURCES/binutils-ppc64le-1.patch b/SOURCES/binutils-ppc64le-1.patch index 259214d..e6efb88 100644 --- a/SOURCES/binutils-ppc64le-1.patch +++ b/SOURCES/binutils-ppc64le-1.patch @@ -4023,9 +4023,9 @@ index 8d6ff30..72ef3f4 100644 -.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start +.* NOTYPE +GLOBAL +DEFAULT +13 __bss_start .* FUNC +GLOBAL +DEFAULT +UND __tls_get_addr_opt --.* NOTYPE +GLOBAL +DEFAULT +11 _edata +-.* NOTYPE +GLOBAL +DEFAULT +12 _edata -.* NOTYPE +GLOBAL +DEFAULT +12 _end -+.* NOTYPE +GLOBAL +DEFAULT +12 _edata ++.* NOTYPE +GLOBAL +DEFAULT +13 _edata +.* NOTYPE +GLOBAL +DEFAULT +13 _end Symbol table '\.symtab' contains [0-9]+ entries: @@ -4049,9 +4049,9 @@ index 8d6ff30..72ef3f4 100644 -.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start +.* NOTYPE +GLOBAL +DEFAULT +13 __bss_start .* FUNC +GLOBAL +DEFAULT +UND __tls_get_addr_opt --.* NOTYPE +GLOBAL +DEFAULT +11 _edata +-.* NOTYPE +GLOBAL +DEFAULT +12 _edata -.* NOTYPE +GLOBAL +DEFAULT +12 _end -+.* NOTYPE +GLOBAL +DEFAULT +12 _edata ++.* NOTYPE +GLOBAL +DEFAULT +13 _edata +.* NOTYPE +GLOBAL +DEFAULT +13 _end .* TLS +GLOBAL +DEFAULT +9 gd0 .* TLS +GLOBAL +DEFAULT +9 ie0 @@ -4151,9 +4151,9 @@ index 71d6c9e..e6f606b 100644 -.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start +.* NOTYPE +GLOBAL +DEFAULT +13 __bss_start .* FUNC +GLOBAL +DEFAULT +UND __tls_get_addr_opt --.* NOTYPE +GLOBAL +DEFAULT +11 _edata +-.* NOTYPE +GLOBAL +DEFAULT +12 _edata -.* NOTYPE +GLOBAL +DEFAULT +12 _end -+.* NOTYPE +GLOBAL +DEFAULT +12 _edata ++.* NOTYPE +GLOBAL +DEFAULT +13 _edata +.* NOTYPE +GLOBAL +DEFAULT +13 _end Symbol table '\.symtab' contains [0-9]+ entries: @@ -4186,9 +4186,9 @@ index 71d6c9e..e6f606b 100644 -.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start +.* NOTYPE +GLOBAL +DEFAULT +13 __bss_start .* FUNC +GLOBAL +DEFAULT +UND __tls_get_addr_opt --.* NOTYPE +GLOBAL +DEFAULT +11 _edata +-.* NOTYPE +GLOBAL +DEFAULT +12 _edata -.* NOTYPE +GLOBAL +DEFAULT +12 _end -+.* NOTYPE +GLOBAL +DEFAULT +12 _edata ++.* NOTYPE +GLOBAL +DEFAULT +13 _edata +.* NOTYPE +GLOBAL +DEFAULT +13 _end .* TLS +GLOBAL +DEFAULT +9 gd0 .* TLS +GLOBAL +DEFAULT +9 ie0 @@ -4297,10 +4297,10 @@ index fab50e0..6464be0 100644 .* TLS +GLOBAL +DEFAULT +8 ld2 .* TLS +GLOBAL +DEFAULT +8 ld1 -.* NOTYPE +GLOBAL +DEFAULT +11 __bss_start --.* NOTYPE +GLOBAL +DEFAULT +10 _edata +-.* NOTYPE +GLOBAL +DEFAULT +11 _edata -.* NOTYPE +GLOBAL +DEFAULT +11 _end +.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start -+.* NOTYPE +GLOBAL +DEFAULT +11 _edata ++.* NOTYPE +GLOBAL +DEFAULT +12 _edata +.* NOTYPE +GLOBAL +DEFAULT +12 _end .* TLS +GLOBAL +DEFAULT +8 gd0 .* TLS +GLOBAL +DEFAULT +8 ie0 @@ -4322,10 +4322,10 @@ index fab50e0..6464be0 100644 .* TLS +GLOBAL +DEFAULT +8 ld2 .* TLS +GLOBAL +DEFAULT +8 ld1 -.* NOTYPE +GLOBAL +DEFAULT +11 __bss_start --.* NOTYPE +GLOBAL +DEFAULT +10 _edata +-.* NOTYPE +GLOBAL +DEFAULT +11 _edata -.* NOTYPE +GLOBAL +DEFAULT +11 _end +.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start -+.* NOTYPE +GLOBAL +DEFAULT +11 _edata ++.* NOTYPE +GLOBAL +DEFAULT +12 _edata +.* NOTYPE +GLOBAL +DEFAULT +12 _end .* TLS +GLOBAL +DEFAULT +8 gd0 .* TLS +GLOBAL +DEFAULT +8 ie0 @@ -4471,10 +4471,10 @@ index 1ec8b63..f397915 100644 .* TLS +GLOBAL +DEFAULT +8 ld2 .* TLS +GLOBAL +DEFAULT +8 ld1 -.* NOTYPE +GLOBAL +DEFAULT +11 __bss_start --.* NOTYPE +GLOBAL +DEFAULT +10 _edata +-.* NOTYPE +GLOBAL +DEFAULT +11 _edata -.* NOTYPE +GLOBAL +DEFAULT +11 _end +.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start -+.* NOTYPE +GLOBAL +DEFAULT +11 _edata ++.* NOTYPE +GLOBAL +DEFAULT +12 _edata +.* NOTYPE +GLOBAL +DEFAULT +12 _end .* TLS +GLOBAL +DEFAULT +8 gd0 .* TLS +GLOBAL +DEFAULT +8 ie0 @@ -4505,10 +4505,10 @@ index 1ec8b63..f397915 100644 .* TLS +GLOBAL +DEFAULT +8 ld2 .* TLS +GLOBAL +DEFAULT +8 ld1 -.* NOTYPE +GLOBAL +DEFAULT +11 __bss_start --.* NOTYPE +GLOBAL +DEFAULT +10 _edata +-.* NOTYPE +GLOBAL +DEFAULT +11 _edata -.* NOTYPE +GLOBAL +DEFAULT +11 _end +.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start -+.* NOTYPE +GLOBAL +DEFAULT +11 _edata ++.* NOTYPE +GLOBAL +DEFAULT +12 _edata +.* NOTYPE +GLOBAL +DEFAULT +12 _end .* TLS +GLOBAL +DEFAULT +8 gd0 .* TLS +GLOBAL +DEFAULT +8 ie0 diff --git a/SOURCES/binutils-rh1060282.patch b/SOURCES/binutils-rh1060282.patch new file mode 100644 index 0000000..4d86dd7 --- /dev/null +++ b/SOURCES/binutils-rh1060282.patch @@ -0,0 +1,365 @@ +diff -Nrup a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi +--- a/binutils/doc/binutils.texi 2013-02-27 13:28:03.000000000 -0700 ++++ b/binutils/doc/binutils.texi 2015-06-23 09:44:23.938269022 -0600 +@@ -1957,6 +1957,15 @@ expected to contain instructions. + Like @option{-d}, but disassemble the contents of all sections, not just + those expected to contain instructions. + ++This option also has a subtle effect on the disassembly of ++instructions in code sections. When option @option{-d} is in effect ++objdump will assume that any symbols present in a code section occur ++on the boundary between instructions and it will refuse to disassemble ++across such a boundary. When option @option{-D} is in effect however ++this assumption is supressed. This means that it is possible for the ++output of @option{-d} and @option{-D} to differ if, for example, data ++is stored in code sections. ++ + If the target is an ARM architecture this switch also has the effect + of forcing the disassembler to decode pieces of data found in code + sections as if they were instructions. +diff -Nrup a/binutils/objdump.c b/binutils/objdump.c +--- a/binutils/objdump.c 2015-06-23 07:38:21.000000000 -0600 ++++ b/binutils/objdump.c 2015-06-23 09:44:23.939269001 -0600 +@@ -1667,7 +1667,18 @@ disassemble_bytes (struct disassemble_in + } + } + ++ if (! disassemble_all ++ && (section->flags & (SEC_CODE | SEC_HAS_CONTENTS)) ++ == (SEC_CODE | SEC_HAS_CONTENTS)) ++ /* Set a stop_vma so that the disassembler will not read ++ beyond the next symbol. We assume that symbols appear on ++ the boundaries between instructions. We only do this when ++ disassembling code of course, and when -D is in effect. */ ++ inf->stop_vma = section->vma + stop_offset; ++ + octets = (*disassemble_fn) (section->vma + addr_offset, inf); ++ ++ inf->stop_vma = 0; + inf->fprintf_func = (fprintf_ftype) fprintf; + inf->stream = stdout; + if (insn_width == 0 && inf->bytes_per_line != 0) +@@ -1893,7 +1904,7 @@ disassemble_section (bfd *abfd, asection + arelent ** rel_pp = NULL; + arelent ** rel_ppstart = NULL; + arelent ** rel_ppend; +- unsigned long stop_offset; ++ bfd_vma stop_offset; + asymbol * sym = NULL; + long place = 0; + long rel_count; +@@ -2015,7 +2026,7 @@ disassemble_section (bfd *abfd, asection + { + bfd_vma addr; + asymbol *nextsym; +- unsigned long nextstop_offset; ++ bfd_vma nextstop_offset; + bfd_boolean insns; + + addr = section->vma + addr_offset; +@@ -2703,9 +2714,9 @@ dump_section (bfd *abfd, asection *secti + { + bfd_byte *data = 0; + bfd_size_type datasize; +- bfd_size_type addr_offset; +- bfd_size_type start_offset; +- bfd_size_type stop_offset; ++ bfd_vma addr_offset; ++ bfd_vma start_offset; ++ bfd_vma stop_offset; + unsigned int opb = bfd_octets_per_byte (abfd); + /* Bytes per line. */ + const int onaline = 16; +diff -Nrup a/gas/testsuite/gas/arm/backslash-at.d b/gas/testsuite/gas/arm/backslash-at.d +--- a/gas/testsuite/gas/arm/backslash-at.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/arm/backslash-at.d 2015-06-23 09:51:10.167721356 -0600 +@@ -5,13 +5,13 @@ + + Disassembly of section .text: + 0+000 <.*>.*615c.* +-0+002 e3a00000 mov r0, #0 +-0+006 e3a00000 mov r0, #0 +-0+00a e3a00000 mov r0, #0 +-0+00e e3a00001 mov r0, #1 +-0+012 e3a00001 mov r0, #1 +-0+016 e3a00001 mov r0, #1 +-0+01a e3a00002 mov r0, #2 +-0+01e e3a00002 mov r0, #2 +-0+022 e3a00002 mov r0, #2 ++0+004 e3a00000 mov r0, #0 ++0+008 e3a00000 mov r0, #0 ++0+00c e3a00000 mov r0, #0 ++0+010 e3a00001 mov r0, #1 ++0+014 e3a00001 mov r0, #1 ++0+018 e3a00001 mov r0, #1 ++0+01c e3a00002 mov r0, #2 ++0+020 e3a00002 mov r0, #2 ++0+024 e3a00002 mov r0, #2 + #... +Binary files a/gas/testsuite/gas/arm/.backslash-at.d.rej.swp and b/gas/testsuite/gas/arm/.backslash-at.d.rej.swp differ +diff -Nrup a/gas/testsuite/gas/arm/backslash-at.s b/gas/testsuite/gas/arm/backslash-at.s +--- a/gas/testsuite/gas/arm/backslash-at.s 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/arm/backslash-at.s 2015-06-23 09:44:23.939269001 -0600 +@@ -6,9 +6,10 @@ + mov r0, #\@ @comment + .endm + +-.byte '\\ +-.byte '\a +- ++ .byte '\\ ++ .byte '\a ++ .byte 0 ++ .byte 0 + foo: + bar + bar +diff -Nrup a/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval.d b/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval.d +--- a/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval.d 2015-06-23 09:44:23.940268980 -0600 +@@ -12,26 +12,26 @@ Disassembly of section .text: + + 0+1 : + [ ]*[a-f0-9]+: d5 \(bad\) +-[ ]*[a-f0-9]+: 0a d5 or %ch,%dl ++[ ]*[a-f0-9]+: 0a .byte 0xa + + 0+3 : + [ ]*[a-f0-9]+: d5 \(bad\) +-[ ]*[a-f0-9]+: 02 d4 add %ah,%dl ++[ ]*[a-f0-9]+: 02 .byte 0x2 + + 0+5 : + [ ]*[a-f0-9]+: d4 \(bad\) +-[ ]*[a-f0-9]+: 0a d4 or %ah,%dl ++[ ]*[a-f0-9]+: 0a .byte 0xa + + 0+7 : + [ ]*[a-f0-9]+: d4 \(bad\) +-[ ]*[a-f0-9]+: 02 3f add \(%rdi\),%bh ++[ ]*[a-f0-9]+: 02 .byte 0x2 + + 0+9 : + [ ]*[a-f0-9]+: 3f \(bad\) + + 0+a : +-[ ]*[a-f0-9]+: 62 \(bad\) +-[ ]*[a-f0-9]+: 10 27 adc %ah,\(%rdi\) ++[ ]*[a-f0-9]+: 62 .byte 0x62 ++[ ]*[a-f0-9]+: 10 .byte 0x10 + + 0+c : + [ ]*[a-f0-9]+: 27 \(bad\) +diff -Nrup a/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d b/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d +--- a/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d 2015-06-23 09:44:23.939269001 -0600 +@@ -12,26 +12,26 @@ Disassembly of section .text: + + 0+1 : + [ ]*[a-f0-9]+: d5 \(bad\) +-[ ]*[a-f0-9]+: 0a d5 or dl,ch ++[ ]*[a-f0-9]+: 0a .byte 0xa + + 0+3 : + [ ]*[a-f0-9]+: d5 \(bad\) +-[ ]*[a-f0-9]+: 02 d4 add dl,ah ++[ ]*[a-f0-9]+: 02 .byte 0x2 + + 0+5 : + [ ]*[a-f0-9]+: d4 \(bad\) +-[ ]*[a-f0-9]+: 0a d4 or dl,ah ++[ ]*[a-f0-9]+: 0a .byte 0xa + + 0+7 : + [ ]*[a-f0-9]+: d4 \(bad\) +-[ ]*[a-f0-9]+: 02 3f add bh,BYTE PTR \[rdi\] ++[ ]*[a-f0-9]+: 02 .byte 0x2 + + 0+9 : + [ ]*[a-f0-9]+: 3f \(bad\) + + 0+a : +-[ ]*[a-f0-9]+: 62 \(bad\) +-[ ]*[a-f0-9]+: 10 27 adc BYTE PTR \[rdi\],ah ++[ ]*[a-f0-9]+: 62 .byte 0x62 ++[ ]*[a-f0-9]+: 10 .byte 0x10 + + 0+c : + [ ]*[a-f0-9]+: 27 \(bad\) +diff -Nrup a/gas/testsuite/gas/i386/x86-64-opcode-inval.d b/gas/testsuite/gas/i386/x86-64-opcode-inval.d +--- a/gas/testsuite/gas/i386/x86-64-opcode-inval.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/i386/x86-64-opcode-inval.d 2015-06-23 09:44:23.940268980 -0600 +@@ -11,26 +11,26 @@ Disassembly of section .text: + + 0+1 : + [ ]*[a-f0-9]+: d5 \(bad\) +-[ ]*[a-f0-9]+: 0a d5 or %ch,%dl ++[ ]*[a-f0-9]+: 0a .byte 0xa + + 0+3 : + [ ]*[a-f0-9]+: d5 \(bad\) +-[ ]*[a-f0-9]+: 02 d4 add %ah,%dl ++[ ]*[a-f0-9]+: 02 .byte 0x2 + + 0+5 : + [ ]*[a-f0-9]+: d4 \(bad\) +-[ ]*[a-f0-9]+: 0a d4 or %ah,%dl ++[ ]*[a-f0-9]+: 0a .byte 0xa + + 0+7 : + [ ]*[a-f0-9]+: d4 \(bad\) +-[ ]*[a-f0-9]+: 02 3f add \(%rdi\),%bh ++[ ]*[a-f0-9]+: 02 .byte 0x2 + + 0+9 : + [ ]*[a-f0-9]+: 3f \(bad\) + + 0+a : +-[ ]*[a-f0-9]+: 62 \(bad\) +-[ ]*[a-f0-9]+: 10 27 adc %ah,\(%rdi\) ++[ ]*[a-f0-9]+: 62 .byte 0x62 ++[ ]*[a-f0-9]+: 10 .byte 0x10 + + 0+c : + [ ]*[a-f0-9]+: 27 \(bad\) +diff -Nrup a/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d b/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d +--- a/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d 2015-06-23 09:44:23.940268980 -0600 +@@ -12,26 +12,26 @@ Disassembly of section .text: + + 0+1 : + [ ]*[a-f0-9]+: d5 \(bad\) +-[ ]*[a-f0-9]+: 0a d5 or dl,ch ++[ ]*[a-f0-9]+: 0a .byte 0xa + + 0+3 : + [ ]*[a-f0-9]+: d5 \(bad\) +-[ ]*[a-f0-9]+: 02 d4 add dl,ah ++[ ]*[a-f0-9]+: 02 .byte 0x2 + + 0+5 : + [ ]*[a-f0-9]+: d4 \(bad\) +-[ ]*[a-f0-9]+: 0a d4 or dl,ah ++[ ]*[a-f0-9]+: 0a .byte 0xa + + 0+7 : + [ ]*[a-f0-9]+: d4 \(bad\) +-[ ]*[a-f0-9]+: 02 3f add bh,BYTE PTR \[rdi\] ++[ ]*[a-f0-9]+: 02 .byte 0x2 + + 0+9 : + [ ]*[a-f0-9]+: 3f \(bad\) + + 0+a : +-[ ]*[a-f0-9]+: 62 \(bad\) +-[ ]*[a-f0-9]+: 10 27 adc BYTE PTR \[rdi\],ah ++[ ]*[a-f0-9]+: 62 .byte 0x62 ++[ ]*[a-f0-9]+: 10 .byte 0x10 + + 0+c : + [ ]*[a-f0-9]+: 27 \(bad\) +diff -Nrup a/include/dis-asm.h b/include/dis-asm.h +--- a/include/dis-asm.h 2013-02-27 13:28:03.000000000 -0700 ++++ b/include/dis-asm.h 2015-06-23 09:44:23.940268980 -0600 +@@ -213,6 +213,14 @@ typedef struct disassemble_info + /* Command line options specific to the target disassembler. */ + char * disassembler_options; + ++ /* If non-zero then try not disassemble beyond this address, even if ++ there are values left in the buffer. This address is the address ++ of the nearest symbol forwards from the start of the disassembly, ++ and it is assumed that it lies on the boundary between instructions. ++ If an instruction spans this address then this is an error in the ++ file being disassembled. */ ++ bfd_vma stop_vma; ++ + } disassemble_info; + + +diff -Nrup a/opcodes/dis-buf.c b/opcodes/dis-buf.c +--- a/opcodes/dis-buf.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/opcodes/dis-buf.c 2015-06-23 09:44:23.941268959 -0600 +@@ -39,7 +39,9 @@ buffer_read_memory (bfd_vma memaddr, + + if (memaddr < info->buffer_vma + || memaddr - info->buffer_vma > max_addr_offset +- || memaddr - info->buffer_vma + end_addr_offset > max_addr_offset) ++ || memaddr - info->buffer_vma + end_addr_offset > max_addr_offset ++ || (info->stop_vma && (memaddr >= info->stop_vma ++ || memaddr + end_addr_offset > info->stop_vma))) + /* Out of bounds. Use EIO because GDB uses it. */ + return EIO; + memcpy (myaddr, info->buffer + octets, length); +diff -Nrup a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c +--- a/opcodes/mcore-dis.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/opcodes/mcore-dis.c 2015-06-23 09:44:23.941268959 -0600 +@@ -89,9 +89,8 @@ static const char *crname[] = { + static const unsigned isiz[] = { 2, 0, 1, 0 }; + + int +-print_insn_mcore (memaddr, info) +- bfd_vma memaddr; +- struct disassemble_info *info; ++print_insn_mcore (bfd_vma memaddr, ++ struct disassemble_info *info) + { + unsigned char ibytes[4]; + fprintf_ftype print_func = info->fprintf_func; +@@ -234,6 +233,9 @@ print_insn_mcore (memaddr, info) + + val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC; + ++ /* We are not reading an instruction, so allow ++ reads to extend beyond the next symbol. */ ++ info->stop_vma = 0; + status = info->read_memory_func (val, ibytes, 4, info); + if (status != 0) + { +@@ -264,6 +266,9 @@ print_insn_mcore (memaddr, info) + + val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC; + ++ /* We are not reading an instruction, so allow ++ reads to extend beyond the next symbol. */ ++ info->stop_vma = 0; + status = info->read_memory_func (val, ibytes, 4, info); + if (status != 0) + { +diff -Nrup a/opcodes/sh-dis.c b/opcodes/sh-dis.c +--- a/opcodes/sh-dis.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/opcodes/sh-dis.c 2015-06-23 09:44:23.941268959 -0600 +@@ -906,6 +906,8 @@ print_insn_sh (bfd_vma memaddr, struct d + size = 2; + else + size = 4; ++ /* Not reading an instruction - disable stop_vma. */ ++ info->stop_vma = 0; + status = info->read_memory_func (disp_pc_addr, bytes, size, info); + if (status == 0) + { +diff -Nrup a/opcodes/tic6x-dis.c b/opcodes/tic6x-dis.c +--- a/opcodes/tic6x-dis.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/opcodes/tic6x-dis.c 2015-06-23 09:44:23.941268959 -0600 +@@ -178,6 +178,9 @@ print_insn_tic6x (bfd_vma addr, struct d + + fp_offset = addr & 0x1f; + fp_addr = addr - fp_offset; ++ /* Read in a block of instructions. Since there might be a ++ symbol in the middle of this block, disable stop_vma. */ ++ info->stop_vma = 0; + status = info->read_memory_func (fp_addr, fp, 32, info); + if (status) + { +diff -Nrup a/opcodes/vax-dis.c b/opcodes/vax-dis.c +--- a/opcodes/vax-dis.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/opcodes/vax-dis.c 2015-06-23 09:44:23.941268959 -0600 +@@ -403,7 +403,8 @@ print_insn_vax (bfd_vma memaddr, disasse + argp = NULL; + /* Check if the info buffer has more than one byte left since + the last opcode might be a single byte with no argument data. */ +- if (info->buffer_length - (memaddr - info->buffer_vma) > 1) ++ if (info->buffer_length - (memaddr - info->buffer_vma) > 1 ++ && (info->stop_vma == 0 || memaddr < (info->stop_vma - 1))) + { + FETCH_DATA (info, buffer + 2); + } diff --git a/SOURCES/binutils-rh1157276.patch b/SOURCES/binutils-rh1157276.patch new file mode 100644 index 0000000..b887c7c --- /dev/null +++ b/SOURCES/binutils-rh1157276.patch @@ -0,0 +1,296 @@ +diff -rup binutils-2.23.52.0.1.orig/binutils/config.in binutils-2.23.52.0.1/binutils/config.in +--- binutils-2.23.52.0.1.orig/binutils/config.in 2015-06-29 11:32:47.721653986 +0100 ++++ binutils-2.23.52.0.1/binutils/config.in 2015-06-29 11:35:48.377753127 +0100 +@@ -18,6 +18,9 @@ + /* Should ar and ranlib use -D behavior by default? */ + #undef DEFAULT_AR_DETERMINISTIC + ++/* Should strings use -a behavior by default? */ ++#undef DEFAULT_STRINGS_ALL ++ + /* Define to 1 if translation of program messages to the user's native + language is requested. */ + #undef ENABLE_NLS +diff -rup binutils-2.23.52.0.1.orig/binutils/configure binutils-2.23.52.0.1/binutils/configure +--- binutils-2.23.52.0.1.orig/binutils/configure 2015-06-29 11:32:47.699653852 +0100 ++++ binutils-2.23.52.0.1/binutils/configure 2015-06-29 11:36:53.932149340 +0100 +@@ -772,6 +772,7 @@ with_gnu_ld + enable_libtool_lock + enable_targets + enable_deterministic_archives ++enable_default_strings_all + enable_werror + enable_build_warnings + enable_nls +@@ -1421,6 +1422,8 @@ Optional Features: + --enable-targets alternative target configurations + --enable-deterministic-archives + ar and ranlib default to -D behavior ++ --disable-default-strings-all ++ strings defaults to --data behavior + --enable-werror treat compile warnings as errors + --enable-build-warnings enable build-time compiler warnings + --disable-nls do not use Native Language Support +@@ -11602,13 +11605,27 @@ else + default_ar_deterministic=0 + fi + +- +- + cat >>confdefs.h <<_ACEOF + #define DEFAULT_AR_DETERMINISTIC $default_ar_deterministic + _ACEOF + + ++# Check whether --enable-default-strings-all was given. ++if test "${enable_default_strings_all+set}" = set; then : ++ enableval=$enable_default_strings_all; ++if test "${enableval}" = no; then ++ default_strings_all=0 ++else ++ default_strings_all=1 ++fi ++else ++ default_strings_all=1 ++fi ++ ++cat >>confdefs.h <<_ACEOF ++#define DEFAULT_STRINGS_ALL $default_strings_all ++_ACEOF ++ + + GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +diff -rup binutils-2.23.52.0.1.orig/binutils/configure.in binutils-2.23.52.0.1/binutils/configure.in +--- binutils-2.23.52.0.1.orig/binutils/configure.in 2015-06-29 11:32:47.702653870 +0100 ++++ binutils-2.23.52.0.1/binutils/configure.in 2015-06-29 11:37:17.355289171 +0100 +@@ -57,6 +57,18 @@ fi], [default_ar_deterministic=0]) + AC_DEFINE_UNQUOTED(DEFAULT_AR_DETERMINISTIC, $default_ar_deterministic, + [Should ar and ranlib use -D behavior by default?]) + ++AC_ARG_ENABLE(default-strings-all, ++[AS_HELP_STRING([--disable-default-strings-all], ++ [strings defaults to --data behavior])], [ ++if test "${enableval}" = no; then ++ default_strings_all=0 ++else ++ default_strings_all=1 ++fi], [default_strings_all=1]) ++ ++AC_DEFINE_UNQUOTED(DEFAULT_STRINGS_ALL, $default_strings_all, ++ [Should strings use -a behavior by default?]) ++ + AM_BINUTILS_WARNINGS + + AC_CONFIG_HEADERS(config.h:config.in) +diff -rup binutils-2.23.52.0.1.orig/binutils/doc/binutils.texi binutils-2.23.52.0.1/binutils/doc/binutils.texi +--- binutils-2.23.52.0.1.orig/binutils/doc/binutils.texi 2015-06-29 11:32:47.708653907 +0100 ++++ binutils-2.23.52.0.1/binutils/doc/binutils.texi 2015-06-29 11:38:49.645840128 +0100 +@@ -2658,15 +2658,24 @@ strings [@option{-afovV}] [@option{-}@va + + @c man begin DESCRIPTION strings + +-For each @var{file} given, @sc{gnu} @command{strings} prints the printable +-character sequences that are at least 4 characters long (or the number +-given with the options below) and are followed by an unprintable +-character. By default, it only prints the strings from the initialized +-and loaded sections of object files; for other types of files, it prints +-the strings from the whole file. ++For each @var{file} given, @sc{gnu} @command{strings} prints the ++printable character sequences that are at least 4 characters long (or ++the number given with the options below) and are followed by an ++unprintable character. ++ ++Depending upon how the strings program was configured it will default ++to either displaying all the printable sequences that it can find in ++each file, or only those sequences that are in loadable, initialized ++data sections. If the file type in unrecognizable, or if strings is ++reading from stdin then it will always display all of the printable ++sequences that it can find. ++ ++For backwards compatibility any file that occurs after a command line ++option of just @option{-} will also be scanned in full, regardless of ++the presence of any @option{-d} option. + +-@command{strings} is mainly useful for determining the contents of non-text +-files. ++@command{strings} is mainly useful for determining the contents of ++non-text files. + + @c man end + +@@ -2676,8 +2685,25 @@ files. + @item -a + @itemx --all + @itemx - +-Do not scan only the initialized and loaded sections of object files; +-scan the whole files. ++Scan the whole file, regardless of what sections it contains or ++whether those sections are loaded or initialized. Normally this is ++the default behaviour, but strings can be configured so that the ++@option{-d} is the default instead. ++ ++The @option{-} option is position dependent and forces strings to ++perform full scans of any file that is mentioned after the @option{-} ++on the command line, even if the @option{-d} option has been ++specified. ++ ++@item -d ++@itemx --data ++Only print strings from initialized, loaded data sections in the ++file. This may reduce the amount of garbage in the output, but it ++also exposes the strings program to any security flaws that may be ++present in the BFD library used to scan and load sections. Strings ++can be configured so that this option is the default behaviour. In ++such cases the @option{-a} option can be used to avoid using the BFD ++library and instead just print all of the strings found in the file. + + @item -f + @itemx --print-file-name +diff -rup binutils-2.23.52.0.1.orig/binutils/NEWS binutils-2.23.52.0.1/binutils/NEWS +--- binutils-2.23.52.0.1.orig/binutils/NEWS 2015-06-29 11:32:47.701653864 +0100 ++++ binutils-2.23.52.0.1/binutils/NEWS 2015-06-29 11:39:07.052944045 +0100 +@@ -1,5 +1,10 @@ + -*- text -*- + ++* Add --data option to strings to only print strings in loadable, initialized ++ data sections. Change the default behaviour to be --all, but add a new ++ configure time option of --disable-default-strings-all to restore the old ++ default behaviour. ++ + * Objcopy now supports wildcard characters in command line options that take + section names. + +diff -rup binutils-2.23.52.0.1.orig/binutils/strings.c binutils-2.23.52.0.1/binutils/strings.c +--- binutils-2.23.52.0.1.orig/binutils/strings.c 2015-06-29 11:32:47.721653986 +0100 ++++ binutils-2.23.52.0.1/binutils/strings.c 2015-06-29 11:41:06.159655090 +0100 +@@ -23,7 +23,10 @@ + Options: + --all + -a +- - Do not scan only the initialized data section of object files. ++ - Scan each file in its entirety. ++ ++ --data ++ -d Scan only the initialized data section(s) of object files. + + --print-file-name + -f Print the name of the file before each string. +@@ -107,6 +110,7 @@ static int encoding_bytes; + static struct option long_options[] = + { + {"all", no_argument, NULL, 'a'}, ++ {"data", no_argument, NULL, 'd'}, + {"print-file-name", no_argument, NULL, 'f'}, + {"bytes", required_argument, NULL, 'n'}, + {"radix", required_argument, NULL, 't'}, +@@ -158,11 +162,14 @@ main (int argc, char **argv) + string_min = 4; + print_addresses = FALSE; + print_filenames = FALSE; +- datasection_only = TRUE; ++ if (DEFAULT_STRINGS_ALL) ++ datasection_only = FALSE; ++ else ++ datasection_only = TRUE; + target = NULL; + encoding = 's'; + +- while ((optc = getopt_long (argc, argv, "afhHn:ot:e:T:Vv0123456789", ++ while ((optc = getopt_long (argc, argv, "adfhHn:ot:e:T:Vv0123456789", + long_options, (int *) 0)) != EOF) + { + switch (optc) +@@ -171,6 +178,10 @@ main (int argc, char **argv) + datasection_only = FALSE; + break; + ++ case 'd': ++ datasection_only = TRUE; ++ break; ++ + case 'f': + print_filenames = TRUE; + break; +@@ -659,8 +670,18 @@ usage (FILE *stream, int status) + { + fprintf (stream, _("Usage: %s [option(s)] [file(s)]\n"), program_name); + fprintf (stream, _(" Display printable strings in [file(s)] (stdin by default)\n")); +- fprintf (stream, _(" The options are:\n\ ++ fprintf (stream, _(" The options are:\n")); ++ ++ if (DEFAULT_STRINGS_ALL) ++ fprintf (stream, _("\ ++ -a - --all Scan the entire file, not just the data section [default]\n\ ++ -d --data Only scan the data sections in the file\n")); ++ else ++ fprintf (stream, _("\ + -a - --all Scan the entire file, not just the data section\n\ ++ -d --data Only scan the data sections in the file [default]\n")); ++ ++ fprintf (stream, _("\ + -f --print-file-name Print the name of the file before each string\n\ + -n --bytes=[number] Locate & print any NUL-terminated sequence of at\n\ + - least [number] characters (default 4).\n\ +diff -rup binutils-2.23.52.0.1.orig/bfd/elf.c binutils-2.23.52.0.1/bfd/elf.c +--- binutils-2.23.52.0.1.orig/bfd/elf.c 2015-06-29 11:32:47.637653475 +0100 ++++ binutils-2.23.52.0.1/bfd/elf.c 2015-06-29 11:48:24.632272687 +0100 +@@ -613,7 +613,8 @@ setup_group (bfd *abfd, Elf_Internal_Shd + _bfd_error_handler + (_("%B: Corrupt size field in group section header: 0x%lx"), abfd, shdr->sh_size); + bfd_set_error (bfd_error_bad_value); +- return FALSE; ++ -- num_group; ++ continue; + } + + memset (shdr->contents, 0, amt); +@@ -621,7 +622,16 @@ setup_group (bfd *abfd, Elf_Internal_Shd + if (bfd_seek (abfd, shdr->sh_offset, SEEK_SET) != 0 + || (bfd_bread (shdr->contents, shdr->sh_size, abfd) + != shdr->sh_size)) +- return FALSE; ++ { ++ _bfd_error_handler ++ (_("%B: invalid size field in group section header: 0x%lx"), abfd, shdr->sh_size); ++ bfd_set_error (bfd_error_bad_value); ++ -- num_group; ++ /* PR 17510: If the group contents are even partially ++ corrupt, do not allow any of the contents to be used. */ ++ memset (shdr->contents, 0, amt); ++ continue; ++ } + + /* Translate raw contents, a flag word followed by an + array of elf section indices all in target byte order, +@@ -654,6 +664,21 @@ setup_group (bfd *abfd, Elf_Internal_Shd + } + } + } ++ ++ /* PR 17510: Corrupt binaries might contain invalid groups. */ ++ if (num_group != (unsigned) elf_tdata (abfd)->num_group) ++ { ++ elf_tdata (abfd)->num_group = num_group; ++ ++ /* If all groups are invalid then fail. */ ++ if (num_group == 0) ++ { ++ elf_tdata (abfd)->group_sect_ptr = NULL; ++ elf_tdata (abfd)->num_group = num_group = -1; ++ (*_bfd_error_handler) (_("%B: no valid group sections found"), abfd); ++ bfd_set_error (bfd_error_bad_value); ++ } ++ } + } + } + +@@ -719,6 +744,7 @@ setup_group (bfd *abfd, Elf_Internal_Shd + { + (*_bfd_error_handler) (_("%B: no group info for section %A"), + abfd, newsect); ++ return FALSE; + } + return TRUE; + } + diff --git a/SOURCES/binutils-rh1162594.patch b/SOURCES/binutils-rh1162594.patch new file mode 100644 index 0000000..b50b93f --- /dev/null +++ b/SOURCES/binutils-rh1162594.patch @@ -0,0 +1,609 @@ +diff -rup binutils-2.23.52.0.1.orig/bfd/elf.c binutils-2.23.52.0.1/bfd/elf.c +--- binutils-2.23.52.0.1.orig/bfd/elf.c 2015-06-26 14:08:00.082538130 +0100 ++++ binutils-2.23.52.0.1/bfd/elf.c 2015-06-26 15:42:53.056761250 +0100 +@@ -1559,23 +1559,57 @@ bfd_section_from_shdr (bfd *abfd, unsign + Elf_Internal_Ehdr *ehdr; + const struct elf_backend_data *bed; + const char *name; ++ bfd_boolean ret = TRUE; ++ static bfd_boolean * sections_being_created = NULL; ++ static bfd * sections_being_created_abfd = NULL; ++ static unsigned int nesting = 0; + + if (shindex >= elf_numsections (abfd)) + return FALSE; + ++ if (++ nesting > 3) ++ { ++ /* PR17512: A corrupt ELF binary might contain a recursive group of ++ sections, with each the string indicies pointing to the next in the ++ loop. Detect this here, by refusing to load a section that we are ++ already in the process of loading. We only trigger this test if ++ we have nested at least three sections deep as normal ELF binaries ++ can expect to recurse at least once. ++ ++ FIXME: It would be better if this array was attached to the bfd, ++ rather than being held in a static pointer. */ ++ ++ if (sections_being_created_abfd != abfd) ++ sections_being_created = NULL; ++ if (sections_being_created == NULL) ++ { ++ /* FIXME: It would be more efficient to attach this array to the bfd somehow. */ ++ sections_being_created = (bfd_boolean *) ++ bfd_zalloc (abfd, elf_numsections (abfd) * sizeof (bfd_boolean)); ++ sections_being_created_abfd = abfd; ++ } ++ if (sections_being_created [shindex]) ++ { ++ (*_bfd_error_handler) ++ (_("%B: warning: loop in section dependencies detected"), abfd); ++ return FALSE; ++ } ++ sections_being_created [shindex] = TRUE; ++ } ++ + hdr = elf_elfsections (abfd)[shindex]; + ehdr = elf_elfheader (abfd); + name = bfd_elf_string_from_elf_section (abfd, ehdr->e_shstrndx, + hdr->sh_name); + if (name == NULL) +- return FALSE; ++ goto fail; + + bed = get_elf_backend_data (abfd); + switch (hdr->sh_type) + { + case SHT_NULL: + /* Inactive section. Throw it away. */ +- return TRUE; ++ goto success; + + case SHT_PROGBITS: /* Normal section with contents. */ + case SHT_NOBITS: /* .bss section. */ +@@ -1586,11 +1620,13 @@ bfd_section_from_shdr (bfd *abfd, unsign + case SHT_PREINIT_ARRAY: /* .preinit_array section. */ + case SHT_GNU_LIBLIST: /* .gnu.liblist section. */ + case SHT_GNU_HASH: /* .gnu.hash section. */ +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ goto success; + + case SHT_DYNAMIC: /* Dynamic linking information. */ + if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex)) +- return FALSE; ++ goto fail; ++ + if (hdr->sh_link > elf_numsections (abfd)) + { + /* PR 10478: Accept Solaris binaries with a sh_link +@@ -1604,11 +1640,11 @@ bfd_section_from_shdr (bfd *abfd, unsign + break; + /* Otherwise fall through. */ + default: +- return FALSE; ++ goto fail; + } + } + else if (elf_elfsections (abfd)[hdr->sh_link] == NULL) +- return FALSE; ++ goto fail; + else if (elf_elfsections (abfd)[hdr->sh_link]->sh_type != SHT_STRTAB) + { + Elf_Internal_Shdr *dynsymhdr; +@@ -1637,24 +1673,26 @@ bfd_section_from_shdr (bfd *abfd, unsign + } + } + } +- break; ++ goto success; + + case SHT_SYMTAB: /* A symbol table */ + if (elf_onesymtab (abfd) == shindex) +- return TRUE; ++ goto success; + + if (hdr->sh_entsize != bed->s->sizeof_sym) +- return FALSE; ++ goto fail; ++ + if (hdr->sh_info * hdr->sh_entsize > hdr->sh_size) + { + if (hdr->sh_size != 0) +- return FALSE; ++ goto fail; + /* Some assemblers erroneously set sh_info to one with a + zero sh_size. ld sees this as a global symbol count + of (unsigned) -1. Fix it here. */ + hdr->sh_info = 0; +- return TRUE; ++ goto success; + } ++ + BFD_ASSERT (elf_onesymtab (abfd) == 0); + elf_onesymtab (abfd) = shindex; + elf_tdata (abfd)->symtab_hdr = *hdr; +@@ -1671,7 +1709,7 @@ bfd_section_from_shdr (bfd *abfd, unsign + && (abfd->flags & DYNAMIC) != 0 + && ! _bfd_elf_make_section_from_shdr (abfd, hdr, name, + shindex)) +- return FALSE; ++ goto fail; + + /* Go looking for SHT_SYMTAB_SHNDX too, since if there is one we + can't read symbols without that section loaded as well. It +@@ -1697,25 +1735,25 @@ bfd_section_from_shdr (bfd *abfd, unsign + break; + } + if (i != shindex) +- return bfd_section_from_shdr (abfd, i); ++ ret = bfd_section_from_shdr (abfd, i); + } +- return TRUE; ++ goto success; + + case SHT_DYNSYM: /* A dynamic symbol table */ + if (elf_dynsymtab (abfd) == shindex) +- return TRUE; ++ goto success; + + if (hdr->sh_entsize != bed->s->sizeof_sym) +- return FALSE; ++ goto fail; + if (hdr->sh_info * hdr->sh_entsize > hdr->sh_size) + { + if (hdr->sh_size != 0) +- return FALSE; ++ goto fail; + /* Some linkers erroneously set sh_info to one with a + zero sh_size. ld sees this as a global symbol count + of (unsigned) -1. Fix it here. */ + hdr->sh_info = 0; +- return TRUE; ++ goto success; + } + BFD_ASSERT (elf_dynsymtab (abfd) == 0); + elf_dynsymtab (abfd) = shindex; +@@ -1725,33 +1763,34 @@ bfd_section_from_shdr (bfd *abfd, unsign + + /* Besides being a symbol table, we also treat this as a regular + section, so that objcopy can handle it. */ +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ goto success; + + case SHT_SYMTAB_SHNDX: /* Symbol section indices when >64k sections */ + if (elf_symtab_shndx (abfd) == shindex) +- return TRUE; ++ goto success; + + BFD_ASSERT (elf_symtab_shndx (abfd) == 0); + elf_symtab_shndx (abfd) = shindex; + elf_tdata (abfd)->symtab_shndx_hdr = *hdr; + elf_elfsections (abfd)[shindex] = &elf_tdata (abfd)->symtab_shndx_hdr; +- return TRUE; ++ goto success; + + case SHT_STRTAB: /* A string table */ + if (hdr->bfd_section != NULL) +- return TRUE; ++ goto success; + if (ehdr->e_shstrndx == shindex) + { + elf_tdata (abfd)->shstrtab_hdr = *hdr; + elf_elfsections (abfd)[shindex] = &elf_tdata (abfd)->shstrtab_hdr; +- return TRUE; ++ goto success; + } + if (elf_elfsections (abfd)[elf_onesymtab (abfd)]->sh_link == shindex) + { + symtab_strtab: + elf_tdata (abfd)->strtab_hdr = *hdr; + elf_elfsections (abfd)[shindex] = &elf_tdata (abfd)->strtab_hdr; +- return TRUE; ++ goto success; + } + if (elf_elfsections (abfd)[elf_dynsymtab (abfd)]->sh_link == shindex) + { +@@ -1761,8 +1800,9 @@ bfd_section_from_shdr (bfd *abfd, unsign + elf_elfsections (abfd)[shindex] = hdr; + /* We also treat this as a regular section, so that objcopy + can handle it. */ +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, +- shindex); ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, ++ shindex); ++ goto success; + } + + /* If the string table isn't one of the above, then treat it as a +@@ -1780,9 +1820,9 @@ bfd_section_from_shdr (bfd *abfd, unsign + { + /* Prevent endless recursion on broken objects. */ + if (i == shindex) +- return FALSE; ++ goto fail; + if (! bfd_section_from_shdr (abfd, i)) +- return FALSE; ++ goto fail; + if (elf_onesymtab (abfd) == i) + goto symtab_strtab; + if (elf_dynsymtab (abfd) == i) +@@ -1790,7 +1830,8 @@ bfd_section_from_shdr (bfd *abfd, unsign + } + } + } +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ goto success; + + case SHT_REL: + case SHT_RELA: +@@ -1805,7 +1846,7 @@ bfd_section_from_shdr (bfd *abfd, unsign + if (hdr->sh_entsize + != (bfd_size_type) (hdr->sh_type == SHT_REL + ? bed->s->sizeof_rel : bed->s->sizeof_rela)) +- return FALSE; ++ goto fail; + + /* Check for a bogus link to avoid crashing. */ + if (hdr->sh_link >= num_sec) +@@ -1813,8 +1854,9 @@ bfd_section_from_shdr (bfd *abfd, unsign + ((*_bfd_error_handler) + (_("%B: invalid link %lu for reloc section %s (index %u)"), + abfd, hdr->sh_link, name, shindex)); +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, +- shindex); ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, ++ shindex); ++ goto success; + } + + /* For some incomprehensible reason Oracle distributes +@@ -1855,7 +1897,7 @@ bfd_section_from_shdr (bfd *abfd, unsign + if ((elf_elfsections (abfd)[hdr->sh_link]->sh_type == SHT_SYMTAB + || elf_elfsections (abfd)[hdr->sh_link]->sh_type == SHT_DYNSYM) + && ! bfd_section_from_shdr (abfd, hdr->sh_link)) +- return FALSE; ++ goto fail; + + /* If this reloc section does not use the main symbol table we + don't treat it as a reloc section. BFD can't adequately +@@ -1870,14 +1912,17 @@ bfd_section_from_shdr (bfd *abfd, unsign + || hdr->sh_info >= num_sec + || elf_elfsections (abfd)[hdr->sh_info]->sh_type == SHT_REL + || elf_elfsections (abfd)[hdr->sh_info]->sh_type == SHT_RELA) +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, +- shindex); ++ { ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, ++ shindex); ++ goto success; ++ } + + if (! bfd_section_from_shdr (abfd, hdr->sh_info)) +- return FALSE; ++ goto fail; + target_sect = bfd_section_from_elf_index (abfd, hdr->sh_info); + if (target_sect == NULL) +- return FALSE; ++ goto fail; + + esdt = elf_section_data (target_sect); + if (hdr->sh_type == SHT_RELA) +@@ -1885,11 +1930,13 @@ bfd_section_from_shdr (bfd *abfd, unsign + else + p_hdr = &esdt->rel.hdr; + +- BFD_ASSERT (*p_hdr == NULL); ++ /* PR 17512: file: 0b4f81b7. */ ++ if (*p_hdr != NULL) ++ goto fail; + amt = sizeof (*hdr2); + hdr2 = (Elf_Internal_Shdr *) bfd_alloc (abfd, amt); + if (hdr2 == NULL) +- return FALSE; ++ goto fail; + *hdr2 = *hdr; + *p_hdr = hdr2; + elf_elfsections (abfd)[shindex] = hdr2; +@@ -1905,40 +1952,45 @@ bfd_section_from_shdr (bfd *abfd, unsign + target_sect->use_rela_p = 1; + } + abfd->flags |= HAS_RELOC; +- return TRUE; ++ goto success; + } + + case SHT_GNU_verdef: + elf_dynverdef (abfd) = shindex; + elf_tdata (abfd)->dynverdef_hdr = *hdr; +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ goto success; + + case SHT_GNU_versym: + if (hdr->sh_entsize != sizeof (Elf_External_Versym)) +- return FALSE; ++ goto fail; + elf_dynversym (abfd) = shindex; + elf_tdata (abfd)->dynversym_hdr = *hdr; +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ goto success; + + case SHT_GNU_verneed: + elf_dynverref (abfd) = shindex; + elf_tdata (abfd)->dynverref_hdr = *hdr; +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ goto success; + + case SHT_SHLIB: +- return TRUE; ++ goto success; + + case SHT_GROUP: + if (! IS_VALID_GROUP_SECTION_HEADER (hdr, GRP_ENTRY_SIZE)) +- return FALSE; ++ goto fail; + if (!_bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex)) +- return FALSE; ++ goto fail; + if (hdr->contents != NULL) + { + Elf_Internal_Group *idx = (Elf_Internal_Group *) hdr->contents; +- unsigned int n_elt = hdr->sh_size / GRP_ENTRY_SIZE; ++ unsigned int n_elt = hdr->sh_size / sizeof (* idx); + asection *s; + ++ if (n_elt == 0) ++ goto fail; + if (idx->flags & GRP_COMDAT) + hdr->bfd_section->flags + |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD; +@@ -1958,7 +2010,7 @@ bfd_section_from_shdr (bfd *abfd, unsign + } + } + } +- break; ++ goto success; + + default: + /* Possibly an attributes section. */ +@@ -1966,14 +2018,14 @@ bfd_section_from_shdr (bfd *abfd, unsign + || hdr->sh_type == bed->obj_attrs_section_type) + { + if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex)) +- return FALSE; ++ goto fail; + _bfd_elf_parse_attributes (abfd, hdr); +- return TRUE; ++ goto success; + } + + /* Check for any processor-specific section types. */ + if (bed->elf_backend_section_from_shdr (abfd, hdr, name, shindex)) +- return TRUE; ++ goto success; + + if (hdr->sh_type >= SHT_LOUSER && hdr->sh_type <= SHT_HIUSER) + { +@@ -1985,9 +2037,12 @@ bfd_section_from_shdr (bfd *abfd, unsign + "specific section `%s' [0x%8x]"), + abfd, name, hdr->sh_type); + else +- /* Allow sections reserved for applications. */ +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, +- shindex); ++ { ++ /* Allow sections reserved for applications. */ ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, ++ shindex); ++ goto success; ++ } + } + else if (hdr->sh_type >= SHT_LOPROC + && hdr->sh_type <= SHT_HIPROC) +@@ -2008,8 +2063,11 @@ bfd_section_from_shdr (bfd *abfd, unsign + "`%s' [0x%8x]"), + abfd, name, hdr->sh_type); + else +- /* Otherwise it should be processed. */ +- return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ { ++ /* Otherwise it should be processed. */ ++ ret = _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); ++ goto success; ++ } + } + else + /* FIXME: We should handle this section. */ +@@ -2017,10 +2075,20 @@ bfd_section_from_shdr (bfd *abfd, unsign + (_("%B: don't know how to handle section `%s' [0x%8x]"), + abfd, name, hdr->sh_type); + +- return FALSE; ++ goto fail; + } + +- return TRUE; ++ fail: ++ ret = FALSE; ++ success: ++ if (sections_being_created && sections_being_created_abfd == abfd) ++ sections_being_created [shindex] = FALSE; ++ if (-- nesting == 0) ++ { ++ sections_being_created = NULL; ++ sections_being_created_abfd = abfd; ++ } ++ return ret; + } + + /* Return the local symbol specified by ABFD, R_SYMNDX. */ +diff -rup binutils-2.23.52.0.1.orig/bfd/peXXigen.c binutils-2.23.52.0.1/bfd/peXXigen.c +--- binutils-2.23.52.0.1.orig/bfd/peXXigen.c 2015-06-26 14:08:00.109538300 +0100 ++++ binutils-2.23.52.0.1/bfd/peXXigen.c 2015-06-26 16:13:44.023395562 +0100 +@@ -461,6 +461,19 @@ _bfd_XXi_swap_aouthdr_in (bfd * abfd, + { + int idx; + ++ /* PR 17512: Corrupt PE binaries can cause seg-faults. */ ++ if (a->NumberOfRvaAndSizes > IMAGE_NUMBEROF_DIRECTORY_ENTRIES) ++ { ++ (*_bfd_error_handler) ++ (_("%B: aout header specifies an invalid number of data-directory entries: %d"), ++ abfd, a->NumberOfRvaAndSizes); ++ bfd_set_error (bfd_error_bad_value); ++ ++ /* Paranoia: If the number is corrupt, then assume that the ++ actual entries themselves might be corrupt as well. */ ++ a->NumberOfRvaAndSizes = 0; ++ } ++ + for (idx = 0; idx < 16; idx++) + { + /* If data directory is empty, rva also should be 0. */ +@@ -1362,7 +1375,7 @@ pe_print_edata (bfd * abfd, void * vfile + bfd_size_type datasize = 0; + bfd_size_type dataoff; + bfd_size_type i; +- bfd_signed_vma adj; ++ bfd_vma adj; + struct EDT_type + { + long export_flags; /* Reserved - should be zero. */ +@@ -1412,6 +1425,13 @@ pe_print_edata (bfd * abfd, void * vfile + _("\nThere is an export table, but the section containing it could not be found\n")); + return TRUE; + } ++ else if (!(section->flags & SEC_HAS_CONTENTS)) ++ { ++ fprintf (file, ++ _("\nThere is an export table in %s, but that section has no contents\n"), ++ section->name); ++ return TRUE; ++ } + + dataoff = addr - section->vma; + datasize = extra->DataDirectory[PE_EXPORT_TABLE].Size; +@@ -1424,6 +1444,15 @@ pe_print_edata (bfd * abfd, void * vfile + } + } + ++ /* PR 17512: Handle corrupt PE binaries. */ ++ if (datasize < 36) ++ { ++ fprintf (file, ++ _("\nThere is an export table in %s, but it is too small (%d)\n"), ++ section->name, (int) datasize); ++ return TRUE; ++ } ++ + fprintf (file, _("\nThere is an export table in %s at 0x%lx\n"), + section->name, (unsigned long) addr); + +@@ -1467,8 +1496,13 @@ pe_print_edata (bfd * abfd, void * vfile + fprintf (file, + _("Name \t\t\t\t")); + bfd_fprintf_vma (abfd, file, edt.name); +- fprintf (file, +- " %s\n", data + edt.name - adj); ++ ++ if ((edt.name >= adj) && (edt.name < adj + datasize)) ++ fprintf (file, " %.*s\n", ++ (int) (datasize - (edt.name - adj)), ++ data + edt.name - adj); ++ else ++ fprintf (file, "(outside .edata section)\n"); + + fprintf (file, + _("Ordinal Base \t\t\t%ld\n"), edt.base); +@@ -1514,7 +1548,16 @@ pe_print_edata (bfd * abfd, void * vfile + _("\nExport Address Table -- Ordinal Base %ld\n"), + edt.base); + +- for (i = 0; i < edt.num_functions; ++i) ++ /* PR 17512: Handle corrupt PE binaries. */ ++ if (edt.eat_addr + (edt.num_functions * 4) - adj >= datasize ++ /* PR 17512: file: 092b1829 */ ++ || (edt.num_functions * 4) < edt.num_functions ++ /* PR 17512 file: 140-165018-0.004. */ ++ || data + edt.eat_addr - adj < data) ++ fprintf (file, _("\tInvalid Export Address Table rva (0x%lx) or entry count (0x%lx)\n"), ++ (long) edt.eat_addr, ++ (long) edt.num_functions); ++ else for (i = 0; i < edt.num_functions; ++i) + { + bfd_vma eat_member = bfd_get_32 (abfd, + data + edt.eat_addr + (i * 4) - adj); +@@ -1526,11 +1569,12 @@ pe_print_edata (bfd * abfd, void * vfile + /* This rva is to a name (forwarding function) in our section. */ + /* Should locate a function descriptor. */ + fprintf (file, +- "\t[%4ld] +base[%4ld] %04lx %s -- %s\n", ++ "\t[%4ld] +base[%4ld] %04lx %s -- %.*s\n", + (long) i, + (long) (i + edt.base), + (unsigned long) eat_member, + _("Forwarder RVA"), ++ (int)(datasize - (eat_member - adj)), + data + eat_member - adj); + } + else +@@ -1550,21 +1594,40 @@ pe_print_edata (bfd * abfd, void * vfile + fprintf (file, + _("\n[Ordinal/Name Pointer] Table\n")); + +- for (i = 0; i < edt.num_names; ++i) ++ /* PR 17512: Handle corrupt PE binaries. */ ++ if (edt.npt_addr + (edt.num_names * 4) - adj >= datasize ++ /* PR 17512: file: bb68816e. */ ++ || edt.num_names * 4 < edt.num_names ++ || (data + edt.npt_addr - adj) < data) ++ fprintf (file, _("\tInvalid Name Pointer Table rva (0x%lx) or entry count (0x%lx)\n"), ++ (long) edt.npt_addr, ++ (long) edt.num_names); ++ /* PR 17512: file: 140-147171-0.004. */ ++ else if (edt.ot_addr + (edt.num_names * 2) - adj >= datasize ++ || data + edt.ot_addr - adj < data) ++ fprintf (file, _("\tInvalid Ordinal Table rva (0x%lx) or entry count (0x%lx)\n"), ++ (long) edt.ot_addr, ++ (long) edt.num_names); ++ else for (i = 0; i < edt.num_names; ++i) + { +- bfd_vma name_ptr = bfd_get_32 (abfd, +- data + +- edt.npt_addr +- + (i*4) - adj); +- +- char *name = (char *) data + name_ptr - adj; +- +- bfd_vma ord = bfd_get_16 (abfd, +- data + +- edt.ot_addr +- + (i*2) - adj); +- fprintf (file, +- "\t[%4ld] %s\n", (long) ord, name); ++ bfd_vma name_ptr; ++ bfd_vma ord; ++ ++ ord = bfd_get_16 (abfd, data + edt.ot_addr + (i * 2) - adj); ++ name_ptr = bfd_get_32 (abfd, data + edt.npt_addr + (i * 4) - adj); ++ ++ if ((name_ptr - adj) >= datasize) ++ { ++ fprintf (file, _("\t[%4ld] \n"), ++ (long) ord, (long) name_ptr); ++ } ++ else ++ { ++ char * name = (char *) data + name_ptr - adj; ++ ++ fprintf (file, "\t[%4ld] %.*s\n", (long) ord, ++ (int)((char *)(data + datasize) - name), name); ++ } + } + + free (data); diff --git a/SOURCES/binutils-rh1162607.patch b/SOURCES/binutils-rh1162607.patch new file mode 100644 index 0000000..75893d4 --- /dev/null +++ b/SOURCES/binutils-rh1162607.patch @@ -0,0 +1,12 @@ +diff -rup binutils-2.23.52.0.1.orig/bfd/ihex.c binutils-2.23.52.0.1/bfd/ihex.c +--- binutils-2.23.52.0.1.orig/bfd/ihex.c 2015-06-26 16:42:28.555216948 +0100 ++++ binutils-2.23.52.0.1/bfd/ihex.c 2015-06-26 16:51:34.466607406 +0100 +@@ -322,7 +322,7 @@ ihex_scan (bfd *abfd) + { + if (! ISHEX (buf[i])) + { +- ihex_bad_byte (abfd, lineno, hdr[i], error); ++ ihex_bad_byte (abfd, lineno, buf[i], error); + goto error_return; + } + } diff --git a/SOURCES/binutils-rh1162621.patch b/SOURCES/binutils-rh1162621.patch new file mode 100644 index 0000000..9b9f637 --- /dev/null +++ b/SOURCES/binutils-rh1162621.patch @@ -0,0 +1,12 @@ +diff -rup binutils-2.23.52.0.1.orig/bfd/srec.c binutils-2.23.52.0.1/bfd/srec.c +--- binutils-2.23.52.0.1.orig/bfd/srec.c 2015-06-26 16:42:28.563216999 +0100 ++++ binutils-2.23.52.0.1/bfd/srec.c 2015-06-26 17:13:59.978902080 +0100 +@@ -454,7 +454,7 @@ srec_scan (bfd *abfd) + case 'S': + { + file_ptr pos; +- char hdr[3]; ++ unsigned char hdr[3]; + unsigned int bytes; + bfd_vma address; + bfd_byte *data; diff --git a/SOURCES/binutils-rh1162655.patch b/SOURCES/binutils-rh1162655.patch new file mode 100644 index 0000000..adea7d0 --- /dev/null +++ b/SOURCES/binutils-rh1162655.patch @@ -0,0 +1,184 @@ +diff -rcp binutils-2.23.52.0.1.orig/binutils/ar.c binutils-2.23.52.0.1/binutils/ar.c +*** binutils-2.23.52.0.1.orig/binutils/ar.c 2014-11-11 20:51:37.044244928 +0000 +--- binutils-2.23.52.0.1/binutils/ar.c 2014-11-11 20:53:41.245801920 +0000 +*************** extract_file (bfd *abfd) +*** 1013,1018 **** +--- 1013,1027 ---- + bfd_size_type size; + struct stat buf; + ++ /* PR binutils/17533: Do not allow directory traversal ++ outside of the current directory tree. */ ++ if (! is_valid_archive_path (bfd_get_filename (abfd))) ++ { ++ non_fatal (_("illegal pathname found in archive member: %s"), ++ bfd_get_filename (abfd)); ++ return; ++ } ++ + if (bfd_stat_arch_elt (abfd, &buf) != 0) + /* xgettext:c-format */ + fatal (_("internal stat error on %s"), bfd_get_filename (abfd)); +diff -rcp binutils-2.23.52.0.1.orig/binutils/bucomm.c binutils-2.23.52.0.1/binutils/bucomm.c +*** binutils-2.23.52.0.1.orig/binutils/bucomm.c 2014-11-11 20:51:37.022244830 +0000 +--- binutils-2.23.52.0.1/binutils/bucomm.c 2014-11-11 20:52:45.452550953 +0000 +*************** bfd_get_archive_filename (const bfd *abf +*** 624,626 **** +--- 624,652 ---- + bfd_get_filename (abfd)); + return buf; + } ++ ++ /* Returns TRUE iff PATHNAME, a filename of an archive member, ++ is valid for writing. For security reasons absolute paths ++ and paths containing /../ are not allowed. See PR 17533. */ ++ ++ bfd_boolean ++ is_valid_archive_path (char const * pathname) ++ { ++ const char * n = pathname; ++ ++ if (IS_ABSOLUTE_PATH (n)) ++ return FALSE; ++ ++ while (*n) ++ { ++ if (*n == '.' && *++n == '.' && ( ! *++n || IS_DIR_SEPARATOR (*n))) ++ return FALSE; ++ ++ while (*n && ! IS_DIR_SEPARATOR (*n)) ++ n++; ++ while (IS_DIR_SEPARATOR (*n)) ++ n++; ++ } ++ ++ return TRUE; ++ } +diff -rcp binutils-2.23.52.0.1.orig/binutils/bucomm.h binutils-2.23.52.0.1/binutils/bucomm.h +*** binutils-2.23.52.0.1.orig/binutils/bucomm.h 2014-11-11 20:51:37.030244866 +0000 +--- binutils-2.23.52.0.1/binutils/bucomm.h 2014-11-11 20:53:03.228630913 +0000 +*************** bfd_vma parse_vma (const char *, const c +*** 58,63 **** +--- 58,65 ---- + + off_t get_file_size (const char *); + ++ bfd_boolean is_valid_archive_path (char const *); ++ + extern char *program_name; + + /* filemode.c */ +diff -rcp binutils-2.23.52.0.1.orig/binutils/doc/binutils.texi binutils-2.23.52.0.1/binutils/doc/binutils.texi +*** binutils-2.23.52.0.1.orig/binutils/doc/binutils.texi 2014-11-11 20:51:37.052244964 +0000 +--- binutils-2.23.52.0.1/binutils/doc/binutils.texi 2014-11-11 20:56:13.759503335 +0000 +*************** a normal archive. Instead the elements +*** 234,240 **** + individually to the second archive. + + The paths to the elements of the archive are stored relative to the +! archive itself. + + @cindex compatibility, @command{ar} + @cindex @command{ar} compatibility +--- 234,241 ---- + individually to the second archive. + + The paths to the elements of the archive are stored relative to the +! archive itself. For security reasons absolute paths and paths with a +! @code{/../} component are not allowed. + + @cindex compatibility, @command{ar} + @cindex @command{ar} compatibility +diff -rcp binutils-2.23.52.0.1.orig/binutils/objcopy.c binutils-2.23.52.0.1/binutils/objcopy.c +*** binutils-2.23.52.0.1.orig/binutils/objcopy.c 2014-11-11 20:51:37.030244866 +0000 +--- binutils-2.23.52.0.1/binutils/objcopy.c 2014-11-11 20:55:30.431307076 +0000 +*************** copy_archive (bfd *ibfd, bfd *obfd, cons +*** 2182,2187 **** +--- 2182,2197 ---- + bfd_boolean del = TRUE; + bfd_boolean ok_object; + ++ /* PR binutils/17533: Do not allow directory traversal ++ outside of the current directory tree by archive members. */ ++ if (! is_valid_archive_path (bfd_get_filename (this_element))) ++ { ++ non_fatal (_("illegal pathname found in archive member: %s"), ++ bfd_get_filename (this_element)); ++ status = 1; ++ goto cleanup_and_exit; ++ } ++ + /* Create an output file for this member. */ + output_name = concat (dir, "/", + bfd_get_filename (this_element), (char *) 0); +*************** copy_archive (bfd *ibfd, bfd *obfd, cons +*** 2191,2198 **** + { + output_name = make_tempdir (output_name); + if (output_name == NULL) +! fatal (_("cannot create tempdir for archive copying (error: %s)"), +! strerror (errno)); + + l = (struct name_list *) xmalloc (sizeof (struct name_list)); + l->name = output_name; +--- 2201,2212 ---- + { + output_name = make_tempdir (output_name); + if (output_name == NULL) +! { +! non_fatal (_("cannot create tempdir for archive copying (error: %s)"), +! strerror (errno)); +! status = 1; +! goto cleanup_and_exit; +! } + + l = (struct name_list *) xmalloc (sizeof (struct name_list)); + l->name = output_name; +*************** copy_archive (bfd *ibfd, bfd *obfd, cons +*** 2234,2240 **** + { + bfd_nonfatal_message (output_name, NULL, NULL, NULL); + status = 1; +! return; + } + + if (ok_object) +--- 2248,2254 ---- + { + bfd_nonfatal_message (output_name, NULL, NULL, NULL); + status = 1; +! goto cleanup_and_exit; + } + + if (ok_object) +*************** copy_archive (bfd *ibfd, bfd *obfd, cons +*** 2295,2301 **** + { + status = 1; + bfd_nonfatal_message (filename, NULL, NULL, NULL); +- return; + } + + filename = bfd_get_filename (ibfd); +--- 2309,2314 ---- +*************** copy_archive (bfd *ibfd, bfd *obfd, cons +*** 2303,2311 **** + { + status = 1; + bfd_nonfatal_message (filename, NULL, NULL, NULL); +- return; + } + + /* Delete all the files that we opened. */ + for (l = list; l != NULL; l = l->next) + { +--- 2316,2324 ---- + { + status = 1; + bfd_nonfatal_message (filename, NULL, NULL, NULL); + } + ++ cleanup_and_exit: + /* Delete all the files that we opened. */ + for (l = list; l != NULL; l = l->next) + { diff --git a/SOURCES/binutils-rh1162666.patch b/SOURCES/binutils-rh1162666.patch new file mode 100644 index 0000000..6787ff6 --- /dev/null +++ b/SOURCES/binutils-rh1162666.patch @@ -0,0 +1,32 @@ +diff -rup binutils-2.23.52.0.1.orig/bfd/archive.c binutils-2.23.52.0.1/bfd/archive.c +--- binutils-2.23.52.0.1.orig/bfd/archive.c 2015-06-29 15:44:32.451766994 +0100 ++++ binutils-2.23.52.0.1/bfd/archive.c 2015-06-29 15:45:34.835157059 +0100 +@@ -1299,6 +1299,8 @@ _bfd_slurp_extended_name_table (bfd *abf + { + byebye: + free (namedata); ++ bfd_ardata (abfd)->extended_names = NULL; ++ bfd_ardata (abfd)->extended_names_size = 0; + return FALSE; + } + +--- binutils-2.23.52.0.1.orig/bfd/archive.c 2015-10-13 15:04:39.212512284 +0100 ++++ binutils-2.23.52.0.1/bfd/archive.c 2015-10-13 15:06:44.960238452 +0100 +@@ -1292,6 +1292,9 @@ _bfd_slurp_extended_name_table (bfd *abf + amt = namedata->parsed_size; + if (amt + 1 == 0) + goto byebye; ++ /* PR binutils/17533: A corrupt archive can contain an invalid size. */ ++ if (amt > (bfd_size_type) bfd_get_size (abfd)) ++ goto byebye; + + bfd_ardata (abfd)->extended_names_size = amt; + bfd_ardata (abfd)->extended_names = (char *) bfd_zalloc (abfd, amt + 1); +@@ -1309,7 +1312,6 @@ _bfd_slurp_extended_name_table (bfd *abf + if (bfd_get_error () != bfd_error_system_call) + bfd_set_error (bfd_error_malformed_archive); + bfd_release (abfd, (bfd_ardata (abfd)->extended_names)); +- bfd_ardata (abfd)->extended_names = NULL; + goto byebye; + } + diff --git a/SOURCES/binutils-rh1172766-1.patch b/SOURCES/binutils-rh1172766-1.patch new file mode 100644 index 0000000..88864fb --- /dev/null +++ b/SOURCES/binutils-rh1172766-1.patch @@ -0,0 +1,11 @@ +--- binutils-2.23.52.0.1/bfd/elflink.c.~0~ 2015-05-21 19:00:55.000000000 -0400 ++++ binutils-2.23.52.0.1/bfd/elflink.c 2015-05-21 18:58:41.000000000 -0400 +@@ -3803,7 +3803,7 @@ + /* We store a pointer to the hash table entry for each external + symbol. */ + amt = extsymcount * sizeof (struct elf_link_hash_entry *); +- sym_hash = (struct elf_link_hash_entry **) bfd_alloc (abfd, amt); ++ sym_hash = (struct elf_link_hash_entry **) bfd_zalloc (abfd, amt); + if (sym_hash == NULL) + goto error_free_sym; + elf_sym_hashes (abfd) = sym_hash; diff --git a/SOURCES/binutils-rh1172766.patch b/SOURCES/binutils-rh1172766.patch new file mode 100644 index 0000000..1ac8763 --- /dev/null +++ b/SOURCES/binutils-rh1172766.patch @@ -0,0 +1,204 @@ +commit b53dfeb26ed06e97fff1e8f469e33637ebdf6624 +Author: Alan Modra +Date: Sat Oct 18 21:46:48 2014 +1030 + + PowerPC64 ELFv1 function symbol definition vs LTO and discarded sections + + When functions are emitted in comdat groups, global symbols defined in + duplicates of the group are treated as if they were undefined. That + prevents the symbols in the discarded sections from affecting the + linker's global symbol hash table or causing duplicate symbol errors. + Annoyingly, when gcc emits a function to a comdat group, it does not + put *all* of a function's code and data in the comdat group. + Typically, constant tables, exception handling info, and debug info + are emitted to normal sections outside of the group, which is a + perennial source of linker problems due to the special handling needed + to deal with the extra-group pieces that ought to be discarded. In + the case of powerpc64-gcc, the OPD entry for a function is not put in + the group. Since the function symbol is defined on the OPD entry this + means we need to handle symbols in .opd specially. + + To see how this affects LTO in particular, consider the linker + testcase PR ld/12942 (1). This testcase links an LTO object file + pr12942a.o with a normal (non-LTO) object pr12942b.o. Both objects + contain a definition for _Z4testv in a comdat group. On loading + pr12942a.o, the linker sees a comdat group (actually linkonce section) + for _Z4testv and a weak _Z4testv defined in the IR. On loading + pr12942b.o, the linker sees the same comdat group, and thus discards + it. However, _Z4testv is a weak symbol defined in .opd, not part of + the group, so this weak symbol overrides the weak IR symbol. On + (re)loading the LTO version of pr12942a.o, the linker sees another + weak _Z4testv, but this one does not override the value we have from + pr12942b.o. The result is a linker complaint about "`_Z4testv' + ... defined in discarded section `.group' of tmpdir/pr12942b.o". + + * elf64-ppc.c (ppc64_elf_add_symbol_hook): If function code + section for function symbols defined in .opd is discarded, let + the symbol appear to be undefined. + (opd_entry_value): Ensure the result section is that for the + function code section in the same object as the OPD entry. + +--- a/bfd/elf64-ppc.c 2015-02-06 19:28:48.000000000 -0500 ++++ b/bfd/elf64-ppc.c 2015-02-06 19:24:12.000000000 -0500 +@@ -4774,22 +4774,37 @@ + const char **name, + flagword *flags ATTRIBUTE_UNUSED, + asection **sec, +- bfd_vma *value ATTRIBUTE_UNUSED) ++ bfd_vma *value) + { + if ((ibfd->flags & DYNAMIC) == 0 + && ELF_ST_BIND (isym->st_info) == STB_GNU_UNIQUE) + elf_tdata (info->output_bfd)->has_gnu_symbols = TRUE; + +- if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC) ++ if ((ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC) ++ && ((ibfd->flags & DYNAMIC) == 0)) ++ elf_tdata (info->output_bfd)->has_gnu_symbols = TRUE; ++ ++ if (*sec != NULL ++ && strcmp ((*sec)->name, ".opd") == 0) + { +- if ((ibfd->flags & DYNAMIC) == 0) +- elf_tdata (info->output_bfd)->has_gnu_symbols = TRUE; ++ asection *code_sec; ++ ++ if (!(ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC ++ || ELF_ST_TYPE (isym->st_info) == STT_FUNC)) ++ isym->st_info = ELF_ST_INFO (ELF_ST_BIND (isym->st_info), STT_FUNC); ++ ++ /* If the symbol is a function defined in .opd, and the function ++ code is in a discarded group, let it appear to be undefined. */ ++ if (!info->relocatable ++ && (*sec)->reloc_count != 0 ++ && opd_entry_value (*sec, *value, &code_sec, NULL, ++ FALSE) != (bfd_vma) -1 ++ && discarded_section (code_sec)) ++ { ++ *sec = bfd_und_section_ptr; ++ isym->st_shndx = SHN_UNDEF; ++ } + } +- else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC) +- ; +- else if (*sec != NULL +- && strcmp ((*sec)->name, ".opd") == 0) +- isym->st_info = ELF_ST_INFO (ELF_ST_BIND (isym->st_info), STT_FUNC); + + if ((STO_PPC64_LOCAL_MASK & isym->st_other) != 0) + { +@@ -5855,7 +5870,8 @@ + } + + /* OFFSET in OPD_SEC specifies a function descriptor. Return the address +- of the code entry point, and its section. */ ++ of the code entry point, and its section, which must be in the same ++ object as OPD_SEC. Returns (bfd_vma) -1 on error. */ + + static bfd_vma + opd_entry_value (asection *opd_sec, +@@ -5938,32 +5954,10 @@ + && ELF64_R_TYPE ((look + 1)->r_info) == R_PPC64_TOC) + { + unsigned long symndx = ELF64_R_SYM (look->r_info); +- asection *sec; ++ asection *sec = NULL; + +- if (symndx < symtab_hdr->sh_info +- || elf_sym_hashes (opd_bfd) == NULL) +- { +- Elf_Internal_Sym *sym; +- +- sym = (Elf_Internal_Sym *) symtab_hdr->contents; +- if (sym == NULL) +- { +- size_t symcnt = symtab_hdr->sh_info; +- if (elf_sym_hashes (opd_bfd) == NULL) +- symcnt = symtab_hdr->sh_size / symtab_hdr->sh_entsize; +- sym = bfd_elf_get_elf_syms (opd_bfd, symtab_hdr, symcnt, +- 0, NULL, NULL, NULL); +- if (sym == NULL) +- break; +- symtab_hdr->contents = (bfd_byte *) sym; +- } +- +- sym += symndx; +- val = sym->st_value; +- sec = bfd_section_from_elf_index (opd_bfd, sym->st_shndx); +- BFD_ASSERT ((sec->flags & SEC_MERGE) == 0); +- } +- else ++ if (symndx >= symtab_hdr->sh_info ++ && elf_sym_hashes (opd_bfd) != NULL) + { + struct elf_link_hash_entry **sym_hashes; + struct elf_link_hash_entry *rh; +@@ -5977,24 +5971,48 @@ + || rh->root.type == bfd_link_hash_defweak); + val = rh->root.u.def.value; + sec = rh->root.u.def.section; ++ if (sec->owner != opd_bfd) ++ { ++ sec = NULL; ++ val = (bfd_vma) -1; ++ } ++ } ++ } ++ ++ if (sec == NULL) ++ { ++ Elf_Internal_Sym *sym; ++ ++ if (symndx < symtab_hdr->sh_info) ++ { ++ sym = (Elf_Internal_Sym *) symtab_hdr->contents; ++ if (sym == NULL) ++ { ++ size_t symcnt = symtab_hdr->sh_info; ++ sym = bfd_elf_get_elf_syms (opd_bfd, symtab_hdr, ++ symcnt, 0, ++ NULL, NULL, NULL); ++ if (sym == NULL) ++ break; ++ symtab_hdr->contents = (bfd_byte *) sym; ++ } ++ sym += symndx; + } + else + { +- /* Handle the odd case where we can be called +- during bfd_elf_link_add_symbols before the +- symbol hashes have been fully populated. */ +- Elf_Internal_Sym *sym; +- +- sym = bfd_elf_get_elf_syms (opd_bfd, symtab_hdr, 1, +- symndx, NULL, NULL, NULL); ++ sym = bfd_elf_get_elf_syms (opd_bfd, symtab_hdr, ++ 1, symndx, ++ NULL, NULL, NULL); + if (sym == NULL) + break; +- +- val = sym->st_value; +- sec = bfd_section_from_elf_index (opd_bfd, sym->st_shndx); +- free (sym); + } ++ sec = bfd_section_from_elf_index (opd_bfd, sym->st_shndx); ++ if (sec == NULL) ++ break; ++ BFD_ASSERT ((sec->flags & SEC_MERGE) == 0); ++ val = sym->st_value; + } ++ + val += look->r_addend; + if (code_off != NULL) + *code_off = val; +@@ -6005,7 +6023,7 @@ + else + *code_sec = sec; + } +- if (sec != NULL && sec->output_section != NULL) ++ if (sec->output_section != NULL) + val += sec->output_section->vma + sec->output_offset; + } + break; diff --git a/SOURCES/binutils-rh1175624.patch b/SOURCES/binutils-rh1175624.patch new file mode 100644 index 0000000..4460d0a --- /dev/null +++ b/SOURCES/binutils-rh1175624.patch @@ -0,0 +1,191 @@ +Binary files a/bfd/.elf64-ppc.c.swp and b/bfd/.elf64-ppc.c.swp differ +diff -Nrup a/ld/emulparams/elf64ppc.sh b/ld/emulparams/elf64ppc.sh +--- a/ld/emulparams/elf64ppc.sh 2013-02-27 13:28:03.000000000 -0700 ++++ b/ld/emulparams/elf64ppc.sh 2015-03-27 14:03:16.832434850 -0600 +@@ -15,11 +15,8 @@ ARCH=powerpc:common64 + MACHINE= + NOP=0x60000000 + OTHER_TEXT_SECTIONS="*(.sfpr .glink)" +-BSS_PLT= +-OTHER_BSS_SYMBOLS=" ++OTHER_SDATA_SECTIONS=" + .tocbss ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { *(.tocbss)}" +-OTHER_PLT_RELOC_SECTIONS=" +- .rela.tocbss ${RELOCATING-0} : { *(.rela.tocbss) }" + + if test x${RELOCATING+set} = xset; then + GOT=" +@@ -34,11 +31,22 @@ INITIAL_RELOC_SECTIONS=" + .rela.opd ${RELOCATING-0} : { *(.rela.opd) }" + OTHER_GOT_RELOC_SECTIONS=" + .rela.toc ${RELOCATING-0} : { *(.rela.toc) } ++ .rela.toc1 ${RELOCATING-0} : { *(.rela.toc1) } ++ .rela.tocbss ${RELOCATING-0} : { *(.rela.tocbss) } + .rela.branch_lt ${RELOCATING-0} : { *(.rela.branch_lt) }" +-OTHER_READWRITE_SECTIONS=" +- .toc1 ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { *(.toc1) } ++OTHER_RELRO_SECTIONS_2=" + .opd ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { KEEP (*(.opd)) } ++ .toc1 ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { *(.toc1) } + .branch_lt ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { *(.branch_lt) }" ++# Put .got before .data ++DATA_GOT=" " ++# Always make .got read-only after relocation ++SEPARATE_GOTPLT=0 ++# Also put .sdata before .data ++DATA_SDATA=" " ++# and .plt/.iplt before .data ++DATA_PLT= ++PLT_BEFORE_GOT=" " + + # Treat a host that matches the target with the possible exception of "64" + # in the name as if it were native. +diff -Nrup a/ld/scripttempl/elf.sc b/ld/scripttempl/elf.sc +--- a/ld/scripttempl/elf.sc 2013-02-27 13:28:03.000000000 -0700 ++++ b/ld/scripttempl/elf.sc 2015-03-27 13:34:43.700386810 -0600 +@@ -14,6 +14,7 @@ + # (e.g., .PARISC.global) + # OTHER_RELRO_SECTIONS - other than .data.rel.ro ... + # (e.g. PPC32 .fixup, .got[12]) ++# OTHER_RELRO_SECTIONS_2 - as above, but after .dynamic in text segment + # OTHER_BSS_SECTIONS - other than .bss .sbss ... + # ATTRS_SECTIONS - at the end + # OTHER_SECTIONS - at the end +@@ -195,12 +196,12 @@ if test -z "${NO_SMALL_DATA}"; then + else + NO_SMALL_DATA=" " + fi +-if test -z "${DATA_GOT}"; then ++if test -z "${SDATA_GOT}${DATA_GOT}"; then + if test -n "${NO_SMALL_DATA}"; then + DATA_GOT=" " + fi + fi +-if test -z "${SDATA_GOT}"; then ++if test -z "${SDATA_GOT}${DATA_GOT}"; then + if test -z "${NO_SMALL_DATA}"; then + SDATA_GOT=" " + fi +@@ -593,10 +594,16 @@ cat <: +- ffffc: d503201f nop +- 100000: 58800000 ldr x0, 0 .* ++0000000000100004 <_start>: ++ 100004: d503201f nop ++ 100008: 58800000 ldr x0, 8 .* +diff --git a/ld/testsuite/ld-aarch64/emit-relocs-309-up.d b/ld/testsuite/ld-aarch64/emit-relocs-309-up.d +index a84c343..32922ee 100644 +--- a/ld/testsuite/ld-aarch64/emit-relocs-309-up.d ++++ b/ld/testsuite/ld-aarch64/emit-relocs-309-up.d +@@ -1,7 +1,7 @@ + #name: aarch64-emit-relocs-309-up + #source: emit-relocs-309.s + #as: +-#ld: -Ttext 0x0 --section-start .got=0x100000 ++#ld: -Ttext 0x0 --section-start .got=0xffff8 + #objdump: -dr + #... + +diff --git a/ld/testsuite/ld-aarch64/emit-relocs-311.d b/ld/testsuite/ld-aarch64/emit-relocs-311.d +index 5f1b47f..578d6d3 100644 +--- a/ld/testsuite/ld-aarch64/emit-relocs-311.d ++++ b/ld/testsuite/ld-aarch64/emit-relocs-311.d +@@ -10,5 +10,5 @@ + +1000c: R_AARCH64_ADR_PREL_PG_HI21 tempy2 + +10010: b0ffff91 adrp x17, 1000 + +10010: R_AARCH64_ADR_PREL_PG_HI21 tempy3 +- +10014: 90000083 adrp x3, 20000 ++ +10014: 90000083 adrp x3, 20000 <_GLOBAL_OFFSET_TABLE_> + +10014: R_AARCH64_ADR_GOT_PAGE gempy +diff --git a/ld/testsuite/ld-aarch64/emit-relocs-312.d b/ld/testsuite/ld-aarch64/emit-relocs-312.d +index 8d50d8d..c10dc1e 100644 +--- a/ld/testsuite/ld-aarch64/emit-relocs-312.d ++++ b/ld/testsuite/ld-aarch64/emit-relocs-312.d +@@ -10,10 +10,10 @@ + +1000c: R_AARCH64_LD_PREL_LO19 tempy2 + +10010: 58f89131 ldr x17, 1234 + +10010: R_AARCH64_LD_PREL_LO19 tempy3 +- +10014: f9400843 ldr x3, \[x2.* ++ +10014: f9400c43 ldr x3, \[x2.* + +10014: R_AARCH64_LD64_GOT_LO12_NC jempy +- +10018: f9400444 ldr x4, \[x2.* ++ +10018: f9400844 ldr x4, \[x2.* + +10018: R_AARCH64_LD64_GOT_LO12_NC gempy +- +1001c: f9400045 ldr x5, \[x2.* ++ +1001c: f9400445 ldr x5, \[x2.* + +1001c: R_AARCH64_LD64_GOT_LO12_NC lempy + +diff --git a/ld/testsuite/ld-aarch64/tls-desc-ie.d b/ld/testsuite/ld-aarch64/tls-desc-ie.d +index 712e39c..037da07 100644 +--- a/ld/testsuite/ld-aarch64/tls-desc-ie.d ++++ b/ld/testsuite/ld-aarch64/tls-desc-ie.d +@@ -3,18 +3,18 @@ + #objdump: -dr + #... + +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> +- +10004: 91002000 add x0, x0, #0x8 ++ +10004: 91004000 add x0, x0, #0x10 + +10008: 94000016 bl 10060 + +1000c: d503201f nop + +10010: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> +- +10014: f9400000 ldr x0, \[x0\] ++ +10014: f9400400 ldr x0, \[x0,#8\] + +10018: d503201f nop + +1001c: d503201f nop + +10020: d53bd041 mrs x1, tpidr_el0 + +10024: 8b000020 add x0, x1, x0 + +10028: d53bd042 mrs x2, tpidr_el0 + +1002c: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> +- +10030: f9400000 ldr x0, \[x0\] ++ +10030: f9400400 ldr x0, \[x0,#8\] + +10034: 8b000040 add x0, x2, x0 + +10038: b9400000 ldr w0, \[x0\] + +1003c: 0b000020 add w0, w1, w0 +@@ -24,13 +24,13 @@ Disassembly of section .plt: + 0000000000010040 <.plt>: + +10040: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + +10044: 90000090 adrp x16, 20000 <_GLOBAL_OFFSET_TABLE_> +- +10048: f9401611 ldr x17, \[x16,#40\] +- +1004c: 9100a210 add x16, x16, #0x28 ++ +10048: f9401a11 ldr x17, \[x16,#48\] ++ +1004c: 9100c210 add x16, x16, #0x30 + +10050: d61f0220 br x17 + +10054: d503201f nop + +10058: d503201f nop + +1005c: d503201f nop + +10060: 90000090 adrp x16, 20000 <_GLOBAL_OFFSET_TABLE_> +- +10064: f9401a11 ldr x17, \[x16,#48\] +- +10068: 9100c210 add x16, x16, #0x30 ++ +10064: f9401e11 ldr x17, \[x16,#56\] ++ +10068: 9100e210 add x16, x16, #0x38 + +1006c: d61f0220 br x17 +diff --git a/ld/testsuite/ld-aarch64/tls-relax-all.d b/ld/testsuite/ld-aarch64/tls-relax-all.d +index d3db04d..b36b634 100644 +--- a/ld/testsuite/ld-aarch64/tls-relax-all.d ++++ b/ld/testsuite/ld-aarch64/tls-relax-all.d +@@ -4,8 +4,8 @@ + #... + +10000: a9bf7bfd stp x29, x30, \[sp,#-16\]! + +10004: 910003fd mov x29, sp +- +10008: 90000080 adrp x0, 20000 +- +1000c: f9400000 ldr x0, \[x0\] ++ +10008: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> ++ +1000c: f9400400 ldr x0, \[x0,#8\] + +10010: d503201f nop + +10014: d503201f nop + +10018: d53bd041 mrs x1, tpidr_el0 +@@ -19,8 +19,8 @@ + +10038: 8b000040 add x0, x2, x0 + +1003c: b9400000 ldr w0, \[x0\] + +10040: 0b000021 add w1, w1, w0 +- +10044: 90000080 adrp x0, 20000 +- +10048: f9400400 ldr x0, \[x0,#8\] ++ +10044: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> ++ +10048: f9400800 ldr x0, \[x0,#16\] + +1004c: d53bd041 mrs x1, tpidr_el0 + +10050: 8b000020 add x0, x1, x0 + +10054: b9400000 ldr w0, \[x0\] +diff --git a/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d b/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d +index a142f54..d3783ac 100644 +--- a/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d ++++ b/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d +@@ -2,8 +2,8 @@ + #ld: -T relocs.ld -e0 + #objdump: -dr + #... +- +10000: 90000080 adrp x0, 20000 +- +10004: f9400000 ldr x0, \[x0\] ++ +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> ++ +10004: f9400400 ldr x0, \[x0,#8\] + +10008: d53bd041 mrs x1, tpidr_el0 + +1000c: 8b000020 add x0, x1, x0 + +10010: b9400000 ldr w0, \[x0\] +diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d +index f3307ae..92002de 100644 +--- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d ++++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d +@@ -2,9 +2,9 @@ + #ld: -T relocs.ld -e0 + #objdump: -dr + #... +- +10000: 90000080 adrp x0, 20000 ++ +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> + +10004: d503201f nop +- +10008: f9400000 ldr x0, \[x0\] ++ +10008: f9400400 ldr x0, \[x0,#8\] + +1000c: d503201f nop + +10010: d503201f nop + +10014: d503201f nop +diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d +index 691df06..634a55a 100644 +--- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d ++++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d +@@ -2,8 +2,8 @@ + #ld: -T relocs.ld -e0 + #objdump: -dr + #... +- +10000: 90000080 adrp x0, 20000 +- +10004: f9400000 ldr x0, \[x0\] ++ +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> ++ +10004: f9400400 ldr x0, \[x0,#8\] + +10008: d503201f nop + +1000c: d503201f nop + +10010: d53bd041 mrs x1, tpidr_el0 +diff --git a/ld/testsuite/ld-elf/eh5.d b/ld/testsuite/ld-elf/eh5.d +index f862382..1a5148c 100644 +--- a/ld/testsuite/ld-elf/eh5.d ++++ b/ld/testsuite/ld-elf/eh5.d +@@ -4,11 +4,11 @@ + #ld: + #readelf: -wf + #target: cfi +-#notarget: alpha* hppa64* tile* ++#notarget: alpha* hppa64* tile* visium* + + Contents of the .eh_frame section: + +-00000000 0000001[04] 00000000 CIE ++0+0000 0+001[04] 0+0000 CIE + Version: 1 + Augmentation: "zR" + Code alignment factor: .* +@@ -20,14 +20,14 @@ Contents of the .eh_frame section: + DW_CFA_nop + DW_CFA_nop + #... +-0000001[48] 00000014 0000001[8c] FDE cie=00000000 pc=.* ++0+001[48] 0+0014 0+001[8c] FDE cie=0+0000 pc=.* + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +-000000(2c|30) 00000014 00000000 CIE ++0+00(2c|30) 0+0014 0+0000 CIE + Version: 1 + Augmentation: "zPR" + Code alignment factor: .* +@@ -37,21 +37,21 @@ Contents of the .eh_frame section: + + DW_CFA_nop + +-0000004[48] 00000014 0000001c FDE cie=000000(2c|30) pc=.* ++0+004[48] 0+0014 0+001c FDE cie=0+00(2c|30) pc=.* + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +-000000(5c|60) 00000014 0000006[04] FDE cie=00000000 pc=.* ++0+00(5c|60) 0+0014 0+006[04] FDE cie=0+0000 pc=.* + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +-0000007[48] 0000001[8c] 00000000 CIE ++0+007[48] 0+001[8c] 0+0000 CIE + Version: 1 + Augmentation: "zPLR" + Code alignment factor: .* +@@ -63,16 +63,16 @@ Contents of the .eh_frame section: + DW_CFA_nop + DW_CFA_nop + #... +-0000009[08] 0000001c 0000002[04] FDE cie=0000007[48] pc=.* ++0+009[08] 0+001c 0+002[04] FDE cie=0+007[48] pc=.* + Augmentation data: (ef be ad de 00 00 00 00|00 00 00 00 de ad be ef) + + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +-000000b[08] 0000001[04] 00000000 CIE ++0+00b[08] 0+001[04] 0+0000 CIE + Version: 1 + Augmentation: "zR" + Code alignment factor: .* +@@ -80,14 +80,14 @@ Contents of the .eh_frame section: + Return address column: .* + Augmentation data: (0b|1b) + +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + #... +-000000(c4|d0) 0000001[04] 0000001[8c] FDE cie=000000b[08] pc=.* ++0+00(c4|d0) 0+001[04] 0+001[8c] FDE cie=0+00b[08] pc=.* + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + #... +-000000[de]8 00000014 00000000 CIE ++0+00[de]8 0+0014 0+0000 CIE + Version: 1 + Augmentation: "zPR" + Code alignment factor: .* +@@ -97,19 +97,19 @@ Contents of the .eh_frame section: + + DW_CFA_nop + +-00000(0f|10)0 00000014 0000001c FDE cie=000000[de]8 pc=.* ++0+0(0f|10)0 0+0014 0+001c FDE cie=0+00[de]8 pc=.* + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +-000001[01]8 0000001[04] 000000(5c|64) FDE cie=000000b[08] pc=.* ++0+01[01]8 0+001[04] 0+00(5c|64) FDE cie=0+00b[08] pc=.* + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + #... +-000001(1c|30) 0000001[8c] 00000000 CIE ++0+01(1c|30) 0+001[8c] 0+0000 CIE + Version: 1 + Augmentation: "zPLR" + Code alignment factor: .* +@@ -121,41 +121,41 @@ Contents of the .eh_frame section: + DW_CFA_nop + DW_CFA_nop + #... +-000001(38|50) 0000001c 0000002[04] FDE cie=000001(1c|30) pc=.* ++0+01(38|50) 0+001c 0+002[04] FDE cie=0+01(1c|30) pc=.* + Augmentation data: (ef be ad de 00 00 00 00|00 00 00 00 de ad be ef) + + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +-000001(58|70) 00000014 000001(5c|74) FDE cie=00000000 pc=.* ++0+01(58|70) 0+0014 0+01(5c|74) FDE cie=0+0000 pc=.* + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + #... +-000001(70|88) 00000014 00000(01c|148|15c) FDE cie=00000(02c|030|170) pc=.* ++0+01(70|88) 0+0014 0+0(01c|148|15c) FDE cie=0+0(02c|030|170) pc=.* + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +-000001(88|a0) 00000014 000001(8c|a4) FDE cie=00000000 pc=.* ++0+01(88|a0) 0+0014 0+01(8c|a4) FDE cie=0+0000 pc=.* + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + #... +-000001(a0|b8|d4) 0000001c 00000(020|130|144) FDE cie=00000(074|078|1b8) pc=.* ++0+01(a0|b8|d4) 0+001c 0+0(020|130|144) FDE cie=0+0(074|078|1b8) pc=.* + Augmentation data: (ef be ad de 00 00 00 00|00 00 00 00 de ad be ef) + + DW_CFA_advance_loc: 4 to .* +- DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16 ++ DW_CFA_def_cfa: r0(.*) ofs 16 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +diff --git a/ld/testsuite/ld-shared/shared.exp b/ld/testsuite/ld-shared/shared.exp +index 07fc881..7f418dc 100644 +--- a/ld/testsuite/ld-shared/shared.exp ++++ b/ld/testsuite/ld-shared/shared.exp +@@ -1,7 +1,5 @@ + # Expect script for ld-shared tests +-# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, +-# 2004, 2005, 2007, 2008, 2009, 2010, 2012 +-# Free Software Foundation, Inc. ++# Copyright (C) 1994-2015 Free Software Foundation, Inc. + # + # This file is part of the GNU Binutils. + # +@@ -111,8 +109,8 @@ if [istarget arm*-*-linux*] { + # the linker doesn't support when compiling -shared without -fpic. The + # test to find out whether we want to XFAIL the non-PIC tests requires + # a compile - so we pre-calculate it here. We also note that this can +- # only affect arm*-*-*eabi targets as the old ABI doesn't support v7. +- if [istarget arm*-*-*eabi] { ++ # only affect arm*-*-*eabi* targets as the old ABI doesn't support v7. ++ if [istarget arm*-*-*eabi*] { + set file [open $tmpdir/movw-detect.c w] + puts $file "void foo(void) { __asm (\"movw r0, #0\"); }" + close $file +@@ -246,6 +244,7 @@ if ![ld_compile "$CC $CFLAGS $SHCFLAG" $srcdir/$subdir/main.c $tmpdir/mainnp.o] + if [ string match $shared_needs_pic "yes" ] { + setup_xfail "arm*-*-linux*" + } ++ setup_xfail "aarch64*-*-linux*" + shared_test shnp "shared (non PIC)" mainnp.o sh1np.o sh2np.o shared + + # Test ELF shared library relocations with a non-zero load +@@ -272,6 +271,7 @@ if ![ld_compile "$CC $CFLAGS $SHCFLAG" $srcdir/$subdir/main.c $tmpdir/mainnp.o] + if [ string match $shared_needs_pic "yes" ] { + setup_xfail "arm*-*-linux*" + } ++ setup_xfail "aarch64*-*-linux*" + shared_test shnp "shared (non PIC, load offset)" \ + mainnp.o sh1np.o sh2np.o shared \ + "-T $srcdir/$subdir/elf-offset.ld" +@@ -328,6 +328,7 @@ if ![ld_compile "$CC $CFLAGS $SHCFLAG $picflag" $srcdir/$subdir/main.c $tmpdir/m + if [ string match $shared_needs_pic "yes" ] { + setup_xfail "arm*-*-linux*" + } ++ setup_xfail "aarch64*-*-linux*" + shared_test shmpnp "shared (PIC main, non PIC so)" mainp.o sh1np.o sh2np.o shared + } + } else { diff --git a/SOURCES/binutils-rh1182153.patch b/SOURCES/binutils-rh1182153.patch new file mode 100644 index 0000000..52930a6 --- /dev/null +++ b/SOURCES/binutils-rh1182153.patch @@ -0,0 +1,5412 @@ +diff -Nrup a/bfd/bfd-in2.h b/bfd/bfd-in2.h +--- a/bfd/bfd-in2.h 2015-05-04 15:06:06.275747019 -0600 ++++ b/bfd/bfd-in2.h 2015-05-04 15:13:38.612180994 -0600 +@@ -4301,12 +4301,24 @@ in .byte hlo8(symbol) */ + /* 16 bit GOT offset. */ + BFD_RELOC_390_GOT16, + ++/* PC relative 12 bit shifted by 1. */ ++ BFD_RELOC_390_PC12DBL, ++ ++/* 12 bit PC rel. PLT shifted by 1. */ ++ BFD_RELOC_390_PLT12DBL, ++ + /* PC relative 16 bit shifted by 1. */ + BFD_RELOC_390_PC16DBL, + + /* 16 bit PC rel. PLT shifted by 1. */ + BFD_RELOC_390_PLT16DBL, + ++/* PC relative 24 bit shifted by 1. */ ++ BFD_RELOC_390_PC24DBL, ++ ++/* 24 bit PC rel. PLT shifted by 1. */ ++ BFD_RELOC_390_PLT24DBL, ++ + /* PC relative 32 bit shifted by 1. */ + BFD_RELOC_390_PC32DBL, + +diff -Nrup a/bfd/cpu-s390.c b/bfd/cpu-s390.c +--- a/bfd/cpu-s390.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/bfd/cpu-s390.c 2015-05-04 15:15:27.186883101 -0600 +@@ -23,44 +23,31 @@ + #include "bfd.h" + #include "libbfd.h" + +-const bfd_arch_info_type bfd_s390_64_arch = +-{ +- 64, /* bits in a word */ +- 64, /* bits in an address */ +- 8, /* bits in a byte */ +- bfd_arch_s390, +- bfd_mach_s390_64, +- "s390", +- "s390:64-bit", +- 3, /* section alignment power */ +-#if BFD_DEFAULT_TARGET_SIZE == 64 +- TRUE, /* the default */ +-#else +- FALSE, /* the default */ +-#endif +- bfd_default_compatible, +- bfd_default_scan, +- bfd_arch_default_fill, +- NULL +-}; ++#define N(bits, number, print, is_default, next) \ ++ { \ ++ bits, /* bits in a word */ \ ++ bits, /* bits in an address */ \ ++ 8, /* bits in a byte */ \ ++ bfd_arch_s390, \ ++ number, \ ++ "s390", \ ++ print, \ ++ 3, /* section alignment power */ \ ++ is_default, \ ++ bfd_default_compatible, \ ++ bfd_default_scan, \ ++ bfd_arch_default_fill, \ ++ next \ ++ } + +-const bfd_arch_info_type bfd_s390_arch = +-{ +- 32, /* bits in a word */ +- 32, /* bits in an address */ +- 8, /* bits in a byte */ +- bfd_arch_s390, +- bfd_mach_s390_31, +- "s390", +- "s390:31-bit", +- 3, /* section alignment power */ + #if BFD_DEFAULT_TARGET_SIZE == 64 +- FALSE, /* the default */ ++static const bfd_arch_info_type bfd_s390_31_arch = ++ N (32, bfd_mach_s390_31, "s390:31-bit", FALSE, NULL); ++const bfd_arch_info_type bfd_s390_arch = ++ N (64, bfd_mach_s390_64, "s390:64-bit", TRUE, &bfd_s390_31_arch); + #else +- TRUE, /* the default */ ++static const bfd_arch_info_type bfd_s390_64_arch = ++ N (64, bfd_mach_s390_64, "s390:64-bit", FALSE, NULL); ++const bfd_arch_info_type bfd_s390_arch = ++ N (32, bfd_mach_s390_31, "s390:31-bit", TRUE, &bfd_s390_64_arch); + #endif +- bfd_default_compatible, +- bfd_default_scan, +- bfd_arch_default_fill, +- &bfd_s390_64_arch +-}; +diff -Nrup a/bfd/elf-bfd.h b/bfd/elf-bfd.h +--- a/bfd/elf-bfd.h 2015-05-04 15:06:06.281746893 -0600 ++++ b/bfd/elf-bfd.h 2015-05-04 15:15:23.107969428 -0600 +@@ -2315,6 +2315,10 @@ extern char *elfcore_write_s390_system_c + (bfd *, char *, int *, const void *, int); + extern char *elfcore_write_s390_tdb + (bfd *, char *, int *, const void *, int); ++extern char *elfcore_write_s390_vxrs_low ++ (bfd *, char *, int *, const void *, int); ++extern char *elfcore_write_s390_vxrs_high ++ (bfd *, char *, int *, const void *, int); + extern char *elfcore_write_arm_vfp + (bfd *, char *, int *, const void *, int); + extern char *elfcore_write_aarch_tls +diff -Nrup a/bfd/elf.c b/bfd/elf.c +--- a/bfd/elf.c 2015-05-04 15:06:06.663738829 -0600 ++++ b/bfd/elf.c 2015-05-04 15:15:23.109969386 -0600 +@@ -8293,6 +8293,18 @@ elfcore_grok_s390_tdb (bfd *abfd, Elf_In + } + + static bfd_boolean ++elfcore_grok_s390_vxrs_low (bfd *abfd, Elf_Internal_Note *note) ++{ ++ return elfcore_make_note_pseudosection (abfd, ".reg-s390-vxrs-low", note); ++} ++ ++static bfd_boolean ++elfcore_grok_s390_vxrs_high (bfd *abfd, Elf_Internal_Note *note) ++{ ++ return elfcore_make_note_pseudosection (abfd, ".reg-s390-vxrs-high", note); ++} ++ ++static bfd_boolean + elfcore_grok_arm_vfp (bfd *abfd, Elf_Internal_Note *note) + { + return elfcore_make_note_pseudosection (abfd, ".reg-arm-vfp", note); +@@ -8756,6 +8768,20 @@ elfcore_grok_note (bfd *abfd, Elf_Intern + else + return TRUE; + ++ case NT_S390_VXRS_LOW: ++ if (note->namesz == 6 ++ && strcmp (note->namedata, "LINUX") == 0) ++ return elfcore_grok_s390_vxrs_low (abfd, note); ++ else ++ return TRUE; ++ ++ case NT_S390_VXRS_HIGH: ++ if (note->namesz == 6 ++ && strcmp (note->namedata, "LINUX") == 0) ++ return elfcore_grok_s390_vxrs_high (abfd, note); ++ else ++ return TRUE; ++ + case NT_ARM_VFP: + if (note->namesz == 6 + && strcmp (note->namedata, "LINUX") == 0) +@@ -9622,6 +9648,31 @@ elfcore_write_s390_tdb (bfd *abfd, + } + + char * ++elfcore_write_s390_vxrs_low (bfd *abfd, ++ char *buf, ++ int *bufsiz, ++ const void *s390_vxrs_low, ++ int size) ++{ ++ char *note_name = "LINUX"; ++ return elfcore_write_note (abfd, buf, bufsiz, ++ note_name, NT_S390_VXRS_LOW, s390_vxrs_low, size); ++} ++ ++char * ++elfcore_write_s390_vxrs_high (bfd *abfd, ++ char *buf, ++ int *bufsiz, ++ const void *s390_vxrs_high, ++ int size) ++{ ++ char *note_name = "LINUX"; ++ return elfcore_write_note (abfd, buf, bufsiz, ++ note_name, NT_S390_VXRS_HIGH, ++ s390_vxrs_high, size); ++} ++ ++char * + elfcore_write_arm_vfp (bfd *abfd, + char *buf, + int *bufsiz, +@@ -9705,6 +9756,10 @@ elfcore_write_register_note (bfd *abfd, + return elfcore_write_s390_system_call (abfd, buf, bufsiz, data, size); + if (strcmp (section, ".reg-s390-tdb") == 0) + return elfcore_write_s390_tdb (abfd, buf, bufsiz, data, size); ++ if (strcmp (section, ".reg-s390-vxrs-low") == 0) ++ return elfcore_write_s390_vxrs_low (abfd, buf, bufsiz, data, size); ++ if (strcmp (section, ".reg-s390-vxrs-high") == 0) ++ return elfcore_write_s390_vxrs_high (abfd, buf, bufsiz, data, size); + if (strcmp (section, ".reg-arm-vfp") == 0) + return elfcore_write_arm_vfp (abfd, buf, bufsiz, data, size); + if (strcmp (section, ".reg-aarch-tls") == 0) +diff -Nrup a/bfd/elf32-s390.c b/bfd/elf32-s390.c +--- a/bfd/elf32-s390.c 2015-05-04 15:06:06.666738766 -0600 ++++ b/bfd/elf32-s390.c 2015-05-04 15:13:44.590054477 -0600 +@@ -40,7 +40,7 @@ static reloc_howto_type elf_howto_table[ + { + HOWTO (R_390_NONE, /* type */ + 0, /* rightshift */ +- 0, /* size (0 = byte, 1 = short, 2 = long) */ ++ 0, /* size (0 = byte, 1 = 2 byte, 2 = 4 byte) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ +@@ -161,6 +161,14 @@ static reloc_howto_type elf_howto_table[ + s390_elf_ldisp_reloc, "R_390_TLS_GOTIE20", FALSE, 0,0x0fffff00, FALSE), + HOWTO(R_390_IRELATIVE, 0, 2, 32, TRUE, 0, complain_overflow_bitfield, + bfd_elf_generic_reloc, "R_390_IRELATIVE", FALSE, 0, 0xffffffff, FALSE), ++ HOWTO(R_390_PC12DBL, 1, 1, 12, TRUE, 0, complain_overflow_bitfield, ++ bfd_elf_generic_reloc, "R_390_PC12DBL", FALSE, 0,0x00000fff, TRUE), ++ HOWTO(R_390_PLT12DBL, 1, 1, 12, TRUE, 0, complain_overflow_bitfield, ++ bfd_elf_generic_reloc, "R_390_PLT12DBL", FALSE, 0,0x00000fff, TRUE), ++ HOWTO(R_390_PC24DBL, 1, 2, 24, TRUE, 0, complain_overflow_bitfield, ++ bfd_elf_generic_reloc, "R_390_PC24DBL", FALSE, 0,0x00ffffff, TRUE), ++ HOWTO(R_390_PLT24DBL, 1, 2, 24, TRUE, 0, complain_overflow_bitfield, ++ bfd_elf_generic_reloc, "R_390_PLT24DBL", FALSE, 0,0x00ffffff, TRUE), + }; + + /* GNU extension to record C++ vtable hierarchy. */ +@@ -211,10 +219,18 @@ elf_s390_reloc_type_lookup (bfd *abfd AT + return &elf_howto_table[(int) R_390_GOT16]; + case BFD_RELOC_16_PCREL: + return &elf_howto_table[(int) R_390_PC16]; ++ case BFD_RELOC_390_PC12DBL: ++ return &elf_howto_table[(int) R_390_PC12DBL]; ++ case BFD_RELOC_390_PLT12DBL: ++ return &elf_howto_table[(int) R_390_PLT12DBL]; + case BFD_RELOC_390_PC16DBL: + return &elf_howto_table[(int) R_390_PC16DBL]; + case BFD_RELOC_390_PLT16DBL: + return &elf_howto_table[(int) R_390_PLT16DBL]; ++ case BFD_RELOC_390_PC24DBL: ++ return &elf_howto_table[(int) R_390_PC24DBL]; ++ case BFD_RELOC_390_PLT24DBL: ++ return &elf_howto_table[(int) R_390_PLT24DBL]; + case BFD_RELOC_390_PC32DBL: + return &elf_howto_table[(int) R_390_PC32DBL]; + case BFD_RELOC_390_PLT32DBL: +@@ -1103,7 +1119,9 @@ elf_s390_check_relocs (bfd *abfd, + are done. */ + break; + ++ case R_390_PLT12DBL: + case R_390_PLT16DBL: ++ case R_390_PLT24DBL: + case R_390_PLT32DBL: + case R_390_PLT32: + case R_390_PLTOFF16: +@@ -1244,7 +1262,9 @@ elf_s390_check_relocs (bfd *abfd, + case R_390_16: + case R_390_32: + case R_390_PC16: ++ case R_390_PC12DBL: + case R_390_PC16DBL: ++ case R_390_PC24DBL: + case R_390_PC32DBL: + case R_390_PC32: + if (h != NULL) +@@ -1289,7 +1309,9 @@ elf_s390_check_relocs (bfd *abfd, + if ((info->shared + && (sec->flags & SEC_ALLOC) != 0 + && ((ELF32_R_TYPE (rel->r_info) != R_390_PC16 ++ && ELF32_R_TYPE (rel->r_info) != R_390_PC12DBL + && ELF32_R_TYPE (rel->r_info) != R_390_PC16DBL ++ && ELF32_R_TYPE (rel->r_info) != R_390_PC24DBL + && ELF32_R_TYPE (rel->r_info) != R_390_PC32DBL + && ELF32_R_TYPE (rel->r_info) != R_390_PC32) + || (h != NULL +@@ -1366,7 +1388,9 @@ elf_s390_check_relocs (bfd *abfd, + + p->count += 1; + if (ELF32_R_TYPE (rel->r_info) == R_390_PC16 ++ || ELF32_R_TYPE (rel->r_info) == R_390_PC12DBL + || ELF32_R_TYPE (rel->r_info) == R_390_PC16DBL ++ || ELF32_R_TYPE (rel->r_info) == R_390_PC24DBL + || ELF32_R_TYPE (rel->r_info) == R_390_PC32DBL + || ELF32_R_TYPE (rel->r_info) == R_390_PC32) + p->pc_count += 1; +@@ -1533,14 +1557,18 @@ elf_s390_gc_sweep_hook (bfd *abfd, + case R_390_20: + case R_390_32: + case R_390_PC16: ++ case R_390_PC12DBL: + case R_390_PC16DBL: ++ case R_390_PC24DBL: + case R_390_PC32DBL: + case R_390_PC32: + if (info->shared) + break; + /* Fall through. */ + ++ case R_390_PLT12DBL: + case R_390_PLT16DBL: ++ case R_390_PLT24DBL: + case R_390_PLT32DBL: + case R_390_PLT32: + case R_390_PLTOFF16: +@@ -2511,6 +2539,36 @@ elf_s390_relocate_section (bfd *output_b + base_got->contents + off); + h->got.offset |= 1; + } ++ ++ if ((h->def_regular ++ && info->shared ++ && SYMBOL_REFERENCES_LOCAL (info, h)) ++ /* lrl rx,sym@GOTENT -> larl rx, sym */ ++ && ((r_type == R_390_GOTENT ++ && (bfd_get_16 (input_bfd, ++ contents + rel->r_offset - 2) ++ & 0xff0f) == 0xc40d) ++ /* ly rx, sym@GOT(r12) -> larl rx, sym */ ++ || (r_type == R_390_GOT20 ++ && (bfd_get_32 (input_bfd, ++ contents + rel->r_offset - 2) ++ & 0xff00f000) == 0xe300c000 ++ && bfd_get_8 (input_bfd, ++ contents + rel->r_offset + 3) == 0x58))) ++ { ++ unsigned short new_insn = ++ (0xc000 | (bfd_get_8 (input_bfd, ++ contents + rel->r_offset - 1) & 0xf0)); ++ bfd_put_16 (output_bfd, new_insn, ++ contents + rel->r_offset - 2); ++ r_type = R_390_PC32DBL; ++ rel->r_addend = 2; ++ howto = elf_howto_table + r_type; ++ relocation = h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset; ++ goto do_relocation; ++ } + } + else + unresolved_reloc = FALSE; +@@ -2591,7 +2649,9 @@ elf_s390_relocate_section (bfd *output_b + unresolved_reloc = FALSE; + break; + ++ case R_390_PLT12DBL: + case R_390_PLT16DBL: ++ case R_390_PLT24DBL: + case R_390_PLT32DBL: + case R_390_PLT32: + /* Relocation is to the entry for this symbol in the +@@ -2654,7 +2714,9 @@ elf_s390_relocate_section (bfd *output_b + case R_390_16: + case R_390_32: + case R_390_PC16: ++ case R_390_PC12DBL: + case R_390_PC16DBL: ++ case R_390_PC24DBL: + case R_390_PC32DBL: + case R_390_PC32: + if (h != NULL +@@ -2726,7 +2788,9 @@ elf_s390_relocate_section (bfd *output_b + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak) + && ((r_type != R_390_PC16 ++ && r_type != R_390_PC12DBL + && r_type != R_390_PC16DBL ++ && r_type != R_390_PC24DBL + && r_type != R_390_PC32DBL + && r_type != R_390_PC32) + || !SYMBOL_CALLS_LOCAL (info, h))) +@@ -2767,7 +2831,9 @@ elf_s390_relocate_section (bfd *output_b + else if (h != NULL + && h->dynindx != -1 + && (r_type == R_390_PC16 ++ || r_type == R_390_PC12DBL + || r_type == R_390_PC16DBL ++ || r_type == R_390_PC24DBL + || r_type == R_390_PC32DBL + || r_type == R_390_PC32 + || !info->shared +@@ -3245,6 +3311,13 @@ elf_s390_relocate_section (bfd *output_b + + do_relocation: + ++ /* When applying a 24 bit reloc we need to start one byte ++ earlier. Otherwise the 32 bit get/put bfd operations might ++ access a byte after the actual section. */ ++ if (r_type == R_390_PC24DBL ++ || r_type == R_390_PLT24DBL) ++ rel->r_offset--; ++ + if (r_type == R_390_20 + || r_type == R_390_GOT20 + || r_type == R_390_GOTPLT20 +diff -Nrup a/bfd/elf64-s390.c b/bfd/elf64-s390.c +--- a/bfd/elf64-s390.c 2015-05-04 15:06:06.667738744 -0600 ++++ b/bfd/elf64-s390.c 2015-05-04 15:13:44.591054456 -0600 +@@ -43,7 +43,7 @@ static reloc_howto_type elf_howto_table[ + { + HOWTO (R_390_NONE, /* type */ + 0, /* rightshift */ +- 0, /* size (0 = byte, 1 = short, 2 = long) */ ++ 0, /* size (0 = byte, 1 = 2 byte, 2 = 4 byte) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ +@@ -171,7 +171,14 @@ static reloc_howto_type elf_howto_table[ + s390_elf_ldisp_reloc, "R_390_TLS_GOTIE20", FALSE, 0,0x0fffff00, FALSE), + HOWTO(R_390_IRELATIVE, 0, 4, 64, FALSE, 0, complain_overflow_bitfield, + bfd_elf_generic_reloc, "R_390_IRELATIVE", FALSE, 0, MINUS_ONE, FALSE), +- ++ HOWTO(R_390_PC12DBL, 1, 1, 12, TRUE, 0, complain_overflow_bitfield, ++ bfd_elf_generic_reloc, "R_390_PC12DBL", FALSE, 0,0x00000fff, TRUE), ++ HOWTO(R_390_PLT12DBL, 1, 1, 12, TRUE, 0, complain_overflow_bitfield, ++ bfd_elf_generic_reloc, "R_390_PLT12DBL", FALSE, 0,0x00000fff, TRUE), ++ HOWTO(R_390_PC24DBL, 1, 2, 24, TRUE, 0, complain_overflow_bitfield, ++ bfd_elf_generic_reloc, "R_390_PC24DBL", FALSE, 0,0x00ffffff, TRUE), ++ HOWTO(R_390_PLT24DBL, 1, 2, 24, TRUE, 0, complain_overflow_bitfield, ++ bfd_elf_generic_reloc, "R_390_PLT24DBL", FALSE, 0,0x00ffffff, TRUE), + }; + + /* GNU extension to record C++ vtable hierarchy. */ +@@ -222,10 +229,18 @@ elf_s390_reloc_type_lookup (bfd *abfd AT + return &elf_howto_table[(int) R_390_GOT16]; + case BFD_RELOC_16_PCREL: + return &elf_howto_table[(int) R_390_PC16]; ++ case BFD_RELOC_390_PC12DBL: ++ return &elf_howto_table[(int) R_390_PC12DBL]; ++ case BFD_RELOC_390_PLT12DBL: ++ return &elf_howto_table[(int) R_390_PLT12DBL]; + case BFD_RELOC_390_PC16DBL: + return &elf_howto_table[(int) R_390_PC16DBL]; + case BFD_RELOC_390_PLT16DBL: + return &elf_howto_table[(int) R_390_PLT16DBL]; ++ case BFD_RELOC_390_PC24DBL: ++ return &elf_howto_table[(int) R_390_PC24DBL]; ++ case BFD_RELOC_390_PLT24DBL: ++ return &elf_howto_table[(int) R_390_PLT24DBL]; + case BFD_RELOC_390_PC32DBL: + return &elf_howto_table[(int) R_390_PC32DBL]; + case BFD_RELOC_390_PLT32DBL: +@@ -1033,7 +1048,9 @@ elf_s390_check_relocs (bfd *abfd, + are done. */ + break; + ++ case R_390_PLT12DBL: + case R_390_PLT16DBL: ++ case R_390_PLT24DBL: + case R_390_PLT32: + case R_390_PLT32DBL: + case R_390_PLT64: +@@ -1178,8 +1195,10 @@ elf_s390_check_relocs (bfd *abfd, + case R_390_16: + case R_390_32: + case R_390_64: ++ case R_390_PC12DBL: + case R_390_PC16: + case R_390_PC16DBL: ++ case R_390_PC24DBL: + case R_390_PC32: + case R_390_PC32DBL: + case R_390_PC64: +@@ -1225,7 +1244,9 @@ elf_s390_check_relocs (bfd *abfd, + if ((info->shared + && (sec->flags & SEC_ALLOC) != 0 + && ((ELF64_R_TYPE (rel->r_info) != R_390_PC16 ++ && ELF64_R_TYPE (rel->r_info) != R_390_PC12DBL + && ELF64_R_TYPE (rel->r_info) != R_390_PC16DBL ++ && ELF64_R_TYPE (rel->r_info) != R_390_PC24DBL + && ELF64_R_TYPE (rel->r_info) != R_390_PC32 + && ELF64_R_TYPE (rel->r_info) != R_390_PC32DBL + && ELF64_R_TYPE (rel->r_info) != R_390_PC64) +@@ -1302,6 +1323,8 @@ elf_s390_check_relocs (bfd *abfd, + + p->count += 1; + if (ELF64_R_TYPE (rel->r_info) == R_390_PC16 ++ || ELF64_R_TYPE (rel->r_info) == R_390_PC12DBL ++ || ELF64_R_TYPE (rel->r_info) == R_390_PC16DBL + || ELF64_R_TYPE (rel->r_info) == R_390_PC16DBL + || ELF64_R_TYPE (rel->r_info) == R_390_PC32 + || ELF64_R_TYPE (rel->r_info) == R_390_PC32DBL +@@ -1473,7 +1496,9 @@ elf_s390_gc_sweep_hook (bfd *abfd, + case R_390_32: + case R_390_64: + case R_390_PC16: ++ case R_390_PC12DBL: + case R_390_PC16DBL: ++ case R_390_PC24DBL: + case R_390_PC32: + case R_390_PC32DBL: + case R_390_PC64: +@@ -1481,7 +1506,9 @@ elf_s390_gc_sweep_hook (bfd *abfd, + break; + /* Fall through */ + ++ case R_390_PLT12DBL: + case R_390_PLT16DBL: ++ case R_390_PLT24DBL: + case R_390_PLT32: + case R_390_PLT32DBL: + case R_390_PLT64: +@@ -2472,6 +2499,37 @@ elf_s390_relocate_section (bfd *output_b + base_got->contents + off); + h->got.offset |= 1; + } ++ ++ if ((h->def_regular ++ && info->shared ++ && SYMBOL_REFERENCES_LOCAL (info, h)) ++ /* lgrl rx,sym@GOTENT -> larl rx, sym */ ++ && ((r_type == R_390_GOTENT ++ && (bfd_get_16 (input_bfd, ++ contents + rel->r_offset - 2) ++ & 0xff0f) == 0xc408) ++ /* lg rx, sym@GOT(r12) -> larl rx, sym */ ++ || (r_type == R_390_GOT20 ++ && (bfd_get_32 (input_bfd, ++ contents + rel->r_offset - 2) ++ & 0xff00f000) == 0xe300c000 ++ && bfd_get_8 (input_bfd, ++ contents + rel->r_offset + 3) == 0x04))) ++ ++ { ++ unsigned short new_insn = ++ (0xc000 | (bfd_get_8 (input_bfd, ++ contents + rel->r_offset - 1) & 0xf0)); ++ bfd_put_16 (output_bfd, new_insn, ++ contents + rel->r_offset - 2); ++ r_type = R_390_PC32DBL; ++ rel->r_addend = 2; ++ howto = elf_howto_table + r_type; ++ relocation = h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset; ++ goto do_relocation; ++ } + } + else + unresolved_reloc = FALSE; +@@ -2553,7 +2611,9 @@ elf_s390_relocate_section (bfd *output_b + unresolved_reloc = FALSE; + break; + ++ case R_390_PLT12DBL: + case R_390_PLT16DBL: ++ case R_390_PLT24DBL: + case R_390_PLT32: + case R_390_PLT32DBL: + case R_390_PLT64: +@@ -2618,7 +2678,9 @@ elf_s390_relocate_section (bfd *output_b + case R_390_32: + case R_390_64: + case R_390_PC16: ++ case R_390_PC12DBL: + case R_390_PC16DBL: ++ case R_390_PC24DBL: + case R_390_PC32: + case R_390_PC32DBL: + case R_390_PC64: +@@ -2692,7 +2754,9 @@ elf_s390_relocate_section (bfd *output_b + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak) + && ((r_type != R_390_PC16 ++ && r_type != R_390_PC12DBL + && r_type != R_390_PC16DBL ++ && r_type != R_390_PC24DBL + && r_type != R_390_PC32 + && r_type != R_390_PC32DBL + && r_type != R_390_PC64) +@@ -2734,7 +2798,9 @@ elf_s390_relocate_section (bfd *output_b + else if (h != NULL + && h->dynindx != -1 + && (r_type == R_390_PC16 ++ || r_type == R_390_PC12DBL + || r_type == R_390_PC16DBL ++ || r_type == R_390_PC24DBL + || r_type == R_390_PC32 + || r_type == R_390_PC32DBL + || r_type == R_390_PC64 +@@ -3171,6 +3237,13 @@ elf_s390_relocate_section (bfd *output_b + + do_relocation: + ++ /* When applying a 24 bit reloc we need to start one byte ++ earlier. Otherwise the 32 bit get/put bfd operations might ++ access a byte after the actual section. */ ++ if (r_type == R_390_PC24DBL ++ || r_type == R_390_PLT24DBL) ++ rel->r_offset--; ++ + if (r_type == R_390_20 + || r_type == R_390_GOT20 + || r_type == R_390_GOTPLT20 +diff -Nrup a/bfd/libbfd.h b/bfd/libbfd.h +--- a/bfd/libbfd.h 2013-02-27 13:28:03.000000000 -0700 ++++ b/bfd/libbfd.h 2015-05-04 15:13:38.614180951 -0600 +@@ -2006,8 +2006,12 @@ static const char *const bfd_reloc_code_ + "BFD_RELOC_390_RELATIVE", + "BFD_RELOC_390_GOTPC", + "BFD_RELOC_390_GOT16", ++ "BFD_RELOC_390_PC12DBL", ++ "BFD_RELOC_390_PLT12DBL", + "BFD_RELOC_390_PC16DBL", + "BFD_RELOC_390_PLT16DBL", ++ "BFD_RELOC_390_PC24DBL", ++ "BFD_RELOC_390_PLT24DBL", + "BFD_RELOC_390_PC32DBL", + "BFD_RELOC_390_PLT32DBL", + "BFD_RELOC_390_GOTPCDBL", +diff -Nrup a/bfd/reloc.c b/bfd/reloc.c +--- a/bfd/reloc.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/bfd/reloc.c 2015-05-04 15:13:50.108937674 -0600 +@@ -4657,6 +4657,14 @@ ENUM + ENUMDOC + 16 bit GOT offset. + ENUM ++ BFD_RELOC_390_PC12DBL ++ENUMDOC ++ PC relative 12 bit shifted by 1. ++ENUM ++ BFD_RELOC_390_PLT12DBL ++ENUMDOC ++ 12 bit PC rel. PLT shifted by 1. ++ENUM + BFD_RELOC_390_PC16DBL + ENUMDOC + PC relative 16 bit shifted by 1. +@@ -4665,6 +4673,14 @@ ENUM + ENUMDOC + 16 bit PC rel. PLT shifted by 1. + ENUM ++ BFD_RELOC_390_PC24DBL ++ENUMDOC ++ PC relative 24 bit shifted by 1. ++ENUM ++ BFD_RELOC_390_PLT24DBL ++ENUMDOC ++ 24 bit PC rel. PLT shifted by 1. ++ENUM + BFD_RELOC_390_PC32DBL + ENUMDOC + PC relative 32 bit shifted by 1. +@@ -5686,7 +5702,7 @@ ENUMX + BFD_RELOC_NIOS2_HIADJ16 + ENUMX + BFD_RELOC_NIOS2_GPREL +-ENUMX ++ENUMX + BFD_RELOC_NIOS2_UJMP + ENUMX + BFD_RELOC_NIOS2_CJMP +diff -Nrup a/binutils/readelf.c b/binutils/readelf.c +--- a/binutils/readelf.c 2015-05-04 15:06:06.283746851 -0600 ++++ b/binutils/readelf.c 2015-05-04 15:15:23.111969343 -0600 +@@ -12850,6 +12850,10 @@ get_note_type (unsigned e_type) + return _("NT_S390_SYSTEM_CALL (s390 system call restart data)"); + case NT_S390_TDB: + return _("NT_S390_TDB (s390 transaction diagnostic block)"); ++ case NT_S390_VXRS_LOW: ++ return _("NT_S390_VXRS_LOW (s390 vector registers 0-15 upper half)"); ++ case NT_S390_VXRS_HIGH: ++ return _("NT_S390_VXRS_HIGH (s390 vector registers 16-31)"); + case NT_ARM_VFP: + return _("NT_ARM_VFP (arm VFP registers)"); + case NT_ARM_TLS: +diff -Nrup a/gas/config/tc-s390.c b/gas/config/tc-s390.c +--- a/gas/config/tc-s390.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/config/tc-s390.c 2015-05-04 15:15:30.842805727 -0600 +@@ -110,138 +110,35 @@ const pseudo_typeS md_pseudo_table[] = + { NULL, NULL, 0 } + }; + +- +-/* Structure to hold information about predefined registers. */ +-struct pd_reg +- { +- char *name; +- int value; +- }; +- +-/* List of registers that are pre-defined: +- +- Each access register has a predefined name of the form: +- a which has the value . +- +- Each control register has a predefined name of the form: +- c which has the value . +- +- Each general register has a predefined name of the form: +- r which has the value . +- +- Each floating point register a has predefined name of the form: +- f which has the value . +- +- There are individual registers as well: +- sp has the value 15 +- lit has the value 12 +- +- The table is sorted. Suitable for searching by a binary search. */ +- +-static const struct pd_reg pre_defined_registers[] = +-{ +- { "a0", 0 }, /* Access registers */ +- { "a1", 1 }, +- { "a10", 10 }, +- { "a11", 11 }, +- { "a12", 12 }, +- { "a13", 13 }, +- { "a14", 14 }, +- { "a15", 15 }, +- { "a2", 2 }, +- { "a3", 3 }, +- { "a4", 4 }, +- { "a5", 5 }, +- { "a6", 6 }, +- { "a7", 7 }, +- { "a8", 8 }, +- { "a9", 9 }, +- +- { "c0", 0 }, /* Control registers */ +- { "c1", 1 }, +- { "c10", 10 }, +- { "c11", 11 }, +- { "c12", 12 }, +- { "c13", 13 }, +- { "c14", 14 }, +- { "c15", 15 }, +- { "c2", 2 }, +- { "c3", 3 }, +- { "c4", 4 }, +- { "c5", 5 }, +- { "c6", 6 }, +- { "c7", 7 }, +- { "c8", 8 }, +- { "c9", 9 }, +- +- { "f0", 0 }, /* Floating point registers */ +- { "f1", 1 }, +- { "f10", 10 }, +- { "f11", 11 }, +- { "f12", 12 }, +- { "f13", 13 }, +- { "f14", 14 }, +- { "f15", 15 }, +- { "f2", 2 }, +- { "f3", 3 }, +- { "f4", 4 }, +- { "f5", 5 }, +- { "f6", 6 }, +- { "f7", 7 }, +- { "f8", 8 }, +- { "f9", 9 }, +- +- { "lit", 13 }, /* Pointer to literal pool */ +- +- { "r0", 0 }, /* General purpose registers */ +- { "r1", 1 }, +- { "r10", 10 }, +- { "r11", 11 }, +- { "r12", 12 }, +- { "r13", 13 }, +- { "r14", 14 }, +- { "r15", 15 }, +- { "r2", 2 }, +- { "r3", 3 }, +- { "r4", 4 }, +- { "r5", 5 }, +- { "r6", 6 }, +- { "r7", 7 }, +- { "r8", 8 }, +- { "r9", 9 }, +- +- { "sp", 15 }, /* Stack pointer */ +- +-}; +- +-#define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg)) +- + /* Given NAME, find the register number associated with that name, return + the integer value associated with the given name or -1 on failure. */ + + static int +-reg_name_search (const struct pd_reg *regs, int regcount, const char *name) ++reg_name_search (const char *name) + { +- int middle, low, high; +- int cmp; ++ int val = -1; + +- low = 0; +- high = regcount - 1; ++ if (strcasecmp (name, "lit") == 0) ++ return 13; + +- do ++ if (strcasecmp (name, "sp") == 0) ++ return 15; ++ ++ if (name[0] != 'a' && name[0] != 'c' && name[0] != 'f' ++ && name[0] != 'r' && name[0] != 'v') ++ return -1; ++ ++ if (ISDIGIT (name[1])) + { +- middle = (low + high) / 2; +- cmp = strcasecmp (name, regs[middle].name); +- if (cmp < 0) +- high = middle - 1; +- else if (cmp > 0) +- low = middle + 1; +- else +- return regs[middle].value; ++ val = name[1] - '0'; ++ if (ISDIGIT (name[2])) ++ val = val * 10 + name[2] - '0'; + } +- while (low <= high); + +- return -1; ++ if ((name[0] != 'v' && val > 15) || val > 31) ++ val = -1; ++ ++ return val; + } + + +@@ -273,7 +170,7 @@ register_name (expressionS *expressionP) + return FALSE; + + c = get_symbol_end (); +- reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, name); ++ reg_number = reg_name_search (name); + + /* Put back the delimiting char. */ + *input_line_pointer = c; +@@ -383,6 +280,8 @@ s390_parse_cpu (char *arg) + return S390_OPCODE_Z196; + else if (strcmp (arg, "zEC12") == 0) + return S390_OPCODE_ZEC12; ++ else if (strcmp (arg, "z13") == 0) ++ return S390_OPCODE_Z13; + else if (strcmp (arg, "all") == 0) + return S390_OPCODE_MAXCPU - 1; + else +@@ -634,6 +533,12 @@ s390_insert_operand (unsigned char *insn + max = (((addressT) 1 << (operand->bits - 1)) << 1) - 1; + min = (offsetT) 0; + uval = (addressT) val; ++ ++ /* Vector register operands have an additional bit in the RXB ++ field. */ ++ if (operand->flags & S390_OPERAND_VR) ++ max = (max << 1) | 1; ++ + /* Length x in an instructions has real length x+1. */ + if (operand->flags & S390_OPERAND_LENGTH) + uval--; +@@ -653,6 +558,43 @@ s390_insert_operand (unsigned char *insn + } + } + ++ if (operand->flags & S390_OPERAND_VR) ++ { ++ /* Insert the extra bit into the RXB field. */ ++ switch (operand->shift) ++ { ++ case 8: ++ insn[4] |= (uval & 0x10) >> 1; ++ break; ++ case 12: ++ insn[4] |= (uval & 0x10) >> 2; ++ break; ++ case 16: ++ insn[4] |= (uval & 0x10) >> 3; ++ break; ++ case 32: ++ insn[4] |= (uval & 0x10) >> 4; ++ break; ++ } ++ uval &= 0xf; ++ } ++ ++ if (operand->flags & S390_OPERAND_OR1) ++ uval |= 1; ++ if (operand->flags & S390_OPERAND_OR2) ++ uval |= 2; ++ if (operand->flags & S390_OPERAND_OR8) ++ uval |= 8; ++ ++ /* Duplicate the operand at bit pos 12 to 16. */ ++ if (operand->flags & S390_OPERAND_CP16) ++ { ++ /* Copy VR operand at bit pos 12 to bit pos 16. */ ++ insn[2] |= uval << 4; ++ /* Copy the flag in the RXB field. */ ++ insn[4] |= (insn[4] & 4) >> 1; ++ } ++ + /* Insert fragments of the operand byte for byte. */ + offset = operand->shift + operand->bits; + uval <<= (-offset) & 7; +@@ -1207,6 +1149,14 @@ md_gather_operands (char *str, + + operand = s390_operands + *opindex_ptr; + ++ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) && *str == '\0') ++ { ++ /* Optional parameters might need to be ORed with a ++ value so calling s390_insert_operand is needed. */ ++ s390_insert_operand (insn, operand, 0, NULL, 0); ++ break; ++ } ++ + if (skip_optional && (operand->flags & S390_OPERAND_INDEX)) + { + /* We do an early skip. For D(X,B) constructions the index +@@ -1267,6 +1217,9 @@ md_gather_operands (char *str, + } + else + { ++ if ((operand->flags & S390_OPERAND_LENGTH) ++ && ex.X_op != O_constant) ++ as_fatal (_("invalid length field specified")); + if ((operand->flags & S390_OPERAND_INDEX) + && ex.X_add_number == 0 + && warn_areg_zero) +@@ -1316,9 +1269,15 @@ md_gather_operands (char *str, + else if (suffix == ELF_SUFFIX_PLT) + { + if ((operand->flags & S390_OPERAND_PCREL) +- && (operand->bits == 16)) ++ && (operand->bits == 12)) ++ reloc = BFD_RELOC_390_PLT12DBL; ++ else if ((operand->flags & S390_OPERAND_PCREL) ++ && (operand->bits == 16)) + reloc = BFD_RELOC_390_PLT16DBL; + else if ((operand->flags & S390_OPERAND_PCREL) ++ && (operand->bits == 24)) ++ reloc = BFD_RELOC_390_PLT24DBL; ++ else if ((operand->flags & S390_OPERAND_PCREL) + && (operand->bits == 32)) + reloc = BFD_RELOC_390_PLT32DBL; + } +@@ -1472,6 +1431,10 @@ md_gather_operands (char *str, + as_bad (_("syntax error; ')' not allowed here")); + str++; + } ++ ++ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) && *str == '\0') ++ continue; ++ + /* If there is a next operand it must be separated by a comma. */ + if (opindex_ptr[1] != '\0') + { +@@ -1554,7 +1517,7 @@ md_gather_operands (char *str, + if (!reloc_howto) + abort (); + +- size = bfd_get_reloc_size (reloc_howto); ++ size = ((reloc_howto->bitsize - 1) / 8) + 1; + + if (size < 1 || size > 4) + abort (); +@@ -1841,10 +1804,6 @@ s390_machine (int ignore ATTRIBUTE_UNUSE + { + unsigned int old_cpu = current_cpu; + unsigned int new_cpu; +- char *p; +- +- for (p = cpu_string; *p != 0; p++) +- *p = TOLOWER (*p); + + if (strcmp (cpu_string, "push") == 0) + { +@@ -2034,7 +1993,9 @@ tc_s390_fix_adjustable (fixS *fixP) + || fixP->fx_r_type == BFD_RELOC_390_PLTOFF16 + || fixP->fx_r_type == BFD_RELOC_390_PLTOFF32 + || fixP->fx_r_type == BFD_RELOC_390_PLTOFF64 ++ || fixP->fx_r_type == BFD_RELOC_390_PLT12DBL + || fixP->fx_r_type == BFD_RELOC_390_PLT16DBL ++ || fixP->fx_r_type == BFD_RELOC_390_PLT24DBL + || fixP->fx_r_type == BFD_RELOC_390_PLT32 + || fixP->fx_r_type == BFD_RELOC_390_PLT32DBL + || fixP->fx_r_type == BFD_RELOC_390_PLT64 +@@ -2100,7 +2061,9 @@ tc_s390_force_relocation (struct fix *fi + case BFD_RELOC_390_GOT64: + case BFD_RELOC_390_GOTENT: + case BFD_RELOC_390_PLT32: ++ case BFD_RELOC_390_PLT12DBL: + case BFD_RELOC_390_PLT16DBL: ++ case BFD_RELOC_390_PLT24DBL: + case BFD_RELOC_390_PLT32DBL: + case BFD_RELOC_390_PLT64: + case BFD_RELOC_390_GOTPLT12: +@@ -2192,6 +2155,14 @@ md_apply_fix (fixS *fixP, valueT *valP, + fixP->fx_where += 1; + fixP->fx_r_type = BFD_RELOC_8; + } ++ else if (operand->bits == 12 && operand->shift == 12 ++ && (operand->flags & S390_OPERAND_PCREL)) ++ { ++ fixP->fx_size = 2; ++ fixP->fx_where += 1; ++ fixP->fx_offset += 1; ++ fixP->fx_r_type = BFD_RELOC_390_PC12DBL; ++ } + else if (operand->bits == 16 && operand->shift == 16) + { + fixP->fx_size = 2; +@@ -2204,6 +2175,14 @@ md_apply_fix (fixS *fixP, valueT *valP, + else + fixP->fx_r_type = BFD_RELOC_16; + } ++ else if (operand->bits == 24 && operand->shift == 24 ++ && (operand->flags & S390_OPERAND_PCREL)) ++ { ++ fixP->fx_size = 3; ++ fixP->fx_where += 3; ++ fixP->fx_offset += 3; ++ fixP->fx_r_type = BFD_RELOC_390_PC24DBL; ++ } + else if (operand->bits == 32 && operand->shift == 16 + && (operand->flags & S390_OPERAND_PCREL)) + { +@@ -2242,10 +2221,18 @@ md_apply_fix (fixS *fixP, valueT *valP, + case BFD_RELOC_390_12: + case BFD_RELOC_390_GOT12: + case BFD_RELOC_390_GOTPLT12: ++ case BFD_RELOC_390_PC12DBL: ++ case BFD_RELOC_390_PLT12DBL: ++ if (fixP->fx_pcrel) ++ value++; ++ + if (fixP->fx_done) + { + unsigned short mop; + ++ if (fixP->fx_pcrel) ++ value >>= 1; ++ + mop = bfd_getb16 ((unsigned char *) where); + mop |= (unsigned short) (value & 0xfff); + bfd_putb16 ((bfd_vma) mop, (unsigned char *) where); +@@ -2293,6 +2280,20 @@ md_apply_fix (fixS *fixP, valueT *valP, + md_number_to_chars (where, (offsetT) value >> 1, 2); + break; + ++ case BFD_RELOC_390_PC24DBL: ++ case BFD_RELOC_390_PLT24DBL: ++ value += 3; ++ if (fixP->fx_done) ++ { ++ unsigned int mop; ++ value >>= 1; ++ ++ mop = bfd_getb32 ((unsigned char *) where - 1); ++ mop |= (unsigned int) (value & 0xffffff); ++ bfd_putb32 ((bfd_vma) mop, (unsigned char *) where - 1); ++ } ++ break; ++ + case BFD_RELOC_32: + if (fixP->fx_pcrel) + fixP->fx_r_type = BFD_RELOC_32_PCREL; +@@ -2456,7 +2457,7 @@ tc_s390_regname_to_dw2regnum (char *regn + + if (regname[0] != 'c' && regname[0] != 'a') + { +- regnum = reg_name_search (pre_defined_registers, REG_NAME_CNT, regname); ++ regnum = reg_name_search (regname); + if (regname[0] == 'f' && regnum != -1) + regnum += 16; + } +diff -Nrup a/gas/doc/as.texinfo b/gas/doc/as.texinfo +--- a/gas/doc/as.texinfo 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/doc/as.texinfo 2015-05-04 15:15:18.083075776 -0600 +@@ -1467,7 +1467,7 @@ Architecture (esa) or the z/Architecture + @item -march=@var{processor} + Specify which s390 processor variant is the target, @samp{g6}, @samp{g6}, + @samp{z900}, @samp{z990}, @samp{z9-109}, @samp{z9-ec}, @samp{z10}, +-@samp{z196}, or @samp{zEC12}. ++@samp{z196}, @samp{zEC12}, or @samp{z13}. + @item -mregnames + @itemx -mno-regnames + Allow or disallow symbolic names for registers. +diff -Nrup a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi +--- a/gas/doc/c-s390.texi 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/doc/c-s390.texi 2015-05-04 15:15:18.083075776 -0600 +@@ -17,7 +17,7 @@ + The s390 version of @code{@value{AS}} supports two architectures modes + and seven chip levels. The architecture modes are the Enterprise System + Architecture (ESA) and the newer z/Architecture mode. The chip levels +-are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, and zEC12. ++are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, zEC12, and z13. + + @menu + * s390 Options:: Command-line Options. +@@ -65,8 +65,10 @@ are recognized: + @code{z990}, + @code{z9-109}, + @code{z9-ec}, +-@code{z10} and +-@code{z196}. ++@code{z10}, ++@code{z196}, ++@code{zEC12}, and ++@code{z13}. + Assembling an instruction that is not supported on the target processor + results in an error message. Do not specify @code{g5} or @code{g6} + with @samp{-mzarch}. +diff -Nrup a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d +--- a/gas/testsuite/gas/s390/esa-g5.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/esa-g5.d 2015-05-04 15:15:18.083075776 -0600 +@@ -157,6 +157,7 @@ Disassembly of section .text: + .*: de ff 5f ff af ff [ ]*ed 4095\(256,%r5\),4095\(%r10\) + .*: df ff 5f ff af ff [ ]*edmk 4095\(256,%r5\),4095\(%r10\) + .*: b3 8c 00 69 [ ]*efpc %r6,%r9 ++.*: b3 8c 00 60 [ ]*efpc %r6 + .*: b2 26 00 60 [ ]*epar %r6 + .*: b2 49 00 69 [ ]*ereg %r6,%r9 + .*: b2 27 00 60 [ ]*esar %r6 +@@ -179,27 +180,27 @@ Disassembly of section .text: + .*: b2 21 00 69 [ ]*ipte %r6,%r9 + .*: b2 29 00 69 [ ]*iske %r6,%r9 + .*: b2 23 00 69 [ ]*ivsk %r6,%r9 +-.*: a7 f4 00 00 [ ]*j 274 +-.*: a7 84 00 00 [ ]*je 278 +-.*: a7 24 00 00 [ ]*jh 27c +-.*: a7 a4 00 00 [ ]*jhe 280 +-.*: a7 44 00 00 [ ]*jl 284 +-.*: a7 c4 00 00 [ ]*jle 288 +-.*: a7 64 00 00 [ ]*jlh 28c +-.*: a7 44 00 00 [ ]*jl 290 +-.*: a7 74 00 00 [ ]*jne 294 +-.*: a7 d4 00 00 [ ]*jnh 298 +-.*: a7 54 00 00 [ ]*jnhe 29c +-.*: a7 b4 00 00 [ ]*jnl 2a0 +-.*: a7 34 00 00 [ ]*jnle 2a4 +-.*: a7 94 00 00 [ ]*jnlh 2a8 +-.*: a7 b4 00 00 [ ]*jnl 2ac +-.*: a7 e4 00 00 [ ]*jno 2b0 +-.*: a7 d4 00 00 [ ]*jnh 2b4 +-.*: a7 74 00 00 [ ]*jne 2b8 +-.*: a7 14 00 00 [ ]*jo 2bc +-.*: a7 24 00 00 [ ]*jh 2c0 +-.*: a7 84 00 00 [ ]*je 2c4 ++.*: a7 f4 00 00 [ ]*j 278 ++.*: a7 84 00 00 [ ]*je 27c ++.*: a7 24 00 00 [ ]*jh 280 ++.*: a7 a4 00 00 [ ]*jhe 284 ++.*: a7 44 00 00 [ ]*jl 288 ++.*: a7 c4 00 00 [ ]*jle 28c ++.*: a7 64 00 00 [ ]*jlh 290 ++.*: a7 44 00 00 [ ]*jl 294 ++.*: a7 74 00 00 [ ]*jne 298 ++.*: a7 d4 00 00 [ ]*jnh 29c ++.*: a7 54 00 00 [ ]*jnhe 2a0 ++.*: a7 b4 00 00 [ ]*jnl 2a4 ++.*: a7 34 00 00 [ ]*jnle 2a8 ++.*: a7 94 00 00 [ ]*jnlh 2ac ++.*: a7 b4 00 00 [ ]*jnl 2b0 ++.*: a7 e4 00 00 [ ]*jno 2b4 ++.*: a7 d4 00 00 [ ]*jnh 2b8 ++.*: a7 74 00 00 [ ]*jne 2bc ++.*: a7 14 00 00 [ ]*jo 2c0 ++.*: a7 24 00 00 [ ]*jh 2c4 ++.*: a7 84 00 00 [ ]*je 2c8 + .*: ed 65 af ff 00 18 [ ]*kdb %f6,4095\(%r5,%r10\) + .*: b3 18 00 69 [ ]*kdbr %f6,%f9 + .*: ed 65 af ff 00 08 [ ]*keb %f6,4095\(%r5,%r10\) +@@ -372,6 +373,7 @@ Disassembly of section .text: + .*: b3 0b 00 69 [ ]*sebr %f6,%f9 + .*: 3b 69 [ ]*ser %f6,%f9 + .*: b3 84 00 69 [ ]*sfpc %r6,%r9 ++.*: b3 84 00 60 [ ]*sfpc %r6 + .*: 4b 65 af ff [ ]*sh %r6,4095\(%r5,%r10\) + .*: b2 14 5f ff [ ]*sie 4095\(%r5\) + .*: b2 74 5f ff [ ]*siga 4095\(%r5\) +diff -Nrup a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s +--- a/gas/testsuite/gas/s390/esa-g5.s 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/esa-g5.s 2015-05-04 15:15:18.083075776 -0600 +@@ -151,6 +151,7 @@ foo: + ed 4095(256,%r5),4095(%r10) + edmk 4095(256,%r5),4095(%r10) + efpc %r6,%r9 ++ efpc %r6 + epar %r6 + ereg %r6,%r9 + esar %r6 +@@ -366,6 +367,7 @@ foo: + sebr %f6,%f9 + ser %f6,%f9 + sfpc %r6,%r9 ++ sfpc %r6 + sh %r6,4095(%r5,%r10) + sie 4095(%r5) + siga 4095(%r5) +diff -Nrup a/gas/testsuite/gas/s390/esa-z9-109.d b/gas/testsuite/gas/s390/esa-z9-109.d +--- a/gas/testsuite/gas/s390/esa-z9-109.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/esa-z9-109.d 2015-05-04 15:15:18.083075776 -0600 +@@ -7,7 +7,11 @@ Disassembly of section .text: + + .* : + .*: b9 93 f0 68 [ ]*troo %r6,%r8,15 ++.*: b9 93 00 68 [ ]*troo %r6,%r8 + .*: b9 92 f0 68 [ ]*trot %r6,%r8,15 ++.*: b9 92 00 68 [ ]*trot %r6,%r8 + .*: b9 91 f0 68 [ ]*trto %r6,%r8,15 ++.*: b9 91 00 68 [ ]*trto %r6,%r8 + .*: b9 90 f0 68 [ ]*trtt %r6,%r8,15 ++.*: b9 90 00 68 [ ]*trtt %r6,%r8 + .*: b2 2b 00 69 [ ]*sske %r6,%r9 +diff -Nrup a/gas/testsuite/gas/s390/esa-z9-109.s b/gas/testsuite/gas/s390/esa-z9-109.s +--- a/gas/testsuite/gas/s390/esa-z9-109.s 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/esa-z9-109.s 2015-05-04 15:15:18.083075776 -0600 +@@ -1,9 +1,13 @@ + .text + foo: + troo %r6,%r8,15 ++ troo %r6,%r8 + trot %r6,%r8,15 ++ trot %r6,%r8 + trto %r6,%r8,15 ++ trto %r6,%r8 + trtt %r6,%r8,15 ++ trtt %r6,%r8 + # z9-109 z/Architecture mode extended sske with an additional parameter + # make sure the old version still works for esa + sske %r6,%r9 +diff -Nrup a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp +--- a/gas/testsuite/gas/s390/s390.exp 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/s390.exp 2015-05-04 15:15:18.084075754 -0600 +@@ -26,6 +26,7 @@ if [expr [istarget "s390-*-*"] || [ista + run_dump_test "zarch-z10" "{as -m64} {as -march=z10}" + run_dump_test "zarch-z196" "{as -m64} {as -march=z196}" + run_dump_test "zarch-zEC12" "{as -m64} {as -march=zEC12}" ++ run_dump_test "zarch-z13" "{as -m64} {as -march=z13}" + run_dump_test "zarch-reloc" "{as -m64}" + run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}" + run_dump_test "zarch-machine" "{as -m64} {as -march=z900}" +diff -Nrup a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d +--- a/gas/testsuite/gas/s390/zarch-z10.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/zarch-z10.d 2015-05-04 15:15:18.084075754 -0600 +@@ -371,9 +371,9 @@ Disassembly of section .text: + .*: b9 a2 00 60 [ ]*ptf %r6 + .*: b9 af 00 67 [ ]*pfmf %r6,%r7 + .*: b9 bf a0 67 [ ]*trte %r6,%r7,10 +-.*: b9 bf 00 67 [ ]*trte %r6,%r7,0 ++.*: b9 bf 00 67 [ ]*trte %r6,%r7 + .*: b9 bd a0 67 [ ]*trtre %r6,%r7,10 +-.*: b9 bd 00 67 [ ]*trtre %r6,%r7,0 ++.*: b9 bd 00 67 [ ]*trtre %r6,%r7 + .*: b2 ed 00 67 [ ]*ecpga %r6,%r7 + .*: b2 e4 00 67 [ ]*ecctr %r6,%r7 + .*: b2 e5 00 67 [ ]*epctr %r6,%r7 +diff -Nrup a/gas/testsuite/gas/s390/zarch-z13.d b/gas/testsuite/gas/s390/zarch-z13.d +--- a/gas/testsuite/gas/s390/zarch-z13.d 1969-12-31 17:00:00.000000000 -0700 ++++ b/gas/testsuite/gas/s390/zarch-z13.d 2015-05-04 15:15:39.250627782 -0600 +@@ -0,0 +1,682 @@ ++#name: s390x opcode ++#objdump: -dr ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++.* : ++.*: e7 69 bf a0 d0 27 [ ]*lcbb %r6,4000\(%r9,%r11\),13 ++.*: e7 f6 9f a0 d0 13 [ ]*vgef %v15,4000\(%v6,%r9\),13 ++.*: e7 f6 9f a0 d0 12 [ ]*vgeg %v15,4000\(%v6,%r9\),13 ++.*: e7 f0 ff fd 00 44 [ ]*vgbm %v15,65533 ++.*: e7 f0 00 00 00 44 [ ]*vzero %v15 ++.*: e7 f0 ff ff 00 44 [ ]*vone %v15 ++.*: e7 f0 fd fc b0 46 [ ]*vgm %v15,253,252,11 ++.*: e7 f0 fd fc 00 46 [ ]*vgmb %v15,253,252 ++.*: e7 f0 fd fc 10 46 [ ]*vgmh %v15,253,252 ++.*: e7 f0 fd fc 20 46 [ ]*vgmf %v15,253,252 ++.*: e7 f0 fd fc 30 46 [ ]*vgmg %v15,253,252 ++.*: e7 f6 9f a0 00 06 [ ]*vl %v15,4000\(%r6,%r9\) ++.*: e7 f1 00 00 04 56 [ ]*vlr %v15,%v17 ++.*: e7 f6 9f a0 d0 05 [ ]*vlrep %v15,4000\(%r6,%r9\),13 ++.*: e7 f6 9f a0 00 05 [ ]*vlrepb %v15,4000\(%r6,%r9\) ++.*: e7 f6 9f a0 10 05 [ ]*vlreph %v15,4000\(%r6,%r9\) ++.*: e7 f6 9f a0 20 05 [ ]*vlrepf %v15,4000\(%r6,%r9\) ++.*: e7 f6 9f a0 30 05 [ ]*vlrepg %v15,4000\(%r6,%r9\) ++.*: e7 f6 9f a0 d0 00 [ ]*vleb %v15,4000\(%r6,%r9\),13 ++.*: e7 f6 9f a0 d0 01 [ ]*vleh %v15,4000\(%r6,%r9\),13 ++.*: e7 f6 9f a0 d0 03 [ ]*vlef %v15,4000\(%r6,%r9\),13 ++.*: e7 f6 9f a0 d0 02 [ ]*vleg %v15,4000\(%r6,%r9\),13 ++.*: e7 f0 80 03 c0 40 [ ]*vleib %v15,-32765,12 ++.*: e7 f0 80 03 c0 41 [ ]*vleih %v15,-32765,12 ++.*: e7 f0 80 03 c0 43 [ ]*vleif %v15,-32765,12 ++.*: e7 f0 80 03 c0 42 [ ]*vleig %v15,-32765,12 ++.*: e7 6f 9f a0 d0 21 [ ]*vlgv %r6,%v15,4000\(%r9\),13 ++.*: e7 6f 9f a0 00 21 [ ]*vlgvb %r6,%v15,4000\(%r9\) ++.*: e7 6f 9f a0 10 21 [ ]*vlgvh %r6,%v15,4000\(%r9\) ++.*: e7 6f 9f a0 20 21 [ ]*vlgvf %r6,%v15,4000\(%r9\) ++.*: e7 6f 9f a0 30 21 [ ]*vlgvg %r6,%v15,4000\(%r9\) ++.*: e7 f6 9f a0 d0 04 [ ]*vllez %v15,4000\(%r6,%r9\),13 ++.*: e7 f6 9f a0 00 04 [ ]*vllezb %v15,4000\(%r6,%r9\) ++.*: e7 f6 9f a0 10 04 [ ]*vllezh %v15,4000\(%r6,%r9\) ++.*: e7 f6 9f a0 20 04 [ ]*vllezf %v15,4000\(%r6,%r9\) ++.*: e7 f6 9f a0 30 04 [ ]*vllezg %v15,4000\(%r6,%r9\) ++.*: e7 f1 6f a0 04 36 [ ]*vlm %v15,%v17,4000\(%r6\) ++.*: e7 f6 9f a0 d0 07 [ ]*vlbb %v15,4000\(%r6,%r9\),13 ++.*: e7 f6 9f a0 d0 22 [ ]*vlvg %v15,%r6,4000\(%r9\),13 ++.*: e7 f6 9f a0 00 22 [ ]*vlvgb %v15,%r6,4000\(%r9\) ++.*: e7 f6 9f a0 10 22 [ ]*vlvgh %v15,%r6,4000\(%r9\) ++.*: e7 f6 9f a0 20 22 [ ]*vlvgf %v15,%r6,4000\(%r9\) ++.*: e7 f6 9f a0 30 22 [ ]*vlvgg %v15,%r6,4000\(%r9\) ++.*: e7 f6 90 00 00 62 [ ]*vlvgp %v15,%r6,%r9 ++.*: e7 f6 9f a0 00 37 [ ]*vll %v15,%r6,4000\(%r9\) ++.*: e7 f1 40 00 d6 61 [ ]*vmrh %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 61 [ ]*vmrhb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 61 [ ]*vmrhh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 61 [ ]*vmrhf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 61 [ ]*vmrhg %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 60 [ ]*vmrl %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 60 [ ]*vmrlb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 60 [ ]*vmrlh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 60 [ ]*vmrlf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 60 [ ]*vmrlg %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 94 [ ]*vpk %v15,%v17,%v20,13 ++.*: e7 f1 40 00 16 94 [ ]*vpkh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 94 [ ]*vpkf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 94 [ ]*vpkg %v15,%v17,%v20 ++.*: e7 f1 40 c0 d6 97 [ ]*vpks %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 16 97 [ ]*vpksh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 97 [ ]*vpksf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 97 [ ]*vpksg %v15,%v17,%v20 ++.*: e7 f1 40 10 16 97 [ ]*vpkshs %v15,%v17,%v20 ++.*: e7 f1 40 10 26 97 [ ]*vpksfs %v15,%v17,%v20 ++.*: e7 f1 40 10 36 97 [ ]*vpksgs %v15,%v17,%v20 ++.*: e7 f1 40 c0 d6 95 [ ]*vpkls %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 16 95 [ ]*vpklsh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 95 [ ]*vpklsf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 95 [ ]*vpklsg %v15,%v17,%v20 ++.*: e7 f1 40 10 16 95 [ ]*vpklshs %v15,%v17,%v20 ++.*: e7 f1 40 10 26 95 [ ]*vpklsfs %v15,%v17,%v20 ++.*: e7 f1 40 10 36 95 [ ]*vpklsgs %v15,%v17,%v20 ++.*: e7 f1 40 00 87 8c [ ]*vperm %v15,%v17,%v20,%v24 ++.*: e7 f1 40 00 d6 84 [ ]*vpdi %v15,%v17,%v20,13 ++.*: e7 f1 ff fd c4 4d [ ]*vrep %v15,%v17,65533,12 ++.*: e7 f1 ff fd 04 4d [ ]*vrepb %v15,%v17,65533 ++.*: e7 f1 ff fd 14 4d [ ]*vreph %v15,%v17,65533 ++.*: e7 f1 ff fd 24 4d [ ]*vrepf %v15,%v17,65533 ++.*: e7 f1 ff fd 34 4d [ ]*vrepg %v15,%v17,65533 ++.*: e7 f0 80 03 c0 45 [ ]*vrepi %v15,-32765,12 ++.*: e7 f0 80 03 00 45 [ ]*vrepib %v15,-32765 ++.*: e7 f0 80 03 10 45 [ ]*vrepih %v15,-32765 ++.*: e7 f0 80 03 20 45 [ ]*vrepif %v15,-32765 ++.*: e7 f0 80 03 30 45 [ ]*vrepig %v15,-32765 ++.*: e7 f6 9f a0 d0 1b [ ]*vscef %v15,4000\(%v6,%r9\),13 ++.*: e7 f6 9f a0 d0 1a [ ]*vsceg %v15,4000\(%v6,%r9\),13 ++.*: e7 f1 40 00 87 8d [ ]*vsel %v15,%v17,%v20,%v24 ++.*: e7 f1 00 00 d4 5f [ ]*vseg %v15,%v17,13 ++.*: e7 f1 00 00 04 5f [ ]*vsegb %v15,%v17 ++.*: e7 f1 00 00 14 5f [ ]*vsegh %v15,%v17 ++.*: e7 f1 00 00 24 5f [ ]*vsegf %v15,%v17 ++.*: e7 f6 9f a0 00 0e [ ]*vst %v15,4000\(%r6,%r9\) ++.*: e7 f6 9f a0 d0 08 [ ]*vsteb %v15,4000\(%r6,%r9\),13 ++.*: e7 f6 9f a0 d0 09 [ ]*vsteh %v15,4000\(%r6,%r9\),13 ++.*: e7 f6 9f a0 d0 0b [ ]*vstef %v15,4000\(%r6,%r9\),13 ++.*: e7 f6 9f a0 d0 0a [ ]*vsteg %v15,4000\(%r6,%r9\),13 ++.*: e7 f1 6f a0 04 3e [ ]*vstm %v15,%v17,4000\(%r6\) ++.*: e7 f6 9f a0 00 3f [ ]*vstl %v15,%r6,4000\(%r9\) ++.*: e7 f1 00 00 d4 d7 [ ]*vuph %v15,%v17,13 ++.*: e7 f1 00 00 04 d7 [ ]*vuphb %v15,%v17 ++.*: e7 f1 00 00 14 d7 [ ]*vuphh %v15,%v17 ++.*: e7 f1 00 00 24 d7 [ ]*vuphf %v15,%v17 ++.*: e7 f1 00 00 d4 d5 [ ]*vuplh %v15,%v17,13 ++.*: e7 f1 00 00 04 d5 [ ]*vuplhb %v15,%v17 ++.*: e7 f1 00 00 14 d5 [ ]*vuplhh %v15,%v17 ++.*: e7 f1 00 00 24 d5 [ ]*vuplhf %v15,%v17 ++.*: e7 f1 00 00 d4 d6 [ ]*vupl %v15,%v17,13 ++.*: e7 f1 00 00 04 d6 [ ]*vuplb %v15,%v17 ++.*: e7 f1 00 00 14 d6 [ ]*vuplhw %v15,%v17 ++.*: e7 f1 00 00 24 d6 [ ]*vuplf %v15,%v17 ++.*: e7 f1 00 00 d4 d4 [ ]*vupll %v15,%v17,13 ++.*: e7 f1 00 00 04 d4 [ ]*vupllb %v15,%v17 ++.*: e7 f1 00 00 14 d4 [ ]*vupllh %v15,%v17 ++.*: e7 f1 00 00 24 d4 [ ]*vupllf %v15,%v17 ++.*: e7 f1 40 00 d6 f3 [ ]*va %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 f3 [ ]*vab %v15,%v17,%v20 ++.*: e7 f1 40 00 16 f3 [ ]*vah %v15,%v17,%v20 ++.*: e7 f1 40 00 26 f3 [ ]*vaf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 f3 [ ]*vag %v15,%v17,%v20 ++.*: e7 f1 40 00 46 f3 [ ]*vaq %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 f1 [ ]*vacc %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 f1 [ ]*vaccb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 f1 [ ]*vacch %v15,%v17,%v20 ++.*: e7 f1 40 00 26 f1 [ ]*vaccf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 f1 [ ]*vaccg %v15,%v17,%v20 ++.*: e7 f1 40 00 46 f1 [ ]*vaccq %v15,%v17,%v20 ++.*: e7 f1 4d 00 87 bb [ ]*vac %v15,%v17,%v20,%v24,13 ++.*: e7 f1 44 00 87 bb [ ]*vacq %v15,%v17,%v20,%v24 ++.*: e7 f1 4d 00 87 b9 [ ]*vaccc %v15,%v17,%v20,%v24,13 ++.*: e7 f1 44 00 87 b9 [ ]*vacccq %v15,%v17,%v20,%v24 ++.*: e7 f1 40 00 06 68 [ ]*vn %v15,%v17,%v20 ++.*: e7 f1 40 00 06 69 [ ]*vnc %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 f2 [ ]*vavg %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 f2 [ ]*vavgb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 f2 [ ]*vavgh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 f2 [ ]*vavgf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 f2 [ ]*vavgg %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 f0 [ ]*vavgl %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 f0 [ ]*vavglb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 f0 [ ]*vavglh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 f0 [ ]*vavglf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 f0 [ ]*vavglg %v15,%v17,%v20 ++.*: e7 f1 40 00 06 66 [ ]*vcksm %v15,%v17,%v20 ++.*: e7 f1 00 00 d4 db [ ]*vec %v15,%v17,13 ++.*: e7 f1 00 00 04 db [ ]*vecb %v15,%v17 ++.*: e7 f1 00 00 14 db [ ]*vech %v15,%v17 ++.*: e7 f1 00 00 24 db [ ]*vecf %v15,%v17 ++.*: e7 f1 00 00 34 db [ ]*vecg %v15,%v17 ++.*: e7 f1 00 00 d4 d9 [ ]*vecl %v15,%v17,13 ++.*: e7 f1 00 00 04 d9 [ ]*veclb %v15,%v17 ++.*: e7 f1 00 00 14 d9 [ ]*veclh %v15,%v17 ++.*: e7 f1 00 00 24 d9 [ ]*veclf %v15,%v17 ++.*: e7 f1 00 00 34 d9 [ ]*veclg %v15,%v17 ++.*: e7 f1 40 c0 d6 f8 [ ]*vceq %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 06 f8 [ ]*vceqb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 f8 [ ]*vceqh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 f8 [ ]*vceqf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 f8 [ ]*vceqg %v15,%v17,%v20 ++.*: e7 f1 40 10 06 f8 [ ]*vceqbs %v15,%v17,%v20 ++.*: e7 f1 40 10 16 f8 [ ]*vceqhs %v15,%v17,%v20 ++.*: e7 f1 40 10 26 f8 [ ]*vceqfs %v15,%v17,%v20 ++.*: e7 f1 40 10 36 f8 [ ]*vceqgs %v15,%v17,%v20 ++.*: e7 f1 40 c0 d6 fb [ ]*vch %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 06 fb [ ]*vchb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 fb [ ]*vchh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 fb [ ]*vchf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 fb [ ]*vchg %v15,%v17,%v20 ++.*: e7 f1 40 10 06 fb [ ]*vchbs %v15,%v17,%v20 ++.*: e7 f1 40 10 16 fb [ ]*vchhs %v15,%v17,%v20 ++.*: e7 f1 40 10 26 fb [ ]*vchfs %v15,%v17,%v20 ++.*: e7 f1 40 10 36 fb [ ]*vchgs %v15,%v17,%v20 ++.*: e7 f1 40 c0 d6 f9 [ ]*vchl %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 06 f9 [ ]*vchlb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 f9 [ ]*vchlh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 f9 [ ]*vchlf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 f9 [ ]*vchlg %v15,%v17,%v20 ++.*: e7 f1 40 10 06 f9 [ ]*vchlbs %v15,%v17,%v20 ++.*: e7 f1 40 10 16 f9 [ ]*vchlhs %v15,%v17,%v20 ++.*: e7 f1 40 10 26 f9 [ ]*vchlfs %v15,%v17,%v20 ++.*: e7 f1 40 10 36 f9 [ ]*vchlgs %v15,%v17,%v20 ++.*: e7 f1 00 00 d4 53 [ ]*vclz %v15,%v17,13 ++.*: e7 f1 00 00 04 53 [ ]*vclzb %v15,%v17 ++.*: e7 f1 00 00 14 53 [ ]*vclzh %v15,%v17 ++.*: e7 f1 00 00 24 53 [ ]*vclzf %v15,%v17 ++.*: e7 f1 00 00 34 53 [ ]*vclzg %v15,%v17 ++.*: e7 f1 00 00 d4 52 [ ]*vctz %v15,%v17,13 ++.*: e7 f1 00 00 04 52 [ ]*vctzb %v15,%v17 ++.*: e7 f1 00 00 14 52 [ ]*vctzh %v15,%v17 ++.*: e7 f1 00 00 24 52 [ ]*vctzf %v15,%v17 ++.*: e7 f1 00 00 34 52 [ ]*vctzg %v15,%v17 ++.*: e7 f1 40 00 06 6d [ ]*vx %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 b4 [ ]*vgfm %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 b4 [ ]*vgfmb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 b4 [ ]*vgfmh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 b4 [ ]*vgfmf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 b4 [ ]*vgfmg %v15,%v17,%v20 ++.*: e7 f1 4d 00 87 bc [ ]*vgfma %v15,%v17,%v20,%v24,13 ++.*: e7 f1 40 00 87 bc [ ]*vgfmab %v15,%v17,%v20,%v24 ++.*: e7 f1 41 00 87 bc [ ]*vgfmah %v15,%v17,%v20,%v24 ++.*: e7 f1 42 00 87 bc [ ]*vgfmaf %v15,%v17,%v20,%v24 ++.*: e7 f1 43 00 87 bc [ ]*vgfmag %v15,%v17,%v20,%v24 ++.*: e7 f1 00 00 d4 de [ ]*vlc %v15,%v17,13 ++.*: e7 f1 00 00 04 de [ ]*vlcb %v15,%v17 ++.*: e7 f1 00 00 14 de [ ]*vlch %v15,%v17 ++.*: e7 f1 00 00 24 de [ ]*vlcf %v15,%v17 ++.*: e7 f1 00 00 34 de [ ]*vlcg %v15,%v17 ++.*: e7 f1 00 00 d4 df [ ]*vlp %v15,%v17,13 ++.*: e7 f1 00 00 04 df [ ]*vlpb %v15,%v17 ++.*: e7 f1 00 00 14 df [ ]*vlph %v15,%v17 ++.*: e7 f1 00 00 24 df [ ]*vlpf %v15,%v17 ++.*: e7 f1 00 00 34 df [ ]*vlpg %v15,%v17 ++.*: e7 f1 40 00 d6 ff [ ]*vmx %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 ff [ ]*vmxb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 ff [ ]*vmxh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 ff [ ]*vmxf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 ff [ ]*vmxg %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 fd [ ]*vmxl %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 fd [ ]*vmxlb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 fd [ ]*vmxlh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 fd [ ]*vmxlf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 fd [ ]*vmxlg %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 fe [ ]*vmn %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 fe [ ]*vmnb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 fe [ ]*vmnh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 fe [ ]*vmnf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 fe [ ]*vmng %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 fc [ ]*vmnl %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 fc [ ]*vmnlb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 fc [ ]*vmnlh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 fc [ ]*vmnlf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 fc [ ]*vmnlg %v15,%v17,%v20 ++.*: e7 f1 4d 00 87 aa [ ]*vmal %v15,%v17,%v20,%v24,13 ++.*: e7 f1 40 00 87 aa [ ]*vmalb %v15,%v17,%v20,%v24 ++.*: e7 f1 41 00 87 aa [ ]*vmalhw %v15,%v17,%v20,%v24 ++.*: e7 f1 42 00 87 aa [ ]*vmalf %v15,%v17,%v20,%v24 ++.*: e7 f1 4d 00 87 ab [ ]*vmah %v15,%v17,%v20,%v24,13 ++.*: e7 f1 40 00 87 ab [ ]*vmahb %v15,%v17,%v20,%v24 ++.*: e7 f1 41 00 87 ab [ ]*vmahh %v15,%v17,%v20,%v24 ++.*: e7 f1 42 00 87 ab [ ]*vmahf %v15,%v17,%v20,%v24 ++.*: e7 f1 4d 00 87 a9 [ ]*vmalh %v15,%v17,%v20,%v24,13 ++.*: e7 f1 40 00 87 a9 [ ]*vmalhb %v15,%v17,%v20,%v24 ++.*: e7 f1 41 00 87 a9 [ ]*vmalhh %v15,%v17,%v20,%v24 ++.*: e7 f1 42 00 87 a9 [ ]*vmalhf %v15,%v17,%v20,%v24 ++.*: e7 f1 4d 00 87 ae [ ]*vmae %v15,%v17,%v20,%v24,13 ++.*: e7 f1 40 00 87 ae [ ]*vmaeb %v15,%v17,%v20,%v24 ++.*: e7 f1 41 00 87 ae [ ]*vmaeh %v15,%v17,%v20,%v24 ++.*: e7 f1 42 00 87 ae [ ]*vmaef %v15,%v17,%v20,%v24 ++.*: e7 f1 4d 00 87 ac [ ]*vmale %v15,%v17,%v20,%v24,13 ++.*: e7 f1 40 00 87 ac [ ]*vmaleb %v15,%v17,%v20,%v24 ++.*: e7 f1 41 00 87 ac [ ]*vmaleh %v15,%v17,%v20,%v24 ++.*: e7 f1 42 00 87 ac [ ]*vmalef %v15,%v17,%v20,%v24 ++.*: e7 f1 4d 00 87 af [ ]*vmao %v15,%v17,%v20,%v24,13 ++.*: e7 f1 40 00 87 af [ ]*vmaob %v15,%v17,%v20,%v24 ++.*: e7 f1 41 00 87 af [ ]*vmaoh %v15,%v17,%v20,%v24 ++.*: e7 f1 42 00 87 af [ ]*vmaof %v15,%v17,%v20,%v24 ++.*: e7 f1 4d 00 87 ad [ ]*vmalo %v15,%v17,%v20,%v24,13 ++.*: e7 f1 40 00 87 ad [ ]*vmalob %v15,%v17,%v20,%v24 ++.*: e7 f1 41 00 87 ad [ ]*vmaloh %v15,%v17,%v20,%v24 ++.*: e7 f1 42 00 87 ad [ ]*vmalof %v15,%v17,%v20,%v24 ++.*: e7 f1 40 00 d6 a3 [ ]*vmh %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 a3 [ ]*vmhb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 a3 [ ]*vmhh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 a3 [ ]*vmhf %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 a1 [ ]*vmlh %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 a1 [ ]*vmlhb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 a1 [ ]*vmlhh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 a1 [ ]*vmlhf %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 a2 [ ]*vml %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 a2 [ ]*vmlb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 a2 [ ]*vmlhw %v15,%v17,%v20 ++.*: e7 f1 40 00 26 a2 [ ]*vmlf %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 a6 [ ]*vme %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 a6 [ ]*vmeb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 a6 [ ]*vmeh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 a6 [ ]*vmef %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 a4 [ ]*vmle %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 a4 [ ]*vmleb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 a4 [ ]*vmleh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 a4 [ ]*vmlef %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 a7 [ ]*vmo %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 a7 [ ]*vmob %v15,%v17,%v20 ++.*: e7 f1 40 00 16 a7 [ ]*vmoh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 a7 [ ]*vmof %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 a5 [ ]*vmlo %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 a5 [ ]*vmlob %v15,%v17,%v20 ++.*: e7 f1 40 00 16 a5 [ ]*vmloh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 a5 [ ]*vmlof %v15,%v17,%v20 ++.*: e7 f1 40 00 06 6b [ ]*vno %v15,%v17,%v20 ++.*: e7 f1 10 00 06 6b [ ]*vno %v15,%v17,%v17 ++.*: e7 f1 40 00 06 6a [ ]*vo %v15,%v17,%v20 ++.*: e7 f1 00 00 d4 50 [ ]*vpopct %v15,%v17,13 ++.*: e7 f1 40 00 d6 73 [ ]*verllv %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 73 [ ]*verllvb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 73 [ ]*verllvh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 73 [ ]*verllvf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 73 [ ]*verllvg %v15,%v17,%v20 ++.*: e7 f1 6f a0 d4 33 [ ]*verll %v15,%v17,4000\(%r6\),13 ++.*: e7 f1 6f a0 04 33 [ ]*verllb %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 14 33 [ ]*verllh %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 24 33 [ ]*verllf %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 34 33 [ ]*verllg %v15,%v17,4000\(%r6\) ++.*: e7 f1 40 fd c6 72 [ ]*verim %v15,%v17,%v20,253,12 ++.*: e7 f1 40 fd 06 72 [ ]*verimb %v15,%v17,%v20,253 ++.*: e7 f1 40 fd 16 72 [ ]*verimh %v15,%v17,%v20,253 ++.*: e7 f1 40 fd 26 72 [ ]*verimf %v15,%v17,%v20,253 ++.*: e7 f1 40 fd 36 72 [ ]*verimg %v15,%v17,%v20,253 ++.*: e7 f1 40 00 d6 70 [ ]*veslv %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 70 [ ]*veslvb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 70 [ ]*veslvh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 70 [ ]*veslvf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 70 [ ]*veslvg %v15,%v17,%v20 ++.*: e7 f1 6f a0 d4 30 [ ]*vesl %v15,%v17,4000\(%r6\),13 ++.*: e7 f1 6f a0 04 30 [ ]*veslb %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 14 30 [ ]*veslh %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 24 30 [ ]*veslf %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 34 30 [ ]*veslg %v15,%v17,4000\(%r6\) ++.*: e7 f1 40 00 d6 7a [ ]*vesrav %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 7a [ ]*vesravb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 7a [ ]*vesravh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 7a [ ]*vesravf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 7a [ ]*vesravg %v15,%v17,%v20 ++.*: e7 f1 6f a0 d4 3a [ ]*vesra %v15,%v17,4000\(%r6\),13 ++.*: e7 f1 6f a0 04 3a [ ]*vesrab %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 14 3a [ ]*vesrah %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 24 3a [ ]*vesraf %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 34 3a [ ]*vesrag %v15,%v17,4000\(%r6\) ++.*: e7 f1 40 00 d6 78 [ ]*vesrlv %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 78 [ ]*vesrlvb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 78 [ ]*vesrlvh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 78 [ ]*vesrlvf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 78 [ ]*vesrlvg %v15,%v17,%v20 ++.*: e7 f1 6f a0 d4 38 [ ]*vesrl %v15,%v17,4000\(%r6\),13 ++.*: e7 f1 6f a0 04 38 [ ]*vesrlb %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 14 38 [ ]*vesrlh %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 24 38 [ ]*vesrlf %v15,%v17,4000\(%r6\) ++.*: e7 f1 6f a0 34 38 [ ]*vesrlg %v15,%v17,4000\(%r6\) ++.*: e7 f1 40 00 06 74 [ ]*vsl %v15,%v17,%v20 ++.*: e7 f1 40 00 06 75 [ ]*vslb %v15,%v17,%v20 ++.*: e7 f1 40 fd 06 77 [ ]*vsldb %v15,%v17,%v20,253 ++.*: e7 f1 40 00 06 7e [ ]*vsra %v15,%v17,%v20 ++.*: e7 f1 40 00 06 7f [ ]*vsrab %v15,%v17,%v20 ++.*: e7 f1 40 00 06 7c [ ]*vsrl %v15,%v17,%v20 ++.*: e7 f1 40 00 06 7d [ ]*vsrlb %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 f7 [ ]*vs %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 f7 [ ]*vsb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 f7 [ ]*vsh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 f7 [ ]*vsf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 f7 [ ]*vsg %v15,%v17,%v20 ++.*: e7 f1 40 00 46 f7 [ ]*vsq %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 f5 [ ]*vscbi %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 f5 [ ]*vscbib %v15,%v17,%v20 ++.*: e7 f1 40 00 16 f5 [ ]*vscbih %v15,%v17,%v20 ++.*: e7 f1 40 00 26 f5 [ ]*vscbif %v15,%v17,%v20 ++.*: e7 f1 40 00 36 f5 [ ]*vscbig %v15,%v17,%v20 ++.*: e7 f1 40 00 46 f5 [ ]*vscbiq %v15,%v17,%v20 ++.*: e7 f1 4d 00 87 bf [ ]*vsbi %v15,%v17,%v20,%v24,13 ++.*: e7 f1 44 00 87 bf [ ]*vsbiq %v15,%v17,%v20,%v24 ++.*: e7 f1 4d 00 87 bd [ ]*vsbcbi %v15,%v17,%v20,%v24,13 ++.*: e7 f1 44 00 87 bd [ ]*vsbcbiq %v15,%v17,%v20,%v24 ++.*: e7 f1 40 00 d6 65 [ ]*vsumg %v15,%v17,%v20,13 ++.*: e7 f1 40 00 16 65 [ ]*vsumgh %v15,%v17,%v20 ++.*: e7 f1 40 00 26 65 [ ]*vsumgf %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 67 [ ]*vsumq %v15,%v17,%v20,13 ++.*: e7 f1 40 00 26 67 [ ]*vsumqf %v15,%v17,%v20 ++.*: e7 f1 40 00 36 67 [ ]*vsumqg %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 64 [ ]*vsum %v15,%v17,%v20,13 ++.*: e7 f1 40 00 06 64 [ ]*vsumb %v15,%v17,%v20 ++.*: e7 f1 40 00 16 64 [ ]*vsumh %v15,%v17,%v20 ++.*: e7 f1 00 00 04 d8 [ ]*vtm %v15,%v17 ++.*: e7 f1 40 00 d6 82 [ ]*vfae %v15,%v17,%v20,13 ++.*: e7 f1 40 c0 d6 82 [ ]*vfae %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 06 82 [ ]*vfaeb %v15,%v17,%v20 ++.*: e7 f1 40 d0 06 82 [ ]*vfaebs %v15,%v17,%v20,12 ++.*: e7 f1 40 00 16 82 [ ]*vfaeh %v15,%v17,%v20 ++.*: e7 f1 40 d0 16 82 [ ]*vfaehs %v15,%v17,%v20,12 ++.*: e7 f1 40 00 26 82 [ ]*vfaef %v15,%v17,%v20 ++.*: e7 f1 40 d0 26 82 [ ]*vfaefs %v15,%v17,%v20,12 ++.*: e7 f1 40 10 06 82 [ ]*vfaebs %v15,%v17,%v20 ++.*: e7 f1 40 d0 06 82 [ ]*vfaebs %v15,%v17,%v20,12 ++.*: e7 f1 40 10 16 82 [ ]*vfaehs %v15,%v17,%v20 ++.*: e7 f1 40 d0 16 82 [ ]*vfaehs %v15,%v17,%v20,12 ++.*: e7 f1 40 10 26 82 [ ]*vfaefs %v15,%v17,%v20 ++.*: e7 f1 40 d0 26 82 [ ]*vfaefs %v15,%v17,%v20,12 ++.*: e7 f1 40 20 06 82 [ ]*vfaezb %v15,%v17,%v20 ++.*: e7 f1 40 f0 06 82 [ ]*vfaezbs %v15,%v17,%v20,12 ++.*: e7 f1 40 20 16 82 [ ]*vfaezh %v15,%v17,%v20 ++.*: e7 f1 40 f0 16 82 [ ]*vfaezhs %v15,%v17,%v20,12 ++.*: e7 f1 40 20 26 82 [ ]*vfaezf %v15,%v17,%v20 ++.*: e7 f1 40 f0 26 82 [ ]*vfaezfs %v15,%v17,%v20,12 ++.*: e7 f1 40 30 06 82 [ ]*vfaezbs %v15,%v17,%v20 ++.*: e7 f1 40 f0 06 82 [ ]*vfaezbs %v15,%v17,%v20,12 ++.*: e7 f1 40 30 16 82 [ ]*vfaezhs %v15,%v17,%v20 ++.*: e7 f1 40 f0 16 82 [ ]*vfaezhs %v15,%v17,%v20,12 ++.*: e7 f1 40 30 26 82 [ ]*vfaezfs %v15,%v17,%v20 ++.*: e7 f1 40 f0 26 82 [ ]*vfaezfs %v15,%v17,%v20,12 ++.*: e7 f1 40 00 d6 80 [ ]*vfee %v15,%v17,%v20,13 ++.*: e7 f1 40 c0 d6 80 [ ]*vfee %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 06 80 [ ]*vfeeb %v15,%v17,%v20 ++.*: e7 f1 40 d0 06 80 [ ]*vfeeb %v15,%v17,%v20,13 ++.*: e7 f1 40 00 16 80 [ ]*vfeeh %v15,%v17,%v20 ++.*: e7 f1 40 d0 16 80 [ ]*vfeeh %v15,%v17,%v20,13 ++.*: e7 f1 40 00 26 80 [ ]*vfeef %v15,%v17,%v20 ++.*: e7 f1 40 d0 26 80 [ ]*vfeef %v15,%v17,%v20,13 ++.*: e7 f1 40 10 06 80 [ ]*vfeebs %v15,%v17,%v20 ++.*: e7 f1 40 10 16 80 [ ]*vfeehs %v15,%v17,%v20 ++.*: e7 f1 40 10 26 80 [ ]*vfeefs %v15,%v17,%v20 ++.*: e7 f1 40 20 06 80 [ ]*vfeezb %v15,%v17,%v20 ++.*: e7 f1 40 20 16 80 [ ]*vfeezh %v15,%v17,%v20 ++.*: e7 f1 40 20 26 80 [ ]*vfeezf %v15,%v17,%v20 ++.*: e7 f1 40 30 06 80 [ ]*vfeezbs %v15,%v17,%v20 ++.*: e7 f1 40 30 16 80 [ ]*vfeezhs %v15,%v17,%v20 ++.*: e7 f1 40 30 26 80 [ ]*vfeezfs %v15,%v17,%v20 ++.*: e7 f1 40 00 d6 81 [ ]*vfene %v15,%v17,%v20,13 ++.*: e7 f1 40 c0 d6 81 [ ]*vfene %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 06 81 [ ]*vfeneb %v15,%v17,%v20 ++.*: e7 f1 40 d0 06 81 [ ]*vfeneb %v15,%v17,%v20,13 ++.*: e7 f1 40 00 16 81 [ ]*vfeneh %v15,%v17,%v20 ++.*: e7 f1 40 d0 16 81 [ ]*vfeneh %v15,%v17,%v20,13 ++.*: e7 f1 40 00 26 81 [ ]*vfenef %v15,%v17,%v20 ++.*: e7 f1 40 d0 26 81 [ ]*vfenef %v15,%v17,%v20,13 ++.*: e7 f1 40 10 06 81 [ ]*vfenebs %v15,%v17,%v20 ++.*: e7 f1 40 10 16 81 [ ]*vfenehs %v15,%v17,%v20 ++.*: e7 f1 40 10 26 81 [ ]*vfenefs %v15,%v17,%v20 ++.*: e7 f1 40 20 06 81 [ ]*vfenezb %v15,%v17,%v20 ++.*: e7 f1 40 20 16 81 [ ]*vfenezh %v15,%v17,%v20 ++.*: e7 f1 40 20 26 81 [ ]*vfenezf %v15,%v17,%v20 ++.*: e7 f1 40 30 06 81 [ ]*vfenezbs %v15,%v17,%v20 ++.*: e7 f1 40 30 16 81 [ ]*vfenezhs %v15,%v17,%v20 ++.*: e7 f1 40 30 26 81 [ ]*vfenezfs %v15,%v17,%v20 ++.*: e7 f1 00 00 d4 5c [ ]*vistr %v15,%v17,13 ++.*: e7 f1 00 c0 d4 5c [ ]*vistr %v15,%v17,13,12 ++.*: e7 f1 00 00 04 5c [ ]*vistrb %v15,%v17 ++.*: e7 f1 00 d0 04 5c [ ]*vistrb %v15,%v17,13 ++.*: e7 f1 00 00 14 5c [ ]*vistrh %v15,%v17 ++.*: e7 f1 00 d0 14 5c [ ]*vistrh %v15,%v17,13 ++.*: e7 f1 00 00 24 5c [ ]*vistrf %v15,%v17 ++.*: e7 f1 00 d0 24 5c [ ]*vistrf %v15,%v17,13 ++.*: e7 f1 00 10 04 5c [ ]*vistrbs %v15,%v17 ++.*: e7 f1 00 10 14 5c [ ]*vistrhs %v15,%v17 ++.*: e7 f1 00 10 24 5c [ ]*vistrfs %v15,%v17 ++.*: e7 f1 4d 00 87 8a [ ]*vstrc %v15,%v17,%v20,%v24,13 ++.*: e7 f1 4d c0 87 8a [ ]*vstrc %v15,%v17,%v20,%v24,13,12 ++.*: e7 f1 40 00 87 8a [ ]*vstrcb %v15,%v17,%v20,%v24 ++.*: e7 f1 40 d0 87 8a [ ]*vstrcbs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 41 00 87 8a [ ]*vstrch %v15,%v17,%v20,%v24 ++.*: e7 f1 41 d0 87 8a [ ]*vstrchs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 42 00 87 8a [ ]*vstrcf %v15,%v17,%v20,%v24 ++.*: e7 f1 42 d0 87 8a [ ]*vstrcfs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 40 10 87 8a [ ]*vstrcbs %v15,%v17,%v20,%v24 ++.*: e7 f1 40 d0 87 8a [ ]*vstrcbs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 41 10 87 8a [ ]*vstrchs %v15,%v17,%v20,%v24 ++.*: e7 f1 41 d0 87 8a [ ]*vstrchs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 42 10 87 8a [ ]*vstrcfs %v15,%v17,%v20,%v24 ++.*: e7 f1 42 d0 87 8a [ ]*vstrcfs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 40 20 87 8a [ ]*vstrczb %v15,%v17,%v20,%v24 ++.*: e7 f1 40 f0 87 8a [ ]*vstrczbs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 41 20 87 8a [ ]*vstrczh %v15,%v17,%v20,%v24 ++.*: e7 f1 41 f0 87 8a [ ]*vstrczhs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 42 20 87 8a [ ]*vstrczf %v15,%v17,%v20,%v24 ++.*: e7 f1 42 f0 87 8a [ ]*vstrczfs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 40 30 87 8a [ ]*vstrczbs %v15,%v17,%v20,%v24 ++.*: e7 f1 40 f0 87 8a [ ]*vstrczbs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 41 30 87 8a [ ]*vstrczhs %v15,%v17,%v20,%v24 ++.*: e7 f1 41 f0 87 8a [ ]*vstrczhs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 42 30 87 8a [ ]*vstrczfs %v15,%v17,%v20,%v24 ++.*: e7 f1 42 f0 87 8a [ ]*vstrczfs %v15,%v17,%v20,%v24,12 ++.*: e7 f1 40 0c d6 e3 [ ]*vfa %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 36 e3 [ ]*vfadb %v15,%v17,%v20 ++.*: e7 f1 40 08 36 e3 [ ]*wfadb %v15,%v17,%v20 ++.*: e7 f1 00 0c d4 cb [ ]*wfc %v15,%v17,13,12 ++.*: e7 f1 00 00 34 cb [ ]*wfcdb %v15,%v17 ++.*: e7 f1 00 0c d4 ca [ ]*wfk %v15,%v17,13,12 ++.*: e7 f1 00 00 34 ca [ ]*wfkdb %v15,%v17 ++.*: e7 f1 40 bc d6 e8 [ ]*vfce %v15,%v17,%v20,13,12,11 ++.*: e7 f1 40 00 36 e8 [ ]*vfcedb %v15,%v17,%v20 ++.*: e7 f1 40 10 36 e8 [ ]*vfcedbs %v15,%v17,%v20 ++.*: e7 f1 40 08 36 e8 [ ]*wfcedb %v15,%v17,%v20 ++.*: e7 f1 40 18 36 e8 [ ]*wfcedbs %v15,%v17,%v20 ++.*: e7 f1 40 bc d6 eb [ ]*vfch %v15,%v17,%v20,13,12,11 ++.*: e7 f1 40 00 36 eb [ ]*vfchdb %v15,%v17,%v20 ++.*: e7 f1 40 10 36 eb [ ]*vfchdbs %v15,%v17,%v20 ++.*: e7 f1 40 08 36 eb [ ]*wfchdb %v15,%v17,%v20 ++.*: e7 f1 40 18 36 eb [ ]*wfchdbs %v15,%v17,%v20 ++.*: e7 f1 40 bc d6 ea [ ]*vfche %v15,%v17,%v20,13,12,11 ++.*: e7 f1 40 00 36 ea [ ]*vfchedb %v15,%v17,%v20 ++.*: e7 f1 40 10 36 ea [ ]*vfchedbs %v15,%v17,%v20 ++.*: e7 f1 40 08 36 ea [ ]*wfchedb %v15,%v17,%v20 ++.*: e7 f1 40 18 36 ea [ ]*wfchedbs %v15,%v17,%v20 ++.*: e7 f1 00 bc d4 c3 [ ]*vcdg %v15,%v17,13,12,11 ++.*: e7 f1 00 cd 34 c3 [ ]*wcdgb %v15,%v17,5,12 ++.*: e7 f1 00 cd 34 c3 [ ]*wcdgb %v15,%v17,5,12 ++.*: e7 f1 00 bc d4 c1 [ ]*vcdlg %v15,%v17,13,12,11 ++.*: e7 f1 00 cd 34 c1 [ ]*wcdlgb %v15,%v17,5,12 ++.*: e7 f1 00 cd 34 c1 [ ]*wcdlgb %v15,%v17,5,12 ++.*: e7 f1 00 bc d4 c2 [ ]*vcgd %v15,%v17,13,12,11 ++.*: e7 f1 00 cd 34 c2 [ ]*wcgdb %v15,%v17,5,12 ++.*: e7 f1 00 cd 34 c2 [ ]*wcgdb %v15,%v17,5,12 ++.*: e7 f1 00 bc d4 c0 [ ]*vclgd %v15,%v17,13,12,11 ++.*: e7 f1 00 cd 34 c0 [ ]*wclgdb %v15,%v17,5,12 ++.*: e7 f1 00 cd 34 c0 [ ]*wclgdb %v15,%v17,5,12 ++.*: e7 f1 40 0c d6 e5 [ ]*vfd %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 36 e5 [ ]*vfddb %v15,%v17,%v20 ++.*: e7 f1 40 08 36 e5 [ ]*wfddb %v15,%v17,%v20 ++.*: e7 f1 00 bc d4 c7 [ ]*vfi %v15,%v17,13,12,11 ++.*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 ++.*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12 ++.*: e7 f1 00 0c d4 c4 [ ]*vlde %v15,%v17,13,12 ++.*: e7 f1 00 00 24 c4 [ ]*vldeb %v15,%v17 ++.*: e7 f1 00 08 24 c4 [ ]*wldeb %v15,%v17 ++.*: e7 f1 00 bc d4 c5 [ ]*vled %v15,%v17,13,12,11 ++.*: e7 f1 00 cd 34 c5 [ ]*wledb %v15,%v17,5,12 ++.*: e7 f1 00 cd 34 c5 [ ]*wledb %v15,%v17,5,12 ++.*: e7 f1 40 0c d6 e7 [ ]*vfm %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 36 e7 [ ]*vfmdb %v15,%v17,%v20 ++.*: e7 f1 40 08 36 e7 [ ]*wfmdb %v15,%v17,%v20 ++.*: e7 f1 4c 0d 87 8f [ ]*vfma %v15,%v17,%v20,%v24,13,12 ++.*: e7 f1 43 00 87 8f [ ]*vfmadb %v15,%v17,%v20,%v24 ++.*: e7 f1 43 08 87 8f [ ]*wfmadb %v15,%v17,%v20,%v24 ++.*: e7 f1 4c 0d 87 8e [ ]*vfms %v15,%v17,%v20,%v24,13,12 ++.*: e7 f1 43 00 87 8e [ ]*vfmsdb %v15,%v17,%v20,%v24 ++.*: e7 f1 43 08 87 8e [ ]*wfmsdb %v15,%v17,%v20,%v24 ++.*: e7 f1 00 bc d4 cc [ ]*vfpso %v15,%v17,13,12,11 ++.*: e7 f1 00 d0 34 cc [ ]*vfpsodb %v15,%v17,13 ++.*: e7 f1 00 d8 34 cc [ ]*wfpsodb %v15,%v17,13 ++.*: e7 f1 00 00 34 cc [ ]*vflcdb %v15,%v17 ++.*: e7 f1 00 08 34 cc [ ]*wflcdb %v15,%v17 ++.*: e7 f1 00 10 34 cc [ ]*vflndb %v15,%v17 ++.*: e7 f1 00 18 34 cc [ ]*wflndb %v15,%v17 ++.*: e7 f1 00 20 34 cc [ ]*vflpdb %v15,%v17 ++.*: e7 f1 00 28 34 cc [ ]*wflpdb %v15,%v17 ++.*: e7 f1 00 0c d4 ce [ ]*vfsq %v15,%v17,13,12 ++.*: e7 f1 00 00 34 ce [ ]*vfsqdb %v15,%v17 ++.*: e7 f1 00 08 34 ce [ ]*wfsqdb %v15,%v17 ++.*: e7 f1 40 0c d6 e2 [ ]*vfs %v15,%v17,%v20,13,12 ++.*: e7 f1 40 00 36 e2 [ ]*vfsdb %v15,%v17,%v20 ++.*: e7 f1 40 08 36 e2 [ ]*wfsdb %v15,%v17,%v20 ++.*: e7 f1 ff db c4 4a [ ]*vftci %v15,%v17,4093,12,11 ++.*: e7 f1 ff d0 34 4a [ ]*vftcidb %v15,%v17,4093 ++.*: e7 f1 ff d8 34 4a [ ]*wftcidb %v15,%v17,4093 ++.*: ed fa 6f a0 3c ae [ ]*cdpt %f3,4000\(251,%r6\),12 ++.*: ed fa 6f a0 1c af [ ]*cxpt %f1,4000\(251,%r6\),12 ++.*: ed fa 6f a0 3c ac [ ]*cpdt %f3,4000\(251,%r6\),12 ++.*: ed fa 6f a0 1c ad [ ]*cpxt %f1,4000\(251,%r6\),12 ++.*: b9 e0 d0 69 [ ]*locfhrnh %r6,%r9 ++.*: b9 e0 10 69 [ ]*locfhro %r6,%r9 ++.*: b9 e0 20 69 [ ]*locfhrh %r6,%r9 ++.*: b9 e0 20 69 [ ]*locfhrh %r6,%r9 ++.*: b9 e0 30 69 [ ]*locfhrnle %r6,%r9 ++.*: b9 e0 40 69 [ ]*locfhrl %r6,%r9 ++.*: b9 e0 40 69 [ ]*locfhrl %r6,%r9 ++.*: b9 e0 50 69 [ ]*locfhrnhe %r6,%r9 ++.*: b9 e0 60 69 [ ]*locfhrlh %r6,%r9 ++.*: b9 e0 70 69 [ ]*locfhrne %r6,%r9 ++.*: b9 e0 70 69 [ ]*locfhrne %r6,%r9 ++.*: b9 e0 80 69 [ ]*locfhre %r6,%r9 ++.*: b9 e0 80 69 [ ]*locfhre %r6,%r9 ++.*: b9 e0 90 69 [ ]*locfhrnlh %r6,%r9 ++.*: b9 e0 a0 69 [ ]*locfhrhe %r6,%r9 ++.*: b9 e0 b0 69 [ ]*locfhrnl %r6,%r9 ++.*: b9 e0 b0 69 [ ]*locfhrnl %r6,%r9 ++.*: b9 e0 c0 69 [ ]*locfhrle %r6,%r9 ++.*: b9 e0 d0 69 [ ]*locfhrnh %r6,%r9 ++.*: b9 e0 d0 69 [ ]*locfhrnh %r6,%r9 ++.*: b9 e0 e0 69 [ ]*locfhrno %r6,%r9 ++.*: eb 6d 98 f0 fd e0 [ ]*locfhnh %r6,-10000\(%r9\) ++.*: eb 61 98 f0 fd e0 [ ]*locfho %r6,-10000\(%r9\) ++.*: eb 62 98 f0 fd e0 [ ]*locfhh %r6,-10000\(%r9\) ++.*: eb 62 98 f0 fd e0 [ ]*locfhh %r6,-10000\(%r9\) ++.*: eb 63 98 f0 fd e0 [ ]*locfhnle %r6,-10000\(%r9\) ++.*: eb 64 98 f0 fd e0 [ ]*locfhl %r6,-10000\(%r9\) ++.*: eb 64 98 f0 fd e0 [ ]*locfhl %r6,-10000\(%r9\) ++.*: eb 65 98 f0 fd e0 [ ]*locfhnhe %r6,-10000\(%r9\) ++.*: eb 66 98 f0 fd e0 [ ]*locfhlh %r6,-10000\(%r9\) ++.*: eb 67 98 f0 fd e0 [ ]*locfhne %r6,-10000\(%r9\) ++.*: eb 67 98 f0 fd e0 [ ]*locfhne %r6,-10000\(%r9\) ++.*: eb 68 98 f0 fd e0 [ ]*locfhe %r6,-10000\(%r9\) ++.*: eb 68 98 f0 fd e0 [ ]*locfhe %r6,-10000\(%r9\) ++.*: eb 69 98 f0 fd e0 [ ]*locfhnlh %r6,-10000\(%r9\) ++.*: eb 6a 98 f0 fd e0 [ ]*locfhhe %r6,-10000\(%r9\) ++.*: eb 6b 98 f0 fd e0 [ ]*locfhnl %r6,-10000\(%r9\) ++.*: eb 6b 98 f0 fd e0 [ ]*locfhnl %r6,-10000\(%r9\) ++.*: eb 6c 98 f0 fd e0 [ ]*locfhle %r6,-10000\(%r9\) ++.*: eb 6d 98 f0 fd e0 [ ]*locfhnh %r6,-10000\(%r9\) ++.*: eb 6d 98 f0 fd e0 [ ]*locfhnh %r6,-10000\(%r9\) ++.*: eb 6e 98 f0 fd e0 [ ]*locfhno %r6,-10000\(%r9\) ++.*: ec 6c 80 03 00 42 [ ]*lochile %r6,-32765 ++.*: ec 61 80 03 00 42 [ ]*lochio %r6,-32765 ++.*: ec 62 80 03 00 42 [ ]*lochih %r6,-32765 ++.*: ec 62 80 03 00 42 [ ]*lochih %r6,-32765 ++.*: ec 63 80 03 00 42 [ ]*lochinle %r6,-32765 ++.*: ec 64 80 03 00 42 [ ]*lochil %r6,-32765 ++.*: ec 64 80 03 00 42 [ ]*lochil %r6,-32765 ++.*: ec 65 80 03 00 42 [ ]*lochinhe %r6,-32765 ++.*: ec 66 80 03 00 42 [ ]*lochilh %r6,-32765 ++.*: ec 67 80 03 00 42 [ ]*lochine %r6,-32765 ++.*: ec 67 80 03 00 42 [ ]*lochine %r6,-32765 ++.*: ec 68 80 03 00 42 [ ]*lochie %r6,-32765 ++.*: ec 68 80 03 00 42 [ ]*lochie %r6,-32765 ++.*: ec 69 80 03 00 42 [ ]*lochinlh %r6,-32765 ++.*: ec 6a 80 03 00 42 [ ]*lochihe %r6,-32765 ++.*: ec 6b 80 03 00 42 [ ]*lochinl %r6,-32765 ++.*: ec 6b 80 03 00 42 [ ]*lochinl %r6,-32765 ++.*: ec 6c 80 03 00 42 [ ]*lochile %r6,-32765 ++.*: ec 6d 80 03 00 42 [ ]*lochinh %r6,-32765 ++.*: ec 6d 80 03 00 42 [ ]*lochinh %r6,-32765 ++.*: ec 6e 80 03 00 42 [ ]*lochino %r6,-32765 ++.*: ec 6c 80 03 00 46 [ ]*locghile %r6,-32765 ++.*: ec 61 80 03 00 46 [ ]*locghio %r6,-32765 ++.*: ec 62 80 03 00 46 [ ]*locghih %r6,-32765 ++.*: ec 62 80 03 00 46 [ ]*locghih %r6,-32765 ++.*: ec 63 80 03 00 46 [ ]*locghinle %r6,-32765 ++.*: ec 64 80 03 00 46 [ ]*locghil %r6,-32765 ++.*: ec 64 80 03 00 46 [ ]*locghil %r6,-32765 ++.*: ec 65 80 03 00 46 [ ]*locghinhe %r6,-32765 ++.*: ec 66 80 03 00 46 [ ]*locghilh %r6,-32765 ++.*: ec 67 80 03 00 46 [ ]*locghine %r6,-32765 ++.*: ec 67 80 03 00 46 [ ]*locghine %r6,-32765 ++.*: ec 68 80 03 00 46 [ ]*locghie %r6,-32765 ++.*: ec 68 80 03 00 46 [ ]*locghie %r6,-32765 ++.*: ec 69 80 03 00 46 [ ]*locghinlh %r6,-32765 ++.*: ec 6a 80 03 00 46 [ ]*locghihe %r6,-32765 ++.*: ec 6b 80 03 00 46 [ ]*locghinl %r6,-32765 ++.*: ec 6b 80 03 00 46 [ ]*locghinl %r6,-32765 ++.*: ec 6c 80 03 00 46 [ ]*locghile %r6,-32765 ++.*: ec 6d 80 03 00 46 [ ]*locghinh %r6,-32765 ++.*: ec 6d 80 03 00 46 [ ]*locghinh %r6,-32765 ++.*: ec 6e 80 03 00 46 [ ]*locghino %r6,-32765 ++.*: ec 6c 80 03 00 4e [ ]*lochhile %r6,-32765 ++.*: ec 61 80 03 00 4e [ ]*lochhio %r6,-32765 ++.*: ec 62 80 03 00 4e [ ]*lochhih %r6,-32765 ++.*: ec 62 80 03 00 4e [ ]*lochhih %r6,-32765 ++.*: ec 63 80 03 00 4e [ ]*lochhinle %r6,-32765 ++.*: ec 64 80 03 00 4e [ ]*lochhil %r6,-32765 ++.*: ec 64 80 03 00 4e [ ]*lochhil %r6,-32765 ++.*: ec 65 80 03 00 4e [ ]*lochhinhe %r6,-32765 ++.*: ec 66 80 03 00 4e [ ]*lochhilh %r6,-32765 ++.*: ec 67 80 03 00 4e [ ]*lochhine %r6,-32765 ++.*: ec 67 80 03 00 4e [ ]*lochhine %r6,-32765 ++.*: ec 68 80 03 00 4e [ ]*lochhie %r6,-32765 ++.*: ec 68 80 03 00 4e [ ]*lochhie %r6,-32765 ++.*: ec 69 80 03 00 4e [ ]*lochhinlh %r6,-32765 ++.*: ec 6a 80 03 00 4e [ ]*lochhihe %r6,-32765 ++.*: ec 6b 80 03 00 4e [ ]*lochhinl %r6,-32765 ++.*: ec 6b 80 03 00 4e [ ]*lochhinl %r6,-32765 ++.*: ec 6c 80 03 00 4e [ ]*lochhile %r6,-32765 ++.*: ec 6d 80 03 00 4e [ ]*lochhinh %r6,-32765 ++.*: ec 6d 80 03 00 4e [ ]*lochhinh %r6,-32765 ++.*: ec 6e 80 03 00 4e [ ]*lochhino %r6,-32765 ++.*: eb 6d 98 f0 fd e1 [ ]*stocfhnh %r6,-10000\(%r9\) ++.*: eb 61 98 f0 fd e1 [ ]*stocfho %r6,-10000\(%r9\) ++.*: eb 62 98 f0 fd e1 [ ]*stocfhh %r6,-10000\(%r9\) ++.*: eb 62 98 f0 fd e1 [ ]*stocfhh %r6,-10000\(%r9\) ++.*: eb 63 98 f0 fd e1 [ ]*stocfhnle %r6,-10000\(%r9\) ++.*: eb 64 98 f0 fd e1 [ ]*stocfhl %r6,-10000\(%r9\) ++.*: eb 64 98 f0 fd e1 [ ]*stocfhl %r6,-10000\(%r9\) ++.*: eb 65 98 f0 fd e1 [ ]*stocfhnhe %r6,-10000\(%r9\) ++.*: eb 66 98 f0 fd e1 [ ]*stocfhlh %r6,-10000\(%r9\) ++.*: eb 67 98 f0 fd e1 [ ]*stocfhne %r6,-10000\(%r9\) ++.*: eb 67 98 f0 fd e1 [ ]*stocfhne %r6,-10000\(%r9\) ++.*: eb 68 98 f0 fd e1 [ ]*stocfhe %r6,-10000\(%r9\) ++.*: eb 68 98 f0 fd e1 [ ]*stocfhe %r6,-10000\(%r9\) ++.*: eb 69 98 f0 fd e1 [ ]*stocfhnlh %r6,-10000\(%r9\) ++.*: eb 6a 98 f0 fd e1 [ ]*stocfhhe %r6,-10000\(%r9\) ++.*: eb 6b 98 f0 fd e1 [ ]*stocfhnl %r6,-10000\(%r9\) ++.*: eb 6b 98 f0 fd e1 [ ]*stocfhnl %r6,-10000\(%r9\) ++.*: eb 6c 98 f0 fd e1 [ ]*stocfhle %r6,-10000\(%r9\) ++.*: eb 6d 98 f0 fd e1 [ ]*stocfhnh %r6,-10000\(%r9\) ++.*: eb 6d 98 f0 fd e1 [ ]*stocfhnh %r6,-10000\(%r9\) ++.*: eb 6e 98 f0 fd e1 [ ]*stocfhno %r6,-10000\(%r9\) ++.*: e3 69 b8 f0 fd 3a [ ]*llzrgf %r6,-10000\(%r9,%r11\) ++.*: e3 69 b8 f0 fd 3b [ ]*lzrf %r6,-10000\(%r9,%r11\) ++.*: e3 69 b8 f0 fd 2a [ ]*lzrg %r6,-10000\(%r9,%r11\) ++.*: b9 ec 00 69 [ ]*ppno %r6,%r9 +diff -Nrup a/gas/testsuite/gas/s390/zarch-z13.s b/gas/testsuite/gas/s390/zarch-z13.s +--- a/gas/testsuite/gas/s390/zarch-z13.s 1969-12-31 17:00:00.000000000 -0700 ++++ b/gas/testsuite/gas/s390/zarch-z13.s 2015-05-04 15:15:39.250627782 -0600 +@@ -0,0 +1,676 @@ ++.text ++foo: ++ lcbb %r6,4000(%r9,%r11),13 ++ vgef %v15,4000(%r6,%r9),13 ++ vgeg %v15,4000(%r6,%r9),13 ++ vgbm %v15,65533 ++ vzero %v15 ++ vone %v15 ++ vgm %v15,253,252,11 ++ vgmb %v15,253,252 ++ vgmh %v15,253,252 ++ vgmf %v15,253,252 ++ vgmg %v15,253,252 ++ vl %v15,4000(%r6,%r9) ++ vlr %v15,%v17 ++ vlrep %v15,4000(%r6,%r9),13 ++ vlrepb %v15,4000(%r6,%r9) ++ vlreph %v15,4000(%r6,%r9) ++ vlrepf %v15,4000(%r6,%r9) ++ vlrepg %v15,4000(%r6,%r9) ++ vleb %v15,4000(%r6,%r9),13 ++ vleh %v15,4000(%r6,%r9),13 ++ vlef %v15,4000(%r6,%r9),13 ++ vleg %v15,4000(%r6,%r9),13 ++ vleib %v15,-32765,12 ++ vleih %v15,-32765,12 ++ vleif %v15,-32765,12 ++ vleig %v15,-32765,12 ++ vlgv %r6,%v15,4000(%r9),13 ++ vlgvb %r6,%v15,4000(%r9) ++ vlgvh %r6,%v15,4000(%r9) ++ vlgvf %r6,%v15,4000(%r9) ++ vlgvg %r6,%v15,4000(%r9) ++ vllez %v15,4000(%r6,%r9),13 ++ vllezb %v15,4000(%r6,%r9) ++ vllezh %v15,4000(%r6,%r9) ++ vllezf %v15,4000(%r6,%r9) ++ vllezg %v15,4000(%r6,%r9) ++ vlm %v15,%v17,4000(%r6) ++ vlbb %v15,4000(%r6,%r9),13 ++ vlvg %v15,%r6,4000(%r9),13 ++ vlvgb %v15,%r6,4000(%r9) ++ vlvgh %v15,%r6,4000(%r9) ++ vlvgf %v15,%r6,4000(%r9) ++ vlvgg %v15,%r6,4000(%r9) ++ vlvgp %v15,%r6,%r9 ++ vll %v15,%r6,4000(%r9) ++ vmrh %v15,%v17,%v20,13 ++ vmrhb %v15,%v17,%v20 ++ vmrhh %v15,%v17,%v20 ++ vmrhf %v15,%v17,%v20 ++ vmrhg %v15,%v17,%v20 ++ vmrl %v15,%v17,%v20,13 ++ vmrlb %v15,%v17,%v20 ++ vmrlh %v15,%v17,%v20 ++ vmrlf %v15,%v17,%v20 ++ vmrlg %v15,%v17,%v20 ++ vpk %v15,%v17,%v20,13 ++ vpkh %v15,%v17,%v20 ++ vpkf %v15,%v17,%v20 ++ vpkg %v15,%v17,%v20 ++ vpks %v15,%v17,%v20,13,12 ++ vpksh %v15,%v17,%v20 ++ vpksf %v15,%v17,%v20 ++ vpksg %v15,%v17,%v20 ++ vpkshs %v15,%v17,%v20 ++ vpksfs %v15,%v17,%v20 ++ vpksgs %v15,%v17,%v20 ++ vpkls %v15,%v17,%v20,13,12 ++ vpklsh %v15,%v17,%v20 ++ vpklsf %v15,%v17,%v20 ++ vpklsg %v15,%v17,%v20 ++ vpklshs %v15,%v17,%v20 ++ vpklsfs %v15,%v17,%v20 ++ vpklsgs %v15,%v17,%v20 ++ vperm %v15,%v17,%v20,%v24 ++ vpdi %v15,%v17,%v20,13 ++ vrep %v15,%v17,65533,12 ++ vrepb %v15,%v17,65533 ++ vreph %v15,%v17,65533 ++ vrepf %v15,%v17,65533 ++ vrepg %v15,%v17,65533 ++ vrepi %v15,-32765,12 ++ vrepib %v15,-32765 ++ vrepih %v15,-32765 ++ vrepif %v15,-32765 ++ vrepig %v15,-32765 ++ vscef %v15,4000(%r6,%r9),13 ++ vsceg %v15,4000(%r6,%r9),13 ++ vsel %v15,%v17,%v20,%v24 ++ vseg %v15,%v17,13 ++ vsegb %v15,%v17 ++ vsegh %v15,%v17 ++ vsegf %v15,%v17 ++ vst %v15,4000(%r6,%r9) ++ vsteb %v15,4000(%r6,%r9),13 ++ vsteh %v15,4000(%r6,%r9),13 ++ vstef %v15,4000(%r6,%r9),13 ++ vsteg %v15,4000(%r6,%r9),13 ++ vstm %v15,%v17,4000(%r6) ++ vstl %v15,%r6,4000(%r9) ++ vuph %v15,%v17,13 ++ vuphb %v15,%v17 ++ vuphh %v15,%v17 ++ vuphf %v15,%v17 ++ vuplh %v15,%v17,13 ++ vuplhb %v15,%v17 ++ vuplhh %v15,%v17 ++ vuplhf %v15,%v17 ++ vupl %v15,%v17,13 ++ vuplb %v15,%v17 ++ vuplhw %v15,%v17 ++ vuplf %v15,%v17 ++ vupll %v15,%v17,13 ++ vupllb %v15,%v17 ++ vupllh %v15,%v17 ++ vupllf %v15,%v17 ++ va %v15,%v17,%v20,13 ++ vab %v15,%v17,%v20 ++ vah %v15,%v17,%v20 ++ vaf %v15,%v17,%v20 ++ vag %v15,%v17,%v20 ++ vaq %v15,%v17,%v20 ++ vacc %v15,%v17,%v20,13 ++ vaccb %v15,%v17,%v20 ++ vacch %v15,%v17,%v20 ++ vaccf %v15,%v17,%v20 ++ vaccg %v15,%v17,%v20 ++ vaccq %v15,%v17,%v20 ++ vac %v15,%v17,%v20,%v24,13 ++ vacq %v15,%v17,%v20,%v24 ++ vaccc %v15,%v17,%v20,%v24,13 ++ vacccq %v15,%v17,%v20,%v24 ++ vn %v15,%v17,%v20 ++ vnc %v15,%v17,%v20 ++ vavg %v15,%v17,%v20,13 ++ vavgb %v15,%v17,%v20 ++ vavgh %v15,%v17,%v20 ++ vavgf %v15,%v17,%v20 ++ vavgg %v15,%v17,%v20 ++ vavgl %v15,%v17,%v20,13 ++ vavglb %v15,%v17,%v20 ++ vavglh %v15,%v17,%v20 ++ vavglf %v15,%v17,%v20 ++ vavglg %v15,%v17,%v20 ++ vcksm %v15,%v17,%v20 ++ vec %v15,%v17,13 ++ vecb %v15,%v17 ++ vech %v15,%v17 ++ vecf %v15,%v17 ++ vecg %v15,%v17 ++ vecl %v15,%v17,13 ++ veclb %v15,%v17 ++ veclh %v15,%v17 ++ veclf %v15,%v17 ++ veclg %v15,%v17 ++ vceq %v15,%v17,%v20,13,12 ++ vceqb %v15,%v17,%v20 ++ vceqh %v15,%v17,%v20 ++ vceqf %v15,%v17,%v20 ++ vceqg %v15,%v17,%v20 ++ vceqbs %v15,%v17,%v20 ++ vceqhs %v15,%v17,%v20 ++ vceqfs %v15,%v17,%v20 ++ vceqgs %v15,%v17,%v20 ++ vch %v15,%v17,%v20,13,12 ++ vchb %v15,%v17,%v20 ++ vchh %v15,%v17,%v20 ++ vchf %v15,%v17,%v20 ++ vchg %v15,%v17,%v20 ++ vchbs %v15,%v17,%v20 ++ vchhs %v15,%v17,%v20 ++ vchfs %v15,%v17,%v20 ++ vchgs %v15,%v17,%v20 ++ vchl %v15,%v17,%v20,13,12 ++ vchlb %v15,%v17,%v20 ++ vchlh %v15,%v17,%v20 ++ vchlf %v15,%v17,%v20 ++ vchlg %v15,%v17,%v20 ++ vchlbs %v15,%v17,%v20 ++ vchlhs %v15,%v17,%v20 ++ vchlfs %v15,%v17,%v20 ++ vchlgs %v15,%v17,%v20 ++ vclz %v15,%v17,13 ++ vclzb %v15,%v17 ++ vclzh %v15,%v17 ++ vclzf %v15,%v17 ++ vclzg %v15,%v17 ++ vctz %v15,%v17,13 ++ vctzb %v15,%v17 ++ vctzh %v15,%v17 ++ vctzf %v15,%v17 ++ vctzg %v15,%v17 ++ vx %v15,%v17,%v20 ++ vgfm %v15,%v17,%v20,13 ++ vgfmb %v15,%v17,%v20 ++ vgfmh %v15,%v17,%v20 ++ vgfmf %v15,%v17,%v20 ++ vgfmg %v15,%v17,%v20 ++ vgfma %v15,%v17,%v20,%v24,13 ++ vgfmab %v15,%v17,%v20,%v24 ++ vgfmah %v15,%v17,%v20,%v24 ++ vgfmaf %v15,%v17,%v20,%v24 ++ vgfmag %v15,%v17,%v20,%v24 ++ vlc %v15,%v17,13 ++ vlcb %v15,%v17 ++ vlch %v15,%v17 ++ vlcf %v15,%v17 ++ vlcg %v15,%v17 ++ vlp %v15,%v17,13 ++ vlpb %v15,%v17 ++ vlph %v15,%v17 ++ vlpf %v15,%v17 ++ vlpg %v15,%v17 ++ vmx %v15,%v17,%v20,13 ++ vmxb %v15,%v17,%v20 ++ vmxh %v15,%v17,%v20 ++ vmxf %v15,%v17,%v20 ++ vmxg %v15,%v17,%v20 ++ vmxl %v15,%v17,%v20,13 ++ vmxlb %v15,%v17,%v20 ++ vmxlh %v15,%v17,%v20 ++ vmxlf %v15,%v17,%v20 ++ vmxlg %v15,%v17,%v20 ++ vmn %v15,%v17,%v20,13 ++ vmnb %v15,%v17,%v20 ++ vmnh %v15,%v17,%v20 ++ vmnf %v15,%v17,%v20 ++ vmng %v15,%v17,%v20 ++ vmnl %v15,%v17,%v20,13 ++ vmnlb %v15,%v17,%v20 ++ vmnlh %v15,%v17,%v20 ++ vmnlf %v15,%v17,%v20 ++ vmnlg %v15,%v17,%v20 ++ vmal %v15,%v17,%v20,%v24,13 ++ vmalb %v15,%v17,%v20,%v24 ++ vmalhw %v15,%v17,%v20,%v24 ++ vmalf %v15,%v17,%v20,%v24 ++ vmah %v15,%v17,%v20,%v24,13 ++ vmahb %v15,%v17,%v20,%v24 ++ vmahh %v15,%v17,%v20,%v24 ++ vmahf %v15,%v17,%v20,%v24 ++ vmalh %v15,%v17,%v20,%v24,13 ++ vmalhb %v15,%v17,%v20,%v24 ++ vmalhh %v15,%v17,%v20,%v24 ++ vmalhf %v15,%v17,%v20,%v24 ++ vmae %v15,%v17,%v20,%v24,13 ++ vmaeb %v15,%v17,%v20,%v24 ++ vmaeh %v15,%v17,%v20,%v24 ++ vmaef %v15,%v17,%v20,%v24 ++ vmale %v15,%v17,%v20,%v24,13 ++ vmaleb %v15,%v17,%v20,%v24 ++ vmaleh %v15,%v17,%v20,%v24 ++ vmalef %v15,%v17,%v20,%v24 ++ vmao %v15,%v17,%v20,%v24,13 ++ vmaob %v15,%v17,%v20,%v24 ++ vmaoh %v15,%v17,%v20,%v24 ++ vmaof %v15,%v17,%v20,%v24 ++ vmalo %v15,%v17,%v20,%v24,13 ++ vmalob %v15,%v17,%v20,%v24 ++ vmaloh %v15,%v17,%v20,%v24 ++ vmalof %v15,%v17,%v20,%v24 ++ vmh %v15,%v17,%v20,13 ++ vmhb %v15,%v17,%v20 ++ vmhh %v15,%v17,%v20 ++ vmhf %v15,%v17,%v20 ++ vmlh %v15,%v17,%v20,13 ++ vmlhb %v15,%v17,%v20 ++ vmlhh %v15,%v17,%v20 ++ vmlhf %v15,%v17,%v20 ++ vml %v15,%v17,%v20,13 ++ vmlb %v15,%v17,%v20 ++ vmlhw %v15,%v17,%v20 ++ vmlf %v15,%v17,%v20 ++ vme %v15,%v17,%v20,13 ++ vmeb %v15,%v17,%v20 ++ vmeh %v15,%v17,%v20 ++ vmef %v15,%v17,%v20 ++ vmle %v15,%v17,%v20,13 ++ vmleb %v15,%v17,%v20 ++ vmleh %v15,%v17,%v20 ++ vmlef %v15,%v17,%v20 ++ vmo %v15,%v17,%v20,13 ++ vmob %v15,%v17,%v20 ++ vmoh %v15,%v17,%v20 ++ vmof %v15,%v17,%v20 ++ vmlo %v15,%v17,%v20,13 ++ vmlob %v15,%v17,%v20 ++ vmloh %v15,%v17,%v20 ++ vmlof %v15,%v17,%v20 ++ vno %v15,%v17,%v20 ++ vnot %v15,%v17 ++ vo %v15,%v17,%v20 ++ vpopct %v15,%v17,13 ++ verllv %v15,%v17,%v20,13 ++ verllvb %v15,%v17,%v20 ++ verllvh %v15,%v17,%v20 ++ verllvf %v15,%v17,%v20 ++ verllvg %v15,%v17,%v20 ++ verll %v15,%v17,4000(%r6),13 ++ verllb %v15,%v17,4000(%r6) ++ verllh %v15,%v17,4000(%r6) ++ verllf %v15,%v17,4000(%r6) ++ verllg %v15,%v17,4000(%r6) ++ verim %v15,%v17,%v20,253,12 ++ verimb %v15,%v17,%v20,253 ++ verimh %v15,%v17,%v20,253 ++ verimf %v15,%v17,%v20,253 ++ verimg %v15,%v17,%v20,253 ++ veslv %v15,%v17,%v20,13 ++ veslvb %v15,%v17,%v20 ++ veslvh %v15,%v17,%v20 ++ veslvf %v15,%v17,%v20 ++ veslvg %v15,%v17,%v20 ++ vesl %v15,%v17,4000(%r6),13 ++ veslb %v15,%v17,4000(%r6) ++ veslh %v15,%v17,4000(%r6) ++ veslf %v15,%v17,4000(%r6) ++ veslg %v15,%v17,4000(%r6) ++ vesrav %v15,%v17,%v20,13 ++ vesravb %v15,%v17,%v20 ++ vesravh %v15,%v17,%v20 ++ vesravf %v15,%v17,%v20 ++ vesravg %v15,%v17,%v20 ++ vesra %v15,%v17,4000(%r6),13 ++ vesrab %v15,%v17,4000(%r6) ++ vesrah %v15,%v17,4000(%r6) ++ vesraf %v15,%v17,4000(%r6) ++ vesrag %v15,%v17,4000(%r6) ++ vesrlv %v15,%v17,%v20,13 ++ vesrlvb %v15,%v17,%v20 ++ vesrlvh %v15,%v17,%v20 ++ vesrlvf %v15,%v17,%v20 ++ vesrlvg %v15,%v17,%v20 ++ vesrl %v15,%v17,4000(%r6),13 ++ vesrlb %v15,%v17,4000(%r6) ++ vesrlh %v15,%v17,4000(%r6) ++ vesrlf %v15,%v17,4000(%r6) ++ vesrlg %v15,%v17,4000(%r6) ++ vsl %v15,%v17,%v20 ++ vslb %v15,%v17,%v20 ++ vsldb %v15,%v17,%v20,253 ++ vsra %v15,%v17,%v20 ++ vsrab %v15,%v17,%v20 ++ vsrl %v15,%v17,%v20 ++ vsrlb %v15,%v17,%v20 ++ vs %v15,%v17,%v20,13 ++ vsb %v15,%v17,%v20 ++ vsh %v15,%v17,%v20 ++ vsf %v15,%v17,%v20 ++ vsg %v15,%v17,%v20 ++ vsq %v15,%v17,%v20 ++ vscbi %v15,%v17,%v20,13 ++ vscbib %v15,%v17,%v20 ++ vscbih %v15,%v17,%v20 ++ vscbif %v15,%v17,%v20 ++ vscbig %v15,%v17,%v20 ++ vscbiq %v15,%v17,%v20 ++ vsbi %v15,%v17,%v20,%v24,13 ++ vsbiq %v15,%v17,%v20,%v24 ++ vsbcbi %v15,%v17,%v20,%v24,13 ++ vsbcbiq %v15,%v17,%v20,%v24 ++ vsumg %v15,%v17,%v20,13 ++ vsumgh %v15,%v17,%v20 ++ vsumgf %v15,%v17,%v20 ++ vsumq %v15,%v17,%v20,13 ++ vsumqf %v15,%v17,%v20 ++ vsumqg %v15,%v17,%v20 ++ vsum %v15,%v17,%v20,13 ++ vsumb %v15,%v17,%v20 ++ vsumh %v15,%v17,%v20 ++ vtm %v15,%v17 ++ vfae %v15,%v17,%v20,13 ++ vfae %v15,%v17,%v20,13,12 ++ vfaeb %v15,%v17,%v20 ++ vfaeb %v15,%v17,%v20,13 ++ vfaeh %v15,%v17,%v20 ++ vfaeh %v15,%v17,%v20,13 ++ vfaef %v15,%v17,%v20 ++ vfaef %v15,%v17,%v20,13 ++ vfaebs %v15,%v17,%v20 ++ vfaebs %v15,%v17,%v20,13 ++ vfaehs %v15,%v17,%v20 ++ vfaehs %v15,%v17,%v20,13 ++ vfaefs %v15,%v17,%v20 ++ vfaefs %v15,%v17,%v20,13 ++ vfaezb %v15,%v17,%v20 ++ vfaezb %v15,%v17,%v20,13 ++ vfaezh %v15,%v17,%v20 ++ vfaezh %v15,%v17,%v20,13 ++ vfaezf %v15,%v17,%v20 ++ vfaezf %v15,%v17,%v20,13 ++ vfaezbs %v15,%v17,%v20 ++ vfaezbs %v15,%v17,%v20,13 ++ vfaezhs %v15,%v17,%v20 ++ vfaezhs %v15,%v17,%v20,13 ++ vfaezfs %v15,%v17,%v20 ++ vfaezfs %v15,%v17,%v20,13 ++ vfee %v15,%v17,%v20,13 ++ vfee %v15,%v17,%v20,13,12 ++ vfeeb %v15,%v17,%v20 ++ vfeeb %v15,%v17,%v20,13 ++ vfeeh %v15,%v17,%v20 ++ vfeeh %v15,%v17,%v20,13 ++ vfeef %v15,%v17,%v20 ++ vfeef %v15,%v17,%v20,13 ++ vfeebs %v15,%v17,%v20 ++ vfeehs %v15,%v17,%v20 ++ vfeefs %v15,%v17,%v20 ++ vfeezb %v15,%v17,%v20 ++ vfeezh %v15,%v17,%v20 ++ vfeezf %v15,%v17,%v20 ++ vfeezbs %v15,%v17,%v20 ++ vfeezhs %v15,%v17,%v20 ++ vfeezfs %v15,%v17,%v20 ++ vfene %v15,%v17,%v20,13 ++ vfene %v15,%v17,%v20,13,12 ++ vfeneb %v15,%v17,%v20 ++ vfeneb %v15,%v17,%v20,13 ++ vfeneh %v15,%v17,%v20 ++ vfeneh %v15,%v17,%v20,13 ++ vfenef %v15,%v17,%v20 ++ vfenef %v15,%v17,%v20,13 ++ vfenebs %v15,%v17,%v20 ++ vfenehs %v15,%v17,%v20 ++ vfenefs %v15,%v17,%v20 ++ vfenezb %v15,%v17,%v20 ++ vfenezh %v15,%v17,%v20 ++ vfenezf %v15,%v17,%v20 ++ vfenezbs %v15,%v17,%v20 ++ vfenezhs %v15,%v17,%v20 ++ vfenezfs %v15,%v17,%v20 ++ vistr %v15,%v17,13 ++ vistr %v15,%v17,13,12 ++ vistrb %v15,%v17 ++ vistrb %v15,%v17,13 ++ vistrh %v15,%v17 ++ vistrh %v15,%v17,13 ++ vistrf %v15,%v17 ++ vistrf %v15,%v17,13 ++ vistrbs %v15,%v17 ++ vistrhs %v15,%v17 ++ vistrfs %v15,%v17 ++ vstrc %v15,%v17,%v20,%v24,13 ++ vstrc %v15,%v17,%v20,%v24,13,12 ++ vstrcb %v15,%v17,%v20,%v24 ++ vstrcb %v15,%v17,%v20,%v24,13 ++ vstrch %v15,%v17,%v20,%v24 ++ vstrch %v15,%v17,%v20,%v24,13 ++ vstrcf %v15,%v17,%v20,%v24 ++ vstrcf %v15,%v17,%v20,%v24,13 ++ vstrcbs %v15,%v17,%v20,%v24 ++ vstrcbs %v15,%v17,%v20,%v24,13 ++ vstrchs %v15,%v17,%v20,%v24 ++ vstrchs %v15,%v17,%v20,%v24,13 ++ vstrcfs %v15,%v17,%v20,%v24 ++ vstrcfs %v15,%v17,%v20,%v24,13 ++ vstrczb %v15,%v17,%v20,%v24 ++ vstrczb %v15,%v17,%v20,%v24,13 ++ vstrczh %v15,%v17,%v20,%v24 ++ vstrczh %v15,%v17,%v20,%v24,13 ++ vstrczf %v15,%v17,%v20,%v24 ++ vstrczf %v15,%v17,%v20,%v24,13 ++ vstrczbs %v15,%v17,%v20,%v24 ++ vstrczbs %v15,%v17,%v20,%v24,13 ++ vstrczhs %v15,%v17,%v20,%v24 ++ vstrczhs %v15,%v17,%v20,%v24,13 ++ vstrczfs %v15,%v17,%v20,%v24 ++ vstrczfs %v15,%v17,%v20,%v24,13 ++ vfa %v15,%v17,%v20,13,12 ++ vfadb %v15,%v17,%v20 ++ wfadb %v15,%v17,%v20 ++ wfc %v15,%v17,13,12 ++ wfcdb %v15,%v17 ++ wfk %v15,%v17,13,12 ++ wfkdb %v15,%v17 ++ vfce %v15,%v17,%v20,13,12,11 ++ vfcedb %v15,%v17,%v20 ++ vfcedbs %v15,%v17,%v20 ++ wfcedb %v15,%v17,%v20 ++ wfcedbs %v15,%v17,%v20 ++ vfch %v15,%v17,%v20,13,12,11 ++ vfchdb %v15,%v17,%v20 ++ vfchdbs %v15,%v17,%v20 ++ wfchdb %v15,%v17,%v20 ++ wfchdbs %v15,%v17,%v20 ++ vfche %v15,%v17,%v20,13,12,11 ++ vfchedb %v15,%v17,%v20 ++ vfchedbs %v15,%v17,%v20 ++ wfchedb %v15,%v17,%v20 ++ wfchedbs %v15,%v17,%v20 ++ vcdg %v15,%v17,13,12,11 ++ vcdgb %v15,%v17,13,12 ++ wcdgb %v15,%v17,13,12 ++ vcdlg %v15,%v17,13,12,11 ++ vcdlgb %v15,%v17,13,12 ++ wcdlgb %v15,%v17,13,12 ++ vcgd %v15,%v17,13,12,11 ++ vcgdb %v15,%v17,13,12 ++ wcgdb %v15,%v17,13,12 ++ vclgd %v15,%v17,13,12,11 ++ vclgdb %v15,%v17,13,12 ++ wclgdb %v15,%v17,13,12 ++ vfd %v15,%v17,%v20,13,12 ++ vfddb %v15,%v17,%v20 ++ wfddb %v15,%v17,%v20 ++ vfi %v15,%v17,13,12,11 ++ vfidb %v15,%v17,13,12 ++ wfidb %v15,%v17,13,12 ++ vlde %v15,%v17,13,12 ++ vldeb %v15,%v17 ++ wldeb %v15,%v17 ++ vled %v15,%v17,13,12,11 ++ vledb %v15,%v17,13,12 ++ wledb %v15,%v17,13,12 ++ vfm %v15,%v17,%v20,13,12 ++ vfmdb %v15,%v17,%v20 ++ wfmdb %v15,%v17,%v20 ++ vfma %v15,%v17,%v20,%v24,13,12 ++ vfmadb %v15,%v17,%v20,%v24 ++ wfmadb %v15,%v17,%v20,%v24 ++ vfms %v15,%v17,%v20,%v24,13,12 ++ vfmsdb %v15,%v17,%v20,%v24 ++ wfmsdb %v15,%v17,%v20,%v24 ++ vfpso %v15,%v17,13,12,11 ++ vfpsodb %v15,%v17,13 ++ wfpsodb %v15,%v17,13 ++ vflcdb %v15,%v17 ++ wflcdb %v15,%v17 ++ vflndb %v15,%v17 ++ wflndb %v15,%v17 ++ vflpdb %v15,%v17 ++ wflpdb %v15,%v17 ++ vfsq %v15,%v17,13,12 ++ vfsqdb %v15,%v17 ++ wfsqdb %v15,%v17 ++ vfs %v15,%v17,%v20,13,12 ++ vfsdb %v15,%v17,%v20 ++ wfsdb %v15,%v17,%v20 ++ vftci %v15,%v17,4093,12,11 ++ vftcidb %v15,%v17,4093 ++ wftcidb %v15,%v17,4093 ++ cdpt %f3,4000(251,%r6),12 ++ cxpt %f1,4000(251,%r6),12 ++ cpdt %f3,4000(251,%r6),12 ++ cpxt %f1,4000(251,%r6),12 ++ locfhr %r6,%r9,13 ++ locfhro %r6,%r9 ++ locfhrh %r6,%r9 ++ locfhrp %r6,%r9 ++ locfhrnle %r6,%r9 ++ locfhrl %r6,%r9 ++ locfhrm %r6,%r9 ++ locfhrnhe %r6,%r9 ++ locfhrlh %r6,%r9 ++ locfhrne %r6,%r9 ++ locfhrnz %r6,%r9 ++ locfhre %r6,%r9 ++ locfhrz %r6,%r9 ++ locfhrnlh %r6,%r9 ++ locfhrhe %r6,%r9 ++ locfhrnl %r6,%r9 ++ locfhrnm %r6,%r9 ++ locfhrle %r6,%r9 ++ locfhrnh %r6,%r9 ++ locfhrnp %r6,%r9 ++ locfhrno %r6,%r9 ++ locfh %r6,-10000(%r9),13 ++ locfho %r6,-10000(%r9) ++ locfhh %r6,-10000(%r9) ++ locfhp %r6,-10000(%r9) ++ locfhnle %r6,-10000(%r9) ++ locfhl %r6,-10000(%r9) ++ locfhm %r6,-10000(%r9) ++ locfhnhe %r6,-10000(%r9) ++ locfhlh %r6,-10000(%r9) ++ locfhne %r6,-10000(%r9) ++ locfhnz %r6,-10000(%r9) ++ locfhe %r6,-10000(%r9) ++ locfhz %r6,-10000(%r9) ++ locfhnlh %r6,-10000(%r9) ++ locfhhe %r6,-10000(%r9) ++ locfhnl %r6,-10000(%r9) ++ locfhnm %r6,-10000(%r9) ++ locfhle %r6,-10000(%r9) ++ locfhnh %r6,-10000(%r9) ++ locfhnp %r6,-10000(%r9) ++ locfhno %r6,-10000(%r9) ++ lochi %r6,-32765,12 ++ lochio %r6,-32765 ++ lochih %r6,-32765 ++ lochip %r6,-32765 ++ lochinle %r6,-32765 ++ lochil %r6,-32765 ++ lochim %r6,-32765 ++ lochinhe %r6,-32765 ++ lochilh %r6,-32765 ++ lochine %r6,-32765 ++ lochinz %r6,-32765 ++ lochie %r6,-32765 ++ lochiz %r6,-32765 ++ lochinlh %r6,-32765 ++ lochihe %r6,-32765 ++ lochinl %r6,-32765 ++ lochinm %r6,-32765 ++ lochile %r6,-32765 ++ lochinh %r6,-32765 ++ lochinp %r6,-32765 ++ lochino %r6,-32765 ++ locghi %r6,-32765,12 ++ locghio %r6,-32765 ++ locghih %r6,-32765 ++ locghip %r6,-32765 ++ locghinle %r6,-32765 ++ locghil %r6,-32765 ++ locghim %r6,-32765 ++ locghinhe %r6,-32765 ++ locghilh %r6,-32765 ++ locghine %r6,-32765 ++ locghinz %r6,-32765 ++ locghie %r6,-32765 ++ locghiz %r6,-32765 ++ locghinlh %r6,-32765 ++ locghihe %r6,-32765 ++ locghinl %r6,-32765 ++ locghinm %r6,-32765 ++ locghile %r6,-32765 ++ locghinh %r6,-32765 ++ locghinp %r6,-32765 ++ locghino %r6,-32765 ++ lochhi %r6,-32765,12 ++ lochhio %r6,-32765 ++ lochhih %r6,-32765 ++ lochhip %r6,-32765 ++ lochhinle %r6,-32765 ++ lochhil %r6,-32765 ++ lochhim %r6,-32765 ++ lochhinhe %r6,-32765 ++ lochhilh %r6,-32765 ++ lochhine %r6,-32765 ++ lochhinz %r6,-32765 ++ lochhie %r6,-32765 ++ lochhiz %r6,-32765 ++ lochhinlh %r6,-32765 ++ lochhihe %r6,-32765 ++ lochhinl %r6,-32765 ++ lochhinm %r6,-32765 ++ lochhile %r6,-32765 ++ lochhinh %r6,-32765 ++ lochhinp %r6,-32765 ++ lochhino %r6,-32765 ++ stocfh %r6,-10000(%r9),13 ++ stocfho %r6,-10000(%r9) ++ stocfhh %r6,-10000(%r9) ++ stocfhp %r6,-10000(%r9) ++ stocfhnle %r6,-10000(%r9) ++ stocfhl %r6,-10000(%r9) ++ stocfhm %r6,-10000(%r9) ++ stocfhnhe %r6,-10000(%r9) ++ stocfhlh %r6,-10000(%r9) ++ stocfhne %r6,-10000(%r9) ++ stocfhnz %r6,-10000(%r9) ++ stocfhe %r6,-10000(%r9) ++ stocfhz %r6,-10000(%r9) ++ stocfhnlh %r6,-10000(%r9) ++ stocfhhe %r6,-10000(%r9) ++ stocfhnl %r6,-10000(%r9) ++ stocfhnm %r6,-10000(%r9) ++ stocfhle %r6,-10000(%r9) ++ stocfhnh %r6,-10000(%r9) ++ stocfhnp %r6,-10000(%r9) ++ stocfhno %r6,-10000(%r9) ++ llzrgf %r6,-10000(%r9,%r11) ++ lzrf %r6,-10000(%r9,%r11) ++ lzrg %r6,-10000(%r9,%r11) ++ ppno %r6,%r9 +diff -Nrup a/gas/testsuite/gas/s390/zarch-z196.d b/gas/testsuite/gas/s390/zarch-z196.d +--- a/gas/testsuite/gas/s390/zarch-z196.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/zarch-z196.d 2015-05-04 15:14:02.819668662 -0600 +@@ -22,6 +22,7 @@ Disassembly of section .text: + .*: b9 df 00 67 [ ]*clhlr %r6,%r7 + .*: e3 67 85 b3 01 cf [ ]*clhf %r6,5555\(%r7,%r8\) + .*: cc 6f 00 09 eb 10 [ ]*clih %r6,650000 ++.*: cc 9f ee 6b 28 00 [ ]*clih %r9,4000000000 + .*: e3 67 8a 4d fe c0 [ ]*lbh %r6,-5555\(%r7,%r8\) + .*: e3 67 8a 4d fe c4 [ ]*lhh %r6,-5555\(%r7,%r8\) + .*: e3 67 8a 4d fe ca [ ]*lfh %r6,-5555\(%r7,%r8\) +@@ -257,3 +258,4 @@ Disassembly of section .text: + .*: b9 2b 00 56 [ ]*kmo %r5,%r6 + .*: b9 2c 00 00 [ ]*pcc + .*: b9 2d 90 56 [ ]*kmctr %r5,%r6,%r9 ++.*: 07 07 [ ]*nopr %r7 +diff -Nrup a/gas/testsuite/gas/s390/zarch-z196.s b/gas/testsuite/gas/s390/zarch-z196.s +--- a/gas/testsuite/gas/s390/zarch-z196.s 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/zarch-z196.s 2015-05-04 15:14:02.820668641 -0600 +@@ -16,6 +16,7 @@ foo: + clhlr %r6,%r7 + clhf %r6,5555(%r7,%r8) + clih %r6,650000 ++ clih %r9,4000000000 + lbh %r6,-5555(%r7,%r8) + lhh %r6,-5555(%r7,%r8) + lfh %r6,-5555(%r7,%r8) +diff -Nrup a/gas/testsuite/gas/s390/zarch-z9-109.d b/gas/testsuite/gas/s390/zarch-z9-109.d +--- a/gas/testsuite/gas/s390/zarch-z9-109.d 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/zarch-z9-109.d 2015-05-04 15:15:18.084075754 -0600 +@@ -45,12 +45,17 @@ Disassembly of section .text: + .*: c8 60 5f ff af ff [ ]*mvcos 4095\(%r5\),4095\(%r10\),%r6 + .*: b9 aa 9f 65 [ ]*lptea %r6,%r9,%r5,15 + .*: b2 2b f0 69 [ ]*sske %r6,%r9,15 ++.*: b2 2b 00 69 [ ]*sske %r6,%r9 + .*: b9 b1 f0 68 [ ]*cu24 %r6,%r8,15 ++.*: b9 b1 00 68 [ ]*cu24 %r6,%r8 + .*: b2 a6 f0 68 [ ]*cu21 %r6,%r8,15 ++.*: b2 a6 00 68 [ ]*cuutf %r6,%r8 + .*: b9 b3 00 68 [ ]*cu42 %r6,%r8 + .*: b9 b2 00 68 [ ]*cu41 %r6,%r8 + .*: b2 a7 f0 68 [ ]*cu12 %r6,%r8,15 ++.*: b2 a7 00 68 [ ]*cutfu %r6,%r8 + .*: b9 b0 f0 68 [ ]*cu14 %r6,%r8,15 ++.*: b9 b0 00 68 [ ]*cu14 %r6,%r8 + .*: b3 3b 60 95 [ ]*myr %f6,%f9,%f5 + .*: b3 3d 60 95 [ ]*myhr %f6,%f9,%f5 + .*: b3 39 60 95 [ ]*mylr %f6,%f9,%f5 +diff -Nrup a/gas/testsuite/gas/s390/zarch-z9-109.s b/gas/testsuite/gas/s390/zarch-z9-109.s +--- a/gas/testsuite/gas/s390/zarch-z9-109.s 2013-02-27 13:28:03.000000000 -0700 ++++ b/gas/testsuite/gas/s390/zarch-z9-109.s 2015-05-04 15:15:18.084075754 -0600 +@@ -39,12 +39,17 @@ foo: + mvcos 4095(%r5),4095(%r10),%r6 + lptea %r6,%r9,%r5,15 + sske %r6,%r9,15 ++ sske %r6,%r9 + cu24 %r6,%r8,15 ++ cu24 %r6,%r8 + cu21 %r6,%r8,15 ++ cu21 %r6,%r8 + cu42 %r6,%r8 + cu41 %r6,%r8 + cu12 %r6,%r8,15 ++ cu12 %r6,%r8 + cu14 %r6,%r8,15 ++ cu14 %r6,%r8 + myr %f6,%f9,%f5 + myhr %f6,%f9,%f5 + mylr %f6,%f9,%f5 +diff -Nrup a/gas/testsuite/gas/s390/zarch-zEC12.d b/gas/testsuite/gas/s390/zarch-zEC12.d +--- a/gas/testsuite/gas/s390/zarch-zEC12.d 2015-05-04 15:06:06.285746808 -0600 ++++ b/gas/testsuite/gas/s390/zarch-zEC12.d 2015-05-04 15:15:18.084075754 -0600 +@@ -1,5 +1,5 @@ + #name: s390x opcode +-#objdump: -drw ++#objdump: -dr + + .*: +file format .* + +@@ -13,7 +13,7 @@ Disassembly of section .text: + .*: e5 61 6f a0 fd e8 [ ]*tbeginc 4000\(%r6\),65000 + .*: b2 f8 00 00 [ ]*tend + .*: c7 a0 6f a0 00 00 [ ]*bpp 10,1e ,4000\(%r6\) +-.*: c5 a0 00 fe c7 80 [ ]*bprp 10,24 ,-80000 ++.*: c5 a0 00 00 00 0c [ ]*bprp 10,24 ,3c + .*: b2 fa 00 ad [ ]*niai 10,13 + .*: e3 67 8a 4d fe 9f [ ]*lat %r6,-5555\(%r7,%r8\) + .*: e3 67 8a 4d fe 85 [ ]*lgat %r6,-5555\(%r7,%r8\) +@@ -52,6 +52,11 @@ Disassembly of section .text: + .*: ed 0f 8f a0 6d a8 [ ]*czdt %f6,4000\(16,%r8\),13 + .*: ed 21 8f a0 4d a9 [ ]*czxt %f4,4000\(34,%r8\),13 + .*: b2 e8 c0 56 [ ]*ppa %r5,%r6,12 +-.*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9,0 ++.*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9 + .*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1 +-.*: 07 07 [ ]*nopr %r7 ++.*: c5 a0 06 00 00 06 [ ]*bprp 10,11e ,11e ++.*: c5 a0 00 00 00 00 [ ]*bprp 10,118 ,118 ++[ ]*119: R_390_PLT12DBL bar\+0x1 ++[ ]*11b: R_390_PLT24DBL bar\+0x3 ++.* : ++.*: 07 07 [ ]*nopr %r7 +diff -Nrup a/gas/testsuite/gas/s390/zarch-zEC12.s b/gas/testsuite/gas/s390/zarch-zEC12.s +--- a/gas/testsuite/gas/s390/zarch-zEC12.s 2015-05-04 15:06:06.285746808 -0600 ++++ b/gas/testsuite/gas/s390/zarch-zEC12.s 2015-05-04 15:13:38.614180951 -0600 +@@ -7,7 +7,7 @@ foo: + tbeginc 4000(%r6),65000 + tend + bpp 10,.,4000(%r6) +- bprp 10,.,-80000 ++ bprp 10,.,.+24 + niai 10,13 + lat %r6,-5555(%r7,%r8) + lgat %r6,-5555(%r7,%r8) +@@ -52,3 +52,7 @@ foo: + ppa %r5,%r6,12 + crdte %r5,%r6,%r9 + crdte %r5,%r6,%r9,1 ++ ++ bprp 10,bar,bar ++ bprp 10,bar@PLT,bar@PLT ++bar: +diff -Nrup a/include/elf/common.h b/include/elf/common.h +--- a/include/elf/common.h 2015-05-04 15:06:06.283746851 -0600 ++++ b/include/elf/common.h 2015-05-04 15:15:23.111969343 -0600 +@@ -558,6 +558,10 @@ + /* note name must be "LINUX". */ + #define NT_S390_TDB 0x308 /* S390 transaction diagnostic block */ + /* note name must be "LINUX". */ ++#define NT_S390_VXRS_LOW 0x309 /* S390 vector registers 0-15 upper half */ ++ /* note name must be "LINUX". */ ++#define NT_S390_VXRS_HIGH 0x30a /* S390 vector registers 16-31 */ ++ /* note name must be "LINUX". */ + #define NT_ARM_VFP 0x400 /* ARM VFP registers */ + /* The following definitions should really use NT_AARCH_..., but defined + this way for compatibility with Linux. */ +diff -Nrup a/include/elf/s390.h b/include/elf/s390.h +--- a/include/elf/s390.h 2013-02-27 13:28:03.000000000 -0700 ++++ b/include/elf/s390.h 2015-05-04 15:13:38.614180951 -0600 +@@ -57,8 +57,12 @@ START_RELOC_NUMBERS (elf_s390_reloc_type + RELOC_NUMBER (R_390_GOTPC, 14) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_390_GOT16, 15) /* 16 bit GOT offset. */ + RELOC_NUMBER (R_390_PC16, 16) /* PC relative 16 bit. */ ++ RELOC_NUMBER (R_390_PC12DBL, 62) /* PC relative 12 bit shifted by 1. */ ++ RELOC_NUMBER (R_390_PLT12DBL, 63) /* 12 bit PC rel. PLT shifted by 1. */ + RELOC_NUMBER (R_390_PC16DBL, 17) /* PC relative 16 bit shifted by 1. */ + RELOC_NUMBER (R_390_PLT16DBL, 18) /* 16 bit PC rel. PLT shifted by 1. */ ++ RELOC_NUMBER (R_390_PC24DBL, 64) /* PC relative 24 bit shifted by 1. */ ++ RELOC_NUMBER (R_390_PLT24DBL, 65) /* 24 bit PC rel. PLT shifted by 1. */ + RELOC_NUMBER (R_390_PC32DBL, 19) /* PC relative 32 bit shifted by 1. */ + RELOC_NUMBER (R_390_PLT32DBL, 20) /* 32 bit PC rel. PLT shifted by 1. */ + RELOC_NUMBER (R_390_GOTPCDBL, 21) /* 32 bit PC rel. GOT shifted by 1. */ +diff -Nrup a/include/opcode/s390.h b/include/opcode/s390.h +--- a/include/opcode/s390.h 2013-02-27 13:28:03.000000000 -0700 ++++ b/include/opcode/s390.h 2015-05-04 15:15:18.084075754 -0600 +@@ -41,9 +41,13 @@ enum s390_opcode_cpu_val + S390_OPCODE_Z10, + S390_OPCODE_Z196, + S390_OPCODE_ZEC12, ++ S390_OPCODE_Z13, + S390_OPCODE_MAXCPU + }; + ++/* Instruction specific flags. */ ++#define S390_INSTR_FLAG_OPTPARM 0x1 ++ + /* The opcode table is an array of struct s390_opcode. */ + + struct s390_opcode +@@ -74,6 +78,9 @@ struct s390_opcode + + /* First cpu this opcode is available for. */ + enum s390_opcode_cpu_val min_cpu; ++ ++ /* Instruction specific flags. */ ++ unsigned int flags; + }; + + /* The table itself is sorted by major opcode number, and is otherwise +@@ -86,7 +93,7 @@ extern const int s390_num + extern const struct s390_opcode s390_opformats[]; + extern const int s390_num_opformats; + +-/* Values defined for the flags field of a struct powerpc_opcode. */ ++/* Values defined for the flags field of a struct s390_opcode. */ + + /* The operands table is an array of struct s390_operand. */ + +@@ -103,7 +110,7 @@ struct s390_operand + }; + + /* Elements in the table are retrieved by indexing with values from +- the operands field of the powerpc_opcodes table. */ ++ the operands field of the s390_opcodes table. */ + + extern const struct s390_operand s390_operands[]; + +@@ -151,4 +158,14 @@ extern const struct s390_operand s390_op + /* The operand needs to be a valid GP or FP register pair. */ + #define S390_OPERAND_REG_PAIR 0x800 + +- #endif /* S390_H */ ++/* This operand names a vector register. The disassembler uses this ++ to print register names with a leading 'v'. */ ++#define S390_OPERAND_VR 0x1000 ++ ++#define S390_OPERAND_CP16 0x2000 ++ ++#define S390_OPERAND_OR1 0x4000 ++#define S390_OPERAND_OR2 0x8000 ++#define S390_OPERAND_OR8 0x10000 ++ ++#endif /* S390_H */ +diff -Nrup a/ld/testsuite/ld-s390/gotreloc-1.s b/ld/testsuite/ld-s390/gotreloc-1.s +--- a/ld/testsuite/ld-s390/gotreloc-1.s 1969-12-31 17:00:00.000000000 -0700 ++++ b/ld/testsuite/ld-s390/gotreloc-1.s 2015-05-04 15:13:44.591054456 -0600 +@@ -0,0 +1,11 @@ ++ .text ++ .globl foo ++foo: ++ lgrl %r1,bar@GOTENT ++ lg %r1,bar@GOT(%r12) ++ lrl %r1,bar@GOTENT ++ l %r1,bar@GOT(%r12) ++ ly %r1,bar@GOT(%r12) ++ ++.globl bar ++bar: .long 0x123 +diff -Nrup a/ld/testsuite/ld-s390/gotreloc-1.ver b/ld/testsuite/ld-s390/gotreloc-1.ver +--- a/ld/testsuite/ld-s390/gotreloc-1.ver 1969-12-31 17:00:00.000000000 -0700 ++++ b/ld/testsuite/ld-s390/gotreloc-1.ver 2015-05-04 15:13:44.591054456 -0600 +@@ -0,0 +1 @@ ++{ local: bar; }; +--- a/ld/testsuite/ld-s390/gotreloc_31-1.dd 1969-12-31 17:00:00.000000000 -0700 ++++ b/ld/testsuite/ld-s390/gotreloc_31-1.dd 2015-05-06 15:30:44.328896292 -0600 +@@ -0,0 +1,13 @@ ++ ++tmpdir/gotreloc_31-1: file format elf32-s390 ++ ++Disassembly of section .text: ++ ++.* : ++.*: c4 18 00 00 08 4e [ ]*lgrl %r1,11e8 <_GLOBAL_OFFSET_TABLE_\+0xc> ++.*: e3 10 c0 0c 00 04 [ ]*lg %r1,12\(%r12\) ++.*: c0 10 00 00 00 08 [ ]*larl %r1,168 ++.*: 58 10 c0 0c [ ]*l %r1,12\(%r12\) ++.*: c0 10 00 00 00 03 [ ]*larl %r1,168 ++.* : ++.*: 00 00 01 23 .long 0x00000123 +diff -Nrup a/ld/testsuite/ld-s390/gotreloc_64-1.dd b/ld/testsuite/ld-s390/gotreloc_64-1.dd +--- a/ld/testsuite/ld-s390/gotreloc_64-1.dd 1969-12-31 17:00:00.000000000 -0700 ++++ b/ld/testsuite/ld-s390/gotreloc_64-1.dd 2015-05-04 15:13:44.591054456 -0600 +@@ -0,0 +1,12 @@ ++tmpdir/gotreloc_64-1: file format elf64-s390 ++ ++Disassembly of section .text: ++ ++.* : ++.*: c0 10 00 00 00 0e [ ]*larl %r1,.* ++.*: c0 10 00 00 00 0b [ ]*larl %r1,.* ++.*: c4 1d 00 00 08 86 [ ]*lrl %r1,.* <_GLOBAL_OFFSET_TABLE_\+0x18> ++.*: 58 10 c0 18 [ ]*l %r1,24\(%r12\) ++.*: e3 10 c0 18 00 58 [ ]*ly %r1,24\(%r12\) ++.* : ++.*: 00 00 01 23 .long 0x00000123 +diff -Nrup a/ld/testsuite/ld-s390/s390.exp b/ld/testsuite/ld-s390/s390.exp +--- a/ld/testsuite/ld-s390/s390.exp 2013-02-27 13:28:03.000000000 -0700 ++++ b/ld/testsuite/ld-s390/s390.exp 2015-05-04 15:13:44.591054456 -0600 +@@ -48,6 +48,11 @@ set s390tests { + {{readelf -Ssrl tlsbin.rd} {objdump -dzrj.text tlsbin.dd} + {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}} + "tlsbin"} ++ {"GOT: symbol address load from got to larl" ++ "-shared -melf_s390 --version-script=gotreloc-1.ver" "" ++ "-m31" {gotreloc-1.s} ++ {{objdump -dzrj.text gotreloc_31-1.dd}} ++ "gotreloc_31-1"} + } + + set s390xtests { +@@ -64,6 +69,11 @@ set s390xtests { + {{readelf -WSsrl tlsbin_64.rd} {objdump -dzrj.text tlsbin_64.dd} + {objdump -sj.got tlsbin_64.sd} {objdump -sj.tdata tlsbin_64.td}} + "tlsbin_64"} ++ {"GOT: symbol address load from got to larl" ++ "-shared -melf64_s390 --version-script=gotreloc-1.ver" "" ++ "-m64" {gotreloc-1.s} ++ {{objdump -dzrj.text gotreloc_64-1.dd}} ++ "gotreloc_64-1"} + } + + if [istarget "s390-*-*"] { +@@ -71,5 +81,6 @@ if [istarget "s390-*-*"] { + } + + if [istarget "s390x-*-*"] { ++ run_ld_link_tests $s390tests + run_ld_link_tests $s390xtests + } +diff -Nrup a/ld/testsuite/ld-s390/tlsbin.dd b/ld/testsuite/ld-s390/tlsbin.dd +--- a/ld/testsuite/ld-s390/tlsbin.dd 2013-02-27 13:28:03.000000000 -0700 ++++ b/ld/testsuite/ld-s390/tlsbin.dd 2015-05-04 15:15:18.085075733 -0600 +@@ -109,17 +109,17 @@ Disassembly of section .text: + # IE -> LE against global var defined in exec + +[0-9a-f]+: 58 30 d0 38 l %r3,56\(%r13\) + +[0-9a-f]+: 18 43 lr %r4,%r3 +- +[0-9a-f]+: 07 00 nopr %r0 ++ +[0-9a-f]+: 07 00 nopr + +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) + # IE -> LE against local var + +[0-9a-f]+: 58 30 d0 3c l %r3,60\(%r13\) + +[0-9a-f]+: 18 43 lr %r4,%r3 +- +[0-9a-f]+: 07 00 nopr %r0 ++ +[0-9a-f]+: 07 00 nopr + +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) + # IE -> LE against hidden var + +[0-9a-f]+: 58 30 d0 40 l %r3,64\(%r13\) + +[0-9a-f]+: 18 43 lr %r4,%r3 +- +[0-9a-f]+: 07 00 nopr %r0 ++ +[0-9a-f]+: 07 00 nopr + +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) + # IE against global var with small got access (no optimization) + +[0-9a-f]+: 58 30 c0 14 l %r3,20\(%r12\) +@@ -173,17 +173,17 @@ Disassembly of section .text: + # IE -> LE against global var defined in exec + +[0-9a-f]+: 58 30 d0 04 l %r3,4\(%r13\) + +[0-9a-f]+: 18 43 lr %r4,%r3 +- +[0-9a-f]+: 07 00 nopr %r0 ++ +[0-9a-f]+: 07 00 nopr + +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) + # IE -> LE against local var + +[0-9a-f]+: 58 30 d0 08 l %r3,8\(%r13\) + +[0-9a-f]+: 18 43 lr %r4,%r3 +- +[0-9a-f]+: 07 00 nopr %r0 ++ +[0-9a-f]+: 07 00 nopr + +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) + # IE -> LE against hidden but not local var + +[0-9a-f]+: 58 30 d0 0c l %r3,12\(%r13\) + +[0-9a-f]+: 18 43 lr %r4,%r3 +- +[0-9a-f]+: 07 00 nopr %r0 ++ +[0-9a-f]+: 07 00 nopr + +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\) + # LE, global var defined in exec + +[0-9a-f]+: 58 40 d0 10 l %r4,16\(%r13\) +diff -Nrup a/opcodes/s390-dis.c b/opcodes/s390-dis.c +--- a/opcodes/s390-dis.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/opcodes/s390-dis.c 2015-05-04 15:15:18.085075733 -0600 +@@ -36,19 +36,15 @@ static int current_arch_mask = 0; + static void + init_disasm (struct disassemble_info *info) + { +- const struct s390_opcode *opcode; +- const struct s390_opcode *opcode_end; ++ int i; + const char *p; + + memset (opc_index, 0, sizeof (opc_index)); +- opcode_end = s390_opcodes + s390_num_opcodes; +- for (opcode = s390_opcodes; opcode < opcode_end; opcode++) +- { +- opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes; +- while ((opcode < opcode_end) && +- (opcode[1].opcode[0] == opcode->opcode[0])) +- opcode++; +- } ++ ++ /* Reverse order, such that each opc_index ends up pointing to the ++ first matching entry instead of the last. */ ++ for (i = s390_num_opcodes; i--; ) ++ opc_index[s390_opcodes[i].opcode[0]] = i; + + for (p = info->disassembler_options; p != NULL; ) + { +@@ -65,32 +61,54 @@ init_disasm (struct disassemble_info *in + } + + if (!current_arch_mask) +- switch (info->mach) +- { +- case bfd_mach_s390_31: +- current_arch_mask = 1 << S390_OPCODE_ESA; +- break; +- case bfd_mach_s390_64: +- current_arch_mask = 1 << S390_OPCODE_ZARCH; +- break; +- default: +- abort (); +- } ++ current_arch_mask = 1 << S390_OPCODE_ZARCH; + + init_flag = 1; + } + ++/* Derive the length of an instruction from its first byte. */ ++ ++static inline int ++s390_insn_length (const bfd_byte *buffer) ++{ ++ /* 00xxxxxx -> 2, 01xxxxxx/10xxxxxx -> 4, 11xxxxxx -> 6. */ ++ return ((buffer[0] >> 6) + 3) & ~1U; ++} ++ ++/* Match the instruction in BUFFER against the given OPCODE, excluding ++ the first byte. */ ++ ++static inline int ++s390_insn_matches_opcode (const bfd_byte *buffer, ++ const struct s390_opcode *opcode) ++{ ++ return (buffer[1] & opcode->mask[1]) == opcode->opcode[1] ++ && (buffer[2] & opcode->mask[2]) == opcode->opcode[2] ++ && (buffer[3] & opcode->mask[3]) == opcode->opcode[3] ++ && (buffer[4] & opcode->mask[4]) == opcode->opcode[4] ++ && (buffer[5] & opcode->mask[5]) == opcode->opcode[5]; ++} ++ ++union operand_value ++{ ++ int i; ++ unsigned int u; ++}; ++ + /* Extracts an operand value from an instruction. */ + /* We do not perform the shift operation for larl-type address + operands here since that would lead to an overflow of the 32 bit + integer value. Instead the shift operation is done when printing +- the operand in print_insn_s390. */ ++ the operand. */ + +-static inline unsigned int +-s390_extract_operand (unsigned char *insn, const struct s390_operand *operand) ++static inline union operand_value ++s390_extract_operand (const bfd_byte *insn, ++ const struct s390_operand *operand) + { ++ union operand_value ret; + unsigned int val; + int bits; ++ const bfd_byte *orig_insn = insn; + + /* Extract fragments of the operand byte for byte. */ + insn += operand->shift / 8; +@@ -110,15 +128,130 @@ s390_extract_operand (unsigned char *ins + if (operand->bits == 20 && operand->shift == 20) + val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; + +- /* Sign extend value if the operand is signed or pc relative. */ +- if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) +- && (val & (1U << (operand->bits - 1)))) +- val |= (-1U << (operand->bits - 1)) << 1; +- +- /* Length x in an instructions has real length x + 1. */ +- if (operand->flags & S390_OPERAND_LENGTH) +- val++; +- return val; ++ /* Sign extend value if the operand is signed or pc relative. Avoid ++ integer overflows. */ ++ if (operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) ++ { ++ unsigned int m = 1U << (operand->bits - 1); ++ ++ if (val >= m) ++ ret.i = (int) (val - m) - 1 - (int) (m - 1U); ++ else ++ ret.i = (int) val; ++ } ++ else if (operand->flags & S390_OPERAND_LENGTH) ++ /* Length x in an instruction has real length x + 1. */ ++ ret.u = val + 1; ++ ++ else if (operand->flags & S390_OPERAND_VR) ++ { ++ /* Extract the extra bits for a vector register operand stored ++ in the RXB field. */ ++ unsigned vr = operand->shift == 32 ? 3 ++ : (unsigned) operand->shift / 4 - 2; ++ ++ ret.u = val | ((orig_insn[4] & (1 << (3 - vr))) << (vr + 1)); ++ } ++ else ++ ret.u = val; ++ ++ return ret; ++} ++ ++/* Print the S390 instruction in BUFFER, assuming that it matches the ++ given OPCODE. */ ++ ++static void ++s390_print_insn_with_opcode (bfd_vma memaddr, ++ struct disassemble_info *info, ++ const bfd_byte *buffer, ++ const struct s390_opcode *opcode) ++{ ++ const unsigned char *opindex; ++ char separator; ++ ++ /* Mnemonic. */ ++ info->fprintf_func (info->stream, "%s", opcode->name); ++ ++ /* Operands. */ ++ separator = '\t'; ++ for (opindex = opcode->operands; *opindex != 0; opindex++) ++ { ++ const struct s390_operand *operand = s390_operands + *opindex; ++ union operand_value val = s390_extract_operand (buffer, operand); ++ unsigned long flags = operand->flags; ++ ++ if ((flags & S390_OPERAND_INDEX) && val.u == 0) ++ continue; ++ if ((flags & S390_OPERAND_BASE) && ++ val.u == 0 && separator == '(') ++ { ++ separator = ','; ++ continue; ++ } ++ ++ /* For instructions with a last optional operand don't print it ++ if zero. */ ++ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) ++ && val.u == 0 ++ && opindex[1] == 0) ++ break; ++ ++ if (flags & S390_OPERAND_GPR) ++ info->fprintf_func (info->stream, "%c%%r%u", separator, val.u); ++ else if (flags & S390_OPERAND_FPR) ++ info->fprintf_func (info->stream, "%c%%f%u", separator, val.u); ++ else if (flags & S390_OPERAND_VR) ++ info->fprintf_func (info->stream, "%c%%v%i", separator, val.u); ++ else if (flags & S390_OPERAND_AR) ++ info->fprintf_func (info->stream, "%c%%a%u", separator, val.u); ++ else if (flags & S390_OPERAND_CR) ++ info->fprintf_func (info->stream, "%c%%c%u", separator, val.u); ++ else if (flags & S390_OPERAND_PCREL) ++ { ++ info->fprintf_func (info->stream, "%c", separator); ++ info->print_address_func (memaddr + val.i + val.i, info); ++ } ++ else if (flags & S390_OPERAND_SIGNED) ++ info->fprintf_func (info->stream, "%c%i", separator, val.i); ++ else ++ { ++ if (flags & S390_OPERAND_OR1) ++ val.u &= ~1; ++ if (flags & S390_OPERAND_OR2) ++ val.u &= ~2; ++ if (flags & S390_OPERAND_OR8) ++ val.u &= ~8; ++ ++ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) ++ && val.u == 0 ++ && opindex[1] == 0) ++ break; ++ info->fprintf_func (info->stream, "%c%u", separator, val.u); ++ } ++ ++ if (flags & S390_OPERAND_DISP) ++ separator = '('; ++ else if (flags & S390_OPERAND_BASE) ++ { ++ info->fprintf_func (info->stream, ")"); ++ separator = ','; ++ } ++ else ++ separator = ','; ++ } ++} ++ ++/* Check whether opcode A's mask is more specific than that of B. */ ++ ++static int ++opcode_mask_more_specific (const struct s390_opcode *a, ++ const struct s390_opcode *b) ++{ ++ return (((int) a->mask[0] + a->mask[1] + a->mask[2] ++ + a->mask[3] + a->mask[4] + a->mask[5]) ++ > ((int) b->mask[0] + b->mask[1] + b->mask[2] ++ + b->mask[3] + b->mask[4] + b->mask[5])); + } + + /* Print a S390 instruction. */ +@@ -127,11 +260,9 @@ int + print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info) + { + bfd_byte buffer[6]; +- const struct s390_opcode *opcode; +- const struct s390_opcode *opcode_end; ++ const struct s390_opcode *opcode = NULL; + unsigned int value; + int status, opsize, bufsize; +- char separator; + + if (init_flag == 0) + init_disasm (info); +@@ -141,156 +272,72 @@ print_insn_s390 (bfd_vma memaddr, struct + + /* Every S390 instruction is max 6 bytes long. */ + memset (buffer, 0, 6); +- status = (*info->read_memory_func) (memaddr, buffer, 6, info); ++ status = info->read_memory_func (memaddr, buffer, 6, info); + if (status != 0) + { + for (bufsize = 0; bufsize < 6; bufsize++) +- if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0) ++ if (info->read_memory_func (memaddr, buffer, bufsize + 1, info) != 0) + break; + if (bufsize <= 0) + { +- (*info->memory_error_func) (status, memaddr, info); ++ info->memory_error_func (status, memaddr, info); + return -1; + } +- /* Opsize calculation looks strange but it works +- 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes, +- 11xxxxxx -> 6 bytes. */ +- opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; ++ opsize = s390_insn_length (buffer); + status = opsize > bufsize; + } + else + { + bufsize = 6; +- opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; ++ opsize = s390_insn_length (buffer); + } + + if (status == 0) + { + const struct s390_opcode *op; + +- /* Find the first match in the opcode table. */ +- opcode_end = s390_opcodes + s390_num_opcodes; +- for (opcode = s390_opcodes + opc_index[(int) buffer[0]]; +- (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]); +- opcode++) ++ /* Find the "best match" in the opcode table. */ ++ for (op = s390_opcodes + opc_index[buffer[0]]; ++ op != s390_opcodes + s390_num_opcodes ++ && op->opcode[0] == buffer[0]; ++ op++) + { +- const struct s390_operand *operand; +- const unsigned char *opindex; +- +- /* Check architecture. */ +- if (!(opcode->modes & current_arch_mask)) +- continue; +- +- /* Check signature of the opcode. */ +- if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1] +- || (buffer[2] & opcode->mask[2]) != opcode->opcode[2] +- || (buffer[3] & opcode->mask[3]) != opcode->opcode[3] +- || (buffer[4] & opcode->mask[4]) != opcode->opcode[4] +- || (buffer[5] & opcode->mask[5]) != opcode->opcode[5]) +- continue; +- +- /* Advance to an opcode with a more specific mask. */ +- for (op = opcode + 1; op < opcode_end; op++) +- { +- if ((buffer[0] & op->mask[0]) != op->opcode[0]) +- break; +- +- if ((buffer[1] & op->mask[1]) != op->opcode[1] +- || (buffer[2] & op->mask[2]) != op->opcode[2] +- || (buffer[3] & op->mask[3]) != op->opcode[3] +- || (buffer[4] & op->mask[4]) != op->opcode[4] +- || (buffer[5] & op->mask[5]) != op->opcode[5]) +- continue; +- +- if (((int)opcode->mask[0] + opcode->mask[1] + +- opcode->mask[2] + opcode->mask[3] + +- opcode->mask[4] + opcode->mask[5]) < +- ((int)op->mask[0] + op->mask[1] + +- op->mask[2] + op->mask[3] + +- op->mask[4] + op->mask[5])) +- opcode = op; +- } +- +- /* The instruction is valid. */ +- if (opcode->operands[0] != 0) +- (*info->fprintf_func) (info->stream, "%s\t", opcode->name); +- else +- (*info->fprintf_func) (info->stream, "%s", opcode->name); +- +- /* Extract the operands. */ +- separator = 0; +- for (opindex = opcode->operands; *opindex != 0; opindex++) +- { +- operand = s390_operands + *opindex; +- value = s390_extract_operand (buffer, operand); +- +- if ((operand->flags & S390_OPERAND_INDEX) && value == 0) +- continue; +- if ((operand->flags & S390_OPERAND_BASE) && +- value == 0 && separator == '(') +- { +- separator = ','; +- continue; +- } +- +- if (separator) +- (*info->fprintf_func) (info->stream, "%c", separator); +- +- if (operand->flags & S390_OPERAND_GPR) +- (*info->fprintf_func) (info->stream, "%%r%i", value); +- else if (operand->flags & S390_OPERAND_FPR) +- (*info->fprintf_func) (info->stream, "%%f%i", value); +- else if (operand->flags & S390_OPERAND_AR) +- (*info->fprintf_func) (info->stream, "%%a%i", value); +- else if (operand->flags & S390_OPERAND_CR) +- (*info->fprintf_func) (info->stream, "%%c%i", value); +- else if (operand->flags & S390_OPERAND_PCREL) +- (*info->print_address_func) (memaddr + (int)value + (int)value, +- info); +- else if (operand->flags & S390_OPERAND_SIGNED) +- (*info->fprintf_func) (info->stream, "%i", (int) value); +- else +- (*info->fprintf_func) (info->stream, "%u", value); +- +- if (operand->flags & S390_OPERAND_DISP) +- { +- separator = '('; +- } +- else if (operand->flags & S390_OPERAND_BASE) +- { +- (*info->fprintf_func) (info->stream, ")"); +- separator = ','; +- } +- else +- separator = ','; +- } +- +- /* Found instruction, printed it, return its size. */ +- return opsize; ++ if ((op->modes & current_arch_mask) ++ && s390_insn_matches_opcode (buffer, op) ++ && (opcode == NULL ++ || opcode_mask_more_specific (op, opcode))) ++ opcode = op; + } +- /* No matching instruction found, fall through to hex print. */ + } + ++ if (opcode != NULL) ++ { ++ /* The instruction is valid. Print it and return its size. */ ++ s390_print_insn_with_opcode (memaddr, info, buffer, opcode); ++ return opsize; ++ } ++ ++ /* Fall back to hex print. */ + if (bufsize >= 4) + { + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + value = (value << 8) + (unsigned int) buffer[2]; + value = (value << 8) + (unsigned int) buffer[3]; +- (*info->fprintf_func) (info->stream, ".long\t0x%08x", value); ++ info->fprintf_func (info->stream, ".long\t0x%08x", value); + return 4; + } + else if (bufsize >= 2) + { + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; +- (*info->fprintf_func) (info->stream, ".short\t0x%04x", value); ++ info->fprintf_func (info->stream, ".short\t0x%04x", value); + return 2; + } + else + { + value = (unsigned int) buffer[0]; +- (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value); ++ info->fprintf_func (info->stream, ".byte\t0x%02x", value); + return 1; + } + } +diff -Nrup a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c +--- a/opcodes/s390-mkopc.c 2013-02-27 13:28:03.000000000 -0700 ++++ b/opcodes/s390-mkopc.c 2015-05-04 15:15:18.085075733 -0600 +@@ -22,26 +22,7 @@ + #include + #include + #include +- +-/* Taken from opcodes/s390.h */ +-enum s390_opcode_mode_val +- { +- S390_OPCODE_ESA = 0, +- S390_OPCODE_ZARCH +- }; +- +-enum s390_opcode_cpu_val +- { +- S390_OPCODE_G5 = 0, +- S390_OPCODE_G6, +- S390_OPCODE_Z900, +- S390_OPCODE_Z990, +- S390_OPCODE_Z9_109, +- S390_OPCODE_Z9_EC, +- S390_OPCODE_Z10, +- S390_OPCODE_Z196, +- S390_OPCODE_ZEC12 +- }; ++#include "opcode/s390.h" + + struct op_struct + { +@@ -50,6 +31,7 @@ struct op_struct + char format[16]; + int mode_bits; + int min_cpu; ++ int flags; + + unsigned long long sort_value; + int no_nibbles; +@@ -71,7 +53,7 @@ createTable (void) + + static void + insertOpcode (char *opcode, char *mnemonic, char *format, +- int min_cpu, int mode_bits) ++ int min_cpu, int mode_bits, int flags) + { + char *str; + unsigned long long sort_value; +@@ -115,6 +97,7 @@ insertOpcode (char *opcode, char *mnemon + op_array[ix].no_nibbles = no_nibbles; + op_array[ix].min_cpu = min_cpu; + op_array[ix].mode_bits = mode_bits; ++ op_array[ix].flags = flags; + no_ops++; + } + +@@ -176,7 +159,7 @@ const struct s390_cond_ext_format s390_c + + static void + insertExpandedMnemonic (char *opcode, char *mnemonic, char *format, +- int min_cpu, int mode_bits) ++ int min_cpu, int mode_bits, int flags) + { + char *tag; + char prefix[15]; +@@ -189,7 +172,7 @@ insertExpandedMnemonic (char *opcode, ch + + if (!(tag = strpbrk (mnemonic, "*$"))) + { +- insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits); ++ insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits, flags); + return; + } + +@@ -268,7 +251,7 @@ insertExpandedMnemonic (char *opcode, ch + opcode[mask_start] = ext_table[i].nibble; + strcat (new_mnemonic, ext_table[i].extension); + strcat (new_mnemonic, suffix); +- insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits); ++ insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits, flags); + } + return; + +@@ -286,7 +269,10 @@ static const char file_header[] = + " which bits in the actual opcode must match OPCODE.\n" + " OPERANDS is the list of operands.\n\n" + " The disassembler reads the table in order and prints the first\n" +- " instruction which matches. */\n\n" ++ " instruction which matches.\n" ++ " MODE_BITS - zarch or esa\n" ++ " MIN_CPU - number of the min cpu level required\n" ++ " FLAGS - instruction flags. */\n\n" + "const struct s390_opcode s390_opcodes[] =\n {\n"; + + /* `dumpTable': write opcode table. */ +@@ -311,7 +297,8 @@ dumpTable (void) + printf ("MASK_%s, INSTR_%s, ", + op_array[ix].format, op_array[ix].format); + printf ("%i, ", op_array[ix].mode_bits); +- printf ("%i}", op_array[ix].min_cpu); ++ printf ("%i, ", op_array[ix].min_cpu); ++ printf ("%i}", op_array[ix].flags); + if (ix < no_ops-1) + printf (",\n"); + else +@@ -339,67 +326,91 @@ main (void) + char description[80]; + char cpu_string[16]; + char modes_string[16]; ++ char flags_string[80]; + int min_cpu; + int mode_bits; ++ int flag_bits; ++ int num_matched; + char *str; + + if (currentLine[0] == '#' || currentLine[0] == '\n') + continue; + memset (opcode, 0, 8); +- if (sscanf (currentLine, "%15s %15s %15s \"%79[^\"]\" %15s %15s", +- opcode, mnemonic, format, description, +- cpu_string, modes_string) == 6) ++ num_matched = ++ sscanf (currentLine, "%15s %15s %15s \"%79[^\"]\" %15s %15s %79[^\n]", ++ opcode, mnemonic, format, description, ++ cpu_string, modes_string, flags_string); ++ if (num_matched != 6 && num_matched != 7) + { +- if (strcmp (cpu_string, "g5") == 0) +- min_cpu = S390_OPCODE_G5; +- else if (strcmp (cpu_string, "g6") == 0) +- min_cpu = S390_OPCODE_G6; +- else if (strcmp (cpu_string, "z900") == 0) +- min_cpu = S390_OPCODE_Z900; +- else if (strcmp (cpu_string, "z990") == 0) +- min_cpu = S390_OPCODE_Z990; +- else if (strcmp (cpu_string, "z9-109") == 0) +- min_cpu = S390_OPCODE_Z9_109; +- else if (strcmp (cpu_string, "z9-ec") == 0) +- min_cpu = S390_OPCODE_Z9_EC; +- else if (strcmp (cpu_string, "z10") == 0) +- min_cpu = S390_OPCODE_Z10; +- else if (strcmp (cpu_string, "z196") == 0) +- min_cpu = S390_OPCODE_Z196; +- else if (strcmp (cpu_string, "zEC12") == 0) +- min_cpu = S390_OPCODE_ZEC12; +- else { +- fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); +- exit (1); +- } ++ fprintf (stderr, "Couldn't scan line %s\n", currentLine); ++ exit (1); ++ } + +- str = modes_string; +- mode_bits = 0; ++ if (strcmp (cpu_string, "g5") == 0) ++ min_cpu = S390_OPCODE_G5; ++ else if (strcmp (cpu_string, "g6") == 0) ++ min_cpu = S390_OPCODE_G6; ++ else if (strcmp (cpu_string, "z900") == 0) ++ min_cpu = S390_OPCODE_Z900; ++ else if (strcmp (cpu_string, "z990") == 0) ++ min_cpu = S390_OPCODE_Z990; ++ else if (strcmp (cpu_string, "z9-109") == 0) ++ min_cpu = S390_OPCODE_Z9_109; ++ else if (strcmp (cpu_string, "z9-ec") == 0) ++ min_cpu = S390_OPCODE_Z9_EC; ++ else if (strcmp (cpu_string, "z10") == 0) ++ min_cpu = S390_OPCODE_Z10; ++ else if (strcmp (cpu_string, "z196") == 0) ++ min_cpu = S390_OPCODE_Z196; ++ else if (strcmp (cpu_string, "zEC12") == 0) ++ min_cpu = S390_OPCODE_ZEC12; ++ else if (strcmp (cpu_string, "z13") == 0) ++ min_cpu = S390_OPCODE_Z13; ++ else { ++ fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); ++ exit (1); ++ } ++ ++ str = modes_string; ++ mode_bits = 0; ++ do { ++ if (strncmp (str, "esa", 3) == 0 ++ && (str[3] == 0 || str[3] == ',')) { ++ mode_bits |= 1 << S390_OPCODE_ESA; ++ str += 3; ++ } else if (strncmp (str, "zarch", 5) == 0 ++ && (str[5] == 0 || str[5] == ',')) { ++ mode_bits |= 1 << S390_OPCODE_ZARCH; ++ str += 5; ++ } else { ++ fprintf (stderr, "Couldn't parse modes string %s\n", ++ modes_string); ++ exit (1); ++ } ++ if (*str == ',') ++ str++; ++ } while (*str != 0); ++ ++ flag_bits = 0; ++ ++ if (num_matched == 7) ++ { ++ str = flags_string; + do { +- if (strncmp (str, "esa", 3) == 0 +- && (str[3] == 0 || str[3] == ',')) { +- mode_bits |= 1 << S390_OPCODE_ESA; +- str += 3; +- } else if (strncmp (str, "zarch", 5) == 0 +- && (str[5] == 0 || str[5] == ',')) { +- mode_bits |= 1 << S390_OPCODE_ZARCH; +- str += 5; ++ if (strncmp (str, "optparm", 7) == 0 ++ && (str[7] == 0 || str[7] == ',')) { ++ flag_bits |= S390_INSTR_FLAG_OPTPARM; ++ str += 7; + } else { +- fprintf (stderr, "Couldn't parse modes string %s\n", +- modes_string); ++ fprintf (stderr, "Couldn't parse flags string %s\n", ++ flags_string); + exit (1); + } + if (*str == ',') + str++; + } while (*str != 0); +- +- insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits); +- } +- else +- { +- fprintf (stderr, "Couldn't scan line %s\n", currentLine); +- exit (1); + } ++ insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits, flag_bits); + } + + dumpTable (); +diff -Nrup a/opcodes/s390-opc.c b/opcodes/s390-opc.c +--- a/opcodes/s390-opc.c 2015-05-04 15:06:06.285746808 -0600 ++++ b/opcodes/s390-opc.c 2015-05-04 15:15:39.250627782 -0600 +@@ -45,194 +45,210 @@ const struct s390_operand s390_operands[ + + /* General purpose register operands. */ + +-#define R_8 1 /* GPR starting at position 8 */ ++#define R_8 1 /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR }, +-#define R_12 2 /* GPR starting at position 12 */ ++#define R_12 2 /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR }, +-#define RO_12 3 /* optional GPR starting at position 12 */ +- { 4, 12, S390_OPERAND_GPR | S390_OPERAND_OPTIONAL }, +-#define R_16 4 /* GPR starting at position 16 */ ++#define R_16 3 /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR }, +-#define R_20 5 /* GPR starting at position 20 */ ++#define R_20 4 /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR }, +-#define R_24 6 /* GPR starting at position 24 */ ++#define R_24 5 /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR }, +-#define R_28 7 /* GPR starting at position 28 */ ++#define R_28 6 /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR }, +-#define RO_28 8 /* optional GPR starting at position 28 */ +- { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }, +-#define R_32 9 /* GPR starting at position 32 */ ++#define R_32 7 /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR }, + + /* General purpose register pair operands. */ + +-#define RE_8 10 /* GPR starting at position 8 */ ++#define RE_8 8 /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_12 11 /* GPR starting at position 12 */ ++#define RE_12 9 /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_16 12 /* GPR starting at position 16 */ ++#define RE_16 10 /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_20 13 /* GPR starting at position 20 */ ++#define RE_20 11 /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_24 14 /* GPR starting at position 24 */ ++#define RE_24 12 /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_28 15 /* GPR starting at position 28 */ ++#define RE_28 13 /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +-#define RE_32 16 /* GPR starting at position 32 */ ++#define RE_32 14 /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, + +- + /* Floating point register operands. */ + +-#define F_8 17 /* FPR starting at position 8 */ ++#define F_8 15 /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR }, +-#define F_12 18 /* FPR starting at position 12 */ ++#define F_12 16 /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR }, +-#define F_16 19 /* FPR starting at position 16 */ ++#define F_16 17 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +-#define F_20 20 /* FPR starting at position 16 */ ++#define F_20 18 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +-#define F_24 21 /* FPR starting at position 24 */ ++#define F_24 19 /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR }, +-#define F_28 22 /* FPR starting at position 28 */ ++#define F_28 20 /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR }, +-#define F_32 23 /* FPR starting at position 32 */ ++#define F_32 21 /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR }, + + /* Floating point register pair operands. */ + +-#define FE_8 24 /* FPR starting at position 8 */ ++#define FE_8 22 /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_12 25 /* FPR starting at position 12 */ ++#define FE_12 23 /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_16 26 /* FPR starting at position 16 */ ++#define FE_16 24 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_20 27 /* FPR starting at position 16 */ ++#define FE_20 25 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_24 28 /* FPR starting at position 24 */ ++#define FE_24 26 /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_28 29 /* FPR starting at position 28 */ ++#define FE_28 27 /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +-#define FE_32 30 /* FPR starting at position 32 */ ++#define FE_32 28 /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, + ++/* Vector register operands. */ ++ ++/* For each of these operands and additional bit in the RXB operand is ++ needed. */ ++ ++#define V_8 29 /* Vector reg. starting at position 8 */ ++ { 4, 8, S390_OPERAND_VR }, ++#define V_12 30 /* Vector reg. starting at position 12 */ ++ { 4, 12, S390_OPERAND_VR }, ++#define V_CP16_12 31 /* Vector reg. starting at position 12 */ ++ { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ ++#define V_16 32 /* Vector reg. starting at position 16 */ ++ { 4, 16, S390_OPERAND_VR }, ++#define V_32 33 /* Vector reg. starting at position 32 */ ++ { 4, 32, S390_OPERAND_VR }, + + /* Access register operands. */ + +-#define A_8 31 /* Access reg. starting at position 8 */ ++#define A_8 34 /* Access reg. starting at position 8 */ + { 4, 8, S390_OPERAND_AR }, +-#define A_12 32 /* Access reg. starting at position 12 */ ++#define A_12 35 /* Access reg. starting at position 12 */ + { 4, 12, S390_OPERAND_AR }, +-#define A_24 33 /* Access reg. starting at position 24 */ ++#define A_24 36 /* Access reg. starting at position 24 */ + { 4, 24, S390_OPERAND_AR }, +-#define A_28 34 /* Access reg. starting at position 28 */ ++#define A_28 37 /* Access reg. starting at position 28 */ + { 4, 28, S390_OPERAND_AR }, + + /* Control register operands. */ + +-#define C_8 35 /* Control reg. starting at position 8 */ ++#define C_8 38 /* Control reg. starting at position 8 */ + { 4, 8, S390_OPERAND_CR }, +-#define C_12 36 /* Control reg. starting at position 12 */ ++#define C_12 39 /* Control reg. starting at position 12 */ + { 4, 12, S390_OPERAND_CR }, + + /* Base register operands. */ + +-#define B_16 37 /* Base register starting at position 16 */ ++#define B_16 40 /* Base register starting at position 16 */ + { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, +-#define B_32 38 /* Base register starting at position 32 */ ++#define B_32 41 /* Base register starting at position 32 */ + { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, + +-#define X_12 39 /* Index register starting at position 12 */ ++#define X_12 42 /* Index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, + ++#define VX_12 43 /* Vector index register starting at position 12 */ ++ { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR }, ++ + /* Address displacement operands. */ + +-#define D_20 40 /* Displacement starting at position 20 */ ++#define D_20 44 /* Displacement starting at position 20 */ + { 12, 20, S390_OPERAND_DISP }, +-#define DO_20 41 /* optional Displ. starting at position 20 */ +- { 12, 20, S390_OPERAND_DISP | S390_OPERAND_OPTIONAL }, +-#define D_36 42 /* Displacement starting at position 36 */ ++#define D_36 45 /* Displacement starting at position 36 */ + { 12, 36, S390_OPERAND_DISP }, +-#define D20_20 43 /* 20 bit displacement starting at 20 */ ++#define D20_20 46 /* 20 bit displacement starting at 20 */ + { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, + + /* Length operands. */ + +-#define L4_8 44 /* 4 bit length starting at position 8 */ ++#define L4_8 47 /* 4 bit length starting at position 8 */ + { 4, 8, S390_OPERAND_LENGTH }, +-#define L4_12 45 /* 4 bit length starting at position 12 */ ++#define L4_12 48 /* 4 bit length starting at position 12 */ + { 4, 12, S390_OPERAND_LENGTH }, +-#define L8_8 46 /* 8 bit length starting at position 8 */ ++#define L8_8 49 /* 8 bit length starting at position 8 */ + { 8, 8, S390_OPERAND_LENGTH }, + + /* Signed immediate operands. */ + +-#define I8_8 47 /* 8 bit signed value starting at 8 */ ++#define I8_8 50 /* 8 bit signed value starting at 8 */ + { 8, 8, S390_OPERAND_SIGNED }, +-#define I8_32 48 /* 8 bit signed value starting at 32 */ ++#define I8_32 51 /* 8 bit signed value starting at 32 */ + { 8, 32, S390_OPERAND_SIGNED }, +-#define I12_12 49 /* 12 bit signed value starting at 12 */ ++#define I12_12 52 /* 12 bit signed value starting at 12 */ + { 12, 12, S390_OPERAND_SIGNED }, +-#define I16_16 50 /* 16 bit signed value starting at 16 */ ++#define I16_16 53 /* 16 bit signed value starting at 16 */ + { 16, 16, S390_OPERAND_SIGNED }, +-#define I16_32 51 /* 16 bit signed value starting at 32 */ ++#define I16_32 54 /* 16 bit signed value starting at 32 */ + { 16, 32, S390_OPERAND_SIGNED }, +-#define I24_24 52 /* 24 bit signed value starting at 24 */ ++#define I24_24 55 /* 24 bit signed value starting at 24 */ + { 24, 24, S390_OPERAND_SIGNED }, +-#define I32_16 53 /* 32 bit signed value starting at 16 */ ++#define I32_16 56 /* 32 bit signed value starting at 16 */ + { 32, 16, S390_OPERAND_SIGNED }, + + /* Unsigned immediate operands. */ + +-#define U4_8 54 /* 4 bit unsigned value starting at 8 */ ++#define U4_8 57 /* 4 bit unsigned value starting at 8 */ + { 4, 8, 0 }, +-#define U4_12 55 /* 4 bit unsigned value starting at 12 */ ++#define U4_12 58 /* 4 bit unsigned value starting at 12 */ + { 4, 12, 0 }, +-#define U4_16 56 /* 4 bit unsigned value starting at 16 */ ++#define U4_16 59 /* 4 bit unsigned value starting at 16 */ + { 4, 16, 0 }, +-#define U4_20 57 /* 4 bit unsigned value starting at 20 */ ++#define U4_20 60 /* 4 bit unsigned value starting at 20 */ + { 4, 20, 0 }, +-#define U4_24 58 /* 4 bit unsigned value starting at 24 */ ++#define U4_24 61 /* 4 bit unsigned value starting at 24 */ + { 4, 24, 0 }, +-#define U4_28 59 /* 4 bit unsigned value starting at 28 */ ++#define U4_OR1_24 62 /* 4 bit unsigned value starting at 24 */ ++ { 4, 24, S390_OPERAND_OR1 }, ++#define U4_OR2_24 63 /* 4 bit unsigned value starting at 24 */ ++ { 4, 24, S390_OPERAND_OR2 }, ++#define U4_OR3_24 64 /* 4 bit unsigned value starting at 24 */ ++ { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, ++#define U4_28 65 /* 4 bit unsigned value starting at 28 */ + { 4, 28, 0 }, +-#define U4_32 60 /* 4 bit unsigned value starting at 32 */ ++#define U4_OR8_28 66 ++ { 4, 28, S390_OPERAND_OR8 }, ++#define U4_32 67 /* 4 bit unsigned value starting at 32 */ + { 4, 32, 0 }, +-#define U4_36 61 /* 4 bit unsigned value starting at 36 */ ++#define U4_36 68 /* 4 bit unsigned value starting at 36 */ + { 4, 36, 0 }, +-#define U8_8 62 /* 8 bit unsigned value starting at 8 */ ++#define U8_8 69 /* 8 bit unsigned value starting at 8 */ + { 8, 8, 0 }, +-#define U8_16 63 /* 8 bit unsigned value starting at 16 */ ++#define U8_16 70 /* 8 bit unsigned value starting at 16 */ + { 8, 16, 0 }, +-#define U8_24 64 /* 8 bit unsigned value starting at 24 */ ++#define U8_24 71 /* 8 bit unsigned value starting at 24 */ + { 8, 24, 0 }, +-#define U8_32 65 /* 8 bit unsigned value starting at 32 */ ++#define U8_32 72 /* 8 bit unsigned value starting at 32 */ + { 8, 32, 0 }, +-#define U16_16 66 /* 16 bit unsigned value starting at 16 */ ++#define U12_16 73 /* 12 bit unsigned value starting at 16 */ ++ { 12, 16, 0 }, ++#define U16_16 74 /* 16 bit unsigned value starting at 16 */ + { 16, 16, 0 }, +-#define U16_32 67 /* 16 bit unsigned value starting at 32 */ ++#define U16_32 75 /* 16 bit unsigned value starting at 32 */ + { 16, 32, 0 }, +-#define U32_16 68 /* 32 bit unsigned value starting at 16 */ ++#define U32_16 76 /* 32 bit unsigned value starting at 16 */ + { 32, 16, 0 }, + + /* PC-relative address operands. */ + +-#define J12_12 69 /* PC relative offset at 12 */ ++#define J12_12 77 /* 12 bit PC relative offset at 12 */ + { 12, 12, S390_OPERAND_PCREL }, +-#define J16_16 70 /* PC relative offset at 16 */ ++#define J16_16 78 /* 16 bit PC relative offset at 16 */ + { 16, 16, S390_OPERAND_PCREL }, +-#define J16_32 71 /* PC relative offset at 16 */ ++#define J16_32 79 /* 24 bit PC relative offset at 24 */ + { 16, 32, S390_OPERAND_PCREL }, +-#define J32_16 72 /* PC relative offset at 16 */ ++#define J24_24 80 /* 24 bit PC relative offset at 24 */ ++ { 24, 24, S390_OPERAND_PCREL }, ++#define J32_16 81 /* 32 bit PC relative offset at 16 */ + { 32, 16, S390_OPERAND_PCREL }, + +-/* Conditional mask operands. */ +- +-#define M_16OPT 73 /* 4 bit optional mask starting at 16 */ +- { 4, 16, S390_OPERAND_OPTIONAL }, +-#define M_20OPT 74 /* 4 bit optional mask starting at 20 */ +- { 4, 20, S390_OPERAND_OPTIONAL }, +- + }; + + +@@ -242,7 +258,7 @@ const struct s390_operand s390_operands[ + #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } + #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } + #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ +- (x >> 16) & 255, (x >> 8) & 255, x & 255} ++ (x >> 16) & 255, (x >> 8) & 255, x & 255} + + /* The new format of the INSTR_x_y and MASK_x_y defines is based + on the following rules: +@@ -261,7 +277,6 @@ const struct s390_operand s390_operands[ + l - length, 4 or 8 bit + p - pc relative + r - general purpose register +- ro - optional register operand + re - gpr extended operand, a valid general purpose register pair + u - unsigned integer, 4, 8, 16 or 32 bit + m - mode field, 4 bit +@@ -272,7 +287,7 @@ const struct s390_operand s390_operands[ + quite close. + + For example the instruction "mvo" is defined in the PoP as follows: +- ++ + MVO D1(L1,B1),D2(L2,B2) [SS] + + -------------------------------------- +@@ -282,358 +297,447 @@ const struct s390_operand s390_operands[ + + The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ + +-#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ +-#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ +-#define INSTR_MII_UPI 6, { U4_8,J12_12,I24_24 } /* e.g. bprp */ +-#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ +-#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ +-#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ +-#define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ +-#define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ +-#define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ +-#define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ +-#define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ +-#define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ +-#define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ +-#define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ +-#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ +-#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ +-#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ +-#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ +-#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ +-#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ +-#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ +-#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ +-#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ +-#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ +-#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ +-#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ +-#define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ +-#define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ +-#define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ +-#define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ +-#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ +-#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ +-#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ +-#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ +-#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ +-#define INSTR_RRE_FE0 4, { FE_24,0,0,0,0,0 } /* e.g. lzxr */ +-#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ +-#define INSTR_RRE_FEF 4, { FE_24,F_28,0,0,0,0 } /* e.g. lxdbr */ +-#define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */ +-#define INSTR_RRE_FEFE 4, { FE_24,FE_28,0,0,0,0 } /* e.g. dxr */ +-#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ +-#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ +-#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ +-#define INSTR_RRE_RFE 4, { R_24,FE_28,0,0,0,0 } /* e.g. csxtr */ +-#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ +-#define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */ +-#define INSTR_RRE_RERE 4, { RE_24,RE_28,0,0,0,0 } /* e.g. cuse */ +-#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ +-#define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */ +-/* Actually efpc and sfpc do not take an optional operand. +- This is just a workaround for existing code e.g. glibc. */ +-#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ +-#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ +-#define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */ +-#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ +-#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ +-#define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr */ +-#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ +-#define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ +-#define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ +-#define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ +-#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ +-#define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ +-#define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ +-#define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ +-#define INSTR_RRF_RMRR 4, { R_24,R_16,R_28,M_20OPT,0,0 } /* e.g. crdte */ +-#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ +-#define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ +-#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ +-#define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */ +-#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ +-#define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ +-#define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ +-#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ +-#define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ +-#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ +-#define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ +-#define INSTR_RRF_M0RR 4, { R_24,R_28,M_16OPT,0,0,0 } /* e.g. sske */ +-#define INSTR_RRF_M0RER 4, { RE_24,R_28,M_16OPT,0,0,0 } /* e.g. trte */ +-#define INSTR_RRF_M0RERE 4, { RE_24,RE_28,M_16OPT,0,0,0 } /* e.g. troo */ +-#define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */ +-#define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ +-#define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ +-#define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ +-#define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ +-#define INSTR_RRF_UURFE 4, { R_24,U4_16,FE_28,U4_20,0,0 } /* e.g. cfxbra */ +-#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ +-#define INSTR_RR_0R_OPT 2, { RO_12, 0,0,0,0,0 } /* e.g. nopr */ +-#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ +-#define INSTR_RR_FEF 2, { FE_8,F_12,0,0,0,0 } /* e.g. mxdr */ +-#define INSTR_RR_FFE 2, { F_8,FE_12,0,0,0,0 } /* e.g. ldxr */ +-#define INSTR_RR_FEFE 2, { FE_8,FE_12,0,0,0,0 } /* e.g. axr */ +-#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ +-#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ +-#define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */ +-#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ +-#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ +-#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ +-#define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 } /* e.g. axtr */ +-#define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ +-#define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ +-#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ +-#define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ +-#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ +-#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ +-#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ +-#define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ +-#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ +-#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ +-#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ +-#define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ +-#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ +-#define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ +-#define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locgt */ +-#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ +-#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ +-#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ +-#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ +-#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ +-#define INSTR_RS_RE0RD 4, { RE_8,D_20,B_16,0,0,0 } /* e.g. slda */ +-#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ +-#define INSTR_RS_RERERD 4, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. cds */ +-#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ +-#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ +-#define INSTR_RXE_FERRD 6, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. lxdb */ +-#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ +-#define INSTR_RXE_RERRD 6, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. dsg */ +-#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ +-#define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 } /* e.g. my */ +-#define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 } /* e.g. slxt */ +-#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ +-#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ +-#define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ +-#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ +-#define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ +-#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ +-#define INSTR_RX_0RRD_OPT 4, { DO_20,X_12,B_16,0,0,0 } /* e.g. nop */ +-#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ +-#define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ +-#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ +-#define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ +-#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ +-#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ +-#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ +-#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ +-#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ +-#define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ +-#define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ +-#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ +-#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ +-#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ +-#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ +-#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ +-#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ +-#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ +-#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ +-#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ +-#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } +-#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ +-#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ +-#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ +- +-#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_MII_UPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +-#define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +-#define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +-#define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +-#define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +-#define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +-#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +-#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } +-#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +-#define MASK_RRE_FE0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +-#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_FEF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_FFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_FEFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +-#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_RFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_RER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_RERE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_FER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_FE0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_FE0FER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ ++#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ ++#define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */ ++#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ ++#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ ++#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. cgrjne */ ++#define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ ++#define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ ++#define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ ++#define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ ++#define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ ++#define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ ++#define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ ++#define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ ++#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ ++#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ ++#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ ++#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ ++#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ ++#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ ++#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ ++#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ ++#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ ++#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ ++#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ ++#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ ++#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ ++#define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ ++#define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ ++#define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ ++#define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ ++#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ ++#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ ++#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ ++#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ ++#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */ ++#define INSTR_RRE_FE0 4, { FE_24,0,0,0,0,0 } /* e.g. lzxr */ ++#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ ++#define INSTR_RRE_FEF 4, { FE_24,F_28,0,0,0,0 } /* e.g. lxdbr */ ++#define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */ ++#define INSTR_RRE_FEFE 4, { FE_24,FE_28,0,0,0,0 } /* e.g. dxr */ ++#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ ++#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ ++#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. lgdr */ ++#define INSTR_RRE_RFE 4, { R_24,FE_28,0,0,0,0 } /* e.g. csxtr */ ++#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ ++#define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */ ++#define INSTR_RRE_RERE 4, { RE_24,RE_28,0,0,0,0 } /* e.g. cuse */ ++#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ ++#define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */ ++#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ ++#define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */ ++#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ ++#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ ++#define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr */ ++#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ ++#define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ ++#define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ ++#define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ ++#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ ++#define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ ++#define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ ++#define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ ++#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */ ++#define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ ++#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ ++#define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */ ++#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ ++#define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ ++#define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ ++#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ ++#define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ ++#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ ++#define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ ++#define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */ ++#define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */ ++#define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. troo */ ++#define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ ++#define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ ++#define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ ++#define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ ++#define INSTR_RRF_UURFE 4, { R_24,U4_16,FE_28,U4_20,0,0 } /* e.g. cfxbra */ ++#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ ++#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ ++#define INSTR_RR_FEF 2, { FE_8,F_12,0,0,0,0 } /* e.g. mxdr */ ++#define INSTR_RR_FFE 2, { F_8,FE_12,0,0,0,0 } /* e.g. ldxr */ ++#define INSTR_RR_FEFE 2, { FE_8,FE_12,0,0,0,0 } /* e.g. axr */ ++#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ ++#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ ++#define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */ ++#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ ++#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ ++#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ ++#define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 } /* e.g. axtr */ ++#define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ ++#define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ ++#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ ++#define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ ++#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ ++#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ ++#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ ++#define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ ++#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ ++#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ ++#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ ++#define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ ++#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ ++#define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ ++#define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locne */ ++#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ ++#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ ++#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ ++#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ ++#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ ++#define INSTR_RS_RE0RD 4, { RE_8,D_20,B_16,0,0,0 } /* e.g. slda */ ++#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ ++#define INSTR_RS_RERERD 4, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. cds */ ++#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ ++#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. adb */ ++#define INSTR_RXE_FERRD 6, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. lxdb */ ++#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ ++#define INSTR_RXE_RRRDU 6, { R_8,D_20,X_12,B_16,U4_32,0 } /* e.g. lcbb */ ++#define INSTR_RXE_RERRD 6, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. dsg */ ++#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ ++#define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 } /* e.g. my */ ++#define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 } /* e.g. slxt */ ++#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ ++#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ ++#define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ ++#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ ++#define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ ++#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ ++#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ ++#define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ ++#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ ++#define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ ++#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ ++#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ ++#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ ++#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ ++#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ ++#define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ ++#define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ ++#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvcdk */ ++#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ ++#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ ++#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ ++#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ ++#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ ++#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ ++#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ ++#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ ++#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ ++#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ ++#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ ++#define INSTR_VRV_VVXRDU 6, { V_8,D_20,VX_12,B_16,U4_32,0 } /* e.g. vgef */ ++#define INSTR_VRI_V0U 6, { V_8,U16_16,0,0,0,0 } /* e.g. vgbm */ ++#define INSTR_VRI_V 6, { V_8,0,0,0,0,0 } /* e.g. vzero */ ++#define INSTR_VRI_V0UUU 6, { V_8,U8_16,U8_24,U4_32,0,0 } /* e.g. vgm */ ++#define INSTR_VRI_V0UU 6, { V_8,U8_16,U8_24,0,0,0 } /* e.g. vgmb */ ++#define INSTR_VRI_VVUU 6, { V_8,V_12,U16_16,U4_32,0,0 } /* e.g. vrep */ ++#define INSTR_VRI_VVU 6, { V_8,V_12,U16_16,0,0,0 } /* e.g. vrepb */ ++#define INSTR_VRI_VVU2 6, { V_8,V_12,U12_16,0,0,0 } /* e.g. vftcidb */ ++#define INSTR_VRI_V0IU 6, { V_8,I16_16,U4_32,0,0,0 } /* e.g. vrepi */ ++#define INSTR_VRI_V0I 6, { V_8,I16_16,0,0,0,0 } /* e.g. vrepib */ ++#define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ ++#define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ ++#define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ ++#define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ ++#define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ ++#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrp */ ++#define INSTR_VRS_RVRDU 6, { R_8,V_12,D_20,B_16,U4_32,0 } /* e.g. vlgv */ ++#define INSTR_VRS_RVRD 6, { R_8,V_12,D_20,B_16,0,0 } /* e.g. vlgvb */ ++#define INSTR_VRS_VVRDU 6, { V_8,V_12,D_20,B_16,U4_32,0 } /* e.g. verll */ ++#define INSTR_VRS_VVRD 6, { V_8,V_12,D_20,B_16,0,0 } /* e.g. vlm */ ++#define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ ++#define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ ++#define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ ++#define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ ++#define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ ++#define INSTR_VRR_VVV0U1 6, { V_8,V_12,V_16,U4_OR1_24,0,0 } /* e.g. vfaebs*/ ++#define INSTR_VRR_VVV0U2 6, { V_8,V_12,V_16,U4_OR2_24,0,0 } /* e.g. vfaezb*/ ++#define INSTR_VRR_VVV0U3 6, { V_8,V_12,V_16,U4_OR3_24,0,0 } /* e.g. vfaezbs*/ ++#define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */ ++#define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */ ++#define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ ++#define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ ++#define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ ++#define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ ++#define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */ ++#define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ ++#define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ ++#define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */ ++#define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/ ++#define INSTR_VRR_VVVU0VB1 6, { V_8,V_12,V_16,V_32,U4_OR1_24,0 } /* e.g. vstrcbs*/ ++#define INSTR_VRR_VVVU0VB2 6, { V_8,V_12,V_16,V_32,U4_OR2_24,0 } /* e.g. vstrczb*/ ++#define INSTR_VRR_VVVU0VB3 6, { V_8,V_12,V_16,V_32,U4_OR3_24,0 } /* e.g. vstrczbs*/ ++#define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */ ++#define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */ ++#define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/ ++#define INSTR_VRR_VVV0UUU 6, { V_8,V_12,V_16,U4_32,U4_28,U4_24 }/* e.g. vfch */ ++#define INSTR_VRR_VVV0UU 6, { V_8,V_12,V_16,U4_32,U4_28,0 } /* e.g. vfa */ ++#define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ ++#define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ ++#define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ ++ ++#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } ++#define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } ++#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } ++#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } ++#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } ++#define MASK_RRE_FE0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } ++#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_FEF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_FFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_FEFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } ++#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_RFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_RER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_RERE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRE_FER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_FE0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_FE0FER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + #define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_RMRR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_U0RFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_UUFFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_UUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +-#define MASK_RRF_0UFEF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +-#define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_FEFERU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_M0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_M0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +-#define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRF_UURFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_0R_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_FEF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_FFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_FEFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_RER { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +-#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +-#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RSE_RERERD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RS_RE0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RS_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RXE_RERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +-#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +-#define MASK_RXF_FRRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +-#define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +-#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +-#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RX_0RRD_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +-#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +-#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +-#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +- ++#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_U0RFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_UUFFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_UUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } ++#define MASK_RRF_0UFEF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } ++#define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_FEFERU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_U0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_U0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } ++#define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRF_UURFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_FEF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_FFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_FEFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_RER { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } ++#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } ++#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RSE_RERERD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RS_RE0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RS_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RXE_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } ++#define MASK_RXE_RERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } ++#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } ++#define MASK_RXF_FRRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } ++#define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } ++#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } ++#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } ++#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } ++#define MASK_VRV_VVXRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRI_V0U { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRI_V { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff } ++#define MASK_VRI_V0UUU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRI_V0UU { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRI_VVUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRI_VVU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRI_VVU2 { 0xff, 0x00, 0x00, 0x0f, 0xf0, 0xff } ++#define MASK_VRI_V0IU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRI_V0I { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRI_VVV0UU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } ++#define MASK_VRI_VVV0U { 0xff, 0x00, 0x0f, 0x00, 0xf0, 0xff } ++#define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } ++#define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRS_RVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRS_RVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRS_VVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRS_VVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } ++#define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } ++#define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } ++#define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } ++#define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } ++#define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff } ++#define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff } ++#define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff } ++#define MASK_VRR_VVV { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } ++#define MASK_VRR_VVV2 { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } ++#define MASK_VRR_VVV0V { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } ++#define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff } ++#define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } ++#define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } ++#define MASK_VRR_VV0UU2 { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff } ++#define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff } ++#define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } ++#define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff } ++#define MASK_VRR_VVVU0V { 0xff, 0x00, 0x00, 0xff, 0x00, 0xff } ++#define MASK_VRR_VVVU0VB { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } ++#define MASK_VRR_VVVU0VB1 { 0xff, 0x00, 0x0f, 0x1f, 0x00, 0xff } ++#define MASK_VRR_VVVU0VB2 { 0xff, 0x00, 0x0f, 0x2f, 0x00, 0xff } ++#define MASK_VRR_VVVU0VB3 { 0xff, 0x00, 0x0f, 0x3f, 0x00, 0xff } ++#define MASK_VRR_VVV0U0U { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } ++#define MASK_VRR_VVVV { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } ++#define MASK_VRR_VVV0UUU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } ++#define MASK_VRR_VVV0UU { 0xff, 0x00, 0x0f, 0xf0, 0x00, 0xff } ++#define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } ++#define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } ++#define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } + + /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ + + const struct s390_opcode s390_opformats[] = + { +- { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, +- { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, +- { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, +- { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, +- { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, +- { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 }, +- { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, +- { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, +- { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, +- { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 }, +- { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, +- { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, +- { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, +- { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, +- { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, +- { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, +- { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, +- { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, +- { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, +- { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, +- { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, +- { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 }, +- { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, +- { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, +- { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, ++ { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 }, ++ { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 }, ++ { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 }, ++ { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 }, ++ { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 }, ++ { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 ,0 }, ++ { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 }, ++ { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 }, ++ { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 }, ++ { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 ,0 }, ++ { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 }, ++ { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 }, ++ { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 }, ++ { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 }, ++ { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 }, ++ { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 }, ++ { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 ,0 }, ++ { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 }, ++ { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 }, ++ { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 }, ++ { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 }, ++ { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 }, ++ { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 ,0 }, ++ { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 }, ++ { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 ,0 }, + }; + + const int s390_num_opformats = +diff -Nrup a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt +--- a/opcodes/s390-opc.txt 2013-02-27 13:28:03.000000000 -0700 ++++ b/opcodes/s390-opc.txt 2015-05-04 15:15:39.250627782 -0600 +@@ -263,10 +263,10 @@ a700 tmlh RI_RU "test under mask low hig + a700 tmh RI_RU "test under mask high" g5 esa,zarch + a701 tmll RI_RU "test under mask low low" g5 esa,zarch + a701 tml RI_RU "test under mask low" g5 esa,zarch +-0700 nopr RR_0R_OPT "no operation" g5 esa,zarch ++0700 nopr RR_0R "no operation" g5 esa,zarch optparm + 0700 b*8r RR_0R "conditional branch" g5 esa,zarch + 07f0 br RR_0R "unconditional branch" g5 esa,zarch +-4700 nop RX_0RRD_OPT "no operation" g5 esa,zarch ++4700 nop RX_0RRD "no operation" g5 esa,zarch optparm + 4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch + 47f0 b RX_0RRD "unconditional branch" g5 esa,zarch + a704 j*8 RI_0P "conditional jump" g5 esa,zarch +@@ -299,7 +299,7 @@ b30d debr RRE_FF "divide short bfp" g5 e + ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch + b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch + b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch +-b38c efpc RRE_RR_OPT "extract fpc" g5 esa,zarch ++b38c efpc RRE_RR "extract fpc" g5 esa,zarch optparm + b342 ltxbr RRE_FEFE "load and test extended bfp" g5 esa,zarch + b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch + b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch +@@ -342,7 +342,7 @@ b31f msdbr RRF_F0FF "multiply and subtra + ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch + b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch + ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch +-b384 sfpc RRE_RR_OPT "set fpc" g5 esa,zarch ++b384 sfpc RRE_RR "set fpc" g5 esa,zarch optparm + b299 srnm S_RD "set rounding mode" g5 esa,zarch + b316 sqxbr RRE_FEFE "square root extended bfp" g5 esa,zarch + b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch +@@ -766,21 +766,21 @@ c800 mvcos SSF_RRDRD "move with optional + # z9-109 load page-table-entry address instruction + b9aa lptea RRF_RURR2 "load page-table-entry address" z9-109 zarch + # z9-109 conditional sske facility, sske instruction entered twice +-b22b sske RRF_M0RR "set storage key extended" z9-109 zarch ++b22b sske RRF_U0RR "set storage key extended" z9-109 zarch optparm + # z9-109 etf2-enhancement facility, instructions entered twice +-b993 troo RRF_M0RERE "translate one to one" z9-109 esa,zarch +-b992 trot RRF_M0RERE "translate one to two" z9-109 esa,zarch +-b991 trto RRF_M0RERE "translate two to one" z9-109 esa,zarch +-b990 trtt RRF_M0RERE "translate two to two" z9-109 esa,zarch ++b993 troo RRF_U0RERE "translate one to one" z9-109 esa,zarch optparm ++b992 trot RRF_U0RERE "translate one to two" z9-109 esa,zarch optparm ++b991 trto RRF_U0RERE "translate two to one" z9-109 esa,zarch optparm ++b990 trtt RRF_U0RERE "translate two to two" z9-109 esa,zarch optparm + # z9-109 etf3-enhancement facility, some instructions entered twice +-b9b1 cu24 RRF_M0RERE "convert utf-16 to utf-32" z9-109 zarch +-b2a6 cu21 RRF_M0RERE "convert utf-16 to utf-8" z9-109 zarch +-b2a6 cuutf RRF_M0RERE "convert unicode to utf-8" z9-109 zarch ++b9b1 cu24 RRF_U0RERE "convert utf-16 to utf-32" z9-109 zarch optparm ++b2a6 cu21 RRF_U0RERE "convert utf-16 to utf-8" z9-109 zarch optparm ++b2a6 cuutf RRF_U0RERE "convert unicode to utf-8" z9-109 zarch optparm + b9b3 cu42 RRE_RERE "convert utf-32 to utf-16" z9-109 zarch + b9b2 cu41 RRE_RERE "convert utf-32 to utf-8" z9-109 zarch +-b2a7 cu12 RRF_M0RERE "convert utf-8 to utf-16" z9-109 zarch +-b2a7 cutfu RRF_M0RERE "convert utf-8 to unicode" z9-109 zarch +-b9b0 cu14 RRF_M0RERE "convert utf-8 to utf-32" z9-109 zarch ++b2a7 cu12 RRF_U0RERE "convert utf-8 to utf-16" z9-109 zarch optparm ++b2a7 cutfu RRF_U0RERE "convert utf-8 to unicode" z9-109 zarch optparm ++b9b0 cu14 RRF_U0RERE "convert utf-8 to utf-32" z9-109 zarch optparm + b9be srstu RRE_RR "search string unicode" z9-109 zarch + d0 trtr SS_L0RDRD "tranlate and test reverse" z9-109 zarch + # z9-109 unnormalized hfp multiply & multiply and add +@@ -964,8 +964,8 @@ c600 exrl RIL_RP "execute relative long" + af00 mc SI_URD "monitor call" z10 zarch + b9a2 ptf RRE_R0 "perform topology function" z10 zarch + b9af pfmf RRE_RR "perform frame management function" z10 zarch +-b9bf trte RRF_M0RER "translate and test extended" z10 zarch +-b9bd trtre RRF_M0RER "translate and test reverse extended" z10 zarch ++b9bf trte RRF_U0RER "translate and test extended" z10 zarch optparm ++b9bd trtre RRF_U0RER "translate and test reverse extended" z10 zarch optparm + b2ed ecpga RRE_RR "extract coprocessor-group address" z10 zarch + b2e4 ecctr RRE_RR "extract cpu counter" z10 zarch + b2e5 epctr RRE_RR "extract peripheral counter" z10 zarch +@@ -995,7 +995,7 @@ cc0d cih RIL_RI "compare immediate high" + b9cf clhhr RRE_RR "compare logical high high" z196 zarch + b9df clhlr RRE_RR "compare logical high low" z196 zarch + e300000000cf clhf RXY_RRRD "compare logical high" z196 zarch +-cc0f clih RIL_RI "compare logical immediate" z196 zarch ++cc0f clih RIL_RU "compare logical immediate" z196 zarch + e300000000c0 lbh RXY_RRRD "load byte high" z196 zarch + e300000000c4 lhh RXY_RRRD "load halfword high" z196 zarch + e300000000ca lfh RXY_RRRD "load high" z196 zarch +@@ -1082,9 +1082,9 @@ b39e clfxbr RRF_UURFE "convert to 32 bit + b3ac clgebr RRF_UURF "convert to 64 bit fixed logical from short bfp with rounding mode" z196 zarch + b3ad clgdbr RRF_UURF "convert to 64 bit fixed logical from long bfp with rounding mode" z196 zarch + b3ae clgxbr RRF_UURFE "convert to 64 bit fixed logical from extended bfp with rounding mode" z196 zarch +-b357 fiebra RRF_UUFF "load fp integer short bfp with rounding mode" z196 zarch +-b35f fidbra RRF_UUFF "load fp integer long bfp with rounding mode" z196 zarch +-b347 fixbra RRF_UUFEFE "load fp integer extended bfp with rounding mode" z196 zarch ++b357 fiebra RRF_UUFF "load fp integer short bfp with inexact suppression" z196 zarch ++b35f fidbra RRF_UUFF "load fp integer long bfp with inexact suppression" z196 zarch ++b347 fixbra RRF_UUFEFE "load fp integer extended bfp with inexact suppression" z196 zarch + b344 ledbra RRF_UUFF "load rounded short/long bfp to short/long bfp with rounding mode" z196 zarch + b345 ldxbra RRF_UUFEFE "load rounded long/extended bfp to long/extended bfp with rounding mode" z196 zarch + b346 lexbra RRF_UUFEFE "load rounded short/extended bfp to short/extended bfp with rounding mode" z196 zarch +@@ -1126,10 +1126,10 @@ e560 tbegin SIL_RDU "transaction begin" + e561 tbeginc SIL_RDU "constrained transaction begin" zEC12 zarch + b2f8 tend S_00 "transaction end" zEC12 zarch + c7 bpp SMI_U0RDP "branch prediction preload" zEC12 zarch +-c5 bprp MII_UPI "branch prediction relative preload" zEC12 zarch ++c5 bprp MII_UPP "branch prediction relative preload" zEC12 zarch + b2e8 ppa RRF_U0RR "perform processor assist" zEC12 zarch + b2fa niai IE_UU "next instruction access intent" zEC12 zarch +-b98f crdte RRF_RMRR "compare and replace DAT table entry" zEC12 zarch ++b98f crdte RRF_RURR2 "compare and replace DAT table entry" zEC12 zarch optparm + e3000000009f lat RXY_RRRD "load and trap 32 bit" zEC12 zarch + e30000000085 lgat RXY_RRRD "load and trap 64 bit" zEC12 zarch + e300000000c8 lfhat RXY_RRRD "load high and trap" zEC12 zarch +@@ -1144,3 +1144,539 @@ ed00000000aa cdzt RSL_LRDFU "convert fro + ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch + ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch + ed00000000a9 czxt RSL_LRDFEU "convert to zoned extended" zEC12 zarch ++ ++# The new instructions of IBM z13 ++ ++e70000000027 lcbb RXE_RRRDU "load count to block boundary" z13 zarch ++ ++# Chapter 21 ++e70000000013 vgef VRV_VVXRDU "vector gather element 4 byte elements" z13 zarch ++e70000000012 vgeg VRV_VVXRDU "vector gather element 8 byte elements" z13 zarch ++e70000000044 vgbm VRI_V0U "vector generate byte mask" z13 zarch ++e70000000044 vzero VRI_V "vector set to zero" z13 zarch ++e700ffff0044 vone VRI_V "vector set to ones" z13 zarch ++e70000000046 vgm VRI_V0UUU "vector generate mask" z13 zarch ++e70000000046 vgmb VRI_V0UU "vector generate mask byte" z13 zarch ++e70000001046 vgmh VRI_V0UU "vector generate mask halfword" z13 zarch ++e70000002046 vgmf VRI_V0UU "vector generate mask word" z13 zarch ++e70000003046 vgmg VRI_V0UU "vector generate mask double word" z13 zarch ++e70000000006 vl VRX_VRRD "vector memory load" z13 zarch ++e70000000056 vlr VRX_VV "vector register load" z13 zarch ++e70000000005 vlrep VRX_VRRDU "vector load and replicate" z13 zarch ++e70000000005 vlrepb VRX_VRRD "vector load and replicate byte elements" z13 zarch ++e70000001005 vlreph VRX_VRRD "vector load and replicate halfword elements" z13 zarch ++e70000002005 vlrepf VRX_VRRD "vector load and replicate word elements" z13 zarch ++e70000003005 vlrepg VRX_VRRD "vector load and replicate double word elements" z13 zarch ++e70000000000 vleb VRX_VRRDU "vector load byte element" z13 zarch ++e70000000001 vleh VRX_VRRDU "vector load halfword element" z13 zarch ++e70000000003 vlef VRX_VRRDU "vector load word element" z13 zarch ++e70000000002 vleg VRX_VRRDU "vector load double word element" z13 zarch ++e70000000040 vleib VRI_V0IU "vector load byte element immediate" z13 zarch ++e70000000041 vleih VRI_V0IU "vector load halfword element immediate" z13 zarch ++e70000000043 vleif VRI_V0IU "vector load word element immediate" z13 zarch ++e70000000042 vleig VRI_V0IU "vector load double word element immediate" z13 zarch ++e70000000021 vlgv VRS_RVRDU "vector load gr from vr element" z13 zarch ++e70000000021 vlgvb VRS_RVRD "vector load gr from vr byte element" z13 zarch ++e70000001021 vlgvh VRS_RVRD "vector load gr from vr halfword element" z13 zarch ++e70000002021 vlgvf VRS_RVRD "vector load gr from vr word element" z13 zarch ++e70000003021 vlgvg VRS_RVRD "vector load gr from vr double word element" z13 zarch ++e70000000004 vllez VRX_VRRDU "vector load logical element and zero" z13 zarch ++e70000000004 vllezb VRX_VRRD "vector load logical byte element and zero" z13 zarch ++e70000001004 vllezh VRX_VRRD "vector load logical halfword element and zero" z13 zarch ++e70000002004 vllezf VRX_VRRD "vector load logical word element and zero" z13 zarch ++e70000003004 vllezg VRX_VRRD "vector load logical double word element and zero" z13 zarch ++e70000000036 vlm VRS_VVRD "vector load multiple" z13 zarch ++e70000000007 vlbb VRX_VRRDU "vector load to block boundary" z13 zarch ++e70000000022 vlvg VRS_VRRDU "vector load VR element from GR" z13 zarch ++e70000000022 vlvgb VRS_VRRD "vector load VR byte element from GR" z13 zarch ++e70000001022 vlvgh VRS_VRRD "vector load VR halfword element from GR" z13 zarch ++e70000002022 vlvgf VRS_VRRD "vector load VR word element from GR" z13 zarch ++e70000003022 vlvgg VRS_VRRD "vector load VR double word element from GR" z13 zarch ++e70000000062 vlvgp VRR_VRR "vector load VR from GRs disjoint" z13 zarch ++e70000000037 vll VRS_VRRD "vector load with length" z13 zarch ++e70000000061 vmrh VRR_VVV0U "vector merge high" z13 zarch ++e70000000061 vmrhb VRR_VVV "vector merge high byte" z13 zarch ++e70000001061 vmrhh VRR_VVV "vector merge high halfword" z13 zarch ++e70000002061 vmrhf VRR_VVV "vector merge high word" z13 zarch ++e70000003061 vmrhg VRR_VVV "vector merge high double word" z13 zarch ++e70000000060 vmrl VRR_VVV0U "vector merge low" z13 zarch ++e70000000060 vmrlb VRR_VVV "vector merge low byte" z13 zarch ++e70000001060 vmrlh VRR_VVV "vector merge low halfword" z13 zarch ++e70000002060 vmrlf VRR_VVV "vector merge low word" z13 zarch ++e70000003060 vmrlg VRR_VVV "vector merge low double word" z13 zarch ++e70000000094 vpk VRR_VVV0U "vector pack" z13 zarch ++e70000001094 vpkh VRR_VVV "vector pack halfword" z13 zarch ++e70000002094 vpkf VRR_VVV "vector pack word" z13 zarch ++e70000003094 vpkg VRR_VVV "vector pack double word" z13 zarch ++e70000000097 vpks VRR_VVV0U0U "vector pack saturate" z13 zarch ++e70000001097 vpksh VRR_VVV "vector pack saturate halfword" z13 zarch ++e70000002097 vpksf VRR_VVV "vector pack saturate word" z13 zarch ++e70000003097 vpksg VRR_VVV "vector pack saturate double word" z13 zarch ++e70000101097 vpkshs VRR_VVV "vector pack saturate halfword" z13 zarch ++e70000102097 vpksfs VRR_VVV "vector pack saturate word" z13 zarch ++e70000103097 vpksgs VRR_VVV "vector pack saturate double word" z13 zarch ++e70000000095 vpkls VRR_VVV0U0U "vector pack logical saturate" z13 zarch ++e70000001095 vpklsh VRR_VVV "vector pack logical saturate halfword" z13 zarch ++e70000002095 vpklsf VRR_VVV "vector pack logical saturate word" z13 zarch ++e70000003095 vpklsg VRR_VVV "vector pack logical saturate double word" z13 zarch ++e70000101095 vpklshs VRR_VVV "vector pack logical saturate halfword" z13 zarch ++e70000102095 vpklsfs VRR_VVV "vector pack logical saturate word" z13 zarch ++e70000103095 vpklsgs VRR_VVV "vector pack logical saturate double word" z13 zarch ++e7000000008c vperm VRR_VVV0V "vector permute" z13 zarch ++e70000000084 vpdi VRR_VVV0U "vector permute double word immediate" z13 zarch ++e7000000004d vrep VRI_VVUU "vector replicate" z13 zarch ++e7000000004d vrepb VRI_VVU "vector replicate byte" z13 zarch ++e7000000104d vreph VRI_VVU "vector replicate halfword" z13 zarch ++e7000000204d vrepf VRI_VVU "vector replicate word" z13 zarch ++e7000000304d vrepg VRI_VVU "vector replicate double word" z13 zarch ++e70000000045 vrepi VRI_V0IU "vector replicate immediate" z13 zarch ++e70000000045 vrepib VRI_V0I "vector replicate immediate byte" z13 zarch ++e70000001045 vrepih VRI_V0I "vector replicate immediate halfword" z13 zarch ++e70000002045 vrepif VRI_V0I "vector replicate immediate word" z13 zarch ++e70000003045 vrepig VRI_V0I "vector replicate immediate double word" z13 zarch ++e7000000001b vscef VRV_VVXRDU "vector scatter element 4 byte" z13 zarch ++e7000000001a vsceg VRV_VVXRDU "vector scatter element 8 byte" z13 zarch ++e7000000008d vsel VRR_VVV0V "vector select" z13 zarch ++e7000000005f vseg VRR_VV0U "vector sign extend to double word" z13 zarch ++e7000000005f vsegb VRR_VV "vector sign extend byte to double word" z13 zarch ++e7000000105f vsegh VRR_VV "vector sign extend halfword to double word" z13 zarch ++e7000000205f vsegf VRR_VV "vector sign extend word to double word" z13 zarch ++e7000000000e vst VRX_VRRD "vector store" z13 zarch ++e70000000008 vsteb VRX_VRRDU "vector store byte element" z13 zarch ++e70000000009 vsteh VRX_VRRDU "vector store halfword element" z13 zarch ++e7000000000b vstef VRX_VRRDU "vector store word element" z13 zarch ++e7000000000a vsteg VRX_VRRDU "vector store double word element" z13 zarch ++e7000000003e vstm VRS_VVRD "vector store multiple" z13 zarch ++e7000000003f vstl VRS_VRRD "vector store with length" z13 zarch ++e700000000d7 vuph VRR_VV0U "vector unpack high" z13 zarch ++e700000000d7 vuphb VRR_VV "vector unpack high byte" z13 zarch ++e700000010d7 vuphh VRR_VV "vector unpack high halfword" z13 zarch ++e700000020d7 vuphf VRR_VV "vector unpack high word" z13 zarch ++e700000000d5 vuplh VRR_VV0U "vector unpack logical high" z13 zarch ++e700000000d5 vuplhb VRR_VV "vector unpack logical high byte" z13 zarch ++e700000010d5 vuplhh VRR_VV "vector unpack logical high halfword" z13 zarch ++e700000020d5 vuplhf VRR_VV "vector unpack logical high word" z13 zarch ++e700000000d6 vupl VRR_VV0U "vector unpack low" z13 zarch ++e700000000d6 vuplb VRR_VV "vector unpack low byte" z13 zarch ++e700000010d6 vuplhw VRR_VV "vector unpack low halfword" z13 zarch ++e700000020d6 vuplf VRR_VV "vector unpack low word" z13 zarch ++e700000000d4 vupll VRR_VV0U "vector unpack logical low" z13 zarch ++e700000000d4 vupllb VRR_VV "vector unpack logical low byte" z13 zarch ++e700000010d4 vupllh VRR_VV "vector unpack logical low halfword" z13 zarch ++e700000020d4 vupllf VRR_VV "vector unpack logical low word" z13 zarch ++ ++# Chapter 22 ++e700000000f3 va VRR_VVV0U "vector add" z13 zarch ++e700000000f3 vab VRR_VVV "vector add byte" z13 zarch ++e700000010f3 vah VRR_VVV "vector add halfword" z13 zarch ++e700000020f3 vaf VRR_VVV "vector add word" z13 zarch ++e700000030f3 vag VRR_VVV "vector add double word" z13 zarch ++e700000040f3 vaq VRR_VVV "vector add quad word" z13 zarch ++e700000000f1 vacc VRR_VVV0U "vector add compute carry" z13 zarch ++e700000000f1 vaccb VRR_VVV "vector add compute carry byte" z13 zarch ++e700000010f1 vacch VRR_VVV "vector add compute carry halfword" z13 zarch ++e700000020f1 vaccf VRR_VVV "vector add compute carry word" z13 zarch ++e700000030f1 vaccg VRR_VVV "vector add compute carry doubleword" z13 zarch ++e700000040f1 vaccq VRR_VVV "vector add compute carry quadword" z13 zarch ++e700000000bb vac VRR_VVVU0V "vector add with carry" z13 zarch ++e700040000bb vacq VRR_VVV0V "vector add with carry quadword" z13 zarch ++e700000000b9 vaccc VRR_VVVU0V "vector add with carry compute carry" z13 zarch ++e700040000b9 vacccq VRR_VVV0V "vector add with carry compute carry quadword" z13 zarch ++e70000000068 vn VRR_VVV "vector and" z13 zarch ++e70000000069 vnc VRR_VVV "vector and with complement" z13 zarch ++e700000000f2 vavg VRR_VVV0U "vector average" z13 zarch ++e700000000f2 vavgb VRR_VVV "vector average byte" z13 zarch ++e700000010f2 vavgh VRR_VVV "vector average half word" z13 zarch ++e700000020f2 vavgf VRR_VVV "vector average word" z13 zarch ++e700000030f2 vavgg VRR_VVV "vector average double word" z13 zarch ++e700000000f0 vavgl VRR_VVV0U "vector average logical" z13 zarch ++e700000000f0 vavglb VRR_VVV "vector average logical byte" z13 zarch ++e700000010f0 vavglh VRR_VVV "vector average logical half word" z13 zarch ++e700000020f0 vavglf VRR_VVV "vector average logical word" z13 zarch ++e700000030f0 vavglg VRR_VVV "vector average logical double word" z13 zarch ++e70000000066 vcksm VRR_VVV "vector checksum" z13 zarch ++e700000000db vec VRR_VV0U "vector element compare" z13 zarch ++e700000000db vecb VRR_VV "vector element compare byte" z13 zarch ++e700000010db vech VRR_VV "vector element compare half word" z13 zarch ++e700000020db vecf VRR_VV "vector element compare word" z13 zarch ++e700000030db vecg VRR_VV "vector element compare double word" z13 zarch ++e700000000d9 vecl VRR_VV0U "vector element compare logical" z13 zarch ++e700000000d9 veclb VRR_VV "vector element compare logical byte" z13 zarch ++e700000010d9 veclh VRR_VV "vector element compare logical half word" z13 zarch ++e700000020d9 veclf VRR_VV "vector element compare logical word" z13 zarch ++e700000030d9 veclg VRR_VV "vector element compare logical double word" z13 zarch ++e700000000f8 vceq VRR_VVV0U0U "vector compare equal" z13 zarch ++e700000000f8 vceqb VRR_VVV "vector compare equal byte" z13 zarch ++e700000010f8 vceqh VRR_VVV "vector compare equal half word" z13 zarch ++e700000020f8 vceqf VRR_VVV "vector compare equal word" z13 zarch ++e700000030f8 vceqg VRR_VVV "vector compare equal double word" z13 zarch ++e700001000f8 vceqbs VRR_VVV "vector compare equal byte" z13 zarch ++e700001010f8 vceqhs VRR_VVV "vector compare equal half word" z13 zarch ++e700001020f8 vceqfs VRR_VVV "vector compare equal word" z13 zarch ++e700001030f8 vceqgs VRR_VVV "vector compare equal double word" z13 zarch ++e700000000fb vch VRR_VVV0U0U "vector compare high" z13 zarch ++e700000000fb vchb VRR_VVV "vector compare high byte" z13 zarch ++e700000010fb vchh VRR_VVV "vector compare high half word" z13 zarch ++e700000020fb vchf VRR_VVV "vector compare high word" z13 zarch ++e700000030fb vchg VRR_VVV "vector compare high double word" z13 zarch ++e700001000fb vchbs VRR_VVV "vector compare high byte" z13 zarch ++e700001010fb vchhs VRR_VVV "vector compare high half word" z13 zarch ++e700001020fb vchfs VRR_VVV "vector compare high word" z13 zarch ++e700001030fb vchgs VRR_VVV "vector compare high double word" z13 zarch ++e700000000f9 vchl VRR_VVV0U0U "vector compare high logical" z13 zarch ++e700000000f9 vchlb VRR_VVV "vector compare high logical byte" z13 zarch ++e700000010f9 vchlh VRR_VVV "vector compare high logical half word" z13 zarch ++e700000020f9 vchlf VRR_VVV "vector compare high logical word" z13 zarch ++e700000030f9 vchlg VRR_VVV "vector compare high logical double word" z13 zarch ++e700001000f9 vchlbs VRR_VVV "vector compare high logical byte" z13 zarch ++e700001010f9 vchlhs VRR_VVV "vector compare high logical half word" z13 zarch ++e700001020f9 vchlfs VRR_VVV "vector compare high logical word" z13 zarch ++e700001030f9 vchlgs VRR_VVV "vector compare high logical double word" z13 zarch ++e70000000053 vclz VRR_VV0U "vector count leading zeros" z13 zarch ++e70000000053 vclzb VRR_VV "vector count leading zeros byte" z13 zarch ++e70000001053 vclzh VRR_VV "vector count leading zeros halfword" z13 zarch ++e70000002053 vclzf VRR_VV "vector count leading zeros word" z13 zarch ++e70000003053 vclzg VRR_VV "vector count leading zeros doubleword" z13 zarch ++e70000000052 vctz VRR_VV0U "vector count trailing zeros" z13 zarch ++e70000000052 vctzb VRR_VV "vector count trailing zeros byte" z13 zarch ++e70000001052 vctzh VRR_VV "vector count trailing zeros halfword" z13 zarch ++e70000002052 vctzf VRR_VV "vector count trailing zeros word" z13 zarch ++e70000003052 vctzg VRR_VV "vector count trailing zeros doubleword" z13 zarch ++e7000000006d vx VRR_VVV "vector exclusive or" z13 zarch ++e700000000b4 vgfm VRR_VVV0U "vector galois field multiply sum" z13 zarch ++e700000000b4 vgfmb VRR_VVV "vector galois field multiply sum byte" z13 zarch ++e700000010b4 vgfmh VRR_VVV "vector galois field multiply sum halfword" z13 zarch ++e700000020b4 vgfmf VRR_VVV "vector galois field multiply sum word" z13 zarch ++e700000030b4 vgfmg VRR_VVV "vector galois field multiply sum doubleword" z13 zarch ++e700000000bc vgfma VRR_VVVU0V "vector galois field multiply sum and accumulate" z13 zarch ++e700000000bc vgfmab VRR_VVV0V "vector galois field multiply sum and accumulate byte" z13 zarch ++e700010000bc vgfmah VRR_VVV0V "vector galois field multiply sum and accumulate halfword" z13 zarch ++e700020000bc vgfmaf VRR_VVV0V "vector galois field multiply sum and accumulate word" z13 zarch ++e700030000bc vgfmag VRR_VVV0V "vector galois field multiply sum and accumulate doubleword" z13 zarch ++e700000000de vlc VRR_VV0U "vector load complement" z13 zarch ++e700000000de vlcb VRR_VV "vector load complement byte" z13 zarch ++e700000010de vlch VRR_VV "vector load complement halfword" z13 zarch ++e700000020de vlcf VRR_VV "vector load complement word" z13 zarch ++e700000030de vlcg VRR_VV "vector load complement doubleword" z13 zarch ++e700000000df vlp VRR_VV0U "vector load positive" z13 zarch ++e700000000df vlpb VRR_VV "vector load positive byte" z13 zarch ++e700000010df vlph VRR_VV "vector load positive halfword" z13 zarch ++e700000020df vlpf VRR_VV "vector load positive word" z13 zarch ++e700000030df vlpg VRR_VV "vector load positive doubleword" z13 zarch ++e700000000ff vmx VRR_VVV0U "vector maximum" z13 zarch ++e700000000ff vmxb VRR_VVV "vector maximum byte" z13 zarch ++e700000010ff vmxh VRR_VVV "vector maximum halfword" z13 zarch ++e700000020ff vmxf VRR_VVV "vector maximum word" z13 zarch ++e700000030ff vmxg VRR_VVV "vector maximum doubleword" z13 zarch ++e700000000fd vmxl VRR_VVV0U "vector maximum logical" z13 zarch ++e700000000fd vmxlb VRR_VVV "vector maximum logical byte" z13 zarch ++e700000010fd vmxlh VRR_VVV "vector maximum logical halfword" z13 zarch ++e700000020fd vmxlf VRR_VVV "vector maximum logical word" z13 zarch ++e700000030fd vmxlg VRR_VVV "vector maximum logical doubleword" z13 zarch ++e700000000fe vmn VRR_VVV0U "vector minimum" z13 zarch ++e700000000fe vmnb VRR_VVV "vector minimum byte" z13 zarch ++e700000010fe vmnh VRR_VVV "vector minimum halfword" z13 zarch ++e700000020fe vmnf VRR_VVV "vector minimum word" z13 zarch ++e700000030fe vmng VRR_VVV "vector minimum doubleword" z13 zarch ++e700000000fc vmnl VRR_VVV0U "vector minimum logical" z13 zarch ++e700000000fc vmnlb VRR_VVV "vector minimum logical byte" z13 zarch ++e700000010fc vmnlh VRR_VVV "vector minimum logical halfword" z13 zarch ++e700000020fc vmnlf VRR_VVV "vector minimum logical word" z13 zarch ++e700000030fc vmnlg VRR_VVV "vector minimum logical doubleword" z13 zarch ++e700000000aa vmal VRR_VVVU0V "vector multiply and add low" z13 zarch ++e700000000aa vmalb VRR_VVV0V "vector multiply and add low byte" z13 zarch ++e700010000aa vmalhw VRR_VVV0V "vector multiply and add low halfword" z13 zarch ++e700020000aa vmalf VRR_VVV0V "vector multiply and add low word" z13 zarch ++e700000000ab vmah VRR_VVVU0V "vector multiply and add high" z13 zarch ++e700000000ab vmahb VRR_VVV0V "vector multiply and add high byte" z13 zarch ++e700010000ab vmahh VRR_VVV0V "vector multiply and add high halfword" z13 zarch ++e700020000ab vmahf VRR_VVV0V "vector multiply and add high word" z13 zarch ++e700000000a9 vmalh VRR_VVVU0V "vector multiply and add logical high" z13 zarch ++e700000000a9 vmalhb VRR_VVV0V "vector multiply and add logical high byte" z13 zarch ++e700010000a9 vmalhh VRR_VVV0V "vector multiply and add logical high halfword" z13 zarch ++e700020000a9 vmalhf VRR_VVV0V "vector multiply and add logical high word" z13 zarch ++e700000000ae vmae VRR_VVVU0V "vector multiply and add even" z13 zarch ++e700000000ae vmaeb VRR_VVV0V "vector multiply and add even byte" z13 zarch ++e700010000ae vmaeh VRR_VVV0V "vector multiply and add even halfword" z13 zarch ++e700020000ae vmaef VRR_VVV0V "vector multiply and add even word" z13 zarch ++e700000000ac vmale VRR_VVVU0V "vector multiply and add logical even" z13 zarch ++e700000000ac vmaleb VRR_VVV0V "vector multiply and add logical even byte" z13 zarch ++e700010000ac vmaleh VRR_VVV0V "vector multiply and add logical even halfword" z13 zarch ++e700020000ac vmalef VRR_VVV0V "vector multiply and add logical even word" z13 zarch ++e700000000af vmao VRR_VVVU0V "vector multiply and add odd" z13 zarch ++e700000000af vmaob VRR_VVV0V "vector multiply and add odd byte" z13 zarch ++e700010000af vmaoh VRR_VVV0V "vector multiply and add odd halfword" z13 zarch ++e700020000af vmaof VRR_VVV0V "vector multiply and add odd word" z13 zarch ++e700000000ad vmalo VRR_VVVU0V "vector multiply and add logical odd" z13 zarch ++e700000000ad vmalob VRR_VVV0V "vector multiply and add logical odd byte" z13 zarch ++e700010000ad vmaloh VRR_VVV0V "vector multiply and add logical odd halfword" z13 zarch ++e700020000ad vmalof VRR_VVV0V "vector multiply and add logical odd word" z13 zarch ++e700000000a3 vmh VRR_VVV0U "vector multiply high" z13 zarch ++e700000000a3 vmhb VRR_VVV "vector multiply high byte" z13 zarch ++e700000010a3 vmhh VRR_VVV "vector multiply high halfword" z13 zarch ++e700000020a3 vmhf VRR_VVV "vector multiply high word" z13 zarch ++e700000000a1 vmlh VRR_VVV0U "vector multiply logical high" z13 zarch ++e700000000a1 vmlhb VRR_VVV "vector multiply logical high byte" z13 zarch ++e700000010a1 vmlhh VRR_VVV "vector multiply logical high halfword" z13 zarch ++e700000020a1 vmlhf VRR_VVV "vector multiply logical high word" z13 zarch ++e700000000a2 vml VRR_VVV0U "vector multiply low" z13 zarch ++e700000000a2 vmlb VRR_VVV "vector multiply low byte" z13 zarch ++e700000010a2 vmlhw VRR_VVV "vector multiply low halfword" z13 zarch ++e700000020a2 vmlf VRR_VVV "vector multiply low word" z13 zarch ++e700000000a6 vme VRR_VVV0U "vector multiply even" z13 zarch ++e700000000a6 vmeb VRR_VVV "vector multiply even byte" z13 zarch ++e700000010a6 vmeh VRR_VVV "vector multiply even halfword" z13 zarch ++e700000020a6 vmef VRR_VVV "vector multiply even word" z13 zarch ++e700000000a4 vmle VRR_VVV0U "vector multiply logical even" z13 zarch ++e700000000a4 vmleb VRR_VVV "vector multiply logical even byte" z13 zarch ++e700000010a4 vmleh VRR_VVV "vector multiply logical even halfword" z13 zarch ++e700000020a4 vmlef VRR_VVV "vector multiply logical even word" z13 zarch ++e700000000a7 vmo VRR_VVV0U "vector multiply odd" z13 zarch ++e700000000a7 vmob VRR_VVV "vector multiply odd byte" z13 zarch ++e700000010a7 vmoh VRR_VVV "vector multiply odd halfword" z13 zarch ++e700000020a7 vmof VRR_VVV "vector multiply odd word" z13 zarch ++e700000000a5 vmlo VRR_VVV0U "vector multiply logical odd" z13 zarch ++e700000000a5 vmlob VRR_VVV "vector multiply logical odd byte" z13 zarch ++e700000010a5 vmloh VRR_VVV "vector multiply logical odd halfword" z13 zarch ++e700000020a5 vmlof VRR_VVV "vector multiply logical odd word" z13 zarch ++e7000000006b vno VRR_VVV "vector nor" z13 zarch ++e7000000006b vnot VRR_VVV2 "vector not" z13 zarch ++e7000000006a vo VRR_VVV "vector or" z13 zarch ++e70000000050 vpopct VRR_VV0U "vector population count" z13 zarch ++e70000000073 verllv VRR_VVV0U "vector element rotate left logical reg" z13 zarch ++e70000000073 verllvb VRR_VVV "vector element rotate left logical reg byte" z13 zarch ++e70000001073 verllvh VRR_VVV "vector element rotate left logical reg halfword" z13 zarch ++e70000002073 verllvf VRR_VVV "vector element rotate left logical reg word" z13 zarch ++e70000003073 verllvg VRR_VVV "vector element rotate left logical reg doubleword" z13 zarch ++e70000000033 verll VRS_VVRDU "vector element rotate left logical mem" z13 zarch ++e70000000033 verllb VRS_VVRD "vector element rotate left logical mem byte" z13 zarch ++e70000001033 verllh VRS_VVRD "vector element rotate left logical mem halfword" z13 zarch ++e70000002033 verllf VRS_VVRD "vector element rotate left logical mem word" z13 zarch ++e70000003033 verllg VRS_VVRD "vector element rotate left logical mem doubleword" z13 zarch ++e70000000072 verim VRI_VVV0UU "vector element rotate and insert under mask" z13 zarch ++e70000000072 verimb VRI_VVV0U "vector element rotate and insert under mask byte" z13 zarch ++e70000001072 verimh VRI_VVV0U "vector element rotate and insert under mask halfword" z13 zarch ++e70000002072 verimf VRI_VVV0U "vector element rotate and insert under mask word" z13 zarch ++e70000003072 verimg VRI_VVV0U "vector element rotate and insert under mask doubleword" z13 zarch ++e70000000070 veslv VRR_VVV0U "vector element shift left reg" z13 zarch ++e70000000070 veslvb VRR_VVV "vector element shift left reg byte" z13 zarch ++e70000001070 veslvh VRR_VVV "vector element shift left reg halfword" z13 zarch ++e70000002070 veslvf VRR_VVV "vector element shift left reg word" z13 zarch ++e70000003070 veslvg VRR_VVV "vector element shift left reg doubleword" z13 zarch ++e70000000030 vesl VRS_VVRDU "vector element shift left mem" z13 zarch ++e70000000030 veslb VRS_VVRD "vector element shift left mem byte" z13 zarch ++e70000001030 veslh VRS_VVRD "vector element shift left mem halfword" z13 zarch ++e70000002030 veslf VRS_VVRD "vector element shift left mem word" z13 zarch ++e70000003030 veslg VRS_VVRD "vector element shift left mem doubleword" z13 zarch ++e7000000007a vesrav VRR_VVV0U "vector element shift right arithmetic reg" z13 zarch ++e7000000007a vesravb VRR_VVV "vector element shift right arithmetic reg byte" z13 zarch ++e7000000107a vesravh VRR_VVV "vector element shift right arithmetic reg halfword" z13 zarch ++e7000000207a vesravf VRR_VVV "vector element shift right arithmetic reg word" z13 zarch ++e7000000307a vesravg VRR_VVV "vector element shift right arithmetic reg doubleword" z13 zarch ++e7000000003a vesra VRS_VVRDU "vector element shift right arithmetic mem" z13 zarch ++e7000000003a vesrab VRS_VVRD "vector element shift right arithmetic mem byte" z13 zarch ++e7000000103a vesrah VRS_VVRD "vector element shift right arithmetic mem halfword" z13 zarch ++e7000000203a vesraf VRS_VVRD "vector element shift right arithmetic mem word" z13 zarch ++e7000000303a vesrag VRS_VVRD "vector element shift right arithmetic mem doubleword" z13 zarch ++e70000000078 vesrlv VRR_VVV0U "vector element shift right logical reg" z13 zarch ++e70000000078 vesrlvb VRR_VVV "vector element shift right logical reg byte" z13 zarch ++e70000001078 vesrlvh VRR_VVV "vector element shift right logical reg halfword" z13 zarch ++e70000002078 vesrlvf VRR_VVV "vector element shift right logical reg word" z13 zarch ++e70000003078 vesrlvg VRR_VVV "vector element shift right logical reg doubleword" z13 zarch ++e70000000038 vesrl VRS_VVRDU "vector element shift right logical mem" z13 zarch ++e70000000038 vesrlb VRS_VVRD "vector element shift right logical mem byte" z13 zarch ++e70000001038 vesrlh VRS_VVRD "vector element shift right logical mem halfword" z13 zarch ++e70000002038 vesrlf VRS_VVRD "vector element shift right logical mem word" z13 zarch ++e70000003038 vesrlg VRS_VVRD "vector element shift right logical mem doubleword" z13 zarch ++e70000000074 vsl VRR_VVV "vector shift left" z13 zarch ++e70000000075 vslb VRR_VVV "vector shift left by byte" z13 zarch ++e70000000077 vsldb VRI_VVV0U "vector shift left double by byte" z13 zarch ++e7000000007e vsra VRR_VVV "vector shift right arithmetic" z13 zarch ++e7000000007f vsrab VRR_VVV "vector shift right arithmetic by byte" z13 zarch ++e7000000007c vsrl VRR_VVV "vector shift right logical" z13 zarch ++e7000000007d vsrlb VRR_VVV "vector shift right logical by byte" z13 zarch ++e700000000f7 vs VRR_VVV0U "vector subtract" z13 zarch ++e700000000f7 vsb VRR_VVV "vector subtract byte" z13 zarch ++e700000010f7 vsh VRR_VVV "vector subtract halfword" z13 zarch ++e700000020f7 vsf VRR_VVV "vector subtract word" z13 zarch ++e700000030f7 vsg VRR_VVV "vector subtract doubleword" z13 zarch ++e700000040f7 vsq VRR_VVV "vector subtract quadword" z13 zarch ++e700000000f5 vscbi VRR_VVV0U "vector subtract compute borrow indication" z13 zarch ++e700000000f5 vscbib VRR_VVV "vector subtract compute borrow indication byte" z13 zarch ++e700000010f5 vscbih VRR_VVV "vector subtract compute borrow indication halfword" z13 zarch ++e700000020f5 vscbif VRR_VVV "vector subtract compute borrow indication word" z13 zarch ++e700000030f5 vscbig VRR_VVV "vector subtract compute borrow indication doubleword" z13 zarch ++e700000040f5 vscbiq VRR_VVV "vector subtract compute borrow indication quadword" z13 zarch ++e700000000bf vsbi VRR_VVVU0V "vector subtract with borrow indication" z13 zarch ++e700040000bf vsbiq VRR_VVV0V "vector subtract with borrow indication quadword" z13 zarch ++e700000000bd vsbcbi VRR_VVVU0V "vector subtract with borrow compute borrow indication" z13 zarch ++e700040000bd vsbcbiq VRR_VVV0V "vector subtract with borrow compute borrow indication quadword" z13 zarch ++e70000000065 vsumg VRR_VVV0U "vector sum across doubleword" z13 zarch ++e70000001065 vsumgh VRR_VVV "vector sum across doubleword - halfword" z13 zarch ++e70000002065 vsumgf VRR_VVV "vector sum across doubleword - word" z13 zarch ++e70000000067 vsumq VRR_VVV0U "vector sum across quadword" z13 zarch ++e70000002067 vsumqf VRR_VVV "vector sum across quadword - word elements" z13 zarch ++e70000003067 vsumqg VRR_VVV "vector sum across quadword - doubleword elements" z13 zarch ++e70000000064 vsum VRR_VVV0U "vector sum across word" z13 zarch ++e70000000064 vsumb VRR_VVV "vector sum across word - byte elements" z13 zarch ++e70000001064 vsumh VRR_VVV "vector sum across word - halfword elements" z13 zarch ++e700000000d8 vtm VRR_VV "vector test under mask" z13 zarch ++ ++# Chapter 23 - Vector String Instructions ++e70000000082 vfae VRR_VVV0U0U "vector find any element equal" z13 zarch optparm ++e70000000082 vfaeb VRR_VVV0U0 "vector find any element equal byte" z13 zarch optparm ++e70000001082 vfaeh VRR_VVV0U0 "vector find any element equal halfword" z13 zarch optparm ++e70000002082 vfaef VRR_VVV0U0 "vector find any element equal word" z13 zarch optparm ++e70000100082 vfaebs VRR_VVV0U1 "vector find any element equal" z13 zarch optparm ++e70000101082 vfaehs VRR_VVV0U1 "vector find any element equal" z13 zarch optparm ++e70000102082 vfaefs VRR_VVV0U1 "vector find any element equal" z13 zarch optparm ++e70000200082 vfaezb VRR_VVV0U2 "vector find any element equal" z13 zarch optparm ++e70000201082 vfaezh VRR_VVV0U2 "vector find any element equal" z13 zarch optparm ++e70000202082 vfaezf VRR_VVV0U2 "vector find any element equal" z13 zarch optparm ++e70000300082 vfaezbs VRR_VVV0U3 "vector find any element equal" z13 zarch optparm ++e70000301082 vfaezhs VRR_VVV0U3 "vector find any element equal" z13 zarch optparm ++e70000302082 vfaezfs VRR_VVV0U3 "vector find any element equal" z13 zarch optparm ++e70000000080 vfee VRR_VVV0U0U "vector find element equal" z13 zarch optparm ++e70000000080 vfeeb VRR_VVV0U0 "vector find element equal byte" z13 zarch optparm ++e70000001080 vfeeh VRR_VVV0U0 "vector find element equal halfword" z13 zarch optparm ++e70000002080 vfeef VRR_VVV0U0 "vector find element equal word" z13 zarch optparm ++e70000100080 vfeebs VRR_VVV "vector find element equal byte" z13 zarch ++e70000101080 vfeehs VRR_VVV "vector find element equal halfword" z13 zarch ++e70000102080 vfeefs VRR_VVV "vector find element equal word" z13 zarch ++e70000200080 vfeezb VRR_VVV "vector find element equal byte" z13 zarch ++e70000201080 vfeezh VRR_VVV "vector find element equal halfword" z13 zarch ++e70000202080 vfeezf VRR_VVV "vector find element equal word" z13 zarch ++e70000300080 vfeezbs VRR_VVV "vector find element equal byte" z13 zarch ++e70000301080 vfeezhs VRR_VVV "vector find element equal halfword" z13 zarch ++e70000302080 vfeezfs VRR_VVV "vector find element equal word" z13 zarch ++e70000000081 vfene VRR_VVV0U0U "vector find element not equal" z13 zarch optparm ++e70000000081 vfeneb VRR_VVV0U0 "vector find element not equal byte" z13 zarch optparm ++e70000001081 vfeneh VRR_VVV0U0 "vector find element not equal halfword" z13 zarch optparm ++e70000002081 vfenef VRR_VVV0U0 "vector find element not equal word" z13 zarch optparm ++e70000100081 vfenebs VRR_VVV "vector find element not equal byte" z13 zarch ++e70000101081 vfenehs VRR_VVV "vector find element not equal halfword" z13 zarch ++e70000102081 vfenefs VRR_VVV "vector find element not equal word" z13 zarch ++e70000200081 vfenezb VRR_VVV "vector find element not equal byte" z13 zarch ++e70000201081 vfenezh VRR_VVV "vector find element not equal halfword" z13 zarch ++e70000202081 vfenezf VRR_VVV "vector find element not equal word" z13 zarch ++e70000300081 vfenezbs VRR_VVV "vector find element not equal byte" z13 zarch ++e70000301081 vfenezhs VRR_VVV "vector find element not equal halfword" z13 zarch ++e70000302081 vfenezfs VRR_VVV "vector find element not equal word" z13 zarch ++e7000000005c vistr VRR_VV0U0U "vector isolate string" z13 zarch optparm ++e7000000005c vistrb VRR_VV0U2 "vector isolate string byte" z13 zarch optparm ++e7000000105c vistrh VRR_VV0U2 "vector isolate string halfword" z13 zarch optparm ++e7000000205c vistrf VRR_VV0U2 "vector isolate string word" z13 zarch optparm ++e7000010005c vistrbs VRR_VV "vector isolate string byte" z13 zarch ++e7000010105c vistrhs VRR_VV "vector isolate string halfword" z13 zarch ++e7000010205c vistrfs VRR_VV "vector isolate string word" z13 zarch ++e7000000008a vstrc VRR_VVVUU0V "vector string range compare" z13 zarch optparm ++e7000000008a vstrcb VRR_VVVU0VB "vector string range compare byte" z13 zarch optparm ++e7000100008a vstrch VRR_VVVU0VB "vector string range compare halfword" z13 zarch optparm ++e7000200008a vstrcf VRR_VVVU0VB "vector string range compare word" z13 zarch optparm ++e7000010008a vstrcbs VRR_VVVU0VB1 "vector string range compare byte" z13 zarch optparm ++e7000110008a vstrchs VRR_VVVU0VB1 "vector string range compare halfword" z13 zarch optparm ++e7000210008a vstrcfs VRR_VVVU0VB1 "vector string range compare word" z13 zarch optparm ++e7000020008a vstrczb VRR_VVVU0VB2 "vector string range compare byte" z13 zarch optparm ++e7000120008a vstrczh VRR_VVVU0VB2 "vector string range compare halfword" z13 zarch optparm ++e7000220008a vstrczf VRR_VVVU0VB2 "vector string range compare word" z13 zarch optparm ++e7000030008a vstrczbs VRR_VVVU0VB3 "vector string range compare byte" z13 zarch optparm ++e7000130008a vstrczhs VRR_VVVU0VB3 "vector string range compare halfword" z13 zarch optparm ++e7000230008a vstrczfs VRR_VVVU0VB3 "vector string range compare word" z13 zarch optparm ++ ++# Chapter 24 ++e700000000e3 vfa VRR_VVV0UU "vector fp add" z13 zarch ++e700000030e3 vfadb VRR_VVV "vector fp add" z13 zarch ++e700000830e3 wfadb VRR_VVV "vector fp add" z13 zarch ++e700000000cb wfc VRR_VV0UU2 "vector fp compare scalar" z13 zarch ++e700000030cb wfcdb VRR_VV "vector fp compare scalar" z13 zarch ++e700000000ca wfk VRR_VV0UU2 "vector fp compare and signal scalar" z13 zarch ++e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar" z13 zarch ++e700000000e8 vfce VRR_VVV0UUU "vector fp compare equal" z13 zarch ++e700000030e8 vfcedb VRR_VVV "vector fp compare equal" z13 zarch ++e700001030e8 vfcedbs VRR_VVV "vector fp compare equal" z13 zarch ++e700000830e8 wfcedb VRR_VVV "vector fp compare equal" z13 zarch ++e700001830e8 wfcedbs VRR_VVV "vector fp compare equal" z13 zarch ++e700000000eb vfch VRR_VVV0UUU "vector fp compare high" z13 zarch ++e700000030eb vfchdb VRR_VVV "vector fp compare high" z13 zarch ++e700001030eb vfchdbs VRR_VVV "vector fp compare high" z13 zarch ++e700000830eb wfchdb VRR_VVV "vector fp compare high" z13 zarch ++e700001830eb wfchdbs VRR_VVV "vector fp compare high" z13 zarch ++e700000000ea vfche VRR_VVV0UUU "vector fp compare high or equal" z13 zarch ++e700000030ea vfchedb VRR_VVV "vector fp compare high or equal" z13 zarch ++e700001030ea vfchedbs VRR_VVV "vector fp compare high or equal" z13 zarch ++e700000830ea wfchedb VRR_VVV "vector fp compare high or equal" z13 zarch ++e700001830ea wfchedbs VRR_VVV "vector fp compare high or equal" z13 zarch ++e700000000c3 vcdg VRR_VV0UUU "vector fp convert from fixed 64 bit" z13 zarch ++e700000030c3 vcdgb VRR_VV0UU "vector fp convert from fixed 64 bit" z13 zarch ++e700000830c3 wcdgb VRR_VV0UU8 "vector fp convert from fixed 64 bit" z13 zarch ++e700000000c1 vcdlg VRR_VV0UUU "vector fp convert from logical 64 bit" z13 zarch ++e700000030c1 vcdlgb VRR_VV0UU "vector fp convert from logical 64 bit" z13 zarch ++e700000830c1 wcdlgb VRR_VV0UU8 "vector fp convert from logical 64 bit" z13 zarch ++e700000000c2 vcgd VRR_VV0UUU "vector fp convert to fixed 64 bit" z13 zarch ++e700000030c2 vcgdb VRR_VV0UU "vector fp convert to fixed 64 bit" z13 zarch ++e700000830c2 wcgdb VRR_VV0UU8 "vector fp convert to fixed 64 bit" z13 zarch ++e700000000c0 vclgd VRR_VV0UUU "vector fp convert to logical 64 bit" z13 zarch ++e700000030c0 vclgdb VRR_VV0UU "vector fp convert to logical 64 bit" z13 zarch ++e700000830c0 wclgdb VRR_VV0UU8 "vector fp convert to logical 64 bit" z13 zarch ++e700000000e5 vfd VRR_VVV0UU "vector fp divide" z13 zarch ++e700000030e5 vfddb VRR_VVV "vector fp divide" z13 zarch ++e700000830e5 wfddb VRR_VVV "vector fp divide" z13 zarch ++e700000000c7 vfi VRR_VV0UUU "vector load fp integer" z13 zarch ++e700000030c7 vfidb VRR_VV0UU "vector load fp integer" z13 zarch ++e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer" z13 zarch ++e700000000c4 vlde VRR_VV0UU2 "vector fp load lengthened" z13 zarch ++e700000020c4 vldeb VRR_VV "vector fp load lengthened" z13 zarch ++e700000820c4 wldeb VRR_VV "vector fp load lengthened" z13 zarch ++e700000000c5 vled VRR_VV0UUU "vector fp load rounded" z13 zarch ++e700000030c5 vledb VRR_VV0UU "vector fp load rounded" z13 zarch ++e700000830c5 wledb VRR_VV0UU8 "vector fp load rounded" z13 zarch ++e700000000e7 vfm VRR_VVV0UU "vector fp multiply" z13 zarch ++e700000030e7 vfmdb VRR_VVV "vector fp multiply" z13 zarch ++e700000830e7 wfmdb VRR_VVV "vector fp multiply" z13 zarch ++e7000000008f vfma VRR_VVVU0UV "vector fp multiply and add" z13 zarch ++e7000300008f vfmadb VRR_VVVV "vector fp multiply and add" z13 zarch ++e7000308008f wfmadb VRR_VVVV "vector fp multiply and add" z13 zarch ++e7000000008e vfms VRR_VVVU0UV "vector fp multiply and subtract" z13 zarch ++e7000300008e vfmsdb VRR_VVVV "vector fp multiply and subtract" z13 zarch ++e7000308008e wfmsdb VRR_VVVV "vector fp multiply and subtract" z13 zarch ++e700000000cc vfpso VRR_VV0UUU "vector fp perform sign operation" z13 zarch ++e700000030cc vfpsodb VRR_VV0U2 "vector fp perform sign operation" z13 zarch ++e700000830cc wfpsodb VRR_VV0U2 "vector fp perform sign operation" z13 zarch ++e700000030cc vflcdb VRR_VV "vector fp perform sign operation" z13 zarch ++e700000830cc wflcdb VRR_VV "vector fp perform sign operation" z13 zarch ++e700001030cc vflndb VRR_VV "vector fp perform sign operation" z13 zarch ++e700001830cc wflndb VRR_VV "vector fp perform sign operation" z13 zarch ++e700002030cc vflpdb VRR_VV "vector fp perform sign operation" z13 zarch ++e700002830cc wflpdb VRR_VV "vector fp perform sign operation" z13 zarch ++e700000000ce vfsq VRR_VV0UU2 "vector fp square root" z13 zarch ++e700000030ce vfsqdb VRR_VV "vector fp square root" z13 zarch ++e700000830ce wfsqdb VRR_VV "vector fp square root" z13 zarch ++e700000000e2 vfs VRR_VVV0UU "vector fp subtract" z13 zarch ++e700000030e2 vfsdb VRR_VVV "vector fp subtract" z13 zarch ++e700000830e2 wfsdb VRR_VVV "vector fp subtract" z13 zarch ++e7000000004a vftci VRI_VVUUU "vector fp test data class immediate" z13 zarch ++e7000000304a vftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch ++e7000008304a wftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch ++ ++ed00000000ae cdpt RSL_LRDFU "convert from packed to long dfp" z13 zarch ++ed00000000af cxpt RSL_LRDFEU "convert from packed to extended dfp" z13 zarch ++ed00000000ac cpdt RSL_LRDFU "convert from long dfp to packed" z13 zarch ++ed00000000ad cpxt RSL_LRDFEU "convert from extended dfp to packed" z13 zarch ++ ++b9e0 locfhr RRF_U0RR "load high on condition from gpr" z13 zarch ++b9e000000000 locfhr*16 RRF_00RR "load high on condition from gpr" z13 zarch ++eb00000000e0 locfh RSY_RURD2 "load high on condition from memory" z13 zarch ++eb00000000e0 locfh*12 RSY_R0RD "load high on condition from memory" z13 zarch ++ec0000000042 lochi RIE_RUI0 "load halfword immediate on condition into 32 bit gpr" z13 zarch ++ec0000000042 lochi*12 RIE_R0I0 "load halfword immediate on condition into 32 bit gpr" z13 zarch ++ec0000000046 locghi RIE_RUI0 "load halfword immediate on condition into 64 bit gpr" z13 zarch ++ec0000000046 locghi*12 RIE_R0I0 "load halfword immediate on condition into 64 bit gpr" z13 zarch ++ec000000004e lochhi RIE_RUI0 "load halfword high immediate on condition" z13 zarch ++ec000000004e lochhi*12 RIE_R0I0 "load halfword high immediate on condition" z13 zarch ++eb00000000e1 stocfh RSY_RURD2 "store high on condition" z13 zarch ++eb00000000e1 stocfh*12 RSY_R0RD "store high on condition" z13 zarch ++ ++e3000000003a llzrgf RXY_RRRD "load logical and zero rightmost bytes 32->64" z13 zarch ++e3000000003b lzrf RXY_RRRD "load and zero rightmost byte 32->32" z13 zarch ++e3000000002a lzrg RXY_RRRD "load and zero rightmost byte 64->64" z13 zarch ++b9ec ppno RRE_RR "perform pseudorandom number operation" z13 zarch diff --git a/SOURCES/binutils-rh1183838.patch b/SOURCES/binutils-rh1183838.patch new file mode 100644 index 0000000..12d397f --- /dev/null +++ b/SOURCES/binutils-rh1183838.patch @@ -0,0 +1,339 @@ +diff -Nrup a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c +--- a/gas/config/tc-ppc.c 2015-05-07 09:21:42.738374151 -0600 ++++ b/gas/config/tc-ppc.c 2015-05-07 14:58:51.607894208 -0600 +@@ -3143,103 +3143,6 @@ md_assemble (char *str) + break; + } + } +- +- /* For the absolute forms of branches, convert the PC +- relative form back into the absolute. */ +- if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) +- { +- switch (reloc) +- { +- case BFD_RELOC_PPC_B26: +- reloc = BFD_RELOC_PPC_BA26; +- break; +- case BFD_RELOC_PPC_B16: +- reloc = BFD_RELOC_PPC_BA16; +- break; +- case BFD_RELOC_PPC_B16_BRTAKEN: +- reloc = BFD_RELOC_PPC_BA16_BRTAKEN; +- break; +- case BFD_RELOC_PPC_B16_BRNTAKEN: +- reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; +- break; +- default: +- break; +- } +- } +- +- switch (reloc) +- { +- case BFD_RELOC_PPC_TOC16: +- toc_reloc_types |= has_small_toc_reloc; +- break; +- case BFD_RELOC_PPC64_TOC16_LO: +- case BFD_RELOC_PPC64_TOC16_HI: +- case BFD_RELOC_PPC64_TOC16_HA: +- toc_reloc_types |= has_large_toc_reloc; +- break; +- default: +- break; +- } +- +- if ((operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) +- { +- switch (reloc) +- { +- case BFD_RELOC_16: +- reloc = BFD_RELOC_PPC64_ADDR16_DS; +- break; +- case BFD_RELOC_LO16: +- reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; +- break; +- case BFD_RELOC_16_GOTOFF: +- reloc = BFD_RELOC_PPC64_GOT16_DS; +- break; +- case BFD_RELOC_LO16_GOTOFF: +- reloc = BFD_RELOC_PPC64_GOT16_LO_DS; +- break; +- case BFD_RELOC_LO16_PLTOFF: +- reloc = BFD_RELOC_PPC64_PLT16_LO_DS; +- break; +- case BFD_RELOC_16_BASEREL: +- reloc = BFD_RELOC_PPC64_SECTOFF_DS; +- break; +- case BFD_RELOC_LO16_BASEREL: +- reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; +- break; +- case BFD_RELOC_PPC_TOC16: +- reloc = BFD_RELOC_PPC64_TOC16_DS; +- break; +- case BFD_RELOC_PPC64_TOC16_LO: +- reloc = BFD_RELOC_PPC64_TOC16_LO_DS; +- break; +- case BFD_RELOC_PPC64_PLTGOT16: +- reloc = BFD_RELOC_PPC64_PLTGOT16_DS; +- break; +- case BFD_RELOC_PPC64_PLTGOT16_LO: +- reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; +- break; +- case BFD_RELOC_PPC_DTPREL16: +- reloc = BFD_RELOC_PPC64_DTPREL16_DS; +- break; +- case BFD_RELOC_PPC_DTPREL16_LO: +- reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; +- break; +- case BFD_RELOC_PPC_TPREL16: +- reloc = BFD_RELOC_PPC64_TPREL16_DS; +- break; +- case BFD_RELOC_PPC_TPREL16_LO: +- reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; +- break; +- case BFD_RELOC_PPC_GOT_DTPREL16: +- case BFD_RELOC_PPC_GOT_DTPREL16_LO: +- case BFD_RELOC_PPC_GOT_TPREL16: +- case BFD_RELOC_PPC_GOT_TPREL16_LO: +- break; +- default: +- as_bad (_("unsupported relocation for DS offset field")); +- break; +- } +- } + } + #endif /* OBJ_ELF */ + +@@ -3248,11 +3151,13 @@ md_assemble (char *str) + /* Determine a BFD reloc value based on the operand information. + We are only prepared to turn a few of the operands into + relocs. */ +- else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 ++ else if ((operand->flags & (PPC_OPERAND_RELATIVE ++ | PPC_OPERAND_ABSOLUTE)) != 0 + && operand->bitm == 0x3fffffc + && operand->shift == 0) + reloc = BFD_RELOC_PPC_B26; +- else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 ++ else if ((operand->flags & (PPC_OPERAND_RELATIVE ++ | PPC_OPERAND_ABSOLUTE)) != 0 + && operand->bitm == 0xfffc + && operand->shift == 0) + reloc = BFD_RELOC_PPC_B16; +@@ -3268,40 +3173,126 @@ md_assemble (char *str) + && operand->bitm == 0x1fffffe + && operand->shift == 0) + reloc = BFD_RELOC_PPC_VLE_REL24; +- else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0 +- && operand->bitm == 0x3fffffc +- && operand->shift == 0) +- reloc = BFD_RELOC_PPC_BA26; +- else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0 +- && operand->bitm == 0xfffc +- && operand->shift == 0) +- reloc = BFD_RELOC_PPC_BA16; +-#if defined (OBJ_XCOFF) || defined (OBJ_ELF) +- else if ((operand->flags & PPC_OPERAND_PARENS) != 0 ++ else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0 + && (operand->bitm & 0xfff0) == 0xfff0 + && operand->shift == 0) + { ++ reloc = BFD_RELOC_16; ++#if defined OBJ_XCOFF || defined OBJ_ELF + /* Note: the symbol may be not yet defined. */ +- if (ppc_is_toc_sym (ex.X_add_symbol)) ++ if ((operand->flags & PPC_OPERAND_PARENS) != 0 ++ && ppc_is_toc_sym (ex.X_add_symbol)) + { + reloc = BFD_RELOC_PPC_TOC16; + #ifdef OBJ_ELF +- if (ppc_obj64 +- && (operand->flags & PPC_OPERAND_DS) != 0) +- reloc = BFD_RELOC_PPC64_TOC16_DS; ++ as_warn (_("assuming %s on symbol"), ++ ppc_obj64 ? "@toc" : "@xgot"); + #endif + } +- else ++#endif ++ } ++ ++ /* For the absolute forms of branches, convert the PC ++ relative form back into the absolute. */ ++ if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) ++ { ++ switch (reloc) + { +- reloc = BFD_RELOC_16; ++ case BFD_RELOC_PPC_B26: ++ reloc = BFD_RELOC_PPC_BA26; ++ break; ++ case BFD_RELOC_PPC_B16: ++ reloc = BFD_RELOC_PPC_BA16; ++ break; + #ifdef OBJ_ELF +- if (ppc_obj64 +- && (operand->flags & PPC_OPERAND_DS) != 0) +- reloc = BFD_RELOC_PPC64_ADDR16_DS; ++ case BFD_RELOC_PPC_B16_BRTAKEN: ++ reloc = BFD_RELOC_PPC_BA16_BRTAKEN; ++ break; ++ case BFD_RELOC_PPC_B16_BRNTAKEN: ++ reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; ++ break; + #endif ++ default: ++ break; ++ } ++ } ++ ++#ifdef OBJ_ELF ++ switch (reloc) ++ { ++ case BFD_RELOC_PPC_TOC16: ++ toc_reloc_types |= has_small_toc_reloc; ++ break; ++ case BFD_RELOC_PPC64_TOC16_LO: ++ case BFD_RELOC_PPC64_TOC16_HI: ++ case BFD_RELOC_PPC64_TOC16_HA: ++ toc_reloc_types |= has_large_toc_reloc; ++ break; ++ default: ++ break; ++ } ++ ++ if (ppc_obj64 ++ && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) ++ { ++ switch (reloc) ++ { ++ case BFD_RELOC_16: ++ reloc = BFD_RELOC_PPC64_ADDR16_DS; ++ break; ++ case BFD_RELOC_LO16: ++ reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; ++ break; ++ case BFD_RELOC_16_GOTOFF: ++ reloc = BFD_RELOC_PPC64_GOT16_DS; ++ break; ++ case BFD_RELOC_LO16_GOTOFF: ++ reloc = BFD_RELOC_PPC64_GOT16_LO_DS; ++ break; ++ case BFD_RELOC_LO16_PLTOFF: ++ reloc = BFD_RELOC_PPC64_PLT16_LO_DS; ++ break; ++ case BFD_RELOC_16_BASEREL: ++ reloc = BFD_RELOC_PPC64_SECTOFF_DS; ++ break; ++ case BFD_RELOC_LO16_BASEREL: ++ reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; ++ break; ++ case BFD_RELOC_PPC_TOC16: ++ reloc = BFD_RELOC_PPC64_TOC16_DS; ++ break; ++ case BFD_RELOC_PPC64_TOC16_LO: ++ reloc = BFD_RELOC_PPC64_TOC16_LO_DS; ++ break; ++ case BFD_RELOC_PPC64_PLTGOT16: ++ reloc = BFD_RELOC_PPC64_PLTGOT16_DS; ++ break; ++ case BFD_RELOC_PPC64_PLTGOT16_LO: ++ reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; ++ break; ++ case BFD_RELOC_PPC_DTPREL16: ++ reloc = BFD_RELOC_PPC64_DTPREL16_DS; ++ break; ++ case BFD_RELOC_PPC_DTPREL16_LO: ++ reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; ++ break; ++ case BFD_RELOC_PPC_TPREL16: ++ reloc = BFD_RELOC_PPC64_TPREL16_DS; ++ break; ++ case BFD_RELOC_PPC_TPREL16_LO: ++ reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; ++ break; ++ case BFD_RELOC_PPC_GOT_DTPREL16: ++ case BFD_RELOC_PPC_GOT_DTPREL16_LO: ++ case BFD_RELOC_PPC_GOT_TPREL16: ++ case BFD_RELOC_PPC_GOT_TPREL16_LO: ++ break; ++ default: ++ as_bad (_("unsupported relocation for DS offset field")); ++ break; + } + } +-#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ ++#endif + + /* We need to generate a fixup for this expression. */ + if (fc >= MAX_INSN_FIXUPS) +diff -Nrup a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d +--- a/ld/testsuite/ld-powerpc/elfv2exe.d 2015-05-07 09:21:42.727374395 -0600 ++++ b/ld/testsuite/ld-powerpc/elfv2exe.d 2015-05-07 09:26:49.048581753 -0600 +@@ -21,7 +21,7 @@ Disassembly of section \.text: + + 0+100000e0 <_start>: + .*: (02 10 40 3c|3c 40 10 02) lis r2,4098 +-.*: (40 81 42 38|38 42 81 40) addi r2,r2,-32448 ++.*: (38 81 42 38|38 42 81 38) addi r2,r2,-32456 + .*: (a6 02 08 7c|7c 08 02 a6) mflr r0 + .*: (e1 ff 21 f8|f8 21 ff e1) stdu r1,-32\(r1\) + .*: (30 00 01 f8|f8 01 00 30) std r0,48\(r1\) +diff -Nrup a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d +--- a/ld/testsuite/ld-powerpc/elfv2so.d 2015-05-07 09:21:42.688375260 -0600 ++++ b/ld/testsuite/ld-powerpc/elfv2so.d 2015-05-07 09:26:49.048581753 -0600 +@@ -7,33 +7,33 @@ + + Disassembly of section \.text: + +-0+300 <.*\.plt_call\.f4>: ++0+320 <.*\.plt_call\.f4>: + .*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) + .*: (38 80 82 e9|e9 82 80 38) ld r12,-32712\(r2\) + .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 + .*: (20 04 80 4e|4e 80 04 20) bctr + +-0+310 <.*\.plt_call\.f3>: ++0+330 <.*\.plt_call\.f3>: + .*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) + .*: (28 80 82 e9|e9 82 80 28) ld r12,-32728\(r2\) + .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 + .*: (20 04 80 4e|4e 80 04 20) bctr + +-0+320 <.*\.plt_call\.f2>: ++0+340 <.*\.plt_call\.f2>: + .*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) + .*: (30 80 82 e9|e9 82 80 30) ld r12,-32720\(r2\) + .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 + .*: (20 04 80 4e|4e 80 04 20) bctr + +-0+330 <.*\.plt_call\.f1>: ++0+350 <.*\.plt_call\.f1>: + .*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) + .*: (40 80 82 e9|e9 82 80 40) ld r12,-32704\(r2\) + .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 + .*: (20 04 80 4e|4e 80 04 20) bctr + +-0+340 : ++0+360 : + .*: (02 00 4c 3c|3c 4c 00 02) addis r2,r12,2 +-.*: (e0 81 42 38|38 42 81 e0) addi r2,r2,-32288 ++.*: (d8 81 42 38|38 42 81 d8) addi r2,r2,-32296 + .*: (a6 02 08 7c|7c 08 02 a6) mflr r0 + .*: (e1 ff 21 f8|f8 21 ff e1) stdu r1,-32\(r1\) + .*: (30 00 01 f8|f8 01 00 30) std r0,48\(r1\) +@@ -50,10 +50,10 @@ Disassembly of section \.text: + .*: (20 00 21 38|38 21 00 20) addi r1,r1,32 + .*: (a6 03 08 7c|7c 08 03 a6) mtlr r0 + .*: (20 00 80 4e|4e 80 00 20) blr +-.*: (a0 01 01 00|00 00 00 00) .* +-.*: (00 00 00 00|00 01 01 a0) .* ++.*: (98 01 01 00|00 00 00 00) .* ++.*: (00 00 00 00|00 01 01 98) .* + +-0+390 <__glink_PLTresolve>: ++0+3b0 <__glink_PLTresolve>: + .*: (a6 02 08 7c|7c 08 02 a6) mflr r0 + .*: (05 00 9f 42|42 9f 00 05) bcl .* + .*: (a6 02 68 7d|7d 68 02 a6) mflr r11 diff --git a/SOURCES/binutils-rh1194164.patch b/SOURCES/binutils-rh1194164.patch new file mode 100644 index 0000000..1191eef --- /dev/null +++ b/SOURCES/binutils-rh1194164.patch @@ -0,0 +1,267 @@ +diff -Nrup a/bfd/bfd-in2.h b/bfd/bfd-in2.h +--- a/bfd/bfd-in2.h 2015-03-31 11:11:36.351939753 -0600 ++++ b/bfd/bfd-in2.h 2015-03-31 11:12:07.733201604 -0600 +@@ -3191,6 +3191,7 @@ instruction. */ + BFD_RELOC_PPC64_PLTGOT16_LO_DS, + BFD_RELOC_PPC64_ADDR16_HIGH, + BFD_RELOC_PPC64_ADDR16_HIGHA, ++ BFD_RELOC_PPC64_ADDR64_LOCAL, + + /* PowerPC and PowerPC64 thread-local storage relocations. */ + BFD_RELOC_PPC_TLS, +diff -Nrup a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c +--- a/bfd/elf64-ppc.c 2015-03-31 11:11:36.348939823 -0600 ++++ b/bfd/elf64-ppc.c 2015-03-31 11:12:07.735201557 -0600 +@@ -2097,6 +2097,21 @@ static reloc_howto_type ppc64_elf_howto_ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + ++ /* Like ADDR64, but use local entry point of function. */ ++ HOWTO (R_PPC64_ADDR64_LOCAL, /* type */ ++ 0, /* rightshift */ ++ 4, /* size (0=byte, 1=short, 2=long, 4=64 bits) */ ++ 64, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_PPC64_ADDR64_LOCAL", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ ONES (64), /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ + /* GNU extension to record C++ vtable hierarchy. */ + HOWTO (R_PPC64_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ +@@ -2385,6 +2400,8 @@ ppc64_elf_reloc_type_lookup (bfd *abfd A + break; + case BFD_RELOC_HI16_S_PCREL: r = R_PPC64_REL16_HA; + break; ++ case BFD_RELOC_PPC64_ADDR64_LOCAL: r = R_PPC64_ADDR64_LOCAL; ++ break; + case BFD_RELOC_VTABLE_INHERIT: r = R_PPC64_GNU_VTINHERIT; + break; + case BFD_RELOC_VTABLE_ENTRY: r = R_PPC64_GNU_VTENTRY; +@@ -5431,6 +5448,21 @@ ppc64_elf_check_relocs (bfd *abfd, struc + case R_PPC64_REL16_HA: + break; + ++ /* Not supported as a dynamic relocation. */ ++ case R_PPC64_ADDR64_LOCAL: ++ if (info->shared) ++ { ++ if (!ppc64_elf_howto_table[R_PPC64_ADDR32]) ++ ppc_howto_init (); ++ info->callbacks->einfo (_("%P: %H: %s reloc unsupported " ++ "in shared libraries and PIEs.\n"), ++ abfd, sec, rel->r_offset, ++ ppc64_elf_howto_table[r_type]->name); ++ bfd_set_error (bfd_error_bad_value); ++ return FALSE; ++ } ++ break; ++ + case R_PPC64_TOC16: + case R_PPC64_TOC16_DS: + htab->do_multi_toc = 1; +@@ -14162,6 +14194,12 @@ ppc64_elf_relocate_section (bfd *output_ + addend -= htab->elf.tls_sec->vma + DTP_OFFSET; + break; + ++ case R_PPC64_ADDR64_LOCAL: ++ addend += PPC64_LOCAL_ENTRY_OFFSET (h != NULL ++ ? h->elf.other ++ : sym->st_other); ++ break; ++ + case R_PPC64_DTPMOD64: + relocation = 1; + addend = 0; +diff -Nrup a/bfd/libbfd.h b/bfd/libbfd.h +--- a/bfd/libbfd.h 2015-03-31 11:11:36.300940952 -0600 ++++ b/bfd/libbfd.h 2015-03-31 11:12:07.735201557 -0600 +@@ -1398,6 +1398,7 @@ static const char *const bfd_reloc_code_ + "BFD_RELOC_PPC64_PLTGOT16_LO_DS", + "BFD_RELOC_PPC64_ADDR16_HIGH", + "BFD_RELOC_PPC64_ADDR16_HIGHA", ++ "BFD_RELOC_PPC64_ADDR64_LOCAL", + "BFD_RELOC_PPC_TLS", + "BFD_RELOC_PPC_TLSGD", + "BFD_RELOC_PPC_TLSLD", +diff -Nrup a/bfd/reloc.c b/bfd/reloc.c +--- a/bfd/reloc.c 2015-03-31 11:11:36.300940952 -0600 ++++ b/bfd/reloc.c 2015-03-31 11:12:07.736201534 -0600 +@@ -2896,6 +2896,8 @@ ENUMX + BFD_RELOC_PPC64_ADDR16_HIGH + ENUMX + BFD_RELOC_PPC64_ADDR16_HIGHA ++ENUMX ++ BFD_RELOC_PPC64_ADDR64_LOCAL + ENUMDOC + Power(rs6000) and PowerPC relocations. + +diff -Nrup a/elfcpp/powerpc.h b/elfcpp/powerpc.h +--- a/elfcpp/powerpc.h 2015-03-31 11:11:36.301940929 -0600 ++++ b/elfcpp/powerpc.h 2015-03-31 11:12:07.736201534 -0600 +@@ -176,6 +176,8 @@ enum + R_PPC_EMB_BIT_FLD = 115, + R_PPC64_DTPREL16_HIGHA = 115, + R_PPC_EMB_RELSDA = 116, ++ R_PPC64_REL24_NOTOC = 116, ++ R_PPC64_ADDR64_LOCAL = 117, + + R_PPC_VLE_REL8 = 216, + R_PPC_VLE_REL15 = 217, +diff -Nrup a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c +--- a/gas/config/tc-ppc.c 2015-03-31 11:11:36.321940458 -0600 ++++ b/gas/config/tc-ppc.c 2015-03-31 11:12:07.737201510 -0600 +@@ -1952,6 +1952,7 @@ ppc_elf_suffix (char **str_p, expression + MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA), + MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST), + MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA), ++ MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL), + MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH), + MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA), + MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER), +@@ -6868,6 +6869,7 @@ md_apply_fix (fixS *fixP, valueT *valP, + case BFD_RELOC_PPC64_HIGHEST_S: + case BFD_RELOC_PPC64_ADDR16_HIGH: + case BFD_RELOC_PPC64_ADDR16_HIGHA: ++ case BFD_RELOC_PPC64_ADDR64_LOCAL: + break; + + case BFD_RELOC_PPC_DTPMOD: +diff -Nrup a/include/elf/ppc64.h b/include/elf/ppc64.h +--- a/include/elf/ppc64.h 2015-03-31 11:11:36.303940882 -0600 ++++ b/include/elf/ppc64.h 2015-03-31 11:12:07.740201440 -0600 +@@ -149,6 +149,10 @@ START_RELOC_NUMBERS (elf_ppc64_reloc_typ + RELOC_NUMBER (R_PPC64_DTPREL16_HIGH, 114) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHA, 115) + ++/* Added for ELFv2. */ ++ RELOC_NUMBER (R_PPC64_REL24_NOTOC, 116) ++ RELOC_NUMBER (R_PPC64_ADDR64_LOCAL, 117) ++ + #ifndef RELOC_MACROS_GEN_FUNC + /* Fake relocation only used internally by ld. */ + RELOC_NUMBER (R_PPC64_LO_DS_OPT, 128) +diff -Nrup a/ld/testsuite/ld-powerpc/elfv2-2a.s b/ld/testsuite/ld-powerpc/elfv2-2a.s +--- a/ld/testsuite/ld-powerpc/elfv2-2a.s 1969-12-31 17:00:00.000000000 -0700 ++++ b/ld/testsuite/ld-powerpc/elfv2-2a.s 2015-03-31 11:12:07.740201440 -0600 +@@ -0,0 +1,27 @@ ++ .globl f1 ++ .type f1,@function ++ .text ++f1: ++ addis 2,12,.TOC.-f1@ha ++ addi 2,2,.TOC.-f1@l ++ .localentry f1,.-f1 ++ blr ++ .size f1,.-f1 ++ ++ .globl f2 ++ .type f2,@function ++ .text ++f2: ++ addi 2,12,.TOC.-f2 ++ .localentry f2,.-f2 ++ blr ++ .size f2,.-f2 ++ ++ .quad f1 ++ .quad f1@localentry ++ .quad f2 ++ .quad f2@localentry ++ .quad f3 ++ .quad f3@localentry ++ .quad f4 ++ .quad f4@localentry +diff -Nrup a/ld/testsuite/ld-powerpc/elfv2-2b.s b/ld/testsuite/ld-powerpc/elfv2-2b.s +--- a/ld/testsuite/ld-powerpc/elfv2-2b.s 1969-12-31 17:00:00.000000000 -0700 ++++ b/ld/testsuite/ld-powerpc/elfv2-2b.s 2015-03-31 11:12:07.740201440 -0600 +@@ -0,0 +1,17 @@ ++ .globl f3 ++ .type f3,@function ++ .text ++f3: ++ addis 2,12,.TOC.-f3@ha ++ addi 2,2,.TOC.-f3@l ++ .localentry f3,.-f3 ++ blr ++ .size f3,.-f3 ++ ++ .globl f4 ++ .type f4,@function ++ .text ++f4: ++ .localentry f4,0 ++ blr ++ .size f4,.-f4 +diff -Nrup a/ld/testsuite/ld-powerpc/elfv2-2exe.d b/ld/testsuite/ld-powerpc/elfv2-2exe.d +--- a/ld/testsuite/ld-powerpc/elfv2-2exe.d 1969-12-31 17:00:00.000000000 -0700 ++++ b/ld/testsuite/ld-powerpc/elfv2-2exe.d 2015-03-31 11:12:07.740201440 -0600 +@@ -0,0 +1,41 @@ ++#source: elfv2-2a.s ++#source: elfv2-2b.s ++#as: -a64 ++#ld: -melf64ppc -e f1 ++#objdump: -dr ++ ++.* ++ ++Disassembly of section \.text: ++ ++0+10000078 : ++.*: (3c 40 10 01|01 10 40 3c) lis r2,4097 ++.*: (38 42 80 78|78 80 42 38) addi r2,r2,-32648 ++.*: (4e 80 00 20|20 00 80 4e) blr ++0+10000084 : ++.*: (38 4c 7f f4|f4 7f 4c 38) addi r2,r12,32756 ++.*: (4e 80 00 20|20 00 80 4e) blr ++.*: (00 00 00 00|78 00 00 10) .* ++.*: (10 00 00 78|00 00 00 00) .* ++.*: (00 00 00 00|80 00 00 10) .* ++.*: (10 00 00 80|00 00 00 00) .* ++.*: (00 00 00 00|84 00 00 10) .* ++.*: (10 00 00 84|00 00 00 00) .* ++.*: (00 00 00 00|88 00 00 10) .* ++.*: (10 00 00 88|00 00 00 00) .* ++.*: (00 00 00 00|cc 00 00 10) .* ++.*: (10 00 00 cc|00 00 00 00) .* ++.*: (00 00 00 00|d4 00 00 10) .* ++.*: (10 00 00 d4|00 00 00 00) .* ++.*: (00 00 00 00|d8 00 00 10) .* ++.*: (10 00 00 d8|00 00 00 00) .* ++.*: (00 00 00 00|d8 00 00 10) .* ++.*: (10 00 00 d8|00 00 00 00) .* ++ ++0+100000cc : ++.*: (3c 40 10 01|01 10 40 3c) lis r2,4097 ++.*: (38 42 80 78|78 80 42 38) addi r2,r2,-32648 ++.*: (4e 80 00 20|20 00 80 4e) blr ++ ++0+100000d8 : ++.*: (4e 80 00 20|20 00 80 4e) blr +diff -Nrup a/ld/testsuite/ld-powerpc/elfv2-2so.d b/ld/testsuite/ld-powerpc/elfv2-2so.d +--- a/ld/testsuite/ld-powerpc/elfv2-2so.d 1969-12-31 17:00:00.000000000 -0700 ++++ b/ld/testsuite/ld-powerpc/elfv2-2so.d 2015-03-31 11:12:07.740201440 -0600 +@@ -0,0 +1,5 @@ ++#source: elfv2-2a.s ++#source: elfv2-2b.s ++#as: -a64 ++#ld: -melf64ppc -shared -e f1 ++#error: .* R_PPC64_ADDR64_LOCAL reloc unsupported in shared libraries and PIEs.* +diff -Nrup a/ld/testsuite/ld-powerpc/powerpc.exp b/ld/testsuite/ld-powerpc/powerpc.exp +--- a/ld/testsuite/ld-powerpc/powerpc.exp 2015-03-31 11:11:36.355939659 -0600 ++++ b/ld/testsuite/ld-powerpc/powerpc.exp 2015-03-31 11:13:19.569511875 -0600 +@@ -276,6 +276,9 @@ if [ supports_ppc64 ] then { + run_dump_test "ambiguousv1" + run_dump_test "ambiguousv2" + run_dump_test "defsym" ++ run_dump_test "elfv2-2so" ++ run_dump_test "elfv2-2exe" ++ + } + + if { [istarget "powerpc*-eabi*"] } { diff --git a/SOURCES/binutils-rh1200138-1.patch b/SOURCES/binutils-rh1200138-1.patch index 315abf3..4608475 100644 --- a/SOURCES/binutils-rh1200138-1.patch +++ b/SOURCES/binutils-rh1200138-1.patch @@ -118,7 +118,7 @@ diff -Nrup a/ld/testsuite/ld-x86-64/pr14207.d b/ld/testsuite/ld-x86-64/pr14207.d - NULL +.* -#... +Elf file type is DYN \(Shared object file\) -+Entry point 0x1d9 ++Entry point 0x1dc +There are 4 program headers, starting at offset 64 + +Program Headers: diff --git a/SOURCES/binutils-rh1203449-2.patch b/SOURCES/binutils-rh1203449-2.patch new file mode 100644 index 0000000..20d2271 --- /dev/null +++ b/SOURCES/binutils-rh1203449-2.patch @@ -0,0 +1,15 @@ +diff -Nrup a/bfd/elf.c b/bfd/elf.c +--- a/bfd/elf.c 2015-05-26 16:15:38.169585374 -0600 ++++ b/bfd/elf.c 2015-05-26 16:16:07.571947059 -0600 +@@ -3912,6 +3912,11 @@ _bfd_elf_map_sections_to_segments (bfd * + last_size = 0; + phdr_index = 0; + maxpagesize = bed->maxpagesize; ++ /* PR 17512: file: c8455299. ++ Avoid divide-by-zero errors later on. ++ FIXME: Should we abort if the maxpagesize is zero ? */ ++ if (maxpagesize == 0) ++ maxpagesize = 1; + writable = FALSE; + dynsec = bfd_get_section_by_name (abfd, ".dynamic"); + if (dynsec != NULL diff --git a/SOURCES/binutils-rh1203449.patch b/SOURCES/binutils-rh1203449.patch new file mode 100644 index 0000000..009cefd --- /dev/null +++ b/SOURCES/binutils-rh1203449.patch @@ -0,0 +1,20 @@ +--- ld/emultempl/armelf.em~ 2015-03-18 17:32:36.436208938 -0400 ++++ ld/emultempl/armelf.em 2015-03-18 17:32:54.455591126 -0400 +@@ -53,6 +53,7 @@ + input_flags.dynamic = ${DYNAMIC_LINK-TRUE}; + config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`; + config.separate_code = `if test "x${SEPARATE_CODE}" = xyes ; then echo TRUE ; else echo FALSE ; fi`; ++ link_info.relro = TRUE; + } + + static void +--- ld/emultempl/aarch64elf.em~ 2015-03-18 17:32:08.347172011 -0400 ++++ ld/emultempl/aarch64elf.em 2015-03-18 17:32:30.866399906 -0400 +@@ -40,6 +40,7 @@ + input_flags.dynamic = ${DYNAMIC_LINK-TRUE}; + config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`; + config.separate_code = `if test "x${SEPARATE_CODE}" = xyes ; then echo TRUE ; else echo FALSE ; fi`; ++ link_info.relro = TRUE; + } + + static void diff --git a/SOURCES/binutils-rh1225091.patch b/SOURCES/binutils-rh1225091.patch new file mode 100644 index 0000000..27ee0a1 --- /dev/null +++ b/SOURCES/binutils-rh1225091.patch @@ -0,0 +1,31 @@ +diff -Nrup a/bfd/elf64-aarch64.c b/bfd/elf64-aarch64.c +--- a/bfd/elf64-aarch64.c 2015-05-28 11:22:51.726394256 -0600 ++++ b/bfd/elf64-aarch64.c 2015-05-28 11:24:29.923395845 -0600 +@@ -6006,17 +6006,6 @@ elf64_aarch64_reloc_type_class (const El + } + } + +-/* Set the right machine number for an AArch64 ELF file. */ +- +-static bfd_boolean +-elf64_aarch64_section_flags (flagword *flags, const Elf_Internal_Shdr *hdr) +-{ +- if (hdr->sh_type == SHT_NOTE) +- *flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_SAME_CONTENTS; +- +- return TRUE; +-} +- + /* Handle an AArch64 specific section when reading an object file. This is + called when bfd_section_from_shdr finds a section with an unknown + type. */ +@@ -7944,9 +7933,6 @@ const struct elf_size_info elf64_aarch64 + #define elf_backend_reloc_type_class \ + elf64_aarch64_reloc_type_class + +-#define elf_backend_section_flags \ +- elf64_aarch64_section_flags +- + #define elf_backend_section_from_shdr \ + elf64_aarch64_section_from_shdr + diff --git a/SOURCES/binutils-rh1226864.patch b/SOURCES/binutils-rh1226864.patch new file mode 100644 index 0000000..7624ba8 --- /dev/null +++ b/SOURCES/binutils-rh1226864.patch @@ -0,0 +1,159 @@ +diff -Nrup a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c +--- a/bfd/elf64-ppc.c 2015-06-23 07:38:21.531023391 -0600 ++++ b/bfd/elf64-ppc.c 2015-06-23 07:39:23.606689926 -0600 +@@ -4963,81 +4963,77 @@ ppc64_elf_before_check_relocs (bfd *ibfd + { + struct ppc_link_hash_table *htab; + struct ppc_link_hash_entry **p, *eh; ++ asection *opd = bfd_get_section_by_name (ibfd, ".opd"); + +- if (!is_ppc64_elf (info->output_bfd)) +- return TRUE; +- htab = ppc_hash_table (info); +- if (htab == NULL) +- return FALSE; +- +- if (is_ppc64_elf (ibfd)) ++ if (opd != NULL && opd->size != 0) + { +- asection *opd = bfd_get_section_by_name (ibfd, ".opd"); +- +- if (opd != NULL && opd->size != 0) ++ if (abiversion (ibfd) == 0) ++ set_abiversion (ibfd, 1); ++ else if (abiversion (ibfd) == 2) + { +- if (abiversion (ibfd) == 0) +- set_abiversion (ibfd, 1); +- else if (abiversion (ibfd) == 2) +- { +- info->callbacks->einfo (_("%P: %B .opd not allowed in ABI" +- " version %d\n"), +- ibfd, abiversion (ibfd)); +- bfd_set_error (bfd_error_bad_value); +- return FALSE; +- } +- +- if ((ibfd->flags & DYNAMIC) == 0 +- && (opd->flags & SEC_RELOC) != 0 +- && opd->reloc_count != 0 +- && !bfd_is_abs_section (opd->output_section)) +- { +- /* Garbage collection needs some extra help with .opd sections. +- We don't want to necessarily keep everything referenced by +- relocs in .opd, as that would keep all functions. Instead, +- if we reference an .opd symbol (a function descriptor), we +- want to keep the function code symbol's section. This is +- easy for global symbols, but for local syms we need to keep +- information about the associated function section. */ +- bfd_size_type amt; +- asection **opd_sym_map; +- +- amt = opd->size * sizeof (*opd_sym_map) / 8; +- opd_sym_map = bfd_zalloc (ibfd, amt); +- if (opd_sym_map == NULL) +- return FALSE; +- ppc64_elf_section_data (opd)->u.opd.func_sec = opd_sym_map; +- BFD_ASSERT (ppc64_elf_section_data (opd)->sec_type == sec_normal); +- ppc64_elf_section_data (opd)->sec_type = sec_opd; +- } ++ info->callbacks->einfo (_("%P: %B .opd not allowed in ABI" ++ " version %d\n"), ++ ibfd, abiversion (ibfd)); ++ bfd_set_error (bfd_error_bad_value); ++ return FALSE; + } + +- /* For input files without an explicit abiversion in e_flags +- we should have flagged any with symbol st_other bits set +- as ELFv1 and above flagged those with .opd as ELFv2. +- Set the output abiversion if not yet set, and for any input +- still ambiguous, take its abiversion from the output. +- Differences in ABI are reported later. */ +- if (abiversion (info->output_bfd) == 0) +- set_abiversion (info->output_bfd, abiversion (ibfd)); +- else if (abiversion (ibfd) == 0) +- set_abiversion (ibfd, abiversion (info->output_bfd)); +- +- p = &htab->dot_syms; +- while ((eh = *p) != NULL) ++ if ((ibfd->flags & DYNAMIC) == 0 ++ && (opd->flags & SEC_RELOC) != 0 ++ && opd->reloc_count != 0 ++ && !bfd_is_abs_section (opd->output_section)) + { +- *p = NULL; +- if (&eh->elf == htab->elf.hgot) +- ; +- else if (htab->elf.hgot == NULL +- && strcmp (eh->elf.root.root.string, ".TOC.") == 0) +- htab->elf.hgot = &eh->elf; +- else if (!add_symbol_adjust (eh, info)) ++ /* Garbage collection needs some extra help with .opd sections. ++ We don't want to necessarily keep everything referenced by ++ relocs in .opd, as that would keep all functions. Instead, ++ if we reference an .opd symbol (a function descriptor), we ++ want to keep the function code symbol's section. This is ++ easy for global symbols, but for local syms we need to keep ++ information about the associated function section. */ ++ bfd_size_type amt; ++ asection **opd_sym_map; ++ ++ amt = opd->size * sizeof (*opd_sym_map) / 8; ++ opd_sym_map = bfd_zalloc (ibfd, amt); ++ if (opd_sym_map == NULL) + return FALSE; +- p = &eh->u.next_dot_sym; ++ ppc64_elf_section_data (opd)->u.opd.func_sec = opd_sym_map; ++ BFD_ASSERT (ppc64_elf_section_data (opd)->sec_type == sec_normal); ++ ppc64_elf_section_data (opd)->sec_type = sec_opd; + } + } + ++ if (!is_ppc64_elf (info->output_bfd)) ++ return TRUE; ++ htab = ppc_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ /* For input files without an explicit abiversion in e_flags ++ we should have flagged any with symbol st_other bits set ++ as ELFv1 and above flagged those with .opd as ELFv2. ++ Set the output abiversion if not yet set, and for any input ++ still ambiguous, take its abiversion from the output. ++ Differences in ABI are reported later. */ ++ if (abiversion (info->output_bfd) == 0) ++ set_abiversion (info->output_bfd, abiversion (ibfd)); ++ else if (abiversion (ibfd) == 0) ++ set_abiversion (ibfd, abiversion (info->output_bfd)); ++ ++ p = &htab->dot_syms; ++ while ((eh = *p) != NULL) ++ { ++ *p = NULL; ++ if (&eh->elf == htab->elf.hgot) ++ ; ++ else if (htab->elf.hgot == NULL ++ && strcmp (eh->elf.root.root.string, ".TOC.") == 0) ++ htab->elf.hgot = &eh->elf; ++ else if (!add_symbol_adjust (eh, info)) ++ return FALSE; ++ p = &eh->u.next_dot_sym; ++ } ++ + /* Clear the list for non-ppc64 input files. */ + p = &htab->dot_syms; + while ((eh = *p) != NULL) +diff -Nrup a/ld/emultempl/ppc64elf.em b/ld/emultempl/ppc64elf.em +--- a/ld/emultempl/ppc64elf.em 2015-06-23 07:38:21.489024293 -0600 ++++ b/ld/emultempl/ppc64elf.em 2015-06-23 07:39:23.606689926 -0600 +@@ -539,7 +539,8 @@ ppc_finish (void) + /* e_entry on PowerPC64 points to the function descriptor for + _start. If _start is missing, default to the first function + descriptor in the .opd section. */ +- if ((elf_elfheader (link_info.output_bfd)->e_flags & EF_PPC64_ABI) == 1) ++ if (stub_file != NULL ++ && (elf_elfheader (link_info.output_bfd)->e_flags & EF_PPC64_ABI) == 1) + entry_section = ".opd"; + + if (stub_added) diff --git a/SOURCES/binutils-rh1247126.patch b/SOURCES/binutils-rh1247126.patch new file mode 100644 index 0000000..ee58911 --- /dev/null +++ b/SOURCES/binutils-rh1247126.patch @@ -0,0 +1,75 @@ +diff -Nrup a/bfd/elf.c b/bfd/elf.c +--- a/bfd/elf.c 2015-07-28 10:52:10.941754850 -0600 ++++ b/bfd/elf.c 2015-07-28 10:53:34.725982912 -0600 +@@ -4081,11 +4081,18 @@ _bfd_elf_map_sections_to_segments (bfd * + new_segment = TRUE; + } + else if ((last_hdr->flags & (SEC_LOAD | SEC_THREAD_LOCAL)) == 0 +- && (hdr->flags & (SEC_LOAD | SEC_THREAD_LOCAL)) != 0) ++ && (hdr->flags & (SEC_LOAD | SEC_THREAD_LOCAL)) != 0 ++ && ((abfd->flags & D_PAGED) == 0 ++ || (((last_hdr->lma + last_size - 1) & -maxpagesize) ++ != (hdr->lma & -maxpagesize)))) + { +- /* We don't want to put a loadable section after a +- nonloadable section in the same segment. +- Consider .tbss sections as loadable for this purpose. */ ++ /* We don't want to put a loaded section after a ++ nonloaded (ie. bss style) section in the same segment ++ as that will force the non-loaded section to be loaded. ++ Consider .tbss sections as loaded for this purpose. ++ However, like the writable/non-writable case below, ++ if they are on the same page then they must be put ++ in the same segment. */ + new_segment = TRUE; + } + else if ((abfd->flags & D_PAGED) == 0) +diff -Nrup a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d +--- a/ld/testsuite/ld-powerpc/elfv2so.d 2015-07-28 10:52:10.921755273 -0600 ++++ b/ld/testsuite/ld-powerpc/elfv2so.d 2015-07-28 10:41:10.046732001 -0600 +@@ -7,31 +7,31 @@ + + Disassembly of section \.text: + +-0+320 <.*\.plt_call\.f4>: ++0+300 <.*\.plt_call\.f4>: + .*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) + .*: (38 80 82 e9|e9 82 80 38) ld r12,-32712\(r2\) + .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 + .*: (20 04 80 4e|4e 80 04 20) bctr + +-0+330 <.*\.plt_call\.f3>: ++0+310 <.*\.plt_call\.f3>: + .*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) + .*: (28 80 82 e9|e9 82 80 28) ld r12,-32728\(r2\) + .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 + .*: (20 04 80 4e|4e 80 04 20) bctr + +-0+340 <.*\.plt_call\.f2>: ++0+320 <.*\.plt_call\.f2>: + .*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) + .*: (30 80 82 e9|e9 82 80 30) ld r12,-32720\(r2\) + .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 + .*: (20 04 80 4e|4e 80 04 20) bctr + +-0+350 <.*\.plt_call\.f1>: ++0+330 <.*\.plt_call\.f1>: + .*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) + .*: (40 80 82 e9|e9 82 80 40) ld r12,-32704\(r2\) + .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 + .*: (20 04 80 4e|4e 80 04 20) bctr + +-0+360 : ++0+340 : + .*: (02 00 4c 3c|3c 4c 00 02) addis r2,r12,2 + .*: (d8 81 42 38|38 42 81 d8) addi r2,r2,-32296 + .*: (a6 02 08 7c|7c 08 02 a6) mflr r0 +@@ -53,7 +53,7 @@ Disassembly of section \.text: + .*: (98 01 01 00|00 00 00 00) .* + .*: (00 00 00 00|00 01 01 98) .* + +-0+3b0 <__glink_PLTresolve>: ++0+390 <__glink_PLTresolve>: + .*: (a6 02 08 7c|7c 08 02 a6) mflr r0 + .*: (05 00 9f 42|42 9f 00 05) bcl .* + .*: (a6 02 68 7d|7d 68 02 a6) mflr r11 diff --git a/SPECS/binutils.spec b/SPECS/binutils.spec index 1fb4320..ee46a8a 100644 --- a/SPECS/binutils.spec +++ b/SPECS/binutils.spec @@ -19,7 +19,7 @@ Summary: A GNU collection of binary utilities Name: %{?cross}binutils%{?_with_debug:-debug} Version: 2.23.52.0.1 -Release: 30%{?dist}.2 +Release: 55%{?dist} License: GPLv3+ Group: Development/Tools URL: http://sources.redhat.com/binutils @@ -79,7 +79,12 @@ Patch27: binutils-ppc-pgsz.patch # RELRO fixes Patch28: binutils-rh1200138-1.patch Patch29: binutils-rh1200138-2.patch +# Fix to PIE support on s390 Patch30: binutils-rh872148.patch +# Enable RELRO on AArch64 +Patch31: binutils-rh1203449.patch +# Improve RELRO on PPC64 +Patch32: binutils-rh1175624.patch Patch100: binutils-rh1066712.patch Patch101: binutils-rh1075827.patch @@ -96,6 +101,7 @@ Patch117: binutils-aa64-ifunc.patch Patch118: binutils-aa64-gas-movi.patch Patch119: binutils-aa64-dwarf2.patch Patch120: binutils-rh1179810.patch +Patch121: binutils-rh1182111.patch # ppc64 little endian support Patch201: binutils-ppc64le-1.patch @@ -109,6 +115,50 @@ Patch208: binutils-ppc64le-8.patch Patch209: binutils-ppc64le-9.patch Patch210: binutils-ppc64le-10.patch Patch211: binutils-ppc64le-11.patch +Patch212: binutils-rh1194164.patch + +Patch300: binutils-rh1182153.patch +# Undo unnecessary and problematic Gold changes applied in +# binutils-ppc64le-1.patch above (Gold isn't built on ppc64le). +Patch301: binutils-ppc64le-1.1.patch + +# Enable conflicting changes to BFD for powerpc only via #ifdefs. +Patch302: bfd-ppc64le.patch +# Bug 1172766 - ppc64: segv in libbfd +Patch303: binutils-rh1172766.patch + +# Fixes minor testsuite issues after PPC64 merge +Patch304: binutils-rh1183838.patch + +# Tweak for 1172766 ppc64: segv in libbfd. +Patch305: binutils-rh1172766-1.patch + +# Fix segfault building libhugetlbfs when bogus +# max-page-size is passed to ld. +Patch306: binutils-rh1203449-2.patch + +# Don't discard stap probe note sections on aarch64 +Patch307: binutils-rh1225091.patch + +# Fixes ld crash with -oformat binary +Patch308: binutils-rh1226864.patch + +# Avoid reading beyond function boundary when disassembling +Patch309: binutils-rh1060282.patch + +# Patches related to BZ 1168302 - security flaws in the BFD +# library: +Patch400: binutils-rh1157276.patch +Patch401: binutils-rh1162594.patch +Patch402: binutils-rh1162607.patch +Patch403: binutils-rh1162621.patch +Patch404: binutils-rh1162655.patch +Patch405: binutils-rh1162666.patch + +# Fix incorrectly generated ELF binaries and DSOs +Patch406: binutils-rh1247126.patch +# AArch64: Create GOT entries for local symbols: BZ #1238783 +Patch407: binutils-2.23.52.0.1-aarch64-local-GOT-entries.patch Provides: bundled(libiberty) @@ -236,7 +286,9 @@ using libelf instead of BFD. %patch27 -p1 -b .ppc-pgsz~ %patch28 -p1 -b .relro1~ %patch29 -p1 -b .relro2~ -%patch30 -p1 -b .s390x~ +%patch30 -p1 -b .s390pie~ +%patch31 -p0 -b .aarch64relro~ +%patch32 -p1 -b .ppc64relro~ %patch100 -p0 -b .aarch64-fpintfix~ %patch101 -p1 -b .aarch64-101~ %patch102 -p1 -b .aarch64-102~ @@ -251,6 +303,7 @@ using libelf instead of BFD. %patch118 -p1 -b .aarch64-118~ %patch119 -p1 -b .aarch64-119~ %patch120 -p1 -b .aarch64-120~ +%patch121 -p1 -b .aarch64-121~ # We cannot run autotools as there is an exact requirement of autoconf-2.59. @@ -273,9 +326,6 @@ do done touch */configure -%ifarch ppc64le -# ppc64le support has some wholesale replacement of ppc/ppc64 infrastructure -# not suitable for vanilla ppc. %patch201 -p1 %patch202 -p1 %patch203 -p1 @@ -287,7 +337,55 @@ touch */configure %patch209 -p1 %patch210 -p1 %patch211 -p1 -%endif +%patch212 -p1 + +%patch300 -p1 +# Revert bad changes made in patch201. +%patch301 -p1 +# Guard BFD changes with __PPC__. +%patch302 -p1 + +# Fix segfault in bfd for ppc64 +%patch303 -p1 + +# Minor testsuite issues after PPC merge +%patch304 -p1 + +# Tweak for 1172766 ppc64: segv in libbfd. +%patch305 -p1 + +# Fix segfault building libhugetlbfs when bogus +# max-page-size is passed to ld. +%patch306 -p1 + +# Don't discard stap probe note sections on aarch64 +%patch307 -p1 + +# Fix ld segfault with --oformat binary +%patch308 -p1 + +# Avoid reading beyond function boundary when disassembling +%patch309 -p1 + +# Change the strings program to default to -a. +# Fix parsing corrupt ELF group sections. +%patch400 -p1 +# Fix parsing corrupt PE binaries. +%patch401 -p1 +# Fix parsing corrupt iHex files. +%patch402 -p1 +# Fix parsing corrupt SREC files. +%patch403 -p1 +# Fix directory traversal vulnerability. +%patch404 -p1 +# Fix memory corruption parsing a fuzzed archive. +%patch405 -p1 + +# Fix incorrectly generated ELF binaries and DSOs. +%patch406 -p1 + +# Fix generation of GOT entries for local symbols on AArch64 +%patch407 -p1 -b .aarch64-local-GOT %ifarch %{power64} ppc64le %define _target_platform %{_arch}-%{_vendor}-%{_host_os} @@ -395,7 +493,7 @@ install -m 644 libiberty/libiberty.a %{buildroot}%{_libdir} install -m 644 include/libiberty.h %{buildroot}%{_prefix}/include install -m 644 opcodes/libopcodes.a %{buildroot}%{_libdir} # Remove Windows/Novell only man pages -rm -f %{buildroot}%{_mandir}/man1/{dlltool,nlmconv,windres}* +rm -f %{buildroot}%{_mandir}/man1/{dlltool,nlmconv,windres,windmc}* %if %{enable_shared} chmod +x %{buildroot}%{_libdir}/lib*.so* @@ -569,11 +667,92 @@ exit 0 %endif # %{isnative} %changelog -* Tue Mar 30 2015 Jeff Law - 2.23.52.0.1-30.2 +* Tue Oct 13 2015 Nick Clifton 2.23.52.0.1-55 +- Add missing delta to patch that fixes parsing corrupted archives. + (#1162666) + +* Wed Jul 29 2015 Nick Clifton 2.23.52.0.1-54 +- Import patch for PR 18270: Create AArch64 GOT entries for local symbols. + (#1238783) + +* Tue Jul 28 2015 Jeff Law - 2.23.52.0.1-51 +- Fix incorrectly generated binaries and DSOs on PPC platforms. + (#1247126) + +* Mon Jun 29 2015 Nick Clifton - 2.23.52.0.1-50 +- Fix memory corruption parsing corrupt archives. + (#1162666) + +* Mon Jun 29 2015 Nick Clifton - 2.23.52.0.1-49 +- Fix directory traversal vulnerability. + (#1162655) + +* Mon Jun 29 2015 Nick Clifton - 2.23.52.0.1-48 +- Fix stack overflow in SREC parser. + (#1162621) + +* Mon Jun 29 2015 Nick Clifton - 2.23.52.0.1-47 +- Fix stack overflow whilst parsing a corrupt iHex file. + (#1162607) + +* Mon Jun 29 2015 Nick Clifton - 2.23.52.0.1-46 +- Fix out of bounds memory accesses when parsing corrupt PE binaries. + (#1162594, #1162570) + +* Mon Jun 29 2015 Nick Clifton - 2.23.52.0.1-45 +- Change strings program to default to -a. Fix problems parsing + files containg corrupt ELF group sections. (#1157276) + +* Tue Jun 23 2015 Jeff Law - 2.23.52.0.1-44 +- Avoid reading beyond function boundary when disassembling. + (#1060282) + +- For binary ouput, we don't have an ELF bfd output so can't access + elf_elfheader. (#1226864) + +* Thu May 28 2015 Jeff Law - 2.23.52.0.1-43 +- Don't discard stap probe note sections on aarch64 (#1225091) + +* Tue May 26 2015 Jeff Law - 2.23.52.0.1-42 +- Clamp maxpagesize at 1 (rather than 0) to avoid segfaults + in the linker when passed a bogus max-page-size argument. + (#1203449) + +* Thu May 21 2015 Martin Sebor - 2.23.52.0.1-41 +- Fixup bfd elf_link_add_object_symbols for ppc64 to prevent subsequent + uninitialized accesses elsewhere. (#1172766) + +* Thu May 7 2015 Jeff Law - 2.23.52.0.1-40 +- Minor testsuite adjustments for PPC changes in -38/-39. + (#1183838) + Fix md_assemble for PPC to handle arithmetic involving the TOC + better. (#1183838) + +* Wed May 6 2015 Martin Sebor - 2.23.52.0.1-39 +- Fix ppc64: segv in libbfd (#1172766). + +* Wed May 6 2015 Martin Sebor - 2.23.52.0.1-38 +- Unconditionally apply ppc64le patches (#1183838). + +* Mon May 4 2015 Jeff Law - 2.23.52.0.1-37 +- Andreas's backport of z13 and dependent fixes for s390, + including tesetcase fix from Apr 27, 2015. (#1182153) + +* Tue Apr 7 2015 Jeff Law - 2.23.52.0.1-35 +- Fixup testsuite for AArch64 (#1182111) +- Add support for @localentry for LE PPC64 (#1194164) + +* Tue Mar 31 2015 Jeff Law - 2.23.52.0.1-34 +- Do not install windmc(1) man page (#850832) + +* Fri Mar 27 2015 Jeff Law - 2.23.52.0.1-33 - Don't replace R_390_TLS_LE{32,64} with R_390_TLS_TPOFF for PIE - (#872148) (#1207533) - -* Wed Mar 11 2015 Jeff Law - 2.23.52.0.1-30.1 + (#872148) +- Enable relro by default for arm and aarch64 (#1203449) +- Backport 3 RELRO improvements for ppc64/ppc64le from upstream + (#1175624) + +* Wed Mar 11 2015 Jeff Law - 2.23.52.0.1-31 - Backport upstream RELRO fixes. (#1200138) * Thu Jan 15 2015 Jeff Law - 2.23.52.0.1-30